US20070180420A1 - Designing a circuit apparatus with multiple propagation speeds of signals - Google Patents

Abstract

Designing a circuit apparatus involves determining locations and lengths of routing paths for signals, routing paths of a first length range being located in a first layer, and routing paths of a second length range being located in a second layer; determining propagation speeds for the signals to propagate through the routing paths within a propagation time range; and selecting dielectric materials for the layers in accordance with the determined propagation speeds for the routing paths.

Description

REFERENCE TO PRIOR NONPROVISIONAL APPLICATION
• This is a divisional application of application Ser. No. 10/832,633, filed Apr. 27, 2004.
BACKGROUND
• Some signals transferred within computer systems have very strict timing constraints. For example, specifications that define computer bus systems often require that the signals of the bus system arrive at each node of the bus system at the same time, or within an acceptable tolerance. The bus signals must be synchronized so they can be read at a receiving node at the same time. Otherwise, data transmitted over the bus system could be corrupted, and the computer would not work.
• A physical signal-transmission portion of the bus system commonly includes signal lines formed in a printed circuit board (PCB). The bus signals travel, or propagate, through conductive traces disposed in various layers of the PCB between the nodes of the bus system. Each conductive trace forms a segment of one bus signal line.
• In a common situation, the distance between one pair of nodes of the bus system is significantly different from the distance between another pair of nodes. If both conductive traces electrically connecting both pairs of nodes were routed through the PCB in the shortest manner possible, then the length of the conductive traces would potentially be significantly different. The difference in lengths of the conductive traces, if sufficiently large, would significantly impact the timing of the bus signals transmitted between each of the nodes. The specification for the bus system, however, requires that the timing of the bus signals be within an acceptable tolerance of each other.
• To ensure that the signal timing requirements are met, the shorter conductive trace is artificially made longer to have a length about the same as the length of the longer conductive trace. To lengthen the shorter conductive trace, the conductive trace is routed in a serpentine manner for a portion of its length. The bus signals, thus, propagate through the different conductive traces in about the same amount of time.
• The trace-lengthening technique for bus signal synchronization requires that there be sufficient space in the PCB for the added length of some of the conductive traces. However, as ICs become more complex, the number of nodes, and concurrently the number of conductive traces, increases. Additionally, as the PCBs are made smaller, the space available for the conductive traces decreases. The increasing number and density of the conductive traces is incompatible with the decreasing space in the PCBs and places severe constraints on the layout of the PCB.
• One solution to this problem has been to increase the number of layers in the PCB in which the conductive traces can be formed. However, this solution increases the thickness of the PCBs and increases the time, complexity and cost of manufacturing the PCBs.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a simplified block diagram of a computer system according to an embodiment of the present invention.
• FIG. 2 is a simplified cross section of the computer system shown inFIG. 1 and of a PCB incorporated therein according to an embodiment of the present invention.
• FIG. 3 is a simplified schematic view of the PCB shown inFIG. 2 according to an embodiment of the present invention.
• FIG. 4 is another simplified cross section of the PCB shown inFIG. 2 according to an embodiment of the present invention.
• FIG. 5 is another simplified cross section of the PCB shown in FIG.2 according to an embodiment of the present invention.
• FIG. 6 is a simplified cross section of a PCB incorporated in the computer system shown inFIG. 1 according to an alternative embodiment of the present invention.
• FIG. 7 is a simplified timing chart for propagation times of unadjusted exemplary signals propagating through a PCB.
• FIG. 8 is a simplified timing chart for propagation times of adjusted exemplary signals propagating through a PCB incorporated in the computer system shown inFIG. 1 according to an embodiment of the present invention.
DETAILED DESCRIPTION
• Acomputer system200 incorporating an embodiment of the present invention is shown inFIG. 1. Thecomputer system200 generally includes user interface devices, such as a keyboard andpointing device202 and amonitor204. Thecomputer system200 also generally includes various I/O devices206 and various integrated circuits (ICs)208,210 and212. The components202-212 are generally connected by a variety of signals andbus systems214. The ICs208-212 are preferably any appropriate computer chips, such as processors and ASICs (application specific ICs), among others, mounted within ahousing215. Thebus systems214 may include serial (i.e. having one or few signals) and/or parallel (i.e. having several signals) bus systems.
• The ICs208-212 and thebus system214 connecting the ICs208-212 are preferably incorporated in a populated printedcircuit board216 mounted within thehousing215, as shown inFIG. 2. In addition to the lCs208-212, the populated printedcircuit board216 preferably includes aboard218 on which the ICs208-212 and any other components are mounted, e.g. by soldering. The ICs208-212 generally include several I/O points220, e.g. pins, leads, solder balls, etc., connected to theboard218. Theboard218 preferably includesseveral layers222 and224,several vias226,228 and230 and severalconductive traces232 and234. Thevias226,228 and230 and theconductive traces232 and234 generally form signal paths through which electronic signals (e.g. bus signals, clock signals, control signals, etc.) are transferred within theboard218 between the components mounted thereon.
• To form thebus system214, the ICs208-212 are connected together at corresponding I/O points220 by the vias226-230 and theconductive traces232 and234. For example, corresponding I/O points (pin 1s)220 of theICs208 and210 are connected through thevia226, theconductive trace232 and thevia228. Similarly, corresponding I/O points (pin 1s)220 of theICs210 and212 are connected through thevia228, theconductive trace234 and thevia230. Each of theconductive traces232 and234, thus, forms a segment of one signal of thebus system214. Additional conductive traces may form segments of any other signals between the components mounted on theboard218. Since each IC208-212 is connected to more than one other IC208-212 through each signal of thebus system214, thebus system214 is referred to as a “multi-drop bus.” Additional vias and conductive traces within theboard218 may connect other I/O points on the ICs208-212 and/or other components on the populated printedcircuit board216 whether connected by thebus system214 or by any other signal lines.
• As shown inFIG. 3, though not necessarily drawn to scale, each of the signal segments, orconductive traces232 and234, is of a different length, which is preferably minimized so as to take up as little space in theboard218 as possible. In particular,conductive trace232 is longer thanconductive trace234. Bus specifications, however, typically require that the propagation time through each segment of thebus system214 be about the same, within a tolerance (on the order of 10s to 100s of picoseconds) of each other or of a specified time period, or within a specified time range. To ensure that signals arrive at each I/O point220 within a desired propagation time range, the material of eachlayer222 and224 (FIG. 2) surrounding theconductive traces232 and234 is selected for its effect on the propagation speed (measured in picoseconds per inch) of the signals transmitted through theconductive traces232 and234. Since electrical signals propagate faster through conductive traces surrounded by material having a lower dielectric constant, the material of thelayer222 surrounding the longerconductive trace232 preferably has a lower dielectric constant than does the material of thelayer224 surrounding the shorterconductive trace234. In this manner, the signals transferred through the longerconductive trace232 propagate within about the same amount of time as the signals transferred through the shorterconductive trace234. In other words, the “length ratio” of the longerconductive trace232 to the shorterconductive trace234 is preferably about the same as the “speed ratio” of the faster propagation speed to the slower propagation speed for thelayers222 and224. Thus, the speed ratio for thelayers222 and224 may be used to determine a range of allowable lengths for theconductive traces232 and234.
• Although the description herein relates to thebus system214, it is understood that the invention is not so limited, but may also apply to other situations having bus and/or non-bus signals that have preferred timing constraints and which may be selectively placed in thelayers222 and224 in order to affect the timing of these signals as desired. For example, distributed clock signals can be synchronized in this manner across a printed circuit board, an integrated circuit or other appropriate type of circuit apparatus.
• Similarly, as shown inFIG. 4, corresponding I/O points (pin Ns)220 of theICs208 and210 are connected through avia236, aconductive trace238 and a via240. Additionally, corresponding I/O points (pin Ns)220 of theICs210 and212 are connected through thevia240, aconductive trace242 and a via244. Each of theconductive traces238 and242, thus, forms a bus segment of another signal of the bus system214 (FIG. 1). Theconductive trace242 is longer than theconductive trace238. Therefore, the longerconductive trace242 is preferably placed in thelayer222 having the lower dielectric constant and, therefore, the faster propagation speed, and the shorterconductive trace238 is preferably placed in thelayer224 having the higher dielectric constant and, therefore, the slower propagation speed. In this manner, the bus signals transferred through the longerconductive trace242 propagate within about the same amount of time as the bus signals transferred through the shorterconductive trace238.
• Additionally, according to an embodiment shown inFIG. 5, bus segments connecting different pairs of corresponding I/O points220 are placed in thelayers222 and224 depending on the lengths of theconductive traces232 and238. In this case, corresponding I/O points (pin 1s)220 of theICs208 and210 are connected through the via226, theconductive trace232 and the via228, and corresponding I/O points (pin Ns)220 of theICs208 and210 are connected through the via236, theconductive trace238 and thevia240. In this manner, the bus signals transmitted through different bus segments between the same two ICs propagate within about the same amount of time.
• Although not necessarily drawn to scale, the longerconductive trace232 inFIGS. 2 and 5 is not necessarily the same length as the longerconductive trace242 inFIG. 4, even though bothconductive traces232 and242 are shown in thesame layer222. Similarly, although not necessarily drawn to scale, the shorterconductive trace238 inFIGS. 4 and 5 is not necessarily the same length as the shorterconductive trace234 inFIG. 2, even though bothconductive traces238 and234 are shown in thesame layer224. Conductive traces of different lengths may be placed within thesame layer222 or224, however, as long as the propagation times for each conductive trace is within the accepted propagation time range, or within an allowable tolerance of a specified time period.
• The embodiments shown inFIGS. 2, 4 and5 have, for simplicity, shown only twolayers222 and224 in theboard218. However, according to an embodiment of the present invention, as shown inFIG. 6, a populated printedcircuit board246 may include aboard248 having any appropriate number oflayers250a,250band250m(layer 1,layer 2 . . . layer M). The actual number in a given situation may depend on the size of the bus, i.e. a bus with few signals could more easily get by with few layers, but a bus with many signals (e.g. hundreds of signals) may require several layers, each with a different dielectric material with a different propagation speed. In the example shown, thus, the materials for each layer250a-250mare selected to give some of the layers250a-250mdifferent propagation speeds. Conductive traces (e.g.256,258,260 and262) are, therefore, preferably distributed among the layers250a-250maccording to the lengths of the conductive traces256-262. For example, the longer conductive traces (e.g.256) are preferably placed in the layer (e.g.250a) having the fastest dielectric material, the shorter conductive traces (e.g.262) are preferably placed in the layer (e.g.250m) having the slowest dielectric material, and the intermediate-length conductive traces (e.g.258 and260) are preferably placed in the layer(s) (e.g.250b) having intermediate-speed dielectric material(s).
• The effect of the different dielectric materials on the bus signals in the layers250a-250mis illustrated bytime charts264 and266 shown inFIGS. 7 and 8, respectively, for “unadjusted exemplary signals” and “adjusted exemplary signals.” The adjusted exemplary signals are preferably an exemplary set of bus signals propagating through the various layers250a-250mof the board248 (FIG. 6) at different propagation speeds. The unadjusted exemplary signals, on the other hand, represent the same bus signals under a hypothetical condition in which the propagation speeds are not adjusted by having materials with different dielectric constants for the layers250a-250mof theboard248. In other words, the dielectric materials for the layers250a-250mare the same for the unadjusted exemplary signals. Thus, the unadjusted exemplary signals have the same propagation speeds and, therefore, different propagation times.
• In this example, as shown byFIG. 7, the propagation times fall into threeranges268,270 and272, and the unadjusted exemplary signals fall into three corresponding groups ofbus signals274,276 and278. The bus signals274 with the shortest propagation times propagate through the shortest conductive traces in theboard248, the bus signals276 with the intermediate propagation times propagate through the intermediate-length conductive traces in theboard248, and the bus signals278 with the longest propagation times propagate through the longest conductive traces in theboard248. The bus signals274 and276 that do not fall within thepropagation time range268 are to be adjusted according to an embodiment of the present invention, so the short and intermediate bus signals274 and276 will fall within thepropagation time range268.
• The dielectric material for the layer (e.g.250m,FIG. 6), which contains the shortest conductive traces (e.g.262), is selected to have the slowest propagation speed. The dielectric material for the layer (e.g.250a,FIG. 6), which contains the longest conductive traces (e.g.256), is selected to have the fastest propagation speed. The dielectric material for the layer (e.g.250b,FIG. 6), which contains the intermediate-length conductive traces (e.g.258 and260), is selected to have an intermediate propagation speed. In this manner, the propagation times for the bus signals274 and276 are effectively “stretched” to fall within the samepropagation time range268 as for the bus signals278, as shown inFIG. 8. Thus, all of the bus signals274,276 and278 propagate within the acceptablepropagation time range268.
• One of the bus signals280 is illustrated as an exception to the other bus signals in the groups ofbus signals274 and276. If thebus signal280 were placed in theboard248 in the minimum-length, most-economical signal path possible and adjusted only by placing the conductive trace for thebus signal280 in thelayer250bwith the intermediate-speed dielectric material, then the propagation time for thebus signal280 would fall atpoint282, outside of the acceptablepropagation time range268. On the other hand, if thebus signal280 were adjusted by placing the conductive trace for thebus signal280 in thelayer250mwith the slowest dielectric material, then the propagation time for thebus signal280 would fall atpoint284, also outside of the acceptablepropagation time range268. Therefore, thebus signal280 is preferably placed in thelayer250bwith the intermediate-speed dielectric material, and the serpentine technique described in the background is preferably incorporated to “stretch,” or lengthen, thebus signal280 an additional amount oftime286. In this manner, thepropagation time point288 at which thebus signal280 falls is within the acceptablepropagation time range268. By thus combining the serpentine technique with an embodiment of the present invention, only a minimal amount of lengthening of the conductive trace for thebus signal280 is required, so the additional space in theboard248 taken up by the serpentine portion of the conductive trace for thebus signal280 is minimized.
• The selection of the number of layers in the printed circuit board, the dielectric materials for each of the layers and the lengths and placements of each of the conductive traces for any given printed circuit board design may be determined by experiment or simulation. In this manner, timing problems and considerations may be identified for the design. The best placement of the conductive traces in the layers (to take into account such timing problems and considerations) may thus be determined by such methods. The most space-saving placement of the conductive traces typically minimizes the lengths of the conductive traces. Upon determining the minimum length for each conductive trace, the propagation time for a signal passing therethrough may be determined in order to identify timing problems between different signals, assuming initially that the layers are all made of the same dielectric material. If such timing problems exist, then different dielectric materials may be substituted in some or all of the layers, and the conductive traces placed in the appropriate layer. In this manner, the various characteristic propagation speeds of the available dielectric materials for the different layers may be taken into consideration in the design or simulation. A range of allowable lengths for the conductive traces may thus be determined from the ratio of the characteristic propagation speeds between any two layers in conjunction with the allowable propagation time constraints. Other parameters, such as the distance between a conductive trace and a ground plane as well as the thickness, width and resistance of the conductive traces, may also affect propagation speed and should be taken into consideration in designs and simulations. Additionally, when the propagation speeds of selected dielectric materials for different layers are insufficient to compensate for the differences in lengths of conductive traces within the layers, the shorter conductive trace may have to be lengthened accordingly from its minimum, most-direct-route length.
• A common dielectric material for the layers of a printed circuit board is known as FR4. Additional types of material that have lower dielectric constants and faster propagation speeds include SPEEDBOARD ™ C High Performance Prepreg and MICROLAM ™ Dielectrics from W. L. Gore & Associates, Inc. The faster material is generally more expensive, so FR4 is more commonly used.
• Dielectric constants (Er) for some materials may range between 1 (e.g. for a vacuum) and about 80 (e.g. for water). FR4, for instance, has an Er of about 4.7 for a propagation time of about 183.7ps/in. SPEEDBOARD ™ C has an Er of about 2.6 for a propagation time of about 137ps/in. Practical dielectric constants, however, typically range from about 2 to about 5.
• Additionally, it is known that the dielectric constant of, and the relative propagation speed through, the material may be affected by varying the construction techniques of the dielectric material. Thus, different processes, as well as different materials, may be used in construction of the printed circuit board to achieve the desired results of having a variety of propagation speeds in the printed circuit board.
• An exemplary procedure for manufacturing a printed circuit board according to the present invention will be described with reference toFIG. 2. Typically, construction starts with a core layer including a dielectric material290 (e.g. FR4) with a return (ground) orpower plane292 on one side and a conductive trace pattern294 (including the conductive trace234) on the other side. Then a “prepreg” layer (a flexible uncured epoxy resin)296 is placed on thecore layer290/292/294. Thedielectric material290 andprepreg layer296 are preferably of the same or similar dielectric constant, which forms the dielectric surrounding theconductive trace234. Another core layer, including another dielectric material298 (e.g. SPEEDBOARD ™), a return orpower plane300 and a conductive trace pattern302 (including the conductive trace232), is placed on theprepreg layer296. Theprepreg layer296 is then cured. Another prepreg layer (e.g. SPEEDBOARD ™)304 is placed on top of thecore layer298/300/302. Thedielectric material298 andprepreg layer304 are preferably of the same or similar dielectric constant, which forms the dielectric surrounding theconductive trace232. The process of placing core layers and prepreg layers together is repeated until theboard218 has the desired number of layers. Additionally, a final return orpower plane306 is typically placed on top of thelast prepreg layer304.
• An alternative embodiment of the present invention may be incorporated within another type of circuit apparatus, such as an IC chip, as opposed to a printed circuit board (e.g.218,FIG. 2). IC chips generally include several routing layers that have conductive traces within dielectric materials. The dielectric material in each layer, similar to the discussion above, is selected for its dielectric constant and signal propagation speed characteristics. Conductive traces of different lengths, but which carry signals that must be synchronized, are selectively placed within the routing layers depending on the lengths of the conductive traces and the propagation speeds of the routing layers. Thus, the shorter conductive traces are formed in routing layers having slower dielectric materials, and the longer conductive traces are formed in routing layers having faster dielectric materials.

Claims (5)

1. A method for designing a circuit apparatus having a plurality of layers and a plurality of conductors disposed within the layers for conducting a plurality of signals, comprising:

determining locations and lengths of routing paths for the signals, routing paths of a first length range being located in a first one of the layers, and routing paths of a second length range being located in a second one of the layers;

determining propagation speeds for the signals to propagate through the routing paths within a propagation time range; and

selecting dielectric materials for the layers in accordance with the determined propagation speeds for the routing paths.

2. A method as defined inclaim 1 wherein the circuit apparatus comprises a printed circuit board.

3. A method for designing a circuit apparatus having at least first and second layers and at least first and second conductors disposed within the first and second layers, respectively, for conducting at least first and second signals, respectively, comprising:

determining a minimum length for each of the conductors, the first conductor being longer than the second conductor;

determining a propagation time for the first and second signals to propagate through the first and second conductors and whether the propagation time for each signal is within a time constraint; and

upon determining that the propagation times for the signals are not within the time constraint, selecting first and second dielectric materials having different characteristic propagation speeds for the first and second layers, respectively, the characteristic propagation speed of the first dielectric material being faster than the characteristic propagation speed of the second dielectric material.

4. A method as defined inclaim 3, further comprising:

selecting the first and second dielectric materials to minimize a difference between a ratio of the length of$-the first conductor to the length of the second conductor and a ratio of the characteristic propagation speed of the first dielectric material to the characteristic propagation speed of the second dielectric material.

5. A method for designing a circuit apparatus having a plurality of layers and a plurality of conductors disposed within the layers for conducting a plurality of signals according to time constraints, comprising:

selecting dielectric materials having different characteristic propagation speeds for the layers;

determining a ratio between the characteristic propagation speeds of the dielectric materials of two of the layers; and

determining a range of allowable lengths of the conductors disposed in the two layers depending on the ratio between the characteristic propagation speeds of the dielectric materials of the two layers and on the time constraints.

Images