US20070172983A1 - Three-dimensional package and method of making the same - Google Patents
Three-dimensional package and method of making the sameDownload PDFInfo
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- US20070172983A1 US20070172983A1US11/645,039US64503906AUS2007172983A1US 20070172983 A1US20070172983 A1US 20070172983A1US 64503906 AUS64503906 AUS 64503906AUS 2007172983 A1US2007172983 A1US 2007172983A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present inventionrelates to a package and a method of making the same, and more particularly to a three-dimensional package and a method of making the same.
- FIG. 1it shows a schematic view of a three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655.
- the conventional three-dimensional package 1comprises a first unit 10 and a second unit 20 .
- the first unit 10comprises a first wafer 11 , at least one first hole 12 , a first conductive layer 13 and a first solder 14 .
- the first wafer 11has a first surface 111 and a second surface 112 .
- the first surface 111has at least one first pad (not shown) and a first protection layer 113 exposing the first pad.
- the first hole 12penetrates the first wafer 11 .
- the first conductive layer 13is disposed on the side wall of the first hole 12 and covers the first pad and the first protection layer 113 .
- the first solder 14is disposed in the first hole 12 and is electrically connected to the first pad via the first conductive layer 13 .
- the upper end of the first solder 14extends above the first surface 111 of the first wafer 11 , and the lower end extends below the second surface 112 of the first wafer 11 .
- the second unit 20is stacked on the first unit 10 .
- the second unit 20comprises a second wafer 21 , at least one second hole 22 , a second conductive layer 23 and a second solder 24 .
- the second wafer 21has a first surface 211 and a second surface 212 .
- the first surface 211has at least one second pad (not shown) and a second protection layer 213 exposing the second pad.
- the second hole 22penetrates the second wafer 21 .
- the second conductive layer 23is disposed on the side wall of the second hole 22 and covers the second pad and the second protection layer 213 .
- the second solder 24is disposed in the second hole 22 and is electrically connected to the second pad via the second conductive layer 23 .
- the upper end of the second solder 24extends above the first surface 211 of the second wafer 21 , and the lower end of the second solder 24 extends below the second surface 212 of the second wafer 21 .
- the lower end of the second solder 24is aligned with and contacts the upper end of the first solder 14 .
- the first solder 14 and the second solder 24are formed by disposing the first wafer 11 and the second wafer 21 above a solder bath, and the solder enter the first hole 12 and the second hole 22 according to the capillary phenomenon so as to form the first solder 14 and the second solder 24 .
- the disadvantages of the conventional three-dimensional package 1are described as follows.
- the first solder 14 and the second solder 24are formed according to the capillary phenomenon, the upper and the lower ends of the foregoing solders are in a hemispherical shape ( FIG. 1 ).
- the first unit 10 and the second unit 20are aligned and joined, alignment becomes more difficult and the joining between the first unit 10 and the second unit 20 after reflow is not stable.
- the overall heightcannot be effectively reduced due to the excess hemispherical solders.
- the main objective of the inventionis to provide a method of making a three-dimensional package, which comprises the following steps:
- the lower end of the conductive layeris exposed below the second surface of the wafer. Therefore, during the reflow process after stacking, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional package after joining.
- Another objective of the present inventionis to provide a three-dimensional package, which comprises a first unit and a second unit.
- the first unitcomprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, and a first solder.
- the first waferhas a first surface and a second surface.
- the first surfacehas at least one first pad and a first protection layer exposing the first pad.
- the first holepenetrates the first wafer.
- the first isolation layeris disposed on the side wall of the first hole.
- the first conductive layercovers the first pad, a part of the first protection layer, and the first isolation layer. The lower end of the first conductive layer extends below the second surface of the first wafer.
- the first solderis disposed in the first hole, and is electrically connected to the first pad via the first conductive layer.
- the second unitis stacked on the first unit.
- the second unitcomprises a second wafer, at least one second hole, a second isolation layer, a second conductive layer, and a second solder.
- the second waferhas a first surface and a second surface.
- the first surfacehas at least one second pad and a second protection layer exposing the second pad.
- the second holepenetrates the second wafer.
- the second isolation layeris disposed on the side wall of the second hole.
- the second conductive layercovers the second pad, a part of the second protection layer, and the second isolation layer.
- the lower end of the second conductive layerextends to below the second surface of the second wafer and contacts the upper end of the first solder.
- the second solderis disposed in the second hole and is electrically connected to the second pad via the second conductive layer.
- FIG. 1shows a schematic view of the three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655;
- FIG. 2shows a schematic view of the three-dimensional package after reflow disclosed in U.S. Pat. No. 4,499,655;
- FIG. 3shows a schematic flow chart of the method for making a three-dimensional package according to the first embodiment of the present invention
- FIGS. 4 to 17show the schematic views of each step of the method of making a three-dimensional package according to the first embodiment of the present invention
- FIG. 18shows a schematic flow chart of the method for making a three-dimensional package according to the second embodiment of the present invention.
- FIGS. 19 to 21show the schematic views of a part of the steps of the method for making a three-dimensional package according to the second embodiment of the present invention.
- FIG. 22shows a cross-sectional view of the three-dimensional package according to the present invention.
- FIG. 3it shows a schematic flow chart of the method for making a three-dimensional package according to the first embodiment of the present invention.
- FIGS. 4 to 17the schematic views of each step of the method for making a three-dimensional package according to the first embodiment of the present invention are shown.
- a wafer 31is provided.
- the wafer 31has a first surface 311 and a second surface 312 .
- the first surface 311has at least one pad 32 and a protection layer 33 exposing the pad 32 .
- step S 302at least one blind hole 34 is formed in the first surface 311 of the wafer 31 .
- the blind hole 34is disposed beside the pad 32 .
- the blind hole 34can penetrate the pad 32 .
- an isolation layer 35is formed on the side wall of the blind hole 34 .
- a conductive layer 36is formed to cover the pad 32 , the protection layer 33 , and the isolation layer 35 .
- the conductive layer 36is made of Ti, Cu, Cu/Ti alloy, or other metals.
- a dry film 37is formed on the conductive layer 36 .
- the dry film 37has an opening 371 at the position corresponding to the blind hole 34 .
- the blind hole 34is filled with a solder 38 .
- the blind hole 34is filled with the solder 38 by plating.
- the blind hole 34can be filled with the solder 38 by other manners.
- step S 307the dry film 37 is removed, and the conductive layer 36 is patterned.
- a passivation layer 39is formed on the conductive layer 36 to protect the patterned conductive layer 36 .
- the passivation layer 39can be formed by any conventional manners. Moreover, it should be understood that this step is optional.
- step S 309a part of the second surface 312 of the wafer 31 and a part of the isolation layer 35 are removed to expose a part of the conductive layer 36 .
- the second surface 312 of the wafer 31is first ground by means of backside grinding until the second surface 312 and the lower end of the isolation layer 35 are at the same level, i.e., the lower end of the isolation layer 35 is exposed on the second surface 312 .
- the second surface 312 of the wafer 31 and the lower end of the isolation layer 35are etched to expose the lower end of the conductive layer 36 .
- the lower end of the conductive layer 36extends below the second surface 312 of the wafer 31 , as shown in FIG. 13 .
- the second surface 312 of the wafer 31can be directly etched to expose the lower end of the conductive layer 36 , without using the backside grinding method.
- a barrier layer 40is formed on the lower end of the conductive layer 36 , and covers the lower end of the exposed conductive layer 36 .
- the barrier layer 40is Ni, Cr, Cr/Cu alloy, or other metals. It should be understood that this step is optional.
- a lower solder 41is further formed below the barrier layer 40 or the conductive layer 36 and is attached to the barrier layer 40 or the lower end of the exposed conductive layer 36 . It should be understood that this step is also optional.
- step S 311a plurality of the wafers 31 are stacked.
- the conductive layers 36 and the solders 38 of the upper and lower wafers 31are aligned with each other.
- step S 312the reflow process is performed to make the wafers 31 joined by welding the conductive layer 36 and the solder 38 .
- step S 313the stacked wafer 31 is cut to form a plurality of three-dimensional package structures 42 .
- step S 314at least one solder ball 43 is formed below the three-dimensional package structure 42 .
- the solder ball 43is disposed on the lower end of the conductive layer 36 in the lower wafer 31 . It should be understood that this step is optional.
- FIG. 18it shows the schematic flow chart of the method for making a three-dimensional package structure according to the second embodiment of the present invention.
- the steps S 401 to S 410are identical to the steps S 301 to S 310 of the first embodiment.
- the difference between the second embodiment and the first embodimentis described as follows.
- the wafer 31is cut to form a plurality of units 44 , 45 , as shown in FIG. 19 .
- the units 44 , 45are stacked, wherein the conductive layers 36 and the solders 38 of the upper and the lower wafers 31 are aligned with each other, as shown in FIG. 20 .
- step S 413the reflow process is performed to form a plurality of three-dimensional package structures 42 , as shown in FIG. 21 .
- the three-dimensional package structure 42 ( FIG. 21 ) made according to this embodimentis identical to the three-dimensional package structure 42 ( FIG. 17 ) made according to the first embodiment.
- step S 414at least one solder ball 43 is formed below the three-dimensional package structure 42 .
- the solder ball 43is disposed on the lower end of the conductive layer 36 in the lower wafer 31 . It should be understood that this step is optional.
- FIG. 22it shows a cross-sectional view of the three-dimensional package of the present invention.
- the three-dimensional package 5 in this figureis identical to the three-dimensional package 42 in FIGS. 17 and 21 . However, for the convenience of illustration, the identical elements are designated by different reference numbers.
- the three-dimensional package 5comprises a first unit 50 and a second unit 60 .
- the first unit 50comprises a first wafer 51 , at least one first hole 52 , a first isolation layer 53 , a first conductive layer 54 , and a first solder 55 .
- the first wafer 51is a wafer or a chip, and has a first surface 511 and a second surface 512 .
- the first surface 511has at least one first pad 513 and a first protection layer 514 exposing the first pad 513 .
- the first hole 52penetrates the first wafer 51 .
- the first hole 52is disposed beside the first pad 513 .
- the first hole 52can penetrate the first pad 513 .
- the first isolation layer 53is disposed on the side wall of the first hole 52 .
- the first conductive layer 54covers the first pad 513 , a part of the first protection layer 514 , and the first isolation layer 53 .
- the lower end of the first conductive layer 54extends below the lower end of the second surface 512 of the first wafer 51 .
- the first unit 50further comprises a first barrier layer (not shown) covering the lower end of the first conductive layer 54 .
- the first solder 55is disposed inside the first hole 52 , and is electrically connected to the first pad 513 via the first conductive layer 54 .
- a passivation layer(not shown) is further disposed above the first conductive layer 54 and covers the first conductive layer 54 to protect the first conductive layer 54 .
- the second unit 60is stacked above the first unit 50 .
- the second unit 60comprises a second wafer 61 , at least one second hole 62 , a second isolation layer 63 , a second conductive layer 64 , and a second solder 65 .
- the second wafer 61is a wafer or a chip, and has a first surface 611 and a second surface 612 .
- the first surface 611has at least one second pad 613 and a second protection layer 614 exposing the second pad 613 .
- the second hole 62penetrates the second wafer 61 .
- the second hole 62is disposed beside the second pad 613 . However, in other applications, the second hole 62 can penetrate the second pad 613 .
- the second isolation layer 63is dispose on the side wall of the second hole 62 .
- the second conductive layer 64covers the second pad 613 , a part of the second protection layer 614 , and the second isolation layer 63 .
- the lower end of the second conductive layer 64extends below the second surface 612 of the second wafer 61 and contacts the upper end of the first solder 55 .
- the second unit 60further comprises a second barrier layer (not shown) covering the lower end of the second conductive layer 64 .
- the second solder 65is disposed inside the second hole 62 and is electrically connected to the second pad 613 via the second conductive layer 64 .
- a passivation layer(not shown) is disposed above the second conductive layer 64 and covers the second conductive layer 64 to protect the second conductive layer 64 .
- the three-dimensional package structure 5further comprises at least one solder ball 43 disposed on the lower end of the first conductive layer 54 .
- the lower end of the second conductive layer 64is inserted into the first solder 55 , so as to enhance the joint between the second conductive layer 64 and the first solder 55 .
- the first hole 52 and the second hole 62can be designed as a taper shape to enhance the foregoing joint.
- the lower end of the second conductive layer 64is inserted into the first solder 55 , such that the overall height of the three-dimensional package 5 after joining can be effectively reduced.
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a package and a method of making the same, and more particularly to a three-dimensional package and a method of making the same.
- 2. Description of the Related Art
- Referring to
FIG. 1 , it shows a schematic view of a three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655. The conventional three-dimensional package 1 comprises afirst unit 10 and asecond unit 20. Thefirst unit 10 comprises afirst wafer 11, at least onefirst hole 12, a firstconductive layer 13 and afirst solder 14. Thefirst wafer 11 has afirst surface 111 and asecond surface 112. Thefirst surface 111 has at least one first pad (not shown) and afirst protection layer 113 exposing the first pad. Thefirst hole 12 penetrates thefirst wafer 11. The firstconductive layer 13 is disposed on the side wall of thefirst hole 12 and covers the first pad and thefirst protection layer 113. Thefirst solder 14 is disposed in thefirst hole 12 and is electrically connected to the first pad via the firstconductive layer 13. The upper end of thefirst solder 14 extends above thefirst surface 111 of thefirst wafer 11, and the lower end extends below thesecond surface 112 of thefirst wafer 11. - The
second unit 20 is stacked on thefirst unit 10. Thesecond unit 20 comprises asecond wafer 21, at least onesecond hole 22, a secondconductive layer 23 and asecond solder 24. Thesecond wafer 21 has afirst surface 211 and asecond surface 212. Thefirst surface 211 has at least one second pad (not shown) and asecond protection layer 213 exposing the second pad. Thesecond hole 22 penetrates thesecond wafer 21. The secondconductive layer 23 is disposed on the side wall of thesecond hole 22 and covers the second pad and thesecond protection layer 213. Thesecond solder 24 is disposed in thesecond hole 22 and is electrically connected to the second pad via the secondconductive layer 23. The upper end of thesecond solder 24 extends above thefirst surface 211 of thesecond wafer 21, and the lower end of thesecond solder 24 extends below thesecond surface 212 of thesecond wafer 21. The lower end of thesecond solder 24 is aligned with and contacts the upper end of thefirst solder 14. After performing a reflow process, thefirst unit 10 and thesecond unit 20 are joined to form a conventional three-dimensional package 1, as shown inFIG. 2 . - In the conventional three-
dimensional package 1, thefirst solder 14 and thesecond solder 24 are formed by disposing thefirst wafer 11 and thesecond wafer 21 above a solder bath, and the solder enter thefirst hole 12 and thesecond hole 22 according to the capillary phenomenon so as to form thefirst solder 14 and thesecond solder 24. - The disadvantages of the conventional three-
dimensional package 1 are described as follows. As thefirst solder 14 and thesecond solder 24 are formed according to the capillary phenomenon, the upper and the lower ends of the foregoing solders are in a hemispherical shape (FIG. 1 ). As such, when thefirst unit 10 and thesecond unit 20 are aligned and joined, alignment becomes more difficult and the joining between thefirst unit 10 and thesecond unit 20 after reflow is not stable. Moreover, after the joining of thefirst unit 10 and thesecond unit 20, the overall height cannot be effectively reduced due to the excess hemispherical solders. - Therefore, it is necessary to provide a three-dimensional package and a method of making the same to solve the above problems.
- The main objective of the invention is to provide a method of making a three-dimensional package, which comprises the following steps:
- (a) providing a wafer, having a first surface and a second surface, the first surface having at least one pad and a protection layer exposing the pad;
- (b) forming at least one blind hole on the first surface of the wafer;
- (c) forming an isolation layer on the side wall of the blind hole;
- (d) forming a conductive layer covering the pad, the protection layer, and the isolation layer;
- (e) forming a dry film on the conductive layer, wherein the dry film has an opening at the position corresponding to the blind hole;
- (f) filling the blind hole with a solder;
- (g) removing the dry film;
- (h) patterning the conductive layer;
- (i) removing a part of the second surface of the wafer and a part is of the isolation layer, so as to expose a part of the conductive layer;
- (j) stacking a plurality of the wafers, so as to perform the reflow process; and
- (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages.
- As such, the lower end of the conductive layer is exposed below the second surface of the wafer. Therefore, during the reflow process after stacking, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional package after joining.
- Another objective of the present invention is to provide a three-dimensional package, which comprises a first unit and a second unit. The first unit comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, and a first solder.
- The first wafer has a first surface and a second surface. The first surface has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The first conductive layer covers the first pad, a part of the first protection layer, and the first isolation layer. The lower end of the first conductive layer extends below the second surface of the first wafer. The first solder is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer.
- The second unit is stacked on the first unit. The second unit comprises a second wafer, at least one second hole, a second isolation layer, a second conductive layer, and a second solder. The second wafer has a first surface and a second surface. The first surface has at least one second pad and a second protection layer exposing the second pad. The second hole penetrates the second wafer. The second isolation layer is disposed on the side wall of the second hole. The second conductive layer covers the second pad, a part of the second protection layer, and the second isolation layer. The lower end of the second conductive layer extends to below the second surface of the second wafer and contacts the upper end of the first solder. The second solder is disposed in the second hole and is electrically connected to the second pad via the second conductive layer.
FIG. 1 shows a schematic view of the three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655;FIG. 2 shows a schematic view of the three-dimensional package after reflow disclosed in U.S. Pat. No. 4,499,655;FIG. 3 shows a schematic flow chart of the method for making a three-dimensional package according to the first embodiment of the present invention;FIGS. 4 to 17 show the schematic views of each step of the method of making a three-dimensional package according to the first embodiment of the present invention;FIG. 18 shows a schematic flow chart of the method for making a three-dimensional package according to the second embodiment of the present invention;FIGS. 19 to 21 show the schematic views of a part of the steps of the method for making a three-dimensional package according to the second embodiment of the present invention; andFIG. 22 shows a cross-sectional view of the three-dimensional package according to the present invention.- Referring to
FIG. 3 , it shows a schematic flow chart of the method for making a three-dimensional package according to the first embodiment of the present invention. Referring toFIGS. 4 to 17 , the schematic views of each step of the method for making a three-dimensional package according to the first embodiment of the present invention are shown. First, referring toFIGS. 3 and 4 , as shown in step S301, awafer 31 is provided. Thewafer 31 has afirst surface 311 and asecond surface 312. Thefirst surface 311 has at least onepad 32 and aprotection layer 33 exposing thepad 32. - Then, referring to
FIGS. 3 and 5 , as shown in step S302, at least oneblind hole 34 is formed in thefirst surface 311 of thewafer 31. In the embodiment, theblind hole 34 is disposed beside thepad 32. However, in other applications, theblind hole 34 can penetrate thepad 32. - Next, referring to
FIGS. 3 and 6 , as shown in step S303, anisolation layer 35 is formed on the side wall of theblind hole 34. - Afterward, referring to
FIGS. 3 and 7 , as shown in step S304, aconductive layer 36 is formed to cover thepad 32, theprotection layer 33, and theisolation layer 35. Theconductive layer 36 is made of Ti, Cu, Cu/Ti alloy, or other metals. - Then, referring to
FIGS. 3 and 8 , as shown in step S305, adry film 37 is formed on theconductive layer 36. Thedry film 37 has anopening 371 at the position corresponding to theblind hole 34. - After that, referring to
FIGS. 3 and 9 , preferably, as shown in step S306, theblind hole 34 is filled with asolder 38. In the embodiment, theblind hole 34 is filled with thesolder 38 by plating. However, it should be understood that theblind hole 34 can be filled with thesolder 38 by other manners. - Then, referring to
FIGS. 3 and 10 , as shown in step S307, thedry film 37 is removed, and theconductive layer 36 is patterned. - Afterward, referring to
FIGS. 3 and 11 , preferably, as shown in step S308, apassivation layer 39 is formed on theconductive layer 36 to protect the patternedconductive layer 36. Thepassivation layer 39 can be formed by any conventional manners. Moreover, it should be understood that this step is optional. - Then, as shown in step S309, a part of the
second surface 312 of thewafer 31 and a part of theisolation layer 35 are removed to expose a part of theconductive layer 36. Referring toFIG. 12 , in the present embodiment, thesecond surface 312 of thewafer 31 is first ground by means of backside grinding until thesecond surface 312 and the lower end of theisolation layer 35 are at the same level, i.e., the lower end of theisolation layer 35 is exposed on thesecond surface 312. Then, thesecond surface 312 of thewafer 31 and the lower end of theisolation layer 35 are etched to expose the lower end of theconductive layer 36. At this moment, the lower end of theconductive layer 36 extends below thesecond surface 312 of thewafer 31, as shown inFIG. 13 . However, it should be understood that in other applications, thesecond surface 312 of thewafer 31 can be directly etched to expose the lower end of theconductive layer 36, without using the backside grinding method. - Afterward, referring to
FIGS. 3 and 14 , preferably, as shown in step S310, abarrier layer 40 is formed on the lower end of theconductive layer 36, and covers the lower end of the exposedconductive layer 36. Thebarrier layer 40 is Ni, Cr, Cr/Cu alloy, or other metals. It should be understood that this step is optional. Moreover, preferably, alower solder 41 is further formed below thebarrier layer 40 or theconductive layer 36 and is attached to thebarrier layer 40 or the lower end of the exposedconductive layer 36. It should be understood that this step is also optional. - Next, referring to
FIGS. 3 and 15 , as shown in step S311, a plurality of thewafers 31 are stacked. Theconductive layers 36 and thesolders 38 of the upper andlower wafers 31 are aligned with each other. - Then, referring to
FIGS. 3 and 16 , as shown in step S312, the reflow process is performed to make thewafers 31 joined by welding theconductive layer 36 and thesolder 38. - Finally, referring to
FIGS. 3 and 17 , as shown in step S313, the stackedwafer 31 is cut to form a plurality of three-dimensional package structures 42. Preferably, as shown in step S314, at least onesolder ball 43 is formed below the three-dimensional package structure 42. Thesolder ball 43 is disposed on the lower end of theconductive layer 36 in thelower wafer 31. It should be understood that this step is optional. - Referring to
FIG. 18 , it shows the schematic flow chart of the method for making a three-dimensional package structure according to the second embodiment of the present invention. The steps S401 to S410 are identical to the steps S301 to S310 of the first embodiment. The difference between the second embodiment and the first embodiment is described as follows. In the step S411 of the present embodiment, thewafer 31 is cut to form a plurality ofunits FIG. 19 . Then, in step S412, theunits conductive layers 36 and thesolders 38 of the upper and thelower wafers 31 are aligned with each other, as shown inFIG. 20 . Finally, in step S413, the reflow process is performed to form a plurality of three-dimensional package structures 42, as shown inFIG. 21 . The three-dimensional package structure42 (FIG. 21 ) made according to this embodiment is identical to the three-dimensional package structure42 (FIG. 17 ) made according to the first embodiment. - Preferably, in step S414, at least one
solder ball 43 is formed below the three-dimensional package structure 42. Thesolder ball 43 is disposed on the lower end of theconductive layer 36 in thelower wafer 31. It should be understood that this step is optional. - Referring to
FIG. 22 , it shows a cross-sectional view of the three-dimensional package of the present invention. The three-dimensional package 5 in this figure is identical to the three-dimensional package 42 inFIGS. 17 and 21 . However, for the convenience of illustration, the identical elements are designated by different reference numbers. The three-dimensional package 5 comprises afirst unit 50 and asecond unit 60. Thefirst unit 50 comprises afirst wafer 51, at least onefirst hole 52, afirst isolation layer 53, a firstconductive layer 54, and afirst solder 55. - The
first wafer 51 is a wafer or a chip, and has afirst surface 511 and asecond surface 512. Thefirst surface 511 has at least onefirst pad 513 and a first protection layer514 exposing thefirst pad 513. Thefirst hole 52 penetrates thefirst wafer 51. In the present embodiment, thefirst hole 52 is disposed beside thefirst pad 513. However, in other applications, thefirst hole 52 can penetrate thefirst pad 513. - The
first isolation layer 53 is disposed on the side wall of thefirst hole 52. The firstconductive layer 54 covers thefirst pad 513, a part of the first protection layer514, and thefirst isolation layer 53. The lower end of the firstconductive layer 54 extends below the lower end of thesecond surface 512 of thefirst wafer 51. Preferably, thefirst unit 50 further comprises a first barrier layer (not shown) covering the lower end of the firstconductive layer 54. - The
first solder 55 is disposed inside thefirst hole 52, and is electrically connected to thefirst pad 513 via the firstconductive layer 54. Preferably, a passivation layer (not shown) is further disposed above the firstconductive layer 54 and covers the firstconductive layer 54 to protect the firstconductive layer 54. - The
second unit 60 is stacked above thefirst unit 50. Thesecond unit 60 comprises asecond wafer 61, at least onesecond hole 62, asecond isolation layer 63, a secondconductive layer 64, and asecond solder 65. Thesecond wafer 61 is a wafer or a chip, and has a first surface611 and a second surface612. The first surface611 has at least onesecond pad 613 and asecond protection layer 614 exposing thesecond pad 613. Thesecond hole 62 penetrates thesecond wafer 61. In the present embodiment, thesecond hole 62 is disposed beside thesecond pad 613. However, in other applications, thesecond hole 62 can penetrate thesecond pad 613. - The
second isolation layer 63 is dispose on the side wall of thesecond hole 62. The secondconductive layer 64 covers thesecond pad 613, a part of thesecond protection layer 614, and thesecond isolation layer 63. The lower end of the secondconductive layer 64 extends below the second surface612 of thesecond wafer 61 and contacts the upper end of thefirst solder 55. Preferably, thesecond unit 60 further comprises a second barrier layer (not shown) covering the lower end of the secondconductive layer 64. - The
second solder 65 is disposed inside thesecond hole 62 and is electrically connected to thesecond pad 613 via the secondconductive layer 64. Preferably, a passivation layer (not shown) is disposed above the secondconductive layer 64 and covers the secondconductive layer 64 to protect the secondconductive layer 64. - Preferably, the three-
dimensional package structure 5 further comprises at least onesolder ball 43 disposed on the lower end of the firstconductive layer 54. - In the three-
dimensional package structure 5, as the lower end of the secondconductive layer 64 is exposed below the second surface612 of thesecond unit 60, during the reflow process, the lower end of the secondconductive layer 64 is inserted into thefirst solder 55, so as to enhance the joint between the secondconductive layer 64 and thefirst solder 55. Further, thefirst hole 52 and thesecond hole 62 can be designed as a taper shape to enhance the foregoing joint. Moreover, the lower end of the secondconductive layer 64 is inserted into thefirst solder 55, such that the overall height of the three-dimensional package 5 after joining can be effectively reduced. - While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope as defined in the appended claims.
Claims (8)
1. A three-dimensional package, comprising:
a first unit, comprising:
a first wafer, having a first surface and a second surface, the first surface having at least one first pad and a first protection layer exposing the first pad;
at least one first hole, penetrating the first wafer;
a first isolation layer, disposed on the side wall of the first hole;
a first conductive layer, covering the first pad, a part of the first protection layer, and the first isolation layer, wherein the lower end of the first conductive layer extends below the second surface of the first wafer; and
a first solder, disposed in the first hole and electrically connected to the first pad via the first conductive layer; and
a second unit stacked on the first unit, comprising:
a second wafer, having a first surface and a second surface, wherein the first surface has at least one second pad and a second protection layer exposing the second pad;
at least one second hole penetrating the second wafer;
a second isolation layer, disposed on the side wall of the second hole;
a second conductive layer, covering the second pad, a part of the second protection layer, and the second isolation layer, wherein the lower end of the second conductive layer extends to below the second surface of the second wafer and contacts the upper end of the first solder, and
a second solder, disposed in the second hole and electrically connected to the second pad via the second conductive layer.
2. The three-dimensional package according toclaim 1 , wherein the first hole penetrates the first pad.
3. The three-dimensional package according toclaim 1 , wherein the second hole penetrates the second pad.
4. The three-dimensional package according toclaim 1 , wherein the first unit further comprises a first passivation layer covering the first conductive layer.
5. The three-dimensional package according toclaim 1 , wherein the second unit further comprises a second passivation layer covering the second conductive layer.
6. The three-dimensional package according toclaim 1 , wherein the first unit further comprises a first barrier layer covering the lower end of the first conductive layer.
7. The three-dimensional package according toclaim 1 , wherein the second unit further comprises a second barrier layer covering the lower end of the second conductive layer.
8. The three-dimensional package according toclaim 1 , further comprising at least one solder ball disposed at the lower end of the first conductive layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW095102836 | 2006-01-25 | ||
| TW095102836ATWI293499B (en) | 2006-01-25 | 2006-01-25 | Three dimensional package and method of making the same |
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| US20070172983A1true US20070172983A1 (en) | 2007-07-26 |
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| US11/645,040Active2028-11-10US7741152B2 (en) | 2006-01-25 | 2006-12-26 | Three-dimensional package and method of making the same |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
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| US11/645,040Active2028-11-10US7741152B2 (en) | 2006-01-25 | 2006-12-26 | Three-dimensional package and method of making the same |
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| TW (1) | TWI293499B (en) |
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| US20100072599A1 (en)* | 2008-09-22 | 2010-03-25 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming a Wafer Level Package with Top and Bottom Solder Bump Interconnection |
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| US9589876B2 (en) | 2008-09-22 | 2017-03-07 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection |
| US20100320591A1 (en)* | 2009-06-19 | 2010-12-23 | Zigmund Ramirez Camacho | Integrated circuit packaging system with contact pads and method of manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI293499B (en) | 2008-02-11 |
| TW200729417A (en) | 2007-08-01 |
| US7741152B2 (en) | 2010-06-22 |
| US20070172984A1 (en) | 2007-07-26 |
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