US20070170440A1

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Publication number: US20070170440A1
Application number: US11/600,860
Authority: US
Inventors: Aaron Partridge; Markus Lutz; Pavan Gupta
Original assignee: Individual
Current assignee: Individual
Priority date: 2006-01-20
Filing date: 2006-11-16
Publication date: 2007-07-26
Also published as: US20210221678A1; US20070170528A1; US20070170438A1; US20240002218A1; US8871551B2; US10450190B2; US20070170529A1; US20070170532A1; US20160167950A1; US20150041928A1; US9758371B2; US20070170530A1; US20070172976A1; US9434608B2; US10099917B2; US9440845B2; US20190055121A1; WO2007087021A2; US11685650B2; US20070170531A1

Abstract

There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or resonator. The fabricating or manufacturing microelectromechanical systems of the present invention, and the systems manufactured thereby, employ wafer bonding encapsulation techniques.

Description

BACKGROUND

There are many inventions described and illustrated herein. The inventions relate to encapsulation electromechanical structures, for example, microelectromechanical and/or nanoelectromechanical structure (collectively hereinafter “microelectromechanical structures”) and devices/systems including same; and more particularly, in one aspect, for fabricating or manufacturing microelectromechanical systems having mechanical structures that are encapsulated using wafer level encapsulation techniques, and devices/systems incorporated same.

Microelectromechanical systems, for example, gyroscopes, resonators and accelerometers, utilize micromachining techniques (i.e., lithographic and other precision fabrication techniques) to reduce mechanical components to a scale that is generally comparable to microelectronics. Microelectromechanical systems typically include a mechanical structure fabricated from or on, for example, a silicon substrate using micromachining techniques.

The mechanical structures are typically sealed in a chamber. The delicate mechanical structure may be sealed in, for example, a hermetically sealed metal or ceramic container or bonded to a semiconductor or glass-like substrate having a chamber to house, accommodate or cover the mechanical structure. In the context of the hermetically sealed metal or ceramic container, the substrate on, or in which, the mechanical structure resides may be disposed in and affixed to the metal or ceramic container. The hermetically sealed metal or ceramic container often also serves as a primary package as well.

In the context of the semiconductor or glass-like substrate packaging technique, the substrate of the mechanical structure may be bonded to another substrate (i.e., a “cover” wafer) whereby the bonded substrates form a chamber within which the mechanical structure resides. In this way, the operating environment of the mechanical structure may be controlled and the structure itself protected from, for example, inadvertent contact.

SUMMARY OF THE INVENTIONS

There are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.

In one aspect, the present inventions are directed to a microelectromechanical device comprising a first substrate, a chamber, and a microelectromechanical structure, wherein the microelectromechanical structure is (i) formed from a portion of the first substrate and (ii) at least partially disposed in the chamber. In addition, in this aspect, the microelectromechanical device further includes a second substrate, bonded to the first substrate, wherein a surface of the second substrate forms a wall of the chamber, as well as a contact. The contact includes (1) a first portion of the contact is (i) formed from a portion of the first substrate and (ii) at least a portion thereof is disposed outside the chamber, and (2) a second portion of the contact is formed from a portion of the second substrate.

In one embodiment, the second substrate includes polycrystalline silicon, porous polycrystalline silicon, amorphous silicon, silicon carbide, silicon/germanium, germanium, or gallium arsenide. The first substrate may include polycrystalline silicon, porous polycrystalline silicon, amorphous silicon, silicon carbide, silicon/germanium, germanium, or gallium arsenide.

In addition, in one embodiment, the first portion of the contact is a semiconductor material having a first conductivity, the second substrate is a semiconductor material having a second conductivity, and the second portion of the contact is a semiconductor material having the first conductivity. Notably, the second portion of the contact may be a polycrystalline or monocrystalline silicon that is counterdoped to include the first conductivity.

The microelectromechanical device may further include a trench, disposed in the second substrate and around at least a portion of the second portion of the contact. The trench may include a first material (for example, an insulation material) disposed therein to electrically isolate the second portion of the contact from the second substrate.

Notably, the first substrate is a semiconductor on insulator substrate.

In another principle aspect, the present inventions are directed to a microelectromechanical device comprising a first substrate, a second substrate, wherein the second substrate is bonded to the first substrate, a chamber, and a microelectromechanical structure, wherein the microelectromechanical structure is (i) formed from a portion of the second substrate and (ii) at least partially disposed in the chamber. The microelectromechanical device may further include a third substrate, bonded to the second substrate, wherein a surface of the third substrate forms a wall of the chamber. The microelectromechanical device may also include a contact having (1) a first portion of the contact is (i) formed from a portion of the second substrate and (ii) at least a portion thereof is disposed outside the chamber, and (2) a second portion of the contact is formed from a portion of the third substrate.

The second substrate may include polycrystalline silicon, porous polycrystalline silicon, amorphous silicon, silicon carbide, silicon/germanium, germanium, or gallium arsenide. The third substrate may include polycrystalline silicon, porous polycrystalline silicon, amorphous silicon, silicon carbide, silicon/germanium, germanium, or gallium arsenide.

In one embodiment, the first portion of the contact is a semiconductor material having a first conductivity, the third substrate is a semiconductor material having a second conductivity, and the second portion of the contact is a semiconductor material having the first conductivity. Notably, in one embodiment, the second portion of the contact may be a polycrystalline or monocrystalline silicon that is counterdoped to include the first conductivity.

The microelectromechanical device may further include a trench, disposed in the third substrate and around at least a portion of the second portion of the contact. The trench may include a first material (for example, an insulation material) disposed therein to electrically isolate the second portion of the contact from the third substrate.

The microelectromechanical device may also include an isolation region disposed in the second substrate such that the trench is aligned with and juxtaposed to the isolation region. In this embodiment, the first portion of the contact may be a semiconductor material having a first conductivity, the isolation region may be a semiconductor material having a second conductivity, and the second portion of the contact may be a semiconductor material having the first conductivity. A trench may be included to electrically isolate the second portion of the contact from the second substrate. The trench may include a semiconductor material, disposed therein, having the second conductivity.

In another embodiment, the microelectromechanical device may include an isolation region disposed in the first substrate such that the first portion of the contact is aligned with and juxtaposed to the isolation region.

In yet another embodiment, the microelectromechanical device may include a first isolation region and a second isolation region. The first isolation region may be disposed in the first substrate such that the first portion of the contact is aligned with and juxtaposed to the first isolation region. The second isolation region may be disposed in the second substrate such that the second portion of the contact is aligned with and juxtaposed to the second isolation region. In this embodiment, the first and second portions of the contact may be semiconductor materials having a first conductivity, and the first and second isolation regions may be semiconductor materials having the second conductivity.

The microelectromechanical device of this embodiment may also include a trench, disposed in the third substrate and around at least a portion of the second portion of the contact. The trench may include a first material (for example, an insulator material) disposed therein to electrically isolate the second portion of the contact from the third substrate. The trench may be aligned with and juxtaposed to the second isolation region.

Notably, all forms of bonding, whether now known or later developed, are intended to fall within the scope of the present invention. For example, bonding techniques such as fusion bonding, anodic-like bonding, silicon direct bonding, soldering (for example, eutectic soldering), thermo compression, thermo-sonic bonding, laser bonding and/or glass reflow bonding, and/or combinations thereof.

Moreover, any of the embodiments described and illustrated herein may employ a bonding material and/or a bonding facilitator material (disposed between substrates, for example, the second and third substrates) to, for example, enhance the attachment of or the “seal” between the substrates (for example, the first and second, and/or the second and third), address/compensate for planarity considerations between substrates to be bonded (for example, compensate for differences in planarity between bonded substrates), and/or to reduce and/or minimize differences in thermal expansion (that is materials having different coefficients of thermal expansion) of the substrates and materials therebetween (if any). Such materials may be, for example, solder, metals, frit, adhesives, BPSG, PSG, or SOG, or combinations thereof.

Again, there are many inventions, and aspects of the inventions, described and illustrated herein. This Summary of the Inventions is not exhaustive of the scope of the present inventions. Moreover, this Summary of the Inventions is not intended to be limiting of the inventions and should not be interpreted in that manner. While certain embodiments have been described and/or outlined in this Summary of the Inventions, it should be understood that the present inventions are not limited to such embodiments, description and/or outline, nor are the claims limited in such a manner. Indeed, many others embodiments, which may be different from and/or similar to, the embodiments presented in this Summary, will be apparent from the description, illustrations and claims, which follow. In addition, although various features, attributes and advantages have been described in this Summary of the Inventions and/or are apparent in light thereof, it should be understood that such features, attributes and advantages are not required whether in one, some or all of the embodiments of the present inventions and, indeed, need not be present in any of the embodiments of the present inventions.

BRIEF DESCRIPTION OF THE DRAWINGS

In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present inventions and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated and are within the scope of the present inventions.

FIG. 1A is a block diagram representation of a mechanical structure disposed on a substrate and encapsulated via at least a second substrate;

FIG. 1B is a block diagram representation of a mechanical structure and circuitry, each disposed on one or more substrates and encapsulated via a substrate;

FIG. 2 illustrates a top view of a portion of a mechanical structure of a conventional resonator, including moveable electrode, fixed electrode, and a contact;

FIG. 3 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the first substrate employs an SOI wafer;

FIGS. 4A-4G illustrate cross-sectional views (sectioned along dotted line A-A′ ofFIG. 2) of the fabrication of the mechanical structure ofFIGS. 2 and 3 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 5 illustrates a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2, wherein microelectromechanical system includes electronic or electrical circuitry in conjunction with micromachined mechanical structure ofFIG. 2, in accordance with an exemplary embodiment of the present inventions;

FIGS. 6A-6D illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 5 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIGS. 7A-7C, and8A and8B illustrate cross-sectional views of two exemplary embodiments of the fabrication of the portion of the microelectromechanical system ofFIG. 5 using processing techniques wherein electronic or electrical circuitry (at various stages of completeness) is formed in the second substrate prior to encapsulating the mechanical structure via securing the second substrate to the first substrate;

FIG. 9 illustrates a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2, wherein micromachined mechanical structure ofFIG. 2 includes an isolation trench to electrically isolate the contact, in accordance with an exemplary embodiment of the present inventions;

FIGS. 10A-10I illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 9 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 11 illustrates a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2, wherein micromachined mechanical structure ofFIG. 2 includes isolation regions and an isolation trench (aligned therewith) to electrically isolate the contact, in accordance with an exemplary embodiment of the present inventions;

FIGS. 12A-12J illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 11 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 13A illustrates a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2, wherein micromachined mechanical structure ofFIG. 2 includes isolation regions and an isolation trench (aligned therewith), including an oppositely doped semiconductor (relative to the conductivity ofsecond substrate14b), to electrically isolate the contact, in accordance with an exemplary embodiment of the present inventions;

FIGS. 13B and 13C illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 13A at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 14 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an embodiment of the present inventions wherein the microelectromechanical system employs three substrates;

FIGS. 15A-15H illustrate cross-sectional views (sectioned along dotted line A-A′ ofFIG. 2) of the fabrication of the mechanical structure ofFIGS. 2 and 14 at various stages of a process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 16 illustrates a cross-sectional view of an embodiment of the fabrication of the microelectromechanical system ofFIG. 14 wherein electronic or electrical circuitry (after fabrication) is formed in the third substrate according to certain aspects of the present inventions;

FIG. 17 illustrates a cross-sectional view of an exemplary embodiment of the present inventions of the microelectromechanical system including a plurality of micromachined mechanical structures wherein a first micromachined mechanical structure is formed in the second substrate and a second micromachined mechanical structure is formed in the third substrate wherein a fourth substrate encapsulates one or more of the micromachined mechanical structures according to certain aspects of the present inventions;

FIG. 18 illustrates a cross-sectional view of an exemplary embodiment of the present inventions of the microelectromechanical system including a plurality of micromachined mechanical structures wherein a first micromachined mechanical structure is formed in the second substrate and a second micromachined mechanical structure is formed in the third substrate wherein a fourth substrate encapsulates one or more of the micromachined mechanical structures and includes electronic or electrical circuitry according to certain aspects of the present inventions;

FIG. 19 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates and cavities are formed in the first and third substrates;

FIGS. 20A-20H illustrate cross-sectional views (sectioned along dotted line A-A′ ofFIG. 2) of the fabrication of the mechanical structure ofFIGS. 2 and 19 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 21 illustrates a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2, wherein the first cavity is formed in the second substrate and a second cavity is formed in a third substrate according to certain aspects of the present inventions;

FIG. 22 illustrates a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2, wherein the first and second cavities are formed in the second substrate, according to certain aspects of the present inventions;

FIG. 23 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates and the second and third substrates include the same conductivity types;

FIGS. 24A-24I illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 23 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 25 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates and the first and second substrates include the same conductivity types;

FIGS. 26A-26H illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 25 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 27 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates which include the same conductivity types;

FIGS. 28A-28I illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 27 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 29 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates which include the same conductivity types;

FIGS. 30A-30I illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 29 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIGS. 31A-31D illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 27 at various stages of an exemplary process that employs grinding and/or polishing to provide a desired surface, according to certain aspects of the present inventions;

FIG. 32 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates;

FIGS. 33A-33I illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 32 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 34 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates wherein an insulative layer is disposed between each of the substrates;

FIGS. 35A-35L illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 34 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 36 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates wherein an insulative layer is disposed between two of the substrates;

FIGS. 37A-37I illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 36 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 38 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates wherein an insulative layer is disposed between two of the substrates and isolation trenches and regions electrically isolate the contact;

FIGS. 39A-39K illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 38 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 40 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates wherein an intermediate layer (for example, a native oxide layer) is disposed between two of the substrates;

FIGS. 41A-41H illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 40 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIGS. 42A and 42B are cross-sectional views (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of exemplary embodiments of the present inventions wherein the microelectromechanical system employs three substrates wherein an intermediate layer (for example, a native oxide layer) is disposed (for example, deposited or grown) between two of the substrates;

FIGS. 43A-43K illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical systems ofFIGS. 42A and 42B at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 44 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates and the processing techniques include alternative processing margins;

FIGS. 45A-45I illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 44 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 46A is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates and the processing techniques include alternative processing margins wherein the isolation trenches include an over etch;

FIG. 46B is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates and a selected trench includes alternative processing margins;

FIGS. 47A-47D and48A-48C are cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an embodiment of the present inventions having alternative exemplary processing techniques, flows and orders thereof;

FIGS. 49A-49G,50A-50G and51A-51J are cross-sectional views (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of exemplary embodiments of the present inventions having alternative processing techniques, flows and orders thereof relative to one or more of substrates;

FIG. 52 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates wherein isolation regions are implanted in a cover substrate to electrically isolate the contact;

FIGS. 53A-53H illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 52 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 54 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein the microelectromechanical system employs three substrates wherein isolation regions include an insulation material (for example, a silicon nitride or silicon dioxide);

FIGS. 55A-55K illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 54 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 56 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein a contact area is etched and formed in one of the “cover” substrate to provide for electrical conductivity with the an underlying contact area;

FIGS. 57A-57J illustrate cross-sectional views of an exemplary flow of the fabrication of the portion of the microelectromechanical system ofFIG. 56 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 58 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of an exemplary embodiment of the present inventions wherein bonding material and/or a bonding facilitator material is employed between substrates;

FIGS. 59A-59J illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 58 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIG. 60 is a cross-sectional view (sectioned along dotted line A-A′ ofFIG. 2) of a portion of the moveable electrode, fixed electrode, and the contact ofFIG. 2 of another exemplary embodiment of the present inventions wherein bonding material and/or a bonding facilitator material is employed between substrates;

FIGS. 61A-61K illustrate cross-sectional views of the fabrication of the portion of the microelectromechanical system ofFIG. 58 at various stages of an exemplary process that employs an encapsulation technique according to certain aspects of the present inventions;

FIGS. 62-64 illustrates cross-sectional views of several embodiments of the fabrication of microelectromechanical systems of the present inventions wherein the microelectromechanical systems include electronic or electrical circuitry formed in a substrate, according to certain aspects of the present inventions; and

FIGS.65 and66A-66F are block diagram illustrations of various embodiments of the microelectromechanical systems of the present inventions wherein the microelectromechanical systems includes at least three substrates wherein one or more substrates include one or more micromachined mechanical structures and/or electronic or electrical circuitry, according to certain aspects of the present inventions.

DESCRIPTION OF THE INVENTIONS

There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or resonator The fabricating or manufacturing microelectromechanical systems of the present invention, and the systems manufactured thereby, employ wafer bonding encapsulation techniques.

With reference toFIGS. 1A,1B and2, in one exemplary embodiment,microelectromechanical device10 includes micromachinedmechanical structure12 that is disposed onsubstrate14, for example, a semiconductor, a glass, or an insulator material. Themicroelectromechanical device10 may include electronics or electrical circuitry16 (hereinafter collectively “circuitry16”) to, for example, drivemechanical structure12, sense information frommechanical structure12, process or analyze information generated by, and/or control or monitor the operation of micromachinedmechanical structure12. In addition, circuitry16 (for example, CMOS circuitry) may generate clock signals using, for example, an output signal of micromachinedmechanical structure12, which may be a resonator type electromechanical structure. Under these circumstances,circuitry16 may include frequency and/or phase compensation circuitry (hereinafter “compensation circuitry18”), which receives the output of the resonator and adjusts, compensates, corrects and/or controls the frequency and/or phase of the output of resonator. In this regard, compensation circuitry uses the output of resonator to provide an adjusted, corrected, compensated and/or controlled output having, for example, a desired, selected and/or predetermined frequency and/or phase.

Notably,circuitry16 may include interface circuitry to provide information (from, for example, micromachined mechanical structure12) to an external device (not illustrated), for example, a computer, indicator/display and/or sensor.

With continued reference toFIGS. 1A,1B and2, micromachinedmechanical structure12 may include and/or be fabricated from, for example, materials in column IV of the periodic table, for example silicon, germanium, carbon; also combinations of these, for example silicon germanium, or silicon carbide; also of III-V compounds for example gallium phosphide, aluminum gallium phosphide, or other III-V combinations; also combinations of III, IV, V, or VI materials, for example silicon nitride, silicon oxide, aluminum carbide, or aluminum oxide; also metallic suicides, germanides, and carbides, for example nickel silicide, cobalt silicide, tungsten carbide, or platinum germanium silicide; also doped variations including phosphorus, arsenic, antimony, boron, or aluminum doped silicon or germanium, carbon, or combinations like silicon germanium; also these materials with various crystal structures, including single crystalline, polycrystalline, nanocrystalline, or amorphous; also with combinations of crystal structures, for instance with regions of single crystalline and polycrystalline structure (whether doped or undoped).

As mentioned above, micromachinedmechanical structure12 illustrated inFIG. 2 may be a portion of an accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or resonator. The micromachinedmechanical structure12 may also include mechanical structures of a plurality of transducers or sensors including one or more accelerometers, gyroscopes, pressure sensors, tactile sensors and temperature sensors. In the illustrated embodiment, micromachinedmechanical structure12 includemoveable electrode18.

With continued reference toFIG. 2, micromachinedmechanical structure12 may also includecontact20 disposed on or insubstrate14a. Thecontact20 may provide an electrical path between micromachinedmechanical structure12 andcircuitry16 and/or an external device (not illustrated). Thecontact20 may include and/or be fabricated from, for example, a semiconductor or conductive material, including, for example, silicon, (whether doped or undoped), germanium, silicon/germanium, silicon carbide, and gallium arsenide, and combinations and/or permutations thereof. Notably, micromachinedmechanical structure12 andcircuitry16 may includemultiple contacts20.

In one embodiment, the present inventions employ two or more substrates to form and encapsulate micromachinedmechanical structure12. For example, with reference toFIG. 3, in one embodiment,microelectromechanical system10 includes semiconductor on insulator (“SOI”)substrate14aandcover substrate14b.Briefly, by way of overview, in this embodiment, micromachined mechanical structure12 (includingmoveable electrode18 and contact20) is formed in or onSOI substrate14aand encapsulated viacover substrate14b.In this regard, micromachinedmechanical structure12 is formed in the semiconductor portion ofSOI substrate14athat resides on the insulator portion ofSOI substrate14a.Thereafter,substrate14bis secured (for example, bonded) to the exposed surface of the semiconductor portion ofSOI substrate14ato encapsulate micromachinedmechanical structure12.

In particular, with reference toFIG. 4A,microelectromechanical system10 is formed in or onSOI substrate14a.TheSOI substrate14amay includefirst substrate layer22a(for example, a semiconductor (such as silicon), glass or sapphire),insulation layer22b(for example, a silicon dioxide or silicon nitride layer) andfirst semiconductor layer22c(for example, a materials in column IV of the periodic table, for example silicon, germanium, carbon, as well as combinations of such materials, for example silicon germanium, or silicon carbide). In one embodiment,SOI substrate14ais a SIMOX wafer. WhereSOI substrate36 is a SIMOX wafer, such wafer may be fabricated using well-known techniques including those disclosed, mentioned or referenced in U.S. Pat. Nos. 5,053,627; 5,080,730; 5,196,355; 5,288,650; 6,248,642; 6,417,078; 6,423,975; and 6,433,342 and U.S. Published Patent Applications 2002/0081824 and 2002/0123211, the contents of which are hereby incorporated by reference.

In another embodiment,SOI substrate14amay be a conventional SOI wafer having a relativelythin semiconductor layer22c.In this regard,SOI substrate36 having a relativelythin semiconductor layer22cmay be fabricated using a bulk silicon wafer which is implanted and oxidized by oxygen to thereby form a relatively thinsilicon dioxide layer22bon amonocrystalline wafer surface22a.Thereafter, another wafer (illustrated aslayer22c) is bonded to layer22b.In this exemplary embodiment,semiconductor layer22c(i.e., monocrystalline silicon) is disposed oninsulation layer22b(i.e. silicon dioxide), having a thickness of approximately 350 nm, which is disposed on afirst substrate layer22a(for example, monocrystalline silicon), having a thickness of approximately 190 nm.

Notably, all techniques for providing or fabricatingSOI substrate14a,whether now known or later developed, are intended to be within the scope of the present inventions.

With reference toFIGS. 4A and 4B, an exemplary method of fabricating or forming micromachinedmechanical structure12 according to this embodiment of the present inventions may begin with formingfirst cavity24 insemiconductor layer22cusing well-known lithographic and etching techniques. In this way, a selected portion ofsemiconductor layer22c(for example, 1 μm) is removed to form first cavity24(which forms a portion of the chamber in which the mechanical structure, for example,moveable electrode18, resides).

With reference toFIGS. 4C and 4D, thereafter,moveable electrode18 and contact area26 are formed insemiconductor layer22candmoveable electrode18 is “released” frominsulation layer22b.In this regard, trenches28a-care formed insemiconductor layer22cto definemoveable electrode18 and contact area26 therefrom. (See,FIG. 4C). The trenches28a-cmay be formed using well-known deposition and lithographic techniques. Notably, all techniques for forming or fabricating trenches28a-c,whether now known or later developed, are intended to be within the scope of the present inventions.

Aftermoveable electrode18 is defined via

trenches

28band28c,

moveable electrode

18 may be “released” by etching portions ofinsulation layer22bthat are disposed undermoveable electrode18. For example, in one embodiment, whereinsulation layer22bis comprised of silicon dioxide, selected portions may be removed/etched using well-known wet etching techniques and buffered HF mixtures (i.e., a buffered oxide etch) or well-known vapor etching techniques using vapor HF. The

trenches

28band28c,in addition to defining the features ofmoveable electrode18, may also permit etching and/or removal of at least selected portions ofinsulation layer22bthereby providing a void orcavity30 beneathmoveable electrode18. (See,FIG. 4D). Proper design of mechanical structures12 (and in particular moveable electrode18) and control of the HF etching process parameters may permitinsulation layer22bto be sufficiently removed or etched to releasemoveable electrode18 and permit proper operation of micromachinedmechanical structure12 andmicroelectromechanical system10. Notably,

cavities

24 and30 form the chamber in which the mechanical structure, for example,moveable electrode18, resides.

With reference toFIG. 4E,second substrate14bmay be fixed to the exposed portion(s) ofsemiconductor layer22c.Thesecond substrate14bmay be secured to the exposed portion(s) ofsemiconductor layer22cusing, for example, well-known bonding techniques such as fusion bonding, anodic-like bonding and/or silicon direct bonding. Other bonding technologies are suitable including soldering (for example, eutectic soldering), thermo compression bonding, thermo-sonic bonding, laser bonding and/or glass reflow, and/or combinations thereof. Indeed, all forms of bonding, whether now known or later developed, are intended to fall within the scope of the present invention.

In conjunction with securingsecond substrate14bto the exposed portion(s) ofsemiconductor layer22c,the atmosphere (including its characteristics) in whichmoveable electrode18 operates may also be defined. In this regard, the chamber in which themoveable electrode18 reside may be defined whensecond substrate14bis secured and/or fixed to the exposed portion(s) ofsemiconductor layer22cor after further processing (for example, an annealing step may be employed to adjust the pressure). Notably, all techniques of defining the atmosphere, including the pressure thereof, during the process of securingsecond substrate14btosemiconductor layer22c,whether now known or later developed, are intended to be within the scope of the present inventions.

For example,second substrate14bmay be secured to the exposed portion(s) ofsemiconductor layer22cin a nitrogen, oxygen and/or inert gas environment (for example, helium). The pressure of the fluid (gas or vapor) may be selected, defined and/or controlled to provide a suitable and/or predetermined pressure of the fluid in the chamber immediately after fixingsubstrate14bto the exposed portion(s) ofsemiconductor layer22c(in order to avoid damaging portions of micromachined mechanical structure12), after one or more subsequent processing steps (for example, an annealing step) and/or after completion of micromachinedmechanical structure12 and/ormicroelectromechanical system10.

Notably, the gas(es) employed during these processes may provide predetermined reactions (for example, oxygen molecules may react with silicon to provide a silicon oxide). All such techniques are intended to fall within the scope of the present inventions.

Thesecond substrate14bmay be formed from any material now known or later developed. In a preferred embodiment,second substrate14bincludes or is formed from, for example, materials in column IV of the periodic table, for example silicon, germanium, carbon; also combinations of these, for example silicon germanium, or silicon carbide; also of III-V compounds for example gallium phosphide, aluminum gallium phosphide, or other II-V combinations; also combinations of II, IV, V, or VI materials, for example silicon nitride, silicon oxide, aluminum carbide, or aluminum oxide; also metallic silicides, germanides, and carbides, for example nickel silicide, cobalt silicide, tungsten carbide, or platinum germanium silicide; also doped variations including phosphorus, arsenic, antimony, boron, or aluminum doped silicon or germanium, carbon, or combinations like silicon germanium; also these materials with various crystal structures, including single crystalline, polycrystalline, nanocrystalline, or amorphous; also with combinations of crystal structures, for instance with regions of single crystalline and polycrystalline structure (whether doped or undoped).

Before or aftersecond substrate14bis secured to the exposed portion(s) ofsemiconductor layer22c,

contact area

26bmay be formed in a portion ofsecond substrate14bto be aligned with, connect to or overliecontact area26ain order to provide suitable, desired and/or predetermined electrical conductivity (for example, N-type or P-type) withcontact area26awhensecond substrate14bis secured tofirst substrate14a.(See,FIG. 4F). Thecontact area26bmay be formed insecond substrate14busing well-known lithographic and doping techniques. In this way,contact area26bmay be a highly doped region ofsecond substrate14bwhich provides enhanced electrical conductivity withcontact area26a.

Notably,contact area26bmay be a counter-doped region or heavily counter-doped region ofsecond substrate14bwhich includes a conductivity that is different from the conductivity of the other portions ofsecond substrate14b.In this way,

contact areas

26aand26bare electrically isolated from the other portions ofsecond substrate14b.Thus, in this embodiment,semiconductor layer22cmay be a first conductivity type (for example, an N-type conductivity which may be provided, for example, via introduction of phosphorous and/or arsenic dopant(s), among others) andsecond substrate14bmay be a second conductivity type (for example, a P-type conductivity which may be provided, for example, via introduction of boron dopant(s), among others). As such,contact area26bmay be a counter-doped region or heavily counter-doped N-type region which provides suitable, desired and/or predetermined electrical conductivity characteristics whensecond substrate14bis secured tofirst substrate14aand

contact areas

26aand26bare in physical and electrical contact.

With reference toFIG. 4G,microelectromechanical system10 may be completed by depositing, forming and/or growinginsulation layer32 and a contact opening may be etched to facilitate electrical contact/connection to contactarea26b,via conductive layer34 (for example, a heavily doped polysilicon, metal (such as aluminum, chromium, gold, silver, molybdenum, platinum, palladium, tungsten, titanium, and/or copper), metal stacks, complex metals and/or complex metal stacks) may then be deposited (and/or formed) to provide the appropriate electrical connection to contact areas26 (which includes, in this example,

contacts areas

26aand26b).

Notably,insulation layer32 and/orconductive layer34 may be formed, grown and/or deposited before or aftersecond substrate14bis secured to the exposed portion(s) ofsemiconductor layer22c.Under these circumstances, whensecond substrate14bis secured tofirst substrate14a,themicroelectromechanical system10 may be completed.

The insulatinglayer32 may be, for example, silicon dioxide, silicon nitride, BPSG, PSG, or SOG, or combinations thereof. It may be advantageous to employ silicon nitride because silicon nitride may be deposited in a more conformal manner than silicon oxide. Moreover, silicon nitride is compatible with CMOS processing, in the event thatmicroelectromechanical system10 includes CMOS integrated circuits.

Notably, prior to formation, deposition and/or growth ofinsulation layer32 and/orconductive layer34, additional micromachinedmechanical structures12 and/or transistors ofcircuitry16 may be formed and/or provided insecond substrate14bor in other substrates that may be fixed tofirst substrate14aand/orsecond substrate14b.In this regard, the exposed surface ofsecond substrate14bmay be a suitable base upon which integrated circuits (for example, CMOS transistors) and/or micromachinedmechanical structures12 may be fabricated on or in. Such integrated circuits may be fabricated using well-known techniques and equipment. For example, with reference toFIG. 5, in one embodiment,transistor regions36, which may be integrated circuits (for example, CMOS transistors) ofcircuitry16, may be provided insecond substrate14b.Thetransistor regions36 may be formed before or aftersecond substrate14bis secured (for example, bonded) tofirst substrate14a.In this regard, with reference toFIG. 6A,transistor implants38 may be formed using well-known lithographic and implant processes, aftersecond substrate14bis secured tofirst substrate14aand concurrently with the formation ofcontact area26b.

Thereafter, conventional transistor processing (for example, formation of gate and gate insulator40) may be employed to complete the transistors ofcircuitry16. (See,FIG. 6B). The “back-end” processing of microelectromechanical system10 (for example, formation, growth and/or deposition ofinsulation layer32 and conductive layer34) may be performed using the same processing techniques as described above. (See, for example,FIGS. 6C and 6D). In this regard,insulation layer32 may be deposited, formed and/or grown and patterned and, thereafter, conductive layer34 (for example, a heavily doped polysilicon, metal (such as aluminum, chromium, gold, silver, molybdenum, platinum, palladium, tungsten, titanium, and/or copper), metal stacks, complex metals and/or complex metal stacks) is deposited and/or formed. In the illustrative embodiments, contact20 is accessed directly by the transistors ofcircuitry16 viaconductive layer34. Here,conductive layer34 may be a low resistance electrical path that is deposited and patterned to facilitate connection of micromachinedmechanical structure12 andcircuitry16.

As noted above, the transistors oftransistor region36 may be formed prior to securingsecond substrate14btofirst substrate14a.(See, for example,FIGS. 7A and 7B). Indeed, all of the “back-end” processing, in addition to formation of the transistors oftransistor region36, may be completed prior to securingsecond substrate14btofirst substrate14a.(See, for example,FIGS. 8A and 8B).

With reference toFIGS. 9,10A-10I,11 and12A-12J, in another embodiment of the present inventions,semiconductor layer22cofSOI substrate14ais the same conductivity assecond substrate14b.In these embodiments, micromachinedmechanical structure12 may include additional features to electrically isolatecontact20. For example, with reference toFIG. 9, in one embodiment, micromachinedmechanical structure12 includes

isolation trenches

42aand42bthat isolates contact20 (and

contact areas

26aand26b) from portions ofsecond substrate14b.The

isolation trenches

42aand42bmay include an insulator material, for example, silicon dioxide or silicon nitride. Indeed, as illustrated, material that formsinsulation layer32 may also be deposited in

isolation trenches

42aand42b.Notably,FIGS. 10A-10I illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 9.

With reference toFIG. 11, in another exemplary embodiment,

isolation regions

44aand44bare deposited and/or implanted into portions ofsemiconductor layer22cofSOI substrate14ain order to facilitate electrical isolation ofcontact20 aftersecond substrate14bis secured or fixed (via, for example, bonding). The

isolation regions

44aand44bmay be any material or structure that insulatescontact20, for example, an insulator material and/or an oppositely doped semiconductor region.FIGS. 12A-12J illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 11 wherein

isolation regions

44aand44bare oppositely doped semiconductor regions and an insulation material is disposed in

isolation trenches

42aand42b.

FIG. 13A illustrates an exemplarymicroelectromechanical system10 wherein the

isolation regions

44aand44bare oppositely doped semiconductor regions (relative to the conductivity ofsecond substrate14b) and a semiconductor, having a conductivity different from the conductivity of the semiconductor ofsecond substrate14b, is disposed (for example using epitaxial deposition techniques) in

isolation trenches

42aand42b.FIGS. 13B and 13C illustrate selected portions of an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 13A.

Notably, the embodiments ofFIGS. 9,11 and13A may also includecircuitry16 disposed insecond substrate14b.The fabrication techniques described above and illustrated inFIGS. 5-8B may be employed in the embodiments ofFIGS. 9 and 11. Indeed, prior to or after formation, deposition and/or growth ofinsulation layer32 and/orconductive layer34, additional micromachinedmechanical structures12 and/or transistors ofcircuitry16 may be formed and/or provided insecond substrate14bor in other substrates that may be fixed tofirst substrate14aand/orsecond substrate14b.For the sake of brevity, those discussions, in connection with the embodiments ofFIGS. 9,11 and13A, will not be repeated.

The present inventions may also employ more than two substrates to form and encapsulate micromachinedmechanical structure12. For example, with reference toFIG. 14, in one embodiment,microelectromechanical system10 includesfirst substrate14a,

second substrate

14bandthird substrate14c.Briefly, by way of overview, in this embodiment, micromachined mechanical structure12 (includingmoveable electrode18 and contact20) is formed insecond substrate14band encapsulated viathird substrate14c.In this regard, micromachinedmechanical structure12 is formed in a portion ofsubstrate14b.Thereafter,substrate14cis secured (for example, bonded) to exposed surface ofsubstrate14bto encapsulate micromachinedmechanical structure12. In this embodiment, the portion ofsubstrate14bin which micromachinedmechanical structure12 is formed includes a conductivity that is different from the conductivity of the semiconductor offirst substrate14aandthird substrate14c.

With reference toFIGS. 15A and 15B, an exemplary method of fabricating or forming micromachinedmechanical structure12 according to this embodiment of the present inventions may begin with formingfirst cavity24 infirst substrate14ausing well-known lithographic and etching techniques. In one exemplary embodiment,first cavity24 includes a depth of about 1 μm.

With reference toFIGS. 15C and 15D,second substrate14bmay be fixed tofirst substrate14a.Thesecond substrate14bmay be secured to the exposed portion(s) offirst substrate14ausing, for example, well-known bonding techniques such as fusion bonding, anodic-like bonding and/or silicon direct bonding. As mentioned above, other bonding technologies are suitable including soldering (for example, eutectic soldering), thermo compression bonding, thermo-sonic bonding, laser bonding and/or glass reflow, and/or combinations thereof. Indeed, all forms of bonding, whether now known or later developed, are intended to fall within the scope of the present invention.

Before or after securingsecond substrate14btofirst substrate14a,

second cavity

30 may be formed insecond substrate14b—again using well-known lithographic and etching techniques. In one exemplary embodiment,second cavity30 also includes a depth of about 1 μm. Thereafter, the thickness ofsecond substrate14bmay be adjusted to accommodate further processing. For example,second substrate14bmay be grinded and polished (using, for example, well known chemical mechanical polishing (“CMP”) techniques) to a thickness of between 10 μm-30 μm. Notably,

cavities

Thesecond substrate14bmay be formed from any material now known or later developed. In a preferred embodiment,second substrate14bincludes or is formed from, for example, materials in column IV of the periodic table, for example silicon, germanium, carbon; also combinations of these, for example silicon germanium, or silicon carbide; also of III-V compounds for example gallium phosphide, aluminum gallium phosphide, or other II-V combinations; also combinations of III, IV, V, or VI materials, for example silicon nitride, silicon oxide, aluminum carbide, or aluminum oxide; also metallic silicides, germanides, and carbides, for example nickel silicide, cobalt silicide, tungsten carbide, or platinum germanium silicide; also doped variations including phosphorus, arsenic, antimony, boron, or aluminum doped silicon or germanium, carbon, or combinations like silicon germanium; also these materials with various crystal structures, including single crystalline, polycrystalline, nanocrystalline, or amorphous; also with combinations of crystal structures, for instance with regions of single crystalline and polycrystalline structure (whether doped or undoped).

With reference toFIG. 15E,moveable electrode18 and contact area26 are defined and formed insecond substrate14b.In this regard, trenches28a-care formed insecond substrate14bto definemoveable electrode18 and contact area26 therefrom. (See,FIG. 15E). The trenches28a-cmay be formed using well-known deposition and lithographic techniques. Notably, all techniques for forming or fabricating trenches28a-c,whether now known or later developed, are intended to be within the scope of the present inventions.

Thereafter,third substrate14cmay be fixed to the exposed portion(s) ofsecond substrate14b.(See,FIG. 15F). Thethird substrate14cmay also be secured to the exposed portion(s) ofsecond substrate14busing, for example, well-known bonding techniques such as fusion bonding, anodic-like bonding and/or silicon direct bonding. In conjunction with securingthird substrate14ctosecond substrate14b,the atmosphere (including its characteristics) in whichmoveable electrode18 operates may also be defined—for example, as described above. Notably, all techniques of defining the atmosphere, including the pressure thereof, during the process of securingthird substrate14ctosecond substrate14b,whether now known or later developed, are intended to be within the scope of the present inventions.

Thethird substrate14cmay be formed from any material discussed above relative tosecond substrate14b.For the sake of brevity, such discussions will not be repeated.

Before or afterthird substrate14cis secured tosecond substrate14b,

contact area

26bmay be formed in a portion ofthird substrate14cto be aligned with, connect to or overliecontact area26a.Thecontact area26bmay be a semiconductor region that includes a doping that provides the same conductivity ascontact area26a.In this way, a suitable, desired and/or predetermined electrical conductivity is provided withcontact area26awhenthird substrate14cis secured tosecond substrate14b.(See,FIG. 15G). Thus,contact area26bmay be a highly doped region ofthird substrate14cwhich provides enhanced electrical conductivity withcontact area26a.Thecontact area26bmay be formed inthird substrate14cusing well-known lithographic and doping techniques.

Notably,contact area26bmay be a counter-doped region or heavily counter-doped region ofthird substrate14cwhich includes a conductivity that is different from the conductivity of the other portions ofthird substrate14c.In this way,

contact areas

26aand26bare electrically isolated from the other portions ofthird substrate14c.Thus, in this embodiment,second substrate14bmay be a first conductivity type (for example, an N-type conductivity) andthird substrate14cmay be a second conductivity type (for example, a P-type conductivity). As such,contact area26bmay be a counter-doped region or heavily counter-doped N-type region which provides suitable, desired and/or predetermined electrical conductivity characteristics whenthird substrate14cis secured tosecond substrate14band

contact areas

26aand26bare in physical contact.

With reference toFIG. 15H,microelectromechanical system10 may be completed by depositing, forming and/or growinginsulation layer32 and a contact opening may be etched to facilitate electrical contact/connection to contactarea26b.The conductive layer34 (for example, a heavily doped polysilicon, metal (such as aluminum, chromium, gold, silver, molybdenum, platinum, palladium, tungsten, titanium, and/or copper), metal stacks, complex metals and/or complex metal stacks) may then be deposited to provide the appropriate electrical connection to contact26aand26b.

Notably,insulation layer32 and/orconductive layer34 may be formed, grown and/or deposited before or afterthird substrate14cis secured tosecond substrate14b.Under these circumstances, whenthird substrate14cis secured tosecond substrate14b,themicroelectromechanical system10 may be completed.

As mentioned above with respect to other embodiments of the present inventions, prior to formation, deposition and/or growth ofinsulation layer32 and/orconductive layer34, additional micromachinedmechanical structures12 and/or transistors ofcircuitry16 may be formed and/or provided inthird substrate14cor in other substrates that may be fixed tofirst substrate14aand/orsecond substrate14b.(See, for example,FIGS. 16,17 and18). In this regard, the exposed surface ofthird substrate14cor another substrate disposed thereon may be a suitable base upon which integrated circuits (for example, CMOS transistors) (see,FIG. 16) and/or micromachined mechanical structures12 (see,FIGS. 17 and 18). Such integrated circuits and micromachinedmechanical structures12 may be fabricated using the inventive techniques described herein and/or well-known fabrication techniques and equipment.

For example, with reference toFIG. 16, in one embodiment, transistor regions36 (which may be integrated circuits (for example, CMOS transistors) of circuitry16) may be provided insecond substrate14b.Thetransistor regions36 may be formed before or afterthird substrate14cis secured (for example, bonded) tosecond substrate14b.The fabrication techniques described above and illustrated inFIGS. 5-8B may be employed in the embodiments ofFIG. 14. Indeed, prior to or after formation, deposition and/or growth ofinsulation layer32 and/orconductive layer34, additional micromachinedmechanical structures12 and/or transistors ofcircuitry16 may be formed and/or provided insecond substrate14bor in other substrates that may be fixed tofirst substrate14aand/orsecond substrate14b.For the sake of brevity, those discussions, in connection with the embodiments ofFIG. 15, will not be repeated.

Notably, althoughsecond cavity30 is described and illustrated in the previous embodiment as being formed insecond substrate14b,

second cavity

30 may be formed inthird substrate14c,as illustrated in FIGS.19 and20A-20H. Indeed, a portion ofsecond cavity30 may be formed insecond substrate14band a portion ofsecond cavity30 may be formed inthird substrate14c.

With reference toFIGS. 23-30I, in another embodiment of the present inventions,first substrate14aand/orthird substrate14care/is the same conductivity assecond substrate14b.In these embodiments, micromachinedmechanical structure12 may include additional features to electrically isolatecontact20. For example, with reference toFIG. 23, in one embodiment,second substrate14bis a semiconductor having the same conductivity as the conductivity ofthird substrate14c.In this embodiment, micromachinedmechanical structure12 includes

isolation trenches

42aand42bthat isolates contact20 (and

contact areas

26aand26b) from portions ofthird substrate14c.In this exemplary embodiment, the isolation trenches are aligned with

isolation regions

44aand44bwhich are disposed in or onsecond substrate14b.

The

isolation trenches

42aand42bmay include a material that insulates contact20 (and

contact areas

26aand26b) from portions ofthird substrate14c.In the exemplary embodiment ofFIG. 23, an insulating material, for example, silicon dioxide or silicon nitride, is deposited and/or grown in

isolation trenches

42aand42b.Indeed, as illustrated, material that formsinsulation layer32 may also be deposited in

isolation trenches

42aand42b.Notably,FIGS. 24A-24I illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 23.

As mentioned above,

isolation regions

44aand44bwhich are disposed in or onsecond substrate14b.The

isolation regions

44aand44bmay be any material or structure that insulatescontact20, for example, an insulator material and/or an oppositely doped semiconductor region. In the exemplary embodiment ofFIG. 23,

isolation regions

44aand44bincludes oppositely doped semiconductor material.

With reference toFIG. 25, in another exemplary embodiment,first substrate14ais a semiconductor having the same conductivity as the conductivity ofsecond substrate14b.In this embodiment, micromachinedmechanical structure12 includes anisolation region44 that isolates contact20 (and, in particular,contact area26a) from portions offirst substrate14a.In this exemplary embodiment, theisolation region44 is aligned withcavity24 andtrench28ain order to provide suitable contact isolation. Theisolation region44 may include any material or structure that insulatescontact20, for example, an insulator material and/or an oppositely doped semiconductor region. In the exemplary embodiment ofFIG. 25,

isolation regions

44aand44bincludes oppositely doped semiconductor material. Notably,FIGS. 26A-26H illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 25.

In another exemplary embodiment, first, second and

third substrates

14a,14band14cinclude semiconductor regions having the same conductivity. With reference toFIG. 27, in this embodiment, micromachinedmechanical structure12 includes an

44a,44b,and44c,in combination, electrically isolate contact20 (and, in particular,

contact areas

26aand26b) from contiguous portions offirst substrate14aandthird substrates14c.In this exemplary embodiment, theisolation region44ais aligned withcavity24 andtrench28a,and

isolation trenches

42aand42bare aligned with

isolation regions

44band44c.In this way, contact20 includes suitable contact isolation.

The

isolation trenches

42aand42bmay include any material that insulates contact20 (and

contact areas

26aand26b) from portions ofthird substrate14c.In the exemplary embodiment ofFIG. 27, an oppositely doped semiconductor is deposited and/or grown in

44a,44band44cmay be disposed in or onfirst substrate14aand/orsecond substrate14b.In the exemplary embodiment ofFIG. 27,

isolation regions

44aand44bincludes oppositely doped semiconductor material. Notably,FIGS. 28A-28I illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 23.

As mentioned above,

isolation trenches

42aand42bmay include any material or structure that insulatescontact20, for example, an insulator material and/or an oppositely doped semiconductor region. With reference to FIG.29 and30A-30I,

isolation trenches

42aand42bmay include an insulating material (for example, silicon dioxide or silicon nitride) which is deposited and/or grown in

isolation trenches

42aand42b.As illustrated, material that formsinsulation layer32 may also be deposited in

isolation trenches

42aand42b.In this regard,FIGS. 30A-30I illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 29.

Although not previously illustrated, the present inventions may employ grinding and polishing (using, for example, well known chemical mechanical polishing (“CMP”) techniques at various stages in order to, for example, provide a desired surface and/or thickness. For example, with reference toFIGS. 31A-31D, wherematerial46 is deposited and/or grown in

isolation trenches

42aand42b,the exposed surface may be subjected to grinding and polishing in order to remove a portion of the deposited and/or grown material from the upper surface ofsubstrate14c.With reference toFIG. 31C, after grinding and polishing, the surface is prepared for further processing, for example, “back-end” processing (see, for example,FIG. 31D) or incorporation of additional micromachinedmechanical structures12 and/or transistors ofcircuitry16.

Notably, it may be advantageous to employ isolation trenches42 andisolation regions44 in the embodiments where

substrates

14aand14cinclude a conductivity that is different from the conductivity ofsubstrate14b.(See, for example,FIG. 32 andFIGS. 33A-33I). In this embodiment, isolation trenches42 andisolation regions44 provide additional electrical isolation forcontact20. All permutations and/or combinations of such features are intended to fall within the scope of the present inventions.

The embodiments ofFIGS. 23,25,27,29 and32 may also includecircuitry16 disposed inthird substrate14c.The fabrication techniques described above and illustrated inFIGS. 5-8B may be employed in the embodiments ofFIGS. 23,25,27,29 and32. Indeed, prior to or after formation, deposition and/or growth ofinsulation layer32 and/orconductive layer34, additional micromachinedmechanical structures12 and/or transistors ofcircuitry16 may be formed and/or provided inthird substrate14cor in other substrates that may be fixed tofirst substrate14aand/orsecond substrate14b.For the sake of brevity, those discussions, in connection with the embodiments ofFIGS. 23,25,27,29 and32, will not be repeated.

In another aspect, the present inventions may employ an insulative layer between the substrate in which the micromachinedmechanical structures12 resides and one or more opposing or juxtaposed substrates. Such a configuration may provide certain processing advantages as well as enhance the electrical isolation of the micromachinedmechanical structures12 from one or more opposing or juxtaposed substrates. For example, with reference toFIG. 34, in this exemplary embodiment, micromachined mechanical structure12 (includingmoveable electrode18 and contact20) is formed insecond substrate14band encapsulated viathird substrate14c.In this regard, micromachinedmechanical structure12 is formed in a portion ofsubstrate14b.Thereafter,substrate14cis secured (for example, bonded) to exposed surface ofsubstrate14bto encapsulate micromachinedmechanical structure12. In this embodiment, insulative layers48a(having a thickness of about 1 μm) is disposed and patterned onfirst substrate14ato providecavity24 whensecond substrate14bis disposed thereon. Similarly,insulative layer48b(having a thickness of about 1 μm) is disposed and patterned onsecond substrate14bto providecavity30 whenthird substrate14cis disposed thereon. Notably,

substrate

14a,14band14cmay include the same or different conductivities.

The insulative layers48aand48bmay include, for example, an insulation material (for example, a silicon dioxide, nitride, BPSG, PSG, or SOG, or combinations thereof). It may be advantageous to employ silicon nitride because silicon nitride may be deposited, formed and/or grown in a more conformal manner than silicon oxide. Moreover, silicon nitride is compatible with CMOS processing, in the event thatmicroelectromechanical system10 includes CMOS integrated circuits in one or more ofsubstrates14 thereof.

With reference toFIGS. 35A-35C, an exemplary method of fabricating or forming micromachinedmechanical structure12 according to this embodiment of the present inventions may begin with depositing, forming and/or growinginsulative layer48aonfirst substrate14a.Thereafter,first cavity24 is formed ininsulative layer48ausing well-known lithographic and etching techniques. The thickness and characteristics ofinsulative layer48amay be adjusted to accommodate further processing. For example,insulative layer48amay be polished (using, for example, well known CMP techniques) to provide a smooth planar surface for receipt ofsecond substrate14band provide a desired depth offirst cavity24. In one exemplary embodiment,first cavity24 includes a depth of about 1 μm.

With reference toFIGS. 35D-35G,second substrate14bmay be fixed toinsulative layer48ausing, for example, well-known bonding techniques such as fusion bonding and/or anodic-like bonding. Theinsulative layer48bmay then be deposited, formed and/or grown onfirst substrate14b.Thesecond cavity30 may then be formed ininsulative layer48b—again using well-known lithographic and etching techniques. Thereafter, the thickness and characteristics ofinsulative layer48bmay be adjusted to accommodate further processing. For example,insulative layer48bmay be polished (using, for example, well known CMP techniques) to provide a smooth planar surface for receipt ofsecond substrate14cand provide a desired depth ofsecond cavity30. In one exemplary embodiment,second cavity24 includes a depth of about 1 μm.

In addition to formingsecond cavity24 ininsulative layer48b,

contact trench window

50 is also formed therein. (See,FIG. 35G). In this way, trench28amay be formed concurrently with providing

trenches

28band28cwhich permits definition of contact are26aandmoveable electrode18 simultaneously. The trenches28a-cmay be formed using well-known deposition and lithographic techniques. Notably, all techniques for forming or fabricating trenches28a-c,whether now known or later developed, are intended to be within the scope of the present inventions.

Notably, the first andsecond substrates14bmay be formed from any material now known or later developed. In a preferred embodiment,second substrate14bincludes or is formed from, for example, materials in column IV of the periodic table, for example silicon, germanium, carbon; also combinations of these, for example silicon germanium, or silicon carbide; also of III-V compounds for example gallium phosphide, aluminum gallium phosphide, or other III-V combinations; also combinations of III, IV, V, or VI materials, for example silicon nitride, silicon oxide, aluminum carbide, or aluminum oxide; also metallic silicides, germanides, and carbides, for example nickel silicide, cobalt silicide, tungsten carbide, or platinum germanium silicide; also doped variations including phosphorus, arsenic, antimony, boron, or aluminum doped silicon or germanium, carbon, or combinations like silicon germanium; also these materials with various crystal structures, including single crystalline, polycrystalline, nanocrystalline, or amorphous; also with combinations of crystal structures, for instance with regions of single crystalline and polycrystalline structure (whether doped or undoped).

Thereafter,third substrate14cmay be secured to the exposed portion(s) ofinsulative layer48b.(See,FIG. 35H). Thethird substrate14bmay be secured using, for example, well-known bonding techniques such as fusion bonding and/or anodic-like bonding. In conjunction with securingthird substrate14ctosecond substrate14b,the atmosphere (including its characteristics) in whichmoveable electrode18 operates may also be defined. Notably, all techniques of defining the atmosphere, including the pressure thereof, during the process of securingthird substrate14cto insulativelayer48b,whether now known or later developed, are intended to be within the scope of the present inventions.

Thethird substrate14cmay be formed from any material discussed above relative tofirst substrate14aand/orsecond substrate14b.For the sake of brevity, such discussions will not be repeated.

With reference toFIGS. 35I and 35J, afterthird substrate14cis secured to insulativelayer48b,

contact area

26bmay be formed. In this regard,contact area window52 is formed inthird substrate14candinsulative layer48bto expose a portion ofcontact area26a.Such processing may be performed using well-known lithographic and etching techniques. For example, in one embodiment, wherethird substrate14cis a semiconductor material (for example silicon), a portion of may be removed using reactive ion etching. Thereafter, a portion ofinsulative layer48bmay be removed to exposecontact area26b.In this regard, whereinsulative layer48bis comprised of silicon dioxide, selected portions may be removed/etched using well-known wet etching techniques and buffered HF mixtures (i.e., a buffered oxide etch) or well-known vapor etching techniques using vapor HF.

Thecontact area26bmay be deposited, formed and/or grown incontact area window52. Thecontact area26bmay be an epitaxially deposited semiconductor that includes a doping that provides the same conductivity ascontact area26a.In this way, a suitable, desired and/or predetermined electrical conductivity is provided withcontact area26awhenthird substrate14cis secured tosecond substrate14b.(See,FIG. 35K). Thus,contact area26bmay be a highly doped polysilicon region which provides enhanced electrical conductivity withcontact area26a.

As mentioned above, although not illustrated, the present inventions may employ grinding and polishing (using, for example, well known chemical mechanical polishing (“CMP”) techniques at various stages in order to, for example, provide a desired surface and/or thickness. (See, for example,FIGS. 31A-31D). The formation ofcontact area26bwill likely employ such processing in order to provide the cross-sectional view ofFIG. 35K.

With reference toFIG. 35L,microelectromechanical system10 may be completed by depositing, forming and/or growinginsulation layer32 and a contact opening may be etched to facilitate electrical contact/connection to contactarea26b.The conductive layer34 (for example, a heavily doped polysilicon, metal (such as aluminum, chromium, gold, silver, molybdenum, platinum, palladium, tungsten, titanium, and/or copper), metal stacks, complex metals and/or complex metal stacks) may then be deposited to provide appropriate electrical connection to contact26aand26b.

As mentioned above with respect to other embodiments of the present inventions, prior to formation, deposition and/or growth ofinsulation layer32 and/orconductive layer34, additional micromachinedmechanical structures12 and/or transistors ofcircuitry16 may be formed and/or provided inthird substrate14cor in other substrates that may be fixed tofirst substrate14aand/orsecond substrate14b.In this regard, the exposed surface ofthird substrate14cor another substrate disposed thereon may be a suitable base upon which integrated circuits (for example, CMOS transistors) and/or micromachinedmechanical structures12. Such integrated circuits and micromachinedmechanical structures12 may be fabricated using the inventive techniques described herein and/or well-known fabrication techniques and equipment. For the sake of brevity, those discussions, in connection with the embodiments of FIGS.34 and35A-L, will not be repeated.

With reference to FIGS.36 and37A-37I, in another exemplary embodiment,microelectromechanical system10 may be formed using at least threesubstrates14a-candinsulative layer48adisposed between

substrates

14aand14b.In this embodiment, the portion ofsubstrate14bin which micromachinedmechanical structure12 is formed includes a cavity (like that of previous embodiments) as well as a conductivity that is different from the conductivity of the semiconductor ofthird substrate14c.

Briefly, with reference toFIGS. 35A-35C, an exemplary method of fabricating or forming micromachinedmechanical structure12 according to this embodiment of the present inventions may begin with depositing, forming and/or growinginsulative layer48aonfirst substrate14a.As mentioned above,insulative layer48amay include, for example, an insulation material (for example, a silicon dioxide, nitride, BPSG, PSG, or SOG, or combinations thereof).

Thereafter,first cavity24 is formed ininsulative layer48ausing well-known lithographic and etching techniques. (See,FIG. 37C). The thickness and characteristics ofinsulative layer48amay be adjusted to accommodate further processing. For example,insulative layer48amay be polished (using, for example, well known CMP techniques) to provide a smooth planar surface for receipt ofsecond substrate14band provide a desired depth offirst cavity24. In one exemplary embodiment,first cavity24 includes a depth of about 1 μm.

With reference toFIGS. 37D and 37E,second substrate14bmay be fixed toinsulative layer48ausing, for example, well-known bonding techniques such as fusion bonding and/or anodic-like bonding. Before or after securingsecond substrate14btofirst substrate14a,

second cavity

30 may be formed insecond substrate14busing well-known lithographic and etching techniques. In one exemplary embodiment,second cavity30 also includes a depth of about 1 μm. Thereafter, the thickness ofsecond substrate14bmay be adjusted to accommodate further processing. For example,second substrate14bmay be grinded and polished (using, for example, well known chemical mechanical polishing (“CMP”) techniques) to a thickness of between 10 μm-30 μm.

With reference toFIG. 37F, trenches28a-cmay be formed to definemoveable electrode18 andcontact area26a.The trenches may be formed using well-known deposition and lithographic techniques. Notably, all techniques for forming or fabricating trenches28a-c,whether now known or later developed, are intended to be within the scope of the present inventions.

The first and

second substrates

14aand14bmay be formed from any material discussed above relative tofirst substrate14aand/orsecond substrate14bof other embodiments. For the sake of brevity, such discussions will not be repeated.

Thereafter,third substrate14cmay be secured to the exposed portion(s) ofsecond substrate14b.(See,FIG. 35G). Thethird substrate14bmay be secured using, for example, well-known bonding techniques such as fusion bonding, anodic-like bonding and/or silicon direct bonding. In conjunction with securingthird substrate14ctosecond substrate14b,the atmosphere (including its characteristics) in whichmoveable electrode18 operates may also be defined. Notably, all techniques of defining the atmosphere, including the pressure thereof, during the process of securingthird substrate14ctosecond substrate14b,whether now known or later developed, are intended to be within the scope of the present inventions.

14cmay be formed from any material discussed above relative to first, second and/or third substrates of other embodiments. For the sake of brevity, such discussions will not be repeated.

Before or afterthird substrate14cis secured tosecond substrate14b,

contact area

26bmay be formed in a portion ofthird substrate14cto be aligned with, connect to or overliecontact area26a.Thecontact area26bmay be a semiconductor region that includes a doping that provides the same conductivity ascontact area26a.In this way, a suitable, desired and/or predetermined electrical conductivity is provided withcontact area26awhenthird substrate14cis secured tosecond substrate14b.(See,FIG. 37H). Thus,contact area26bmay be a highly doped region ofthird substrate14cwhich provides enhanced electrical conductivity withcontact area26a.Thecontact area26bmay be formed inthird substrate14cusing well-known lithographic and doping techniques.

Notably,contact area26bmay be a heavily counter-doped region ofthird substrate14cwhich includes a conductivity that is different from the conductivity of the other portions ofthird substrate14c.In this way,

contact areas

26aand26bare electrically isolated from the other portions ofthird substrate14c.Thus, in this embodiment,second substrate14bmay be a first conductivity type (for example, an N-type conductivity) andthird substrate14cmay be a second conductivity type (for example, a P-type conductivity). As such,contact area26bmay be a heavily counter-doped N-type region which provides suitable, desired and/or predetermined electrical conductivity characteristics whenthird substrate14cis secured tosecond substrate14band

contact areas

26aand26bare in physical contact.

With reference toFIG. 37I,microelectromechanical system10 may be completed by depositing, forming and/or growinginsulation layer32 and a contact opening may be etched to facilitate electrical contact/connection to contactarea26b.The conductive layer34 (for example, a heavily doped polysilicon, metal (such as aluminum, chromium, gold, silver, molybdenum, platinum, palladium, tungsten, titanium, and/or copper), metal stacks, complex metals and/or complex metal stacks) may then be deposited to provide appropriate electrical connection to contact26aand26b.

As mentioned above with respect to other embodiments of the present inventions, prior to formation, deposition and/or growth ofinsulation layer32 and/orconductive layer34, additional micromachinedmechanical structures12 and/or transistors ofcircuitry16 may be formed and/or provided inthird substrate14cor in other substrates that may be fixed tofirst substrate14aand/orsecond substrate14b.In this regard, the exposed surface ofthird substrate14cor another substrate disposed thereon may be a suitable base upon which integrated circuits (for example, CMOS transistors) and/or micromachinedmechanical structures12. Such integrated circuits and micromachinedmechanical structures12 may be fabricated using the inventive techniques described herein and/or well-known fabrication techniques and equipment. For the sake of brevity, those discussions, in connection with the embodiments of FIGS.36 and37A-I, will not be repeated.

In this embodiment, the portion ofsubstrate14bin which micromachinedmechanical structure12 is formed includes a conductivity that is the same as the conductivity of the semiconductor ofthird substrate14c.In this embodiment, micromachinedmechanical structure12 includes an

44aand44b,in combination, electrically isolate contact20 (and, in particular,

contact areas

26aand26b) from contiguous portions ofthird substrate14c.In this exemplary embodiment,isolation region44ais aligned withcavity24 andtrench28a,and

isolation trenches

42aand42bare aligned with

isolation regions

44band44c.In this way, contact20 includes suitable contact isolation.

Briefly, with reference toFIGS. 39A-39D and39F, an exemplary method of fabricating or forming micromachinedmechanical structure12 according to this embodiment of the present inventions may be substantially the same as with the previous embodiment. For the sake of brevity those discussions will not be repeated.

With reference toFIG. 39E, in this embodiment,

isolation regions

44aand44bare deposited and/or implanted into portions ofsubstrate14bin order to facilitate electrical isolation ofcontact20 aftersecond substrate14bis secured or fixed (via, for example, bonding). The

isolation regions

44aand44bmay be any material or structure that insulatescontact20, for example, an insulator material and/or an oppositely doped semiconductor region. In the illustrative example,

isolation regions

44aand44bare oppositely doped semiconductor region (relative to the conductivity ofsubstrate14c).

With reference toFIG. 39F, trenches28a-cmay be formed to definemoveable electrode18 andcontact area26a.The trenches may be formed using well-known deposition and lithographic techniques. Notably, all techniques for forming or fabricating trenches28a-c,whether now known or later developed, are intended to be within the scope of the present inventions.

Thereafter,third substrate14cmay be secured to the exposed portion(s) ofsecond substrate14b.(See,FIG. 39G). Thethird substrate14bmay be secured using, for example, well-known bonding techniques such as fusion bonding, anodic-like bonding and/or silicon direct bonding. In conjunction with securingthird substrate14ctosecond substrate14b,the atmosphere (including its characteristics) in whichmoveable electrode18 operates may also be defined. Notably, all techniques of defining the atmosphere, including the pressure thereof, during the process of securingthird substrate14ctosecond substrate14b,whether now known or later developed, are intended to be within the scope of the present inventions.

Thereafter,

isolation trenches

42aand42bare formed in portions ofthird substrate14c.(See,FIG. 39H). The

isolation trenches

42aand42bmay be formed using well-known lithographic and etching techniques. In this exemplary embodiment, the isolation trenches are aligned with

isolation regions

44aand44bwhich are disposed in or onsecond substrate14b.

With reference toFIG. 39I,

isolation trenches

42aand42bmay include a material that insulates contact20 (and

contact areas

26aand26b) from portions ofthird substrate14c.In the exemplary embodiment, an insulating material, for example, silicon dioxide or silicon nitride, is deposited and/or grown in

isolation trenches

42aand42b.Notably,

isolation trenches

42aand42bmay include any material that insulates contact20 (and

contact areas

26aand26b) from portions ofthird substrate14c.

With reference toFIG. 39I-39K,microelectromechanical system10 may be completed by depositing, forming and/or growinginsulation layer32 and a contact opening may be etched to facilitate electrical contact/connection to contactarea26b.The processing may be the same or similar to that described herein with any of the other embodiments. For the sake of brevity, those discussions will not be repeated.

Moreover, as mentioned above with respect to other embodiments of the present inventions, prior to formation, deposition and/or growth ofinsulation layer32 and/orconductive layer34, additional micromachinedmechanical structures12 and/or transistors ofcircuitry16 may be formed and/or provided inthird substrate14cor in other substrates that may be fixed tofirst substrate14aand/orsecond substrate14b.In this regard, the exposed surface ofthird substrate14cor another substrate disposed thereon may be a suitable base upon which integrated circuits (for example, CMOS transistors) and/or micromachinedmechanical structures12. Such integrated circuits and micromachinedmechanical structures12 may be fabricated using the inventive techniques described herein and/or well-known fabrication techniques and equipment. For the sake of brevity, those discussions, in connection with the embodiments of FIGS.38 and39A-K, will not be repeated.

In another embodiment, with reference toFIG. 40, after formation ofcavity18 infirst substrate14a,

intermediate layer

54 is deposited or grown before second substrate148 is secured tofirst substrate14a.In one embodiment,intermediate layer54 may be a native oxide. In another embodiment, a thin insulating layer is deposited. In this way,first substrate14ais electrically isolated fromsecond substrate14b.Thereafter,second substrate14bmay be fixed tointermediate layer54 using, for example, well-known bonding techniques such as fusion bonding and/or anodic-like bonding. Before or after securingsecond substrate14btofirst substrate14a,

second cavity

FIGS. 41A-41H illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 23. For the sake of brevity, the exemplary process flow will not be discussed in detail; reference however, is made to the discussions above.

The embodiment includingintermediate layer54 may be employed in conjunction with any of the embodiments described herein. (See, for example,FIGS. 42A and 42B,43A-43K). For the sake of brevity, the exemplary process flow will not be discussed in detail; reference however, is made to the discussions above.

There are many inventions described and illustrated herein. While certain embodiments, features, materials, configurations, attributes and advantages of the inventions have been described and illustrated, it should be understood that many other, as well as different and/or similar embodiments, features, materials, configurations, attributes, structures and advantages of the present inventions that are apparent from the description, illustration and claims (are possible by one skilled in the art after consideration and/or review of this disclosure). As such, the embodiments, features, materials, configurations, attributes, structures and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different, embodiments, features, materials, configurations, attributes, structures and advantages of the present inventions are within the scope of the present inventions.

Each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of such aspects and/or embodiments. (See, for example,FIGS. 42A and 42B,43A-43K). For the sake of brevity, those permutations and combinations will not be discussed separately herein. As such, the present inventions are not limited to any single aspect or embodiment thereof nor to any combinations and/or permutations of such aspects and/or embodiments.

Notably, it may be advantageous to adjust the alignment and etch processes to enhance electrical isolation of portions of micromachinedmechanical structure12, for example, contact20 (including

contact areas

26aand26b). For example, with reference toFIG. 44,trench28amay be aligned to provide suitable or predetermined overlap of

isolation region

44aand44bas well as include suitable or predetermined over etch intoisolation region44a.Further,isolation region44cmay include dimensions such that whencavity30 is formed, a portion ofisolation region44cis removed. (See,FIGS. 45C and 45D). Moreover, with reference toFIG. 46A,

isolation trenches

42aand42bmay include suitable or predetermined over etch into

isolation regions

44aand44b.Indeed,isolation trench28amay be substantially larger and/or have considerably different tolerances than

trenches

28band28cgiven that the dimensions of the trench are insignificant relative to

trenches

28band28cwhich may largely define the mechanical structure of thesystem10. (See,FIG. 46B). Such processing techniques may be applied to any of the embodiments described and/or illustrated herein.

Further, the processing flows described and illustrated herein are exemplary. These flows, and the order thereof, may be modified. All process flows, and orders thereof, to providemicroelectromechanical system10 and/or micromachinedmechanical structure12, whether now known or later developed, are intended to fall within the scope of the present inventions. For example, there are many techniques to formmoveable electrode18 and contact20 (and inparticular contact area26a). With reference toFIG. 47A-47D, in one embodiment, mask56amay be deposited and patterned. Thereafter,cavity30 may be formed (See,FIGS. 47A and 47B). Thereafter,mask56bmay be deposited and patterned in order to form and definemoveable electrode18 and contact area26 (See,FIGS. 47C and 47D).

Alternatively, with reference toFIGS. 48A-48C, masks56aand56bmay be deposited and patterned. After trenches28a-28care formed,mask56bmay be removed andcavity30 may be formed.

Further,substrates14 may be processed to a predetermined and/or suitable thickness before and/or after other processing during the fabrication ofmicroelectromechanical system10 and/or micromachinedmechanical structure12. For example, with reference toFIGS. 49A-49G, in one embodiment,first substrate14amay be a relatively thick wafer which is grinded (and polished) after

substrates

14band14care secured to a corresponding substrate (for example, bonded) and processed to form, for example, micromachinedmechanical structure12. (Compare, for example,FIGS. 49A-G and49H).

The processing flows described and illustrated with respect tosubstrate14cmay also be modified. For example, with reference toFIGS. 50A-50G, in one embodiment,substrate14cmay be a relatively thick wafer which is grinded (and polished) after secured to a corresponding substrate (for example, bonded). In this exemplary embodiment,substrate14cis grinded and polished after being bonded tosubstrate14b.(Compare, for example,FIGS. 50C and 50D) Thereafter, contact20 may be formed. (See, for example,FIGS. 50E-50G).

Indeed,

substrate

14aand14cmay be processed (for example, grinded and polished) after other processing. (See, for example,FIGS. 51A-51J). Notably, all processing flows with respect tosubstrates14 are intended to fall within the scope of the present invention.

Further, as mentioned above, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of such aspects and/or embodiments. For example, with reference toFIG. 52,microelectromechanical system10 may include

implant regions

58aand58binsubstrate14cto facilitate electrically isolation ofcontact area26bfrom other portions ofsubstrate14c.In this

embodiment implant regions

58aand58bmay be any material or structure that insulatescontact20, for example, an oppositely doped semiconductor region.FIGS. 53A-53H illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 52 wherein

implant regions

58aand58bare oppositely doped semiconductor regions.

Notably,

implant regions

58aand58bmay be employed in any of the embodiments described and illustrated herein. For example, the

implant regions

58aand58bmay be employed in conjunction with or in lieu of

isolation trenches

42aand42b.

In addition, as mentioned above,

isolation regions

44aand44bmay be deposited and/or implanted into portions ofsubstrate14bin order to facilitate electrical isolation ofcontact20 afterthird substrate14c(orsecond substrate14bwhere anSOI substrate14ais employed (see,FIG. 11)) is secured or fixed (via, for example, bonding). The

isolation regions

44aand44bmay be any material or structure that insulatescontact20, for example, an insulation material and/or an oppositely doped semiconductor region.FIGS. 55A-55K illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 54 wherein

isolation regions

44aand44bare insulation material (for example, a silicon nitride or silicon dioxide) and an insulation material is disposed in

isolation trenches

42aand42b.

Further, as an alternative to counter-doping a region insubstrate14cto formcontact area26b,with reference toFIG. 56 andFIGS. 57A-57J,contact area26bmay be formed by providing a “window” insubstrate14c(for example, etching a portion ofsubstrate14cas illustrated inFIG. 57H) and thereafter depositing a suitable material to provide electrical conductivity with theunderlying contact area26a.Notably, the material (for example, a doped polysilicon) which formscontact area26bmay be deposited by epitaxial deposition and thereafter planarized to provide a suitable surface forcontact20 formation. (See, for example,FIGS. 57H and 57I).

As mentioned above, all forms of bonding, whether now known or later developed, are intended to fall within the scope of the present invention. For example, bonding techniques such as fusion bonding, anodic-like bonding, silicon direct bonding, soldering (for example, eutectic soldering), thermo compression, thermo-sonic bonding, laser bonding and/or glass reflow bonding, and/or combinations thereof.

Notably, any of the embodiments described and illustrated herein may employ a bonding material and/or a bonding facilitator material (disposed between substrates, for example, the second and third substrates) to, for example, enhance the attachment of or the “seal” between the substrates (for example, between the first and

second substrates

14aand14b,and/or the second and

third substrates

14band14c), address/compensate for planarity considerations between substrates to be bonded (for example, compensate for differences in planarity between bonded substrates), and/or to reduce and/or minimize differences in thermal expansion (that is materials having different coefficients of thermal expansion) of the substrates and materials therebetween (if any). Such materials may be, for example, solder, metals, frit, adhesives, BPSG, PSG, or SOG, or combinations thereof.

With reference toFIG. 58, in one exemplary embodiment, bonding material orbonding facilitator material60 may be disposed between

substrates

14band14c.Such a configuration may provide certain advantages. For example, in this exemplary embodiment, micromachined mechanical structure12 (includingmoveable electrode18 and contact20) is formed insecond substrate14band encapsulated viathird substrate14c.In this regard, micromachinedmechanical structure12 is formed in a portion ofsubstrate14b.Thereafter,substrate14cis secured (for example, bonded) to exposed surface ofsubstrate14bto encapsulate micromachinedmechanical structure12. In this embodiment, bonding material or bonding facilitator material60 (for example, having a thickness of about 1 μm) is disposed and patterned onsecond substrate14bto providecavity30 whenthird substrate14cis disposed thereon and bonded thereto. Notably,

substrates

14a,14band14cmay include the same or different conductivities.

As mentioned above, bonding material orbonding facilitator material60 may include, for example, solder, metals, frit, adhesives, BPSG, PSG, or SOG, or combinations thereof. It may be advantageous to employ BPSG, PSG, or SOG in order to electrically isolatecontact20 from portions ofsubstrates14band/or14c.Moreover, BPSG, PSG, or SOG is compatible with CMOS processing, in the event thatmicroelectromechanical system10 includes CMOS integrated circuits in one or more ofsubstrates14 thereof.

Notably,FIGS. 59A-59J illustrate an exemplary process flow for fabricatingmicroelectromechanical system10 ofFIG. 58. The process flow may employ a flow which is substantially similar to the process of FIGS.35A-35L—with the exception that bonding material orbonding facilitator material60 is employed (deposited and patterned) in addition to or in lieu ofinsulative layer48bofFIGS. 35E-35L. For the sake of brevity, the discussion will not be repeated here.

An alternative embodiment employing bonding material orbonding facilitator material60, and technique for fabricating such embodiment, is illustrated in FIGS.60 and61A-61K, respectively. In this embodiment, bonding material and/or abonding facilitator material60 is provided prior to formation ofresonator18 andcontact area26a(viacontact area trench28aand

moveable electrode trenches

28band28c). As mentioned above, all process flows, and orders thereof, to providemicroelectromechanical system10 and/or micromachinedmechanical structure12, whether now known or later developed, are intended to fall within the scope of the present inventions.

The embodiments employing bonding material orbonding facilitator material60 may be implemented in any of the embodiments described herein. For example, transistors of a transistor region may be formed prior to securingthird substrate14ctosecond substrate14b.(See, for example,FIGS. 7A and 7B). Indeed, all of the “back-end” processing, in addition to formation of the transistors of transistor region, may be completed prior to securingthird substrate14ctosecond substrate14b.(See, for example,FIGS. 8A and 8B).

Moreover, any of the bonding material or bonding facilitator materials60 (may include, for example, solder, metals, frit, adhesives, BPSG, PSG, or SOG, or combinations thereof) may be implemented between the first and

second substrates

14aand14b,and/or the second and

third substrates

14band14c,and/or any other substrates that are bonded. All such permutations are intended to fall within the scope of the present inventions.

Further, with respect to any of the embodiments described herein,circuitry16 may be integrated in or onsubstrate14, disposed in a separate substrate, and/or in one or more substrates that are connected to substrate14 (for example, in one or more of the encapsulation wafer(s)). (See, for example,FIGS. 62-64). In this regard,microelectromechanical device10 may include micromachinedmechanical structure12 andcircuitry16 as a monolithic-like structure includingmechanical structure12 andcircuitry16 in one substrate.

The micromachinedmechanical structure12 and/orcircuitry16 may also reside on separate, discrete substrates. (See, for example, FIGS.65 and66A-66F). In this regard, in one embodiment, such separate discrete substrate may be bonded to or onsubstrate14, before, during and/or after fabrication of micromachinedmechanical structure12 and/orcircuitry16. (See, for exampleFIGS. 5,6A-6D,7A-7C and8A).

For example, as mentioned above, the electronics or electrical circuitry may be clock alignment circuitry, for example, one or more phase locked loops (PLLs), delay locked loops (DLLs), digital/frequency synthesizer (for example, a direct digital synthesizer (“DDS”), frequency synthesizer, fractional synthesizer and/or numerically controlled oscillator) and/or frequency locked loops (FLLs). In this regard, the output of mechanical structure12 (for example, an microelectromechanical oscillator or microelectromechanical resonator) is employed as a reference input signal (i.e., the reference clock). The PLL, DLL, digital/frequency synthesizer and/or FLL may provide frequency multiplication (i.e., increase the frequency of the output signal of the microelectromechanical oscillator). The PLL, DLL, digital/frequency synthesizer and/or FLL may also provide frequency division (i.e., decrease the frequency of the output signal of the microelectromechanical oscillator). Moreover, the PLL, DLL, digital/frequency synthesizer and/or FLL may also compensate using multiplication and/or division to adjust, correct, compensate and/or control the characteristics (for example, the frequency, phase and/or jitter) of the output signal of the microelectromechanical resonator.

The multiplication or division (and/or phase adjustments) bycompensation circuitry18 may be in fine or coarse increments. For example,compensation circuitry18 may include an integer PLL, a fractional PLL and/or a fine-fractional-N PLL to precisely select, control and/or set the output signal of compensated microelectromechanical oscillator. In this regard, the output of microelectromechanical resonator may be provided to the input of the fractional-N PLL and/or the fine-fractional-N PLL (hereinafter collectively “fractional-N PLL”), which may be pre-set, pre-programmed and/or programmable to provide an output signal having a desired, selected and/or predetermined frequency and/or phase.

Notably, in one embodiment, the parameters, references (for example, frequency and/or phase), values and/or coefficients employed by the compensation circuitry in order to generate and/or provide an adjusted, corrected and/or controlled output having, for example, a desired, selected and/or predetermined frequency and/or phase (i.e., the function of the compensation circuitry), may be externally provided to the compensation circuitry either before or during operation of compensated microelectromechanical oscillator. In this regard, a user or external circuitry/devices/systems may provide information representative of the parameters, references, values and/or coefficients to set, change, enhance and/or optimize the performance of the compensation circuitry and/or compensated microelectromechanical oscillator.

Finally, it should be further noted that while the present inventions will be described in the context of microelectromechanical systems including micromechanical structures or elements, the present inventions are not limited in this regard. Rather, the inventions described herein are applicable to other electromechanical systems including, for example, nanoelectromechanical systems. Thus, the present inventions are pertinent, as mentioned above, to electromechanical systems, for example, gyroscopes, resonators, temperatures sensors, accelerometers and/or other transducers.

The term “depositing” and other forms (i.e., deposit, deposition and deposited) in the claims, means, among other things, depositing, creating, forming and/or growing a layer of material using, for example, a reactor (for example, an epitaxial, a sputtering or a CVD-based reactor (for example, APCVD, LPCVD, or PECVD)).

Further, in the claims, the term “contact” means a conductive region, partially or wholly disposed outside the chamber, for example, the contact area and/or contact via.

It should be further noted that the term “circuit” may mean, among other things, a single component or a multiplicity of components (whether in integrated circuit form or otherwise), which are active and/or passive, and which are coupled together to provide or perform a desired function. The term “circuitry” may mean, among other things, a circuit (whether integrated or otherwise), a group of such circuits, one or more processors, one or more state machines, one or more processors implementing software, or a combination of one or more circuits (whether integrated or otherwise), one or more state machines, one or more processors, and/or one or more processors implementing software. The term “data” may mean, among other things, a current or voltage signal(s) whether in an analog or a digital form.

The embodiments of the inventions described herein may include one or more of the following advantages, among others:

- embodiments presenting mechanically robust encapsulation;
- embodiments presenting clean environment for micromachined mechanical structure12 (and the electrodes thereof);
- embodiments presenting relatively less expensive fabrication in comparison to conventional techniques;
- embodiments presenting relatively smaller footprint in comparison to conventional techniques;
- embodiments presenting one or more surfaces compatible with/for CMOS circuitry/integration;
- embodiments presenting single crystal surfaces (where one or more substrates are single crystal);
- embodiments presenting diffused contacts;
- embodiments eliminating epitaxial depositions;
- embodiments eliminating SOI substrates;
- embodiments presenting improved CMOS compatibility;
- embodiments providing enhanced atmosphere/environment control and characteristics (for example, improved vacuum and lower/no chlorine;
- improved gap control for definition of micromachined mechanical structure;
- embodiments eliminating timed release of moveable electrodes (for example, timed HF (vapor) etch);
- embodiments eliminating oxide stress in substrates;
- embodiments providing enhanced stiction characteristics (for example, less vertical stiction); and
- embodiments eliminating vents in the resonator and the attendant shortcomings of thin film encapsulation.

The above embodiments of the present inventions are merely exemplary embodiments. They are not intended to be exhaustive or to limit the inventions to the precise forms, techniques, materials and/or configurations disclosed. Many modifications and variations are possible in light of the above teaching. It is to be understood that other embodiments may be utilized and operational changes may be made without departing from the scope of the present inventions. As such, the foregoing description of the exemplary embodiments of the inventions has been presented for the purposes of illustration and description. It is intended that the scope of the inventions not be limited to the description above.