US20070164351A1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-8638, filed on Jan. 17, 2006, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• This invention relates to a semiconductor device and method for manufacturing it, for example to a semiconductor memory device including capacitorless DRAM memory cells and a method for manufacturing it.
• 2. Related Art
• A conventional DRAM memory cell of a DRAM includes a capacitor for storing signal charges and a switching transistor (for example, a MOSFET or other FETs) Capacitance of the capacitor required to store signal charges is generally about 30 fF. It is necessary to keep this capacitance of the capacitor of about 30 fF for a DRAM to maintain stable operation, even if the reduced design rule for the DRAM is adopted due to improvement in a degree of cell integration. Therefore, the DRAM memory cell of a conventional DRAM generally have required process improvement for miniaturizing a capacitor, such as thinning an insulating film for a capacitor of stack type or trench type.
• On the contrary, a capacitorless DRAM has been proposed. In a DRAM memory cell of the capacitorless DRAM, a transistor (for example, a MOSFET or other FETs) is necessary, but a capacitor is not required. Therefore, the DRAM memory cell of the capacitorless DRAM may have less possibility to hinder improvement in a degree of cell integration.
• The field of applications of capacitorless DRAM memory cells includes, for example an embedded device with both a logic device and memory device embedded. It is advantageously possible to realize a large-scale embedded device by adopting capacitorless DRAM memory cells while reducing the number of processes for manufacturing memory cells.
• The capacitorless DRAM memory cell has two types of a memory cell, one formed on an SOI substrate and the other formed on a bulk substrate such as a bulk silicon substrate. The memory cell on the SOI substrate is disclosed in Japanese Patent Laid-Open No. 2002-246571, and the memory cell on the bulk substrate such as the bulk silicon substrate is disclosed in “Symposium on VLSI Technology Digest of Technology Paper” by R. Ranica, et al., 2004.
• A typical example of the memory cell on a bulk silicon substrate will be described. On the bulk silicon substrate, there typically exist a gate electrode and a gate oxide film which constitute a MOSFET. In the bulk silicon substrate, there typically exist a p-type well (Pwell) under the MOSFET and an n-type well (Nwell) under the Pwell.
• The Pwell stores holes which are signal charges. The phenomenon that the threshold voltage of a MOSFET varies depending on whether holes exist or not may be used to realize a memory cell. The Pwell includes the Nwell underneath and STIs on sides thereof, since it is necessary, for each MOSFET (each memory cell) to be isolated from neighboring MOSFETs, that Pwell be isolated for each MOSFET (each memory cell).
• An amount of the signal of a memory cell on the bulk silicon substrate δVth is specified in the following expression (1):
• 
  δVth∝Cpn/Cgate   (1).
Where Cgate is the capacitance between the gate electrode and the Pwell, and Cpn is the capacitance between the Pwell and Nwell.
• The amount of the signal6Vth represents difference between the threshold voltage of the MOSFET in the case of existence of holes and that in the case of nonexistence. The capacitance Cpn between the Pwell and Nwell corresponds to depletion layer capacitance of p-n junction formed by the Pwell and Nwell. The expression (1) above may be transformed to the expression (2) which specifies an amount of the signal of a memory cell on an SOI substrate6Vth by substituting the capacitance Cpn between the Pwell and Nwell by capacitance Csoi between the upper portion and lower portion of an SOI insulating film.
• 
  δVth∝Csoi/Cgate   (2).
• Therefore, an increase in the capacitance Csoi may increase6Vth, the amount of the signal of the memory cell on the SOI substrate, and an increase in the capacitance Cpn may increase6Vth, the amount of the signal of the memory cell on the bulk substrate. For the SOI substrate, the capacitance Csoi due to a BOX oxide film (an SOI insulating film) of a thickness of, for example about 25 nm may allow the optimal amount of the signal δVth to be obtained. However, for the bulk substrate, it is difficult to accomplish the optimal amount of signal5Vth, since the amount of the capacitance Cpn is small.
SUMMARY OF THE INVENTION
• An embodiment of the present invention is a semiconductor device including, for example, a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.
• An embodiment of the present invention is a method for manufacturing a semiconductor device including, for example, forming trenches for isolation, on a substrate; forming isolation layers, each of which has an insulating film and a conductive layer, in the trenches; forming a semiconductor layer of a first conductivity type for storing signal charges between the isolation layers so that the semiconductor layer of the first conductivity type is isolated from the conductive layers by the insulating films; forming a semiconductor layer of a second conductivity type under the semiconductor layer of the first conductivity type; and forming a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a side cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention;
• FIG. 2 is a side cross-sectional view of a semiconductor memory device shown as a comparative example;
• FIG. 3 is a schematic diagram illustrative of an amount of a signal and capacitance of the first embodiment;
• FIG. 4 is a schematic diagram illustrative of an amount of a signal and capacitance of the comparative example;
• FIG. 5 shows calculation result of the amount of the signal derived from simulation;
• FIG. 6 shows calculation result of the capacitances derived from simulation;
• FIGS. 7(A) to (E) show side cross-sectional views of the semiconductor memory device of the first embodiment, illustrating a method for manufacturing it;
• FIG. 8 is a side cross-sectional view of a semiconductor memory device according to a second embodiment of the present invention; and
• FIGS. 9(A) to (E) show side cross-sectional views of the semiconductor memory device of the second embodiment, illustrating a method for manufacturing it.
DETAILED DESCRIPTION OF THE INVENTIONFirst Embodiment
• FIG. 1 is a side cross-sectional view of a semiconductor memory device according to a first embodiment. The semiconductor memory device shown inFIG. 1 includes capacitorless DRAM memory cells. A transistor constituting the DRAM memory cell shown inFIG. 1 is an FET (here, a MOSFET).
• The semiconductor memory device shown inFIG. 1 includes asubstrate101, agate oxide film102 constituting the MOSFET, agate electrode103 constituting the MOSFET, a plurality of rows of STIs (Shallow Trench Isolations)104 corresponding to a particular example of isolation layers for isolating MOSFET from one another. Thegate oxide film102 is a particular example of a gate insulator film of the transistor, and thegate electrode103 is a particular example of a gate electrode of the transistor.
• Thesubstrate101 is a bulk substrate (here, a bulk silicon substrate). Thesubstrate101 includes a p-type well (Pwell)111 for storing signal charges corresponding to a particular example of a semiconductor layer of a first conductivity type, an n-type well (Nwell)112 corresponding to a particular example of a semiconductor layer of a second conductivity type, asource region113, and adrain region114. The Pwell111 is formed under the MOSFET for storing signal charges. The Nwell112 is formed under the Pwell111 for isolating Pwell111 for each MOSFET from one another. STIs104 are formed on sides of the Pwell111 for isolating the Pwells for each MOSFET from one another. The Pwell111 is formed between STIs104, and the Nwell112 is formed under STIs104 and the Pwell111. Thegate oxide film102 is formed on the Pwell111, and thegate electrode103 is formed on thegate electroge102.
• The semiconductor memory device inFIG. 1 (the first embodiment) will be compared to a semiconductor memory device inFIG. 2 (a comparative example). Both the semiconductor memory device inFIG. 1 and the semiconductor memory device inFIG. 2 have each ofSTIs104 formed in a trench for eachSTI104 formed on thesubstrate101, however, in the semiconductor memory device inFIG. 1, eachSTI104 has aninsulating film121 and aconductive layer122, and on the contrary, in the semiconductor memory device inFIG. 2, eachSTI104 has only aninsulating film121. InFIG. 1, theinsulating film121 provides most of an outer envelope of theSTI104 and theconductive layer122 provides most of a core portion of theSTI104. InFIG. 1, theinsulating film121 intervenes between theconductive layer122 and the Pwell111, isolating theconductive layer122 from the Pwell111. InFIG. 1, the Pwell111 is opposite through theinsulating film121 to theconductive layer122 and is isolated from theconductive layer122 by theinsulating film121. Therefore, with regard to the semiconductor memory device inFIG. 1, an amount of the signal of a memory cell δVth is specified in the following expression (3), and also, with regard to the semiconductor memory device inFIG. 2, that is specified in the following expression (4):
• 
  δVth∝(Cpn+Csti)/Cgate   (3),
• 
  δVth∝(Cpn)/Cgate   (4).
• The capacitance Cgate corresponds to capacitance existing between thegate electrode103 and thePwell111. The capacitance Cpn corresponds to capacitance existing between thePwell111 and the Nwell112 (depletion layer capacitance of p-n junction). The capacitance Csti corresponds to capacitance betweenconductive layers122 and thePwell111. The capacitances used in the expression (3) are represented in a schematic form inFIG. 3 as a view corresponding to an enlarged view ofFIG. 1 and the capacitances used in the expression (4) are represented in a schematic form inFIG. 4 as a view corresponding to an enlarged view ofFIG. 2.
• As can be seen from the expressions (3,4), in the semiconductor memory devices inFIGS. 1 and 2, an increase in the capacitance Cpn may allow for an increase in the amount of the signal δVth. However, it is difficult to accomplish the optimal amount of the signal δVth by increasing the capacitance Cpn because of the small amount of the capacitance Cpn.
• As can be seen from the expression (3), in the semiconductor memory device inFIG. 1, an increase in the capacitance Csti may also allow for an increase in the amount of the signal δVth. Thus, it is easy to accomplish the optimal amount of the signal δVth by the increase of the capacitance Csti since varying the dielectric constant, a film thickness or a film area of the insulatingfilm121 changes the capacitance Csti.
• Therefore, as such, in the first embodiment,STIs104 having insulatingfilms121 andconductive layers122 may increase the amount of the signal δVth of the memory cell constituting a semiconductor memory device. In the first embodiment, an increase in the amount of the signal δVth of the memory cell may also allow for stability securement of operation of the semiconductor memory device and improvement in yield of the semiconductor memory device.
• In the semiconductor memory device inFIG. 1, insulatingfilms121, here, are formed of silicon oxide, andconductive layers122, here, are formed of polycrystalline silicon. However, insulatingfilms121 may be also formed of material such as material with insulating properties rather than silicon oxide (for example, aluminum oxide, hafnium oxide and the like) andconductive layers122 may be also formed of material such as conductive material rather than polycrystalline silicon (for example, silicon-germanium and the like). In view of setting a higher value of the capacitance Csti, it may be desirable that the dielectric constant of insulatingfilms121 are as high as possible and that the film thickness of insulatingfilms121 are as thin as possible (in the case of silicon oxide, about 8 nm in thickness). Further, it may be also advantageous to adopt silicon oxide for insulatingfilms121 and polycrystalline silicon forconductive layers122 because of their approximately equal coefficients of expansion. Insulatingfilms121 of the semiconductor memory device inFIG. 2, here, are also formed of silicon oxide.
• InFIG. 5, calculation result of the amount of the signal6Vth of the semiconductor memory device inFIG. 1 (the first embodiment) and the semiconductor memory device inFIG. 2 (the comparative example) calculated by using simulation is shown. The vertical axis inFIG. 5 represents the amount of the signal. The lateral axis inFIG. 5 represents a depth of p-n junction plane (a distance from the surface of thesubstrate101 to the p-n junction plane at which thePwell111 and theNwell112 contact one another, seeFIG. 3 andFIG. 4). It can be seen that the amount of the signal of the first embodiment is larger than that of the comparative example. Further, it is appreciated that the amount of the signal of the comparative example does not vary responding to an increase in the depth of the p-n junction plane, and however, the amount of the signal of the first embodiment increases in response to an increase in the depth of the p-n junction plane. This results from an increase in the capacitance Csti in the first embodiment, caused by an increase in a film area of insulatingfilms121 according to the increase in depth of the p-n junction plane.
• InFIG. 6, calculation result of the capacitance Cgate, the capacitance Cpn and the capacitance Csti of the semiconductor memory device inFIG. 1 (the first embodiment) and the semiconductor memory device inFIG. 2 (the comparative example) calculated by using simulation is shown. The calculated data inFIG. 6 commonly applies to both the first embodiment and the comparative example. The calculated data inFIG. 6 forms the basis for calculation inFIG. 5. It can be understood from the calculated data inFIG. 6 that as the depth of the p-n junction plane increases, the capacitance Csti increases accordingly.
• In the semiconductor memory device inFIG. 1, also,conductive layers122, here, are connected to fixed potential.Conductive layers122, here, especially from the point of view of suppressing degradation of electric strength of isolation, are connected to earth potential, and then the potential ofconductive layers122 is fixed to 0 V. The data inFIG. 5 and 6 is obtained from the simulation using the condition under which the potential ofconductive layers122 is fixed to 0 V.
• FIGS. 7(A) to (E) show side cross-sectional views of the semiconductor memory device according to the first embodiment, illustrating a method for manufacturing it.
• First, as shown inFIG. 7(A), asilicon nitride film123 to be mask material for silicon etching process is deposited entirely on the surface of asilicon substrate101. Subsequently, by using lithography and RIE (Reactive Ion Etching), a pattern for an element region of a memory cell is transferred onto thesilicon nitride film123 which is used as mask material for silicon etching process.
• Next, as shown inFIG. 7(B), by using RIE with thesilicon nitride film123 being used as mask material for silicon etching, thesilicon substrate101 is etched to provide regions for formingSTIs104. This process provides trenches for formingSTIs104 on thesilicon substrate101. The trenches forSTIs104 are, for example 0.15 μm in width and, for example 0.30 μm in depth. Subsequently, surfaces (inside surfaces) of the trenches forSTIs104 are oxidized to form silicon oxide films (insulating films)121 thereon.
• Next, as shown inFIG. 7(C), a polycrystalline silicon layer (conductive layer)122 is deposited entirely on the surface of thesilicon substrate104 to fill in the trenches forSTIs104 with thepolycrystalline silicon layer122. It is desirable to dope thepolycrystalline silicon layer122 with arsenic or other doping substances to make it exhibit n-type properties It is noted that thepolycrystalline silicon layer122 is insulated electrically from thesilicon substrate101.
• Next, as shown inFIG. 7(D), by using CMP (Chemical Mechanical Polishing), thepolycrystalline silicon layer122 on the surface of thesilicon substrate101 is planarized. As a result, thepolycrystalline silicon layer122 on the surface of the silicon substrate101 (and also the silicon nitride film123) is removed, so that polycrystalline silicon layers122 in the trenches forSTIs104 remain therein. Then, in order to form thePwell111 betweenSTIs104, thesilicon substrate101 is ion implanted with boron, for example under the conditions of 60 KeV and 5×10¹³cm⁻². Then, in order to form theNwell112 underSTIs104 and thePwell111, thesilicon substrate101 is ion implanted with phosphorus, for example under the conditions of240 KeV and 1×10¹⁴cm⁻².
• Next, as shown inFIG. 7(E), asource region113 and adrain region114 are formed. Subsequently, to form an n-type MOSFET, agate oxide film102 of silicon oxide is formed on thePwell111, and agate electrode103 of polycrystalline silicon is formed on thegate oxide film102. Therefore, an n-type MOSFET having agate oxide film102 and agate electrode103 is completed on thePwell111. Subsequently, thesource region113 is connected to a source line (SL), thedrain region114 is connected a bit line (BL) and thegate electrode103 is connected a word line (WL).
Second Embodiment
• FIG. 8 is a side cross-sectional view of a semiconductor memory device of a second embodiment. Now, difference between the semiconductor memory device of the first embodiment inFIG. 1 and that of the second embodiment inFIG. 8 will be described.
• In both the semiconductor memory devices inFIG. 1 and 8, eachSTI104 has an insulatingfilm121 and aconductive layer122. However, in the semiconductor memory device inFIG. 1, eachSTI104 has the bottom surface and the side surfaces formed by the insulatingfilm121, and on the contrary, in the semiconductor memory device inFIG. 8, eachSTI104 has the side surfaces formed by the insulatingfilm121 and the bottom surface formed by theconductive layer122. Therefore, in the semiconductor memory device inFIG. 1, theconductive layer122 of eachSTI104 is electrically insulated from thesubstrate101, while in the semiconductor memory device inFIG. 8, theconductive layer122 of eachSTI104 is electrically connected to thesubstrate101. Then, in the semiconductor memory device inFIG. 1, it is required, generally, for theconductive layer122 of eachSTI104 to be connected to fixed potential by another means to be adopted, and on the contrary, in the semiconductor memory device inFIG. 8, generally, it is not required for theconductive layer122 of eachSTI104 to be connected to fixed potential by another means to be adopted.
• In such a manner, in the second embodiment, becauseconductive layers122 and the substrate101 (theNwell112 thereof) are electrically connected to one another,conductive layers122 will have a stable potential. Therefore, in the second embodiment, the resultant improvement in resistance to noise, with regard to operation of the semiconductor memory device, may provide improvement in an operational margin of the semiconductor memory device.
• FIGS. 9(A) to (E) show side cross-sectional views of the semiconductor memory device according to the second embodiment, illustrating a method for manufacturing it. Now, difference between the manufacturing method of the semiconductor memory device of the first embodiment inFIG. 7 and that of the second embodiment inFIG. 9 will be described.
• The processes inFIGS. 9(A), (B), (C), (D) and (E) are carried out similarly to the processes inFIGS. 7(A), (B), (C), (D) and (E), respectively. The difference consists in how the manufacturing processes inFIG. 9(B) and 7(B) end. The process inFIG. 7(B) ends after eachsilicon oxide film121 is formed on the sides and bottom surface of the trench for theSTI104. While, the process inFIG. 9(B) ends after eachsilicon oxide film121 is formed on the sides and bottom surface of the trench for theSTI104 and further, by RIE which uses thesilicon nitride film123 as mask material for silicon etching process, eachsilicon oxide film121 affixed on the bottom surface of the trench for the STI104 (i.e. a portion of each silicon oxide film121) is removed. It is noted that inFIG. 7(C), eachpolycrystalline silicon layer122 is electrically insulated from thesilicon substrate101, however, inFIG. 9(C), eachpolycrystalline silicon layer122 is electrically connected to thesilicon substrate101.
• In the process inFIG. 9(B), instead of removal of the entire portion of eachsilicon oxide film121 on the bottom surface of the trench for theSTI104, only a portion of thesilicon oxide film121 on the bottom surface of the trench for theSTI104 may be also removed. In either the former case or the latter case, eachconductive layer122 and thesubstrate101 may be configured to be electrically connected to one another. Further, in the process inFIG. 9(C), instead of contacting eachconductive layer122 with thesubstrate101 to directly connect electrically to one another, eachconductive layer122 and thesubstrate101 may be configured to indirectly connect electrically to one another without direct physical contact.
• In such a manner, the embodiments of the present invention may provide the increase in the amount of the signal in a memory cell (for example, a DRAM memory cell and the like) constituting a semiconductor device (for example, a DRAM and the like).

Claims (20)

1. A semiconductor device, comprising:

a substrate;

isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer;

a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films;

a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and

a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

2. The semiconductor device according toclaim 1, wherein the conductive layer is electrically insulated from the substrate.

3. The semiconductor device according toclaim 2, wherein the insulating film constitutes the sides and bottom surface of the isolation layer.

4. The semiconductor device according toclaim 2, wherein the conductive layer is connected to fixed potential.

5. The semiconductor device according toclaim 1, wherein the conductive layer is electrically connected to the substrate.

6. The semiconductor device according toclaim 5, wherein the insulating film constitutes the sides of the isolation layer, and the conductive layer constitutes the bottom surface of the isolation layer.

7. The semiconductor device according toclaim 1, wherein the insulating film constitutes an outer envelope of the isolation layer, and the conductive layer constitutes a core portion of the isolation layer.

8. The semiconductor device according toclaim 1, wherein the insulating film intervenes between the conductive layer and the semiconductor layer of the first conductivity type and isolates the conductive layer from the semiconductor layer of the first conductivity type.

9. The semiconductor device according toclaim 1, wherein the conductive layer is opposite through the insulating film to the semiconductor layer of the first conductivity type and isolated from the semiconductor layer of the first conductivity type by the insulating film.

10. The semiconductor device according toclaim 1, wherein the insulating film is formed of a silicon oxide film, and the conductive layer is formed of polycrystalline silicon.

11. The semiconductor device according toclaim 1, wherein the semiconductor layer of the first conductivity type is a p-type well, and the semiconductor layer of the second conductivity type is an n-type well.

12. The semiconductor device according toclaim 1, wherein the substrate is a bulk substrate.

13. The semiconductor device according toclaim 1, wherein the transistor is a transistor constituting a capacitorless memory cell.

14. A method for manufacturing a semiconductor device, comprising:

forming trenches for isolation, on a substrate;

forming isolation layers, each of which has an insulating film and a conductive layer, in the trenches;

forming a semiconductor layer of a first conductivity type for storing signal charges between the isolation layers so that the semiconductor layer of the first conductivity type is isolated from the conductive layers by the insulating films;

forming a semiconductor layer of a second conductivity type under the semiconductor layer of the first conductivity type; and

forming a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

15. The method for manufacturing a semiconductor device according toclaim 14, forming each of the isolation layers, by forming the insulating film and then forming the conductive layer so that the conductive layer is electrically insulated from the substrate.

16. The method for manufacturing a semiconductor device according toclaim 15, forming each of the isolation layers, by forming the insulating film on the sides and bottom surface of the trench and then filling in the trench with the conductive layer.

17. The method for manufacturing a semiconductor device according toclaim 14, forming each of the isolation layers, by forming the insulating film, then removing a portion of the insulating film and then forming the conductive layer so that the conductive layer is electrically connected to the substrate.

18. The method for manufacturing a semiconductor device according toclaim 17, forming each of the isolation layers, by forming the insulating film on the sides and bottom surface of the trench, then removing a portion or the entirety of the insulating film formed on the bottom surface of the trench and then filling in the trench with the conductive layer.

19. The method for manufacturing a semiconductor device according toclaim 14, wherein the substrate is a bulk substrate.

20. The method for manufacturing a semiconductor device according toclaim 14, wherein the transistor is a transistor constituting a capacitorless memory cell.

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