US20070137029A1 - Method for fabricating semiconductor component with adjustment circuit for adjusting physical or electrical characteristics of substrate conductors - Google Patents

Abstract

A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This application is a division of Ser. No. 11/210,562, filed Aug. 24, 2005, which is a division of Ser. No. 10/403,741, filed Mar. 31, 2003, U.S. Pat. No. 7,007,375, which is a division of Ser. No. 10/140,340, filed May 6, 2002, U.S. Pat. No. 6,753,482.
• This application is related to Ser. No. 10/745,040, filed Dec. 22, 2003, U.S. Pat. No. 6,914,275.
FIELD OF THE INVENTION
• This invention relates generally to semiconductor manufacture, and more particularly to an improved semiconductor component having adjustable characteristics and configurations. This invention also relates to a method for fabricating the component, and to systems incorporating the component.
BACKGROUND OF THE INVENTION
• Semiconductor components, such as chip scale packages, ball grid array (BGA) devices, flip chip devices, and bare dice include terminal contacts, such as contact balls, contact bumps or contact pins. The terminal contacts provide the input/output configuration for a component, and permit the component to be surface mounted to a supporting substrate, such as a printed circuit board (PCB). Semiconductor components also include semiconductor dice, and the terminal contacts can be formed on substrates attached to the dice, or in some cases formed directly on the dice. For some components, such as chip scale packages, BGA devices, and bumped dice, the terminal contacts can be arranged in a dense grid array, such as a ball grid array (BGA), or a fine ball grid array (FBGA).
• The terminal contacts are in electrical communication with integrated circuits, and other electrical elements, contained on the dice. Typically the components include patterns of conductors that provide separate electrical paths between the terminal contacts and the integrated circuits. The conductors can comprise metal traces formed on substrates attached to the dice, or formed directly on the dice. The physical and electrical characteristics of these conductors can affect the performance of the component, and the integrity of the signals transmitted through the terminal contacts to or from the integrated circuits on the component. For example, plating buses are routinely used to electrically connect all of the conductors on a component during the fabrication process. The plating buses facilitate plating of bonding pads for the terminal contacts, and wire bonding pads for wire bonding the conductors to the dice. Following the plating process, the plating buses are trimmed, such that the conductors are no longer electrically connected to one another. However, portions of the plating buses can remain on some of the conductors following the trimming process. These remnant portions of the plating buses add mass and length to the conductors, which can affect electrical characteristics, such as inductance, capacitance and resistance. Other physical characteristics such as overall lengths, location on the component and proximity to other elements can also affect the electrical characteristics of the conductors.
• The terminal contacts associated with the conductors will also have different electrical characteristics, and the characteristics of the signals transmitted through the terminal contacts will be different. These signal variations can adversely affect the operation of the integrated circuits on the components, particularly at high clocking speeds (e.g., 500 MHz or greater). It would be desirable to have the capability to adjust the electrical characteristics of the conductors and terminal contacts for semiconductor components, and of other elements of the components as well.
• It would be also be advantageous to be able to adjust the electrical configuration of the components as well. For example, it may be necessary to electrically connect or disconnect different terminal contacts on a component to alter the input/output configuration of the component. This may be necessary because standardized components are often fabricated with different types of dice. As such, the configuration of the terminal contacts for a component containing a die with a X4 pin assignment configuration may be different than the configuration required for the same component having a die with a X16 pin assignment configuration. In the prior art different input/output configurations have been achieved by using different layouts for the terminal contacts and the conductors, or by using different wire bonding arrangements between the dice and the conductors.
• Also in the prior art, fuses have been used for isolating defective circuitry and for substituting redundant circuitry on a component. For example, a 16 megabit DRAM memory die may have a small percentage of cells that fail following burn-in testing. Fuses can be used to isolate defective integrated circuitry, and to substitute redundant integrated circuitry. Fuses can be controlled using electrical signals, or by using a laser beam directed at a portion of the fuse.
• Fuses have also been used in the art to lock in operating clock multipliers for microprocessor components. This type of microprocessor is manufactured by Advanced Micro Devices, Inc. of Sunnyvale, Calif., under the trademark “ATHLON”.
• The present invention provides a method for adjusting the characteristics of semiconductor components and elements thereof, and for customizing the input/output and electrical configuration of semiconductor components as well.
SUMMARY OF THE INVENTION
• In accordance with the present invention, an adjustable semiconductor component, a method for fabricating the component, and electronic assemblies incorporating the component, are provided.
• The component includes a substrate, a semiconductor die attached to the substrate, and terminal contacts on the substrate in electrical communication with the die. The component also includes adjustment circuitry on the substrate configured to adjust physical or electrical characteristics of the component or elements thereof.
• The adjustment circuitry includes conductors in electrical communication with the integrated circuits on the die and with the terminal contacts. The adjustment circuitry also includes programmable links, such as fuses or anti-fuses, in electrical communication with the conductors. The programmable links are configured for placement into different states (e.g., short or open) using lasers or electronic signals.
• Depending on the layout of the conductors and programmable links, different physical or electrical characteristics can be adjusted by the adjustment circuitry. For example, the adjustment circuitry can be configured to trim the conductors, such as to trim portions of plating buses associated with the conductors. In addition, the adjustment circuitry can include capacitors for adding capacitance to the conductors. Further, the adjustment circuitry can include conductive loops for adding inductance to the conductors.
• The adjustment circuitry can also be used to change the input/output configuration of the terminal contacts, and thus the electrical configuration of the component. In this regard, standard substrates can be wired to different types of dice using a standardized wire bonding arrangement. The electrical paths to the terminal contacts can then be connected or disconnected using the conductors and the programmable links to achieve a desired input/output configuration. For example, memory dice can be wire bonded to the conductors at the widest configuration possible (e.g., sixteen DQs (X16)). For a die having a sixteen DQs configuration (X16), no changes to the conductors are required. For a die having a four DQs configuration (X4), the programmable links can be configured to remove all of the conductors associated with the unused 12 DQs.
• A method for fabricating the adjustable component can be performed on a strip, such as an organic leadframe, containing multiple substrates, which can be singulated into individual components. The method includes the step of forming the adjustment circuitry on the substrates by forming the conductors and the programmable links in a required layout. Depending on layout and elements, the adjustment circuitry can be configured to adjust different physical and electrical characteristics of the conductors, or the input/output configuration of the terminal contacts. The method also includes the step of placing the programmable links in a selected state (e.g., short or open) to connect or disconnect the conductors, and to achieve the desired adjustment. Depending on the type of programmable link, the placing step can be performed using a laser or electronic signals.
• The component can be used to construct systems such as MCM packages, multi chip modules and circuit boards.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is an enlarged schematic side elevation view illustrating a semiconductor component constructed in accordance with the invention with adjustable electrical characteristics;
• FIG. 2 is an enlarged cross sectional view of the component, taken along line2-2 ofFIG. 1;
• FIG. 3 is a partial, enlarged cross sectional view, taken along line3-3 ofFIG. 2, illustrating adjustment circuitry on the component;
• FIG. 3A is an enlarged cross sectional view, taken alongline3A-3A ofFIG. 3, illustrating a substrate and solder mask of the component;
• FIG. 3B is an enlarged cross sectional view, taken alongline3B-3B ofFIG. 3, illustrating a conductor of the component;
• FIG. 3C is an enlarged cross sectional view, taken alongline3C-3C ofFIG. 3, illustrating a wire bonding pad of the component;
• FIG. 3D is an enlarged cross sectional view, taken alongline3D-3D ofFIG. 3, illustrating a bonding pad for a terminal contact of the component;
• FIG. 3E is an enlarged cross sectional view, taken alongline3E-3E ofFIG. 3, illustrating a programmable link of the component;
• FIG. 4 is an enlarged cross sectional view equivalent toFIG. 3 illustrating adjustment circuitry on an alternate embodiment component having adjustable capacitance characteristics;
• FIG. 5 is an enlarged cross sectional view equivalent toFIG. 3 illustrating adjustment circuitry on an alternate embodiment component having adjustable inductance characteristics;
• FIGS. 6A-6F are schematic cross sectional views illustrating steps in a method for fabricating the semiconductor component;
• FIG. 7A is a view taken alongline7A-7A ofFIG. 6A illustrating a leadframe used in the method;
• FIG. 7B is a view taken alongline7B-7B ofFIG. 6B illustrating adjustment circuitry on the component ofFIG. 4;
• FIG. 7C is a view equivalent toFIG. 7B illustrating adjustment circuitry on the component ofFIG. 4;
• FIG. 7D is a view taken along line7D-7D ofFIG. 6B illustrating adjustment circuitry on the component ofFIG. 5;
• FIGS. 8A and 8B are schematic cross sectional views equivalent toFIGS. 6B and 6C respectively, illustrating an alternate embodiment of the fabrication method wherein electronic signals are utilized to program current-type programmable links;
• FIG. 9A is a schematic plan view of a programmable link in the form of a current fuse configured for use with the fabrication method ofFIGS. 8A and 8B;
• FIG. 9B is a schematic cross sectional view of a programmable link in the form of an anti-fuse configured for use with the fabrication method ofFIGS. 8A and 8B;
• FIG. 10A is a schematic plan view of a multi chip module system constructed using components constructed in accordance with the invention; and
• FIG. 10B is a schematic cross sectional view of a system in a package constructed using components constructed in accordance with the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• Referring toFIGS. 1 and 2, asemiconductor component10 constructed in accordance with the invention is illustrated. As used herein, the term “semiconductor component” refers to an element, or to an assembly, that includes a semiconductor die. In the illustrative embodiment, thecomponent10 comprises a board-on-chip (BOC) semiconductor package. However, thesemiconductor component10 can comprise another type of semiconductor package such as a chip-on-board (COB) package, a chip scale package (CSP), a BGA device, a flip chip device, or a bumped semiconductor die.
• Thecomponent10 includes asubstrate12 having a first surface14 (FIG. 2), and an opposing second surface16 (FIG. 2). Thefirst surface14, and thesecond surface16, are the major planar surfaces of thesubstrate12. Thesubstrate12 also includes awire bonding opening18 therethrough, extending from thefirst surface14 to thesecond surface16.
• In addition, thesubstrate12 includes adjustment circuitry19 (FIG. 2) formed on thefirst surface14 of thesubstrate12, and a die attacharea22 formed on thesecond surface16 of thesubstrate12. Theadjustment circuitry19 includes a pattern of conductors20 (FIG. 2), andprogrammable links50A,50B (FIG. 3) in electrical communication with theconductors20.
• Theconductors20 can comprise a highly conductive metal which is blanket deposited on thesubstrate12, and then etched in required patterns. Alternately, an additive process, such as electroless deposition through a mask, can be used. Suitable metals for theconductors20 include copper, aluminum, titanium, tungsten, tantalum, platinum, molybdenum, cobalt, nickel, gold, and iridium.
• Thesubstrate12 can comprise an electrically insulating material, such as an organic polymer resin reinforced with glass fibers. Suitable materials for thesubstrate12 include bismaleimide-triazine (BT), epoxy resins (e.g., “FR-4” and “FR-5”), and polyimide resins. These materials can be formed with a desired thickness, and then punched, machined, or otherwise formed with a required peripheral configuration, and with required features. A representative thickness of thesubstrate12 can be from about 0.2 mm to 1.6 mm.
• Thesubstrate12 also includes asolder mask24 on thefirst surface14, and asolder mask26 on thesecond surface16. The solder masks24,26 can comprise a photoimageable dielectric material, such as a negative or positive tone resist.
• As shown inFIG. 2, thecomponent10 includes an array ofterminal contacts28 on thesubstrate12 in electrical communication with integrated circuits, or other electrical elements contained on thecomponent10. Theterminal contacts28 provide separate electrical connection points for transmitting (writing) and receiving (reading) electronic signals from thecomponent10. In addition, theterminal contacts28 provide a structure for bonding thecomponent10 to a supporting substrate, such as a printed circuit board or module substrate.
• In the illustrative embodiment, theterminal contacts28 comprise generally spherically shaped contact balls in a ball grid array (BGA), or a fine ball grid array (FBGA). However, theterminal contacts28 can comprise other conventional contacts having other shapes, and arranged in other patterns, to provide multiple electrical connection points for the component. By way of example, representative contacts include bumps, columns, studs, domes, cones, pins and pads. Also, theterminal contacts28 can be made of any electrically conductive material, such as a solder alloy, copper, nickel, or a conductive polymer.
• As shown inFIG. 1, theterminal contacts28 have a diameter “D” and a spacing or pitch “P”. With theterminal contacts28 comprising contact balls in a ball grid array, or a fine ball grid array, a representative range for the diameter D can be from about 0.127 mm (0.005 inch) to 0.762 mm (0.030 inch). A representative range for the pitch P can be from about 0.228 mm (0.008 inch) to 2.0 mm (0.078 inch).
• As shown inFIG. 2, thecomponent10 also includes asemiconductor die30, and adie encapsulant42 on thedie30 and on thesecond surface16 of thesubstrate12. The die30 can comprise a conventional semiconductor die having a desired configuration. For example, the die30 can comprise a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a microprocessor, a digital signal processor (DSP), or an application specific integrated circuit (ASIC).
• Thedie30 includes a row ofbond pads32 formed on a face portion thereof, in electrical communication with the integrated circuits contained on thedie30. Thedie30 is bonded face down to the die attacharea22 of thesubstrate12, with thebond pads32 on the die30 aligned with thebonding opening18 in thesubstrate12.
• As shown inFIG. 2, anadhesive layer34 bonds the die30 to the die attacharea22 on thesubstrate12. Theadhesive layer34 can comprise a filled epoxy, an unfilled epoxy, an acrylic, a polyimide or an adhesive tape material. In addition,wires36 are placed through thewire bonding opening18 in thesubstrate12, and are wire bonded to thebond pads32 on thedie30, and to correspondingwire bonding pads40 on thesubstrate12. Awire bond encapsulant38 fills thewire bonding opening18 and encapsulates thewires36. Thewire bond encapsulant38 can comprise a polymer material, such as a glob top of epoxy or silicone, deposited in a desired shape using a suitable process such as dispensing through a nozzle, and then cured as required.
• Referring toFIG. 3, theadjustment circuitry19 also includes terminalcontact bonding pads44 on thesubstrate12 configured to provide bonding sites for bonding theterminal contacts28 to thesubstrate12. The terminalcontact bonding pads44 are in electrical communication with theconductors20 and with thewire bonding pads40. In addition, the terminalcontact bonding pads44 are in electrical communication with platingconductors20P on thesubstrate12 that extend to anedge54 of thesubstrate12. As will be further explained, the platingconductors20P are initially connected to plating buses, which are used to apply a current to the terminalcontact bonding pads44, and to thewire bonding pads40, for plating non-oxidizing metal layers46 (FIGS. 3C and 3D) such as gold or platinum layers. These non-oxidizing metal layers46 facilitate the bonding process for theterminal contacts28 and the wire bonding process to thedie30.
• As shown inFIGS. 3A and 3B, thesolder mask24 covers thesubstrate12 and theconductors20. However, as shown inFIGS. 3C and 3D, thesolder mask24 includesopenings48 aligned with thewire bonding pads40 and the terminalcontact bonding pads44.
• As shown inFIG. 3, theadjustment circuitry19 also includes firstprogrammable links50A proximate to the platingconductors20P, and secondprogrammable links50B between thewire bonding pads40 and the terminalcontact bonding pads44. As used herein the term “programmable link” means an element that can be placed in either a first state (short) in which electrical current can be transmitted through the link, or in a second state (open) in which electrical current cannot be transmitted through the link.
• Suitable programmable links include laser fuses, current fuses, laser anti-fuses, and current anti-fuses. A laser fuse includes a segment that can be broken by a laser beam to create an open circuit. A voltage fuse includes a segment that can be broken by application of electrical current having a sufficient amperage to create an open circuit. A laser anti-fuse includes conductive segments separated by a dielectric layer that can be broken down by a laser beam to electrically connect the conductive segments to create a short circuit. A current anti fuse has a dielectric layer that can be broken down by application of electrical current having a sufficient amperage to create a short circuit.
• In the embodiment illustrated inFIG. 3, theprogrammable links50A,50B comprise laser fuses which are initially fabricated in the first state (short), but which can be placed in the second state (open) by application of a laser beam. InFIG. 3 theprogrammable links50A,50B in the first state (short) have a continuous line therethrough, whereas theprogrammable links50A,50B in the second state (open) do not have a line therethrough.
• As shown inFIG. 3E, theprogrammable links50A,50B can comprise breakable segments52 having a width W and a thickness T. The width W and the thickness T can be selected such that a laser beam of a predetermined power will sever a breakable segment52. The breakable segments52 can be formed of a same conductive material as theconductors20, or can be formed of a different conductive material. In addition, the breakable segments52 can be aligned withopenings48 in thesolder mask24 to permit access by the laser beam.
• Theprogrammable links50A function as “trimming links” for trimming portions of theconductors20. Specifically, inFIG. 3, theprogrammable links50A have been placed in the second state (open) by application of a laser beam. This removes or “trims” the platingconductors20P from theconductors20. For simplicity, theprogrammable links50A are illustrated in rows proximate to theouter edges54 of thesubstrate12. However, eachprogrammable link50A can be located as close as possible to a corresponding terminalcontact bonding pad44, such that as much length of the platingconductors20P as is possible can be removed. Trimming of the platingconductors20P improves the integrity of the signals transmitted to and from the terminal contacts28 (FIG. 2) because the superfluous conductive path through the platingconductors20P has been removed. In addition, theconductors20 are more evenly matched in length, such that their electrical characteristics and signal transmitting capabilities are more evenly matched.
• Theprogrammable links50B function as “input/output links” for changing the input/output configuration of theterminal contacts28. Specifically, inFIG. 3, some of theprogrammable links50B have been placed in the second state (open) by application of a laser beam, while some of theprogrammable links50B remain in the first state (short). Theprogrammable links50B allow selectedconductors20, and their associated terminalcontact bonding pads44, to be removed or “trimmed” from the input/output circuit of thecomponent10. The trimmed conductors are designated20-T. As such, there is no conductive path between a trimmed conductor20-T and thedie30, and no conductive path between the die30 and the terminal contact28 (FIG. 2) associated with the trimmed conductor20-T. This arrangement permits the input/output configuration of the terminal contacts28 (FIG. 2) to be changed and customized for a particular application. The electrical configuration of thecomponent10 can thus be customized as well.
• In addition, this arrangement permits the wire bonding of the die30 to theconductors20 to be standardized even for different types of dice. For example, a X4 die can be wire bonded in the same manner as a X16 die, but with the unusedterminal contacts28 taken out of the input/output circuit.
• Referring toFIG. 4, a cross section equivalent toFIG. 3, of analternate embodiment component10C is illustrated. Thecomponent10C is constructed substantially as previously described for component10 (FIG. 1), and includes essentially the same elements includingadjustment circuitry19C. However, in this embodiment theadjustment circuitry19C also includescapacitors56 in electrical communication with theconductors20 and the terminalcontact bonding pads44. In addition, theadjustment circuitry19C includesprogrammable links50C in electrical communication with thecapacitors56.
• Theprogrammable links50C can comprise laser fuses, current fuses, laser anti-fuses or current anti-fuses, substantially as previously described forprogrammable links50A,50B inFIG. 3. Thecapacitors56 andprogrammable links50C allow extra capacitance to be added or “trimmed” into theconductors20. Thecapacitors56 and programmable links SOC permit capacitance to be added to the conductive paths through the terminal contacts28 (FIG. 1) such that the capacitance of individualterminal contacts28, and the capacitance of selected groups of theterminal contacts28, can be adjusted and/or matched. For example, theterminal contacts28 representing matching input/output pin groups for thecomponent10C can be matched.
• InFIG. 4, the conductors having added capacitance are designated20C. Theseconductors20C are in electrical communication with aprogrammable link50C in the first state (short) such that electrical communication with acapacitor56 is maintained. Theother conductors20 are in electrical communication with aprogrammable link50C in the second state (open) such that there is no electrical communication with acapacitor56.
• In the illustrative embodiment, thecapacitors56 and theprogrammable links50C are located proximate to the terminalcontact bonding pads44, and are outside of the conductive paths between the terminalcontact bonding pads44 and thedie30. Thecapacitors56 can comprise conductive plates separated by dielectric layers configured to provide a desired capacitance C. Thecapacitors56 can be constructed using techniques that are known in the art, such as by deposition and patterning of metal and dielectric layers. Alternately, thecapacitors56 can comprise surface mount devices that are commercially available from various manufacturers. The value of the capacitance C of eachcapacitor56 can be selected as required, with from micro farads (μF) to pico farads (pF) being representative. In addition to matching the capacitance of the conductive paths for theterminal contacts28, the capacitors can also be used as by-pass filters for filtering transient voltages, power supply noise and spurious signals.
• Referring toFIG. 5, a cross sectional equivalent toFIG. 3, of an alternate embodiment component10I is illustrated. The component10I is constructed substantially as previously described for component10 (FIG. 1), and includes essentially the same elements including adjustment circuitry19I. However, the adjustment circuitry19I also includes inductance conductors20I in electrical communication with theconductors20, and with the terminalcontact bonding pads44. In addition, the inductance conductors20I are in electrical communication with programmable links50I. Each inductance conductor20I and associated programmable link50I forms an adjustable conductive loop that can be either by-passed, or added, depending on the state of the programmable link50I.
• The programmable links50I can comprise laser fuses, current fuses, laser anti-fuses or current anti-fuses, substantially as previously described forprogrammable links50A,50B inFIG. 3. The inductance conductors20I and programmable links50I allow extra inductance and resistance to be added or “trimmed” into theconductors20
• InFIG. 50, the inductance conductors20I in electrical communication with the programmable links50I in the second state (open) are activated, whereas the inductance conductors20I in electrical communication with the programmable links in the first state (short) are bypassed.
• InFIG. 5, the inductance conductors20I and programmable links50I are located between the terminalcontact bonding pads44 and thewire bonding pads40. In addition, eachconductor20 includes three separate inductance conductors20I and programmable links50I. However, this arrangement is merely exemplary and other arrangements are possible.
• Referring toFIGS. 6A-6F, steps in a method for fabricating thecomponent10,10C or10I are illustrated. As shown inFIG. 6A, apanel58 containingmultiple substrates12 is initially provided. Thepanel58 is similar in function to a semiconductor leadframe, permitting the fabrication ofmultiple components10,10C or10I at the same time.
• As shown inFIG. 7A, thepanel58 includescircular indexing openings62 proximate to the longitudinal edges thereof. Theindexing openings62 permit thepanel58 to be handled by automated transfer mechanisms associated with chip bonders, wire bonders, molds, and trim machinery. In addition, thepanel58 includes elongatedseparation openings60 which facilitate singulation of thesubstrates12 on thepanel58 intoseparate components10,10C or10I. Thepanel58 also includes awire bonding opening18 for eachsubstrate12. If desired, thepanel58 can be constructed from a commercially produced bi-material core, such as a copper clad bismaleimide-triazine (BT) core, available from Mitsubishi Gas Chemical Corp., Japan. A representative weight of the copper can be from 0.5 oz to 2 oz. per square foot.
• Next, as shown inFIG. 6B, theadjustment circuitry19 is formed on thesubstrate12. As shown inFIG. 7B, theadjustment circuitry19 includes theconductors20 and theprogrammable links50A,50B which are laid out substantially as previously described and shown inFIG. 3. In addition, theadjustment circuitry19 includes the terminalcontact bonding pads44, and thewire bonding pads40 in electrical communication with theconductors20.
• Theconductors20 can comprise a highly conductive metal layer, which is blanket deposited onto the panel58 (e.g., electroless or electrolytic plating), and then etched in required patterns. Alternately, an additive process, such as electroless deposition through a mask, can be used. Suitable metals include copper, aluminum, titanium, tungsten, tantalum, platinum, molybdenum, cobalt, nickel, gold, and iridium.
• The terminalcontact bonding pads44, and thewire bonding pads40 can be formed at the same time, and using the same process, as for theconductors20. In addition, the non-oxidizing layers46 (FIGS. 3C, 3D) can be formed on the terminalcontact bonding pads44, and thewire bonding pads40 using a plating process, such as electrolytic deposition. As shown inFIG. 7B, platingbuses64 can be used to electrically connect theconductors20 for performing the plating process. These platingbuses64 will be trimmed away during the singulating step to be hereinafter described.
• Theprogrammable links50A,50B can be formed at the same time and using the same process as for theconductors20. For example, theprogrammable links50A,50B can comprise segments of theconductors20 formed by etching a blanket deposited layer using an etch mask, or by depositing metal in a required pattern using a deposition mask. Alternately, theprogrammable links50A,50B can comprise surface mounted devices placed in electrical communication with theconductors20.
• Following formation of theadjustment circuitry19 the solder mask24 (FIG. 3B), and the solder mask26 (FIG. 2) can be formed. Thesolder mask24 includes the openings48 (FIGS. 3C and 3D) for the terminalcontact bonding pads40, thewire bonding pads44 and theprogrammable links50A,50B. Thesolder mask26 includes a die sized opening on the die attach area22 (FIG. 2). The solder masks24,26 can comprise a photoimageable dielectric material, such as a negative or positive tone resist. One suitable resist is commercially available from Taiyo America, Inc., Carson City, Nev. under the trademark “PSR-4000”. The “PSR-4000” resist can be mixed with an epoxy such as epoxy “720” manufactured by Ciba-Geigy (e.g., 80% PSR-4000 and 20% epoxy “720”). Another suitable resist is commercially available from Shipley under the trademark “XP-9500”.
• Referring toFIG. 7C, theadjustment circuitry19C can be configured as previously described and shown inFIG. 4, withcapacitors56 andprogrammable links50C. Thecapacitors56 can comprise etched or deposited metal and dielectric layers formed substantially as previously described for theconductors20. Alternately, thecapacitors56 can comprise surface mounted devices placed in electrical communication with theconductors20. Theprogrammable links50C can be formed substantially as previously described forprogrammable links50A,50B.
• Referring toFIG. 7D, the adjustment circuitry19I can also be configured as previously described and shown inFIG. 5, with inductance conductors20I and programmable links50I. The inductance conductors20I can comprise etched or deposited metal layers formed substantially as previously described for theconductors20. The programmable links50I can be formed substantially as previously described forprogrammable links50A,50B.
• Referring toFIG. 6C, following formation of theadjustment circuitry19, alaser beam66 can be used to place selectedprogrammable links50A,50B (FIG. 7B),50C (FIG. 7C) or50I (FIG. 7D), in the open state such that no current can be transmitted therethrough. Suitable laser systems for laser severing the breakable segments52 (FIG. 3E) of theprogrammable links50A,50B are manufactured by Electro Scientific, Inc., of Portland, Oreg. as well as others.
• Although theprogrammable links50A,50B,50C,50I are illustrated as being laser fuses, it is to be understood that these programmable links can also be configured as laser anti-fuses. In this case thelaser beam66 would be used to place selected programmable links in the short state, such that current can be conducted therethrough.
• Next, as shown inFIG. 6D, the die30 can be attached to thesubstrate12 using conventional adhesives and die attach systems. In addition, the die30 can be wire bonded to the wire bonding pads40 (FIG. 3) using conventional wire bonding equipment.
• Next, as shown inFIG. 6E, thedie encapsulant42 can be formed on thedie30. Thedie encapsulant42 can comprise a deposited or molded polymer. For example, thedie encapsulant42 can comprise a Novolac based epoxy formed in a desired shape using a transfer molding process, and then cured using an oven. For simplicity, inFIG. 6E, thewire bond encapsulant38 is not shown. However, thewire bond encapsulant38 can be formed using a suitable technique such as dispensing and curing a glob top polymer. As also shown inFIG. 6E, theterminal contacts28 can be formed on the terminalcontact bonding pads44 using a bonding process, such as solder reflow of pre-formed balls, or a deposition process such as electroless deposition of metal bumps.
• Next, as shown inFIG. 6F, a singulation step can be performed to singulate thecomponents10,10C or10I from thepanel58. The singulation step can be performed using a saw, a shear or another singulation apparatus. The singulation step also trims the plating buses64 (FIG. 7B) such that theconductors20 are no longer electrically connected to one another.
• Referring toFIGS. 8A-8B and9A-9B, an alternate embodiment of the fabrication method illustrated inFIGS. 6A-6F is illustrated. As shown inFIG. 8A, anadjustment circuit19S is formed on thesubstrate12, substantially as previously described and shown inFIG. 6 foradjustment circuit19. However, theadjustment circuit19S includesprogrammable links50S (FIG. 9A) configured as current fuses, or alternately programmable links50AF configured as anti-fuses.
• As shown inFIG. 9A, eachprogrammable link50S includes a necked down portion72 (FIG. 9A) configured to blow, and form an open circuit upon application of a sufficient current. As shown inFIG. 9B, each programmable link50AF includes a pair ofconductive plates74A,74B separated by adielectric layer76. Upon application of a sufficient current, thedielectric layer76 breaks down, such that electrical communication is established between theconductive plates74A,74B and a short circuit is formed. With the programmable link50AF configured as an anti-fuse the same results can be achieved as with a fuse, provided the state of the link (open or short) is opposite to that of the fuse.
• As shown inFIG. 8B, aprogramming circuit70 is configured to apply the current signals necessary to place theprogrammable links50S or50AF in the required state (i.e., open forprogrammable link50S or short for programmable link50AF). In addition,electrical connectors68 such as “POGO PINS” establish electrical communication between theprogramming circuit70 and theprogrammable links50S or50AF. The electrical connectors can be constructed to electrically engage the terminal contact bonding pads44 (FIG. 3), the wire bonding pads40 (FIG. 3) or other connection points on theadjustment circuit19S.
• Referring toFIGS. 10A and 10B, electronic systems constructed usingcomponents10,10C,10I fabricated in accordance with the invention are illustrated. In general, thecomponents10,10C,10I can be used in any system in which semiconductor components as previously defined are used.
• InFIG. 10A, a multichip module system80 includes amodule substrate82 having anedge connector84, and a plurality ofconductors86 in electrical communication with theedge connector84. Thecomponents10,10C,10I can be flip chip mounted to themodule substrate82, with the terminal contacts28 (FIG. 1) thereon in electrical communication with theconductors86.
• InFIG. 10B, a system in a package (SIP)88 is constructed with one ormore components10,10C,10I. This type of package is also referred to as a multi chip module MCM package. The system in a package (SIP)88 can be configured to perform a desired function such as micro processing. The system in a package (SIP)88 includes asubstrate90 having terminal leads92. Thecomponents10,10C,10I can be flip chip mounted to thesubstrate90, with theterminal contacts28 thereon in electrical communication with the terminal leads92. The system in a package (SIP)88 also includes apackage body94 encapsulating thecomponents110,10C,10I and thesubstrate90.
• Thus the invention provides improved adjustable semiconductor components, methods for fabricating the components, and systems incorporating the component. While the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.

Claims (20)

1. A method for fabricating a semiconductor component comprising:

providing a substrate;

forming an adjustment circuit on the substrate comprising a plurality of conductors, and a plurality of programmable links in electrical communication with the conductors;

attaching a die to the substrate in electrical communication with the conductors; and

changing a physical characteristic or an electrical characteristic of at least one conductor by placing the programmable links in a selected state.

2. The method ofclaim 1 wherein the physical characteristic comprise length and the changing step trims the length.

3. The method ofclaim 1 wherein the electrical characteristic comprises capacitance and the changing step adds capacitance.

4. The method ofclaim 1 wherein the electrical characteristic comprises inductance and the changing step adds inductance.

5. The method ofclaim 1 further comprising forming terminal contacts on the substrate in electrical communication with the conductors and changing an input/output configuration of the terminal contacts using the programmable links.

6. A method for fabricating a semiconductor component comprising:

providing a substrate;

forming an adjustment circuit on the substrate comprising a plurality of conductors, a plurality of programmable links in electrical communication with the conductors, and a plurality of capacitors in electrical communication with the programmable links;

attaching a die to the substrate in electrical communication with the conductors; and

adding capacitance to selected conductors by placing the programmable links in a selected state.

7. The method ofclaim 6 further comprising forming the adjustment circuit with a plurality of second programmable links configured to trim portions of the conductors, and trimming the portions using the second programmable links.

8. The method ofclaim 6 wherein the capacitors comprise metal and dielectric layers deposited on the substrate.

9. The method ofclaim 6 wherein the capacitors comprise surface mounted devices.

10. The method ofclaim 6 further comprising changing a physical characteristic of at least one conductor using at least one programmable link.

11. The method ofclaim 6 further comprising forming terminal contacts on the substrate in electrical communication with the conductors and changing an input/output configuration of the terminal contacts using the programmable links.

12. A method for fabricating a semiconductor component comprising:

providing a substrate;

forming an adjustment circuit on the substrate comprising a plurality of conductors, a plurality of programmable links in electrical communication with the conductors, and a plurality of inductance conductors in electrical communication with the programmable links;

attaching a die to the substrate in electrical communication with the conductors; and

adding inductance to selected conductors by placing the programmable links in a selected state.

13. The method ofclaim 12 further comprising forming the adjustment circuit with a plurality of second programmable links configured to trim portions of the conductors, and trimming the portions using the second programmable links.

14. The method ofclaim 12 wherein each conductor is associated with a plurality of inductance conductors.

15. The method ofclaim 12 further comprising changing a physical characteristic of at least one conductor using at least one programmable link.

16. The method ofclaim 12 further comprising forming terminal contacts on the substrate in electrical communication with the conductors and changing an input/output configuration of the terminal contacts using the programmable links.

17. A method for fabricating a semiconductor component comprising:

providing a substrate comprising a plurality of terminal contacts;

attaching a semiconductor die to the substrate in electrical communication with the terminal contacts;

providing an adjustment circuit on the substrate comprising a plurality of conductors and programmable links in electrical communication with the die and the terminal contacts; and

adjusting an electrical characteristic of at least one conductor and an input/output configuration of the terminal contacts by placing at least one of the programmable links in a selected state.

18. The method ofclaim 17 wherein the electrical characteristic comprises capacitance and the adjusting step adds capacitance.

19. The method ofclaim 17 wherein the electrical characteristic comprises inductance and the adjusting step adds inductance.

20. The method ofclaim 17 further comprising changing a physical characteristic of at least one conductor using at least one programmable link.

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