US20070132056A1 - Isolation structures for semiconductor integrated circuit substrates and methods of forming the same - Google Patents

Abstract

Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.

Description

FIELD OF THE INVENTION
• This invention relates to semiconductor chip fabrication and in particular to methods of fabricating structures to isolate electrically the active or passive devices formed on a semiconductor chip.
BACKGROUND OF THE INVENTION
• In the fabrication of semiconductor integrated circuit (IC) chips, it is frequently necessary to electrically isolate devices that are formed on the surface of the chip. There are various ways of doing this. A way is by using the well-known LOCOS (Local Oxidation Of Silicon) process, wherein the surface of the chip is masked with a relatively hard material such as silicon nitride and a thick oxide layer is grown thermally in an opening in the mask. Another way is to etch a trench in the silicon and then fill the trench with a dielectric material such as silicon oxide.
• It is desirable to form these isolation structures early in the process because they can also act as barriers or stops to the lateral diffusion of dopants, thereby allowing a more closely packed device population on the surface of the chip. In short, a dielectric-filled trench can function as a diffusion stop as well as an electrical isolation structure.
• The problem with forming a dielectric-filled trench early in the process it that subsequent process steps, which frequently include etching and cleaning, can etch or erode the dielectric material in the trench. This can impair the value of the trench as an isolation structure and can create depressions in the top surface of the chip, rendering further processing more difficult.
• This problem is illustrated inFIGS. 1A-1C. InFIG. 1A, atrench101 has been etched in asemiconductor substrate100. InFIG. 1B,trench101 has been filled with adielectric material102 and the top surface has been planarized (e.g., by chemical-mechanical polishing) to form an isolation structure.FIG. 1C shows the isolation structure after further processing, with part of thedielectric material102 removed or eroded so as to form a recess orgap103 on the top surface of the structure. Dielectric materials that are resistant to etching in normal semiconductor processes (e.g., silicon nitride) tend to be hard, brittle, high-stress materials. When these materials are deposited in a trench they tend to crack.
• A second problem stems from the fact that chips are generally divided into two general areas: broad or wide “field” areas and more densely-packed device areas, sometimes referred to as “active” areas. It is preferable to form relatively narrow, deep trenches in the active areas to maintain a tight packing density and to form relatively wide trenches in the field areas to space out the devices over larger distances. This creates a problem in filling the trenches. The narrow trenches may be filled while the wide trenches are difficult to fill. Alternatively, using numerous narrow trenches to cover large distances in the field areas can complicate the topography of the chip.
• Accordingly, it would be desirable to develop a flexible, adaptable technique of forming dielectric-filled isolation structures that avoid the erosion of the dielectric fill material during subsequent processing. It would also be desirable to provide for the formation of relatively wide and narrow structures in the field and active regions, respectively, of the chip.
SUMMARY OF THE INVENTION
• According to this invention, an isolation structure is formed by filling a trench in a semiconductor substrate with a “dielectric fill.” The dielectric fill includes a first dielectric material and a second dielectric material. The first dielectric material is located in a lower portion of the trench; the second dielectric material is located in an upper portion of the trench, the lower portion typically being larger in the vertical dimension than the upper portion. The surface of the second dielectric material is substantially coplanar with a surface of the substrate. The first and second dielectric materials are dissimilar in the sense that the second dielectric material is not etched by a chemical which etches the first dielectric material. Thus in subsequent processing the second dielectric material forms a protective cap over the first dielectric material. Typically, the first dielectric material is a relatively soft, low-stress material and the second dielectric material is a relatively hard, etch-resistant material. Cracking problems can be avoided by limiting the thickness of the second dielectric layer to a value that provides protection during later etching processes but does not create stress problems.
• Alternatively, instead of forming a discrete cap, the trench may be filled with a “graded” dielectric, wherein the proportion of the second dielectric material in the dielectric fill increases gradually as one moves upward towards the mouth of the trench.
• The sidewalls of the trench may be lined with an oxide layer to prevent dopants from the dielectric fill from migrating into the semiconductor substrate.
• In one group of embodiments the first dielectric material is a silicon oxide and silicate glass, either doped or undoped. The second dielectric can be silicon nitride, a polyimide or any dielectric material containing little or no silicon oxide.
• The substrate may also include the lower portion of a field oxide region, typically formed by a local oxidation of silicon (LOCOS) process. The surface of the field oxide region is also substantially coplanar with the surface of the substrate. Alternatively, a protective cap may be formed over the field oxide.
• In another group of embodiments, the substrate contains two isolation structures, the first formed in a relatively shallow, wide trench, the second formed in a relatively narrow, deep trench. Both trenches are filled with a dielectric fill and the surface of the dielectric fill is substantially coplanar with the surface of the substrate. Alternatively, a protective cap of the kind described above may be formed at the mouth of each trench.
• In yet another set of embodiments, one or more field oxide regions are formed in the same substrate as one or more trench isolation structures. Field doping regions of predetermined conductivity type and doping concentration may be formed under the field oxide regions. Optionally, protective dielectric caps may be formed where the trenches and field oxide regions meet the plane of the surface of the substrate. The surface of the entire structure is substantially coplanar. The surface mab be planarized by using a chemical etchback, a plasma-enhanced or reactive ion etch (RIE), chemical-mechanical polishing (CMP) or some combination thereof.
• The invention also includes methods of fabricating isolation structures. One such method includes forming a trench in the semiconductor substrate; depositing a first dielectric material in the trench; removing a portion of the first dielectric material such that a surface of the first dielectric material is located at a first level below a second level of a top surface of the substrate, thereby forming a recess; depositing a second dielectric material in the recess; and removing a portion of the second dielectric material such that a surface of the second dielectric material is substantially coplanar with the surface of the substrate, thereby forming a protective cap in the trench.
• Another method includes thermally forming a field oxide region at a surface of the semiconductor substrate; forming a trench in the substrate; depositing a first dielectric material in the trench; removing a portion of the first dielectric material such that a surface of the first dielectric material is located at a first level below a second level of the surface of the substrate, thereby forming a recess; depositing a second dielectric material in the recess; and removing portions of the field oxide region and the second dielectric material such that a surface of the field oxide region and a surface of the second dielectric material are substantially coplanar with the surface of the substrate, thereby forming a protective cap in the trench.
• The methods of this invention are highly flexible and can be used to form isolation regions necessary meet the varying demands of different regions and devices in a semiconductor substrate. The topography of the substrate is maintained extremely flat, or at least sufficiently flat as not to interfere with or complicate the formation of fine line widths and submicron features or the interconnection thereof during subsequent processing. Protective caps can be used to protect the dielectric materials from erosion during subsequent processing.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIGS. 1A-1C illustrate the problem that occurs when the dielectric in a trench which serves as an isolation structure is eroded during later processing.
• FIGS. 2A-2F illustrate a process for forming an isolation structure that includes a protective cap at the mouth of a dielectric-filled trench.
• FIGS. 3A-3D illustrate a process for forming a modified version of the isolation structure ofFIG. 2F where an oxide layer is formed on the walls of the trench adjacent the protective cap.
• FIG. 4 illustrates how the oxide layer shown inFIG. 3D may be eroded in subsequent processing.
• FIG. 5 is a flow chart, in “card” form, of the processes shown inFIGS. 2A-2F and3A-3D.
• FIGS. 6A-6C illustrate a process for forming isolation structures that include a broad or wide field oxide region and a relatively narrow dielectric-filled trench.
• FIGS. 7A-7H illustrate a processing for forming isolation structures which include a wide, shallow trench and a narrow, deep trench.
• FIGS. 8A-8J illustrate another process for forming isolation structures that include a broad or wide field oxide region and a relatively narrow dielectric-filled trench, with a protective cap formed at the top of each structure.
• FIGS. 9A-9E illustrate a process for forming isolation structures that include a pair of field oxide regions and a dielectric-filled trench, with field doping regions beneath the field oxide regions.
DESCRIPTION OF THE INVENTION
• FIGS. 2A-2F illustrate a process for fabricating a trench isolation structure that avoids the formation of a gap or recess at the top of the trench, as shown inFIG. 1C. As shown inFIG. 2A, an oxide or “hard mask”layer121 is formed on the top surface of asemiconductor substrate120, and aphotoresist layer122 is deposited on top ofhard mask layer121. The term “hard mask” is used herein to refer to a thermally grown or deposited dielectric layer used as a mask during the etching of a trench insemiconductor substrate120. The “hard mask” is distinguished from theorganic photoresist layer122, for example, which is mechanically softer and therefore subject to erosion during the trench etch process. An opening is formed inphotoresist layer122 by a normal photolithographic process, and anopening123 is etched inhard mask layer121 through the opening inphotoresist layer122.
• As shown inFIG. 2B,substrate120 is etched through theopening123 to form atrench124. It is generally preferably to removephotoresist layer132 prior to the etching of the trench, sincephotoresist layer132 may interfere with the trench etching process, change shape during the trench etching process, and possibly introduce undesirable organic contaminants into the trench. A reactive ion etch (RIE) can be used to achieve an anisotropic etch, producing atrench124 having vertical walls. A relativelythin oxide layer125 is grown thermally on the walls and floor oftrench124. If desired, a sacrificial oxide layer can be formed to remove crystal defects caused by the RIE process, the sacrificial oxide layer can be removed, and then a second oxide layer can be grown. The thickness ofoxide layer125 could be from 100 to 1000 Å, typically about 300-400 Å. Iftrench124 is later filled with a doped dielectric material,oxide layer125 will prevent the dopant from entering the semiconductormaterial surrounding trench124.
• As shown inFIG. 2C, a relativelythick layer126 of a glass such as borophosphosilicate glass (BPSG) is spun onto the surface ofsubstrate120, completely fillingtrench124. The BPSG could be doped to reduce its viscosity, or it could be undoped. Alternatively, the BPSG could be deposited by chemical vapor deposition (CVD). As described above, if theBPSG layer126 is doped,oxide layer125 acts as a barrier to prevent the dopant from entering anddoping substrate120.BGSG layer126 is sufficiently thick (e.g., 0.5 to 1.0 μm thick) that its top surface is relatively planar, with only a small dent over the location oftrench124. If desired, a high temperature reflow can be used to further planarize the surface ofBPSG layer126.
• As shown inFIG. 2D,BPSG layer126 andsidewall oxide layer125 are etched back until their top surfaces are below the surface ofsubstrate120, forming arecess130. Following the etchback, the surface ofBPSG layer126 may be from 0.1 to 0.5 μm (typically about 0.2 to 0.3 μm) below the surface ofsubstrate120. Then, as shown inFIG. 2E, alayer131 of another dielectric is deposited, fillingrecess130 and overflowing the surface ofsubstrate120.Layer131 is then planarized by CMP or etchback to form aprotective cap132, which completely covers and protectsoxide layer125 andBPSG layer126. The top surface ofcap132 is preferably coplanar with the surface ofsubstrate120, although it could vary by 0.1 μm in height across the wafer.FIG. 2F shows the structure aftercap132 has been formed.
• Layer131 andcap132 should be formed of a material that is not significantly etched by the cleaning and etching steps that are to take place later in the process. In this embodiment, for example,layer131 may be formed of silicon nitride. In general, the material of whichlayer131 is formed does not etch at all, or etches substantially slower thanBPSG layer126 oroxide layer125, in the subsequent processing steps. A protective cap according to this invention can be formed at any time during the process to protect the trench-fill material from subsequent erosion of the kind shown inFIG. 1C.
• It should be noted that in general materials such as silicon nitride that can provide a protective shield against further etching typically do not deposit very uniformly and thus it is difficult to get them to fill a trench. Moreover, silicon nitride tends to crack when deposited thickly. These problems are overcome by filling the trench with a softer, less brittle material such as BPSG and then covering the material with a relatively thin protective cap of a harder, more brittle material such as silicon nitride.
• Table 1 shows the relative removal rates of materials that can be used to fill the trench for several etchants or removal methods.

  	TABLE 1
  	Etchant or Removal Method

  			Selective	Selective
  Dielectric			plasma oxide	“nitride” plasma
  Fill Materials	100:1 HF	10:1 HF	etch	etch	CMP

  Thermal SiO2	30	Å/min	175	Å/min	Ox: 500 Å/min	Nit: 1200 Å/min
  					Nit: <20 Å/min	Ox: 420 Å/min
  Spin-on glass
  (SOG)
  BPSG	1240	Å/min	7362	Å/min	8200 Å/min		1800 Å/min
  Polyimide
  	5	Å/min	8	Å/min

• There are numerous variations of the process illustrated inFIGS. 2A-2F. One such variation is shown inFIGS. 3A-3D.FIG. 3A is similar toFIG. 2D and shows the structure afterBPSG layer126 andoxide layer125 have been etched back until their top surfaces are below the surface ofsubstrate120. As shown inFIG. 3B, athin oxide layer140 is then thermally grown on the surface ofsubstrate120 and, as shown inFIG. 3C,nitride layer131 is then deposited. In thisembodiment oxide layer140 separatesnitride layer131 fromsemiconductor substrate120. Alternatively, an oxynitride layer may be deposited using chemical vapor deposition (CVD). Whennitride layer131 is planarized or etched back, as shown inFIG. 3D, the nitride cap that remains in the trench is not in contact with the sidewalls of the trench. While this cap may not provide as effective a seal as the embodiment show inFIG. 2F, the presence of oxide (or oxynitride)layer140 on the walls of the trench tends to reduce the stress that is attributable to the different thermal expansion coefficients of nitride and silicon, respectively. Oxide (or oxynitride)layer140 thus provides stress relief.
• Moreover, even ifoxide layer140 is over-etched to leave asmall gap150, as shown inFIG. 4,gap150 is nonetheless much smaller than therecess103, shown inFIG. 1C, and much easier to fill with a subsequent layer of, for example, BPSG. It is preferable, however, not to remove all ofoxide layer140.
• FIG. 5 is a flow chart summarizing the processes described above, each step being represented by a “card” (the clipped cards denoting optional steps). In the first sequence the trench is formed by depositing a hard mask layer (e.g., oxide or nitride), depositing a photoresist layer, patterning the photoresist layer to create a trench mask, etching the hard mask layer through an opening in the trench mask, optionally //the photoresist layer, and etching the trench through an opening in the hard mask layer.
• In the next sequence, optionally a sacrificial oxide layer can be formed on the walls of the trench and removed, a lining oxide layer is grown, the trench is filled with a dielectric (e.g., BPSG), and optionally the dielectric can be planarized by etching or CMP.
• Finally, the dielectric fill is etched back into the trench, optionally an oxynitride or oxide layer is grown or deposited on the walls of the trench, and a nitride layer is deposited and etched back until it is substantially coplanar with the top surface of the substrate.
• The examples above describe a structure wherein the surface of the substrate is essentially planar. Anon-planar structure200 is illustrated inFIG. 6A. Asubstrate205 has atop surface202. Atrench201 has been etched insubstrate205 and afield oxide region203 has been thermally grown in the substrate such that field oxide region extends upward beyond thesurface202 as well as downward into the substrate. Apolysilicon layer204 has been deposited on top offield oxide region203. As is apparent, there is a considerable height difference between the bottom oftrench201 and the top ofpolysilicon layer204. Iftrench201 is filled with a dielectric, an etchback can be used to planarize the surface of the dielectric withsurface202. Otherwise, if CMP is used to planarize the dielectric, it is clear thatpolysilicon layer204 as well as a portion offield oxide region203 will be removed.
• One solution to this problem is to omit the polysilicon204 (or to postpone the formation ofpolysilicon204 until later in the process flow) and to grow thefield oxide region203 thick enough that the portion below thesurface202 is sufficient to provide the necessary electrical characteristics.FIG. 6B showstrench201 lined with anoxide layer206 and filled withBPSG207, both of which have been etched back into the trench. The entire structure is covered with anitride layer208, which also fills the upper portion of the trench. InFIG. 6C, the top surface has been planarized by CMP, leaving the bottom portion209 offield oxide region203 and a protective nitride cap210 over theBPSG207 andoxide layer206. The top surface is totally flat. Since having a nonplanar top surface greatly complicates further processing, the flat structure shown inFIG. 6C is preferable to the structure shown inFIG. 6A. Furthermore, sincefield oxide region203 is grown by thermal means, the remaining region209 can be very wide, whereas the trench can be very narrow. To summarize, the structure shown inFIG. 6C includes a “capped” trench that is resistant to etching because of cap210 and an “uncapped” field oxide region209.
• As an alternative,FIGS. 7A-7H illustrate a process by which a wide isolation trench and a narrow isolation trench can be formed using a minimal number of steps.
• InFIG. 7A, ahard mask layer252 has been deposited on asubstrate251, and aphotoresist layer253 has been deposited on top ofhard mask layer252.Photoresist layer253 is etched to form a wide opening andhard mask layer252 is etched through the wide opening inphotoresist layer253 to form awide opening254 which exposes the surface ofsubstrate251.
• As shown inFIG. 7B,substrate251 is etched by RIE to form awide trench260.Photoresist layer253 is removed and anew photoresist layer257 is deposited. Iftrench260 is not too deep,photoresist layer257 will cover the step between the bottom oftrench260 and the top surface ofsubstrate251. A relatively narrow opening is etched inphotoresist layer257, andhard mask layer252 is etched through the opening inphotoresist layer257 to form anarrow opening256 which exposes the surface ofsubstrate251. Alternatively,layer257 may represent a deposited hard mask dielectric layer patterned and etched by a photoresist layer (not shown).
• As shown inFIG. 7C,substrate251 is etched by RIE to form anarrow trench261. Photoresist (or hard mask)layer257 andhard mask layer252 are then removed, or patterned and etched.
• Optionally, a sacrificial oxide layer (not shown) can be grown intrenches260 and261 and removed to repair any crystal damage resulting from the RIE processes. As shown inFIG. 7D, athin oxide layer262 is grown as a barrier against the diffusion of dopants intosubstrate251, and alayer263 of BPSG is deposited over the entire surface of the structure. Alternatively,layer263 could include any doped or undoped CVD-deposited or spin-on silicon oxide or silicate glass or any other dielectric “fill” material, provided that the dielectric fill material exhibits sufficiently low stress so as to avoid cracking during subsequent processing steps, during assembly, and during temperature variations encountered during device operation.
• Of course, the process sequence could be revised such that the narrower trench is formed before the wider trench.
• Next, as shown inFIG. 7E, the entire top surface of the structure is planarized by CMP or by a short chemical etchback followed by CMP.
• Optionally,oxide layer262 andBPSG layer263 are etched back (e.g., by an acid or dry etch) intotrenches260 and261 to formdepressions270 and271, as shown inFIG. 7F. A dielectric dissimilar to silicon dioxide, silicate glass, or BPSG (e.g., nitride or polyimide) is deposited over the top surface of the structure, as shown inFIG. 7G, and the top surface is again planarized to formprotective caps280 in the mouths oftrenches260 and261, shown inFIG. 7H. Unlike thedielectric fill material263, the material used to formcaps280 may comprise a brittle or high stress material, provided that the material is not eroded by the normal etches encountered during subsequent wafer processing in IC manufacturing and provided thatcaps280 are made sufficiently thin to avoid cracking.
• FIGS. 8A-8J illustrate a process for forming a capped isolation trench and capped field oxide region. As shown inFIG. 8A, apad oxide layer302 is grown onsilicon substrate301, and as in a typical local oxidation of silicon (LOCOS) sequence, anitride layer303 is deposited onpad oxide layer302. Pad oxide layer can be 300 to 1000 Å thick, for example.Nitride layer303 is etched through a mask layer (not shown) to form awide opening304 which exposespad oxide layer302. As shown inFIG. 8B, the structure is heated (for example, to 900-1100° C. for 1 to 4 hours) to form a thickfield oxide region305 inopening304. As is normal in a LOCOS process,nitride layer303 is lifted up by the expanding oxide at the edge of opening304, forming the familiar “bird's beak” shape. Next, the remaining portion ofnitride layer303 is etched (FIG. 8C), and the top surface is planarized by a CMP process, yielding the result shown inFIG. 8D, with a smooth transition between the remainingportion306 offield oxide region305 andpad oxide layer302.
• Next, as shown inFIG. 8E, aphotoresist layer308 is deposited and patterned to form a narrow opening309.Oxide layer307 is etched through opening309 and, as shown inFIG. 8F,substrate301 is etched by an RIE process to form anarrow trench310, withoxide layer307 acting as a hard mask. The remains ofoxide layer307 may be removed in a short cleaning step.
• As shown inFIG. 8G, athin oxide layer311 is grown on the walls oftrench310 and alayer312 of BPSG or any other dielectric filler is deposited. The top surface ofsubstrate301 is planarized by etching or CMP.
• As shown inFIG. 8H,oxide layer311 andBPSG layer312 intrench310 and the remainingportion306 offield oxide region305 are etched back until the top surfaces of these elements are below the top surface ofsubstrate301. Alayer315 of a dissimilar dielectric such as nitride is deposited over the structure (FIG. 8I), and the structure is again subjected to a CMP process to planarize the top surface and create protective caps316 overtrench310 and field oxide306 (FIG. 8J).
• FIGS. 9A-9E illustrate a process that produces a structure having field doping regions under the field oxide isolation regions but not under the trench isolation structures.
• InFIG. 9A, apad oxide layer351 has been grown onsilicon substrate350, and anitride layer352 andphotoresist layer353 have been deposited in that order on top ofpad oxide layer351.Photoresist layer353 is patterned to form twoopenings354A and354B, andnitride layer352 is etched throughopenings354A and354B to exposepad oxide layer351. Phosphorus (P+) is implanted throughopenings354A and354B to form N-type regions356A. The dose of the phosphorus implant is typically in the range of 5×10¹²to 3×10¹³cm⁻²and the implant energy is typically from about 80 to 120 keV. Alternatively, a layer of polyimide may be substituted fornitride layer352 and may be used to form the hard mask for etching trench374.
• As shown inFIG. 9B,photoresist layer353 is removed, and anew photoresist layer355 is deposited and patterned to form an opening that includes the location offormer opening354B inphotoresist layer353. Boron (B+) is implanted through the opening inphotoresist layer355 to form a P-type region356B. Since the dose of the boron implant is typically an order of magnitude greater than the phosphorus implant (e.g., 8×10¹³to 2×10¹⁴cm⁻²) the boron counterdopes the phosphorus region under opening354B to form P-type region356B. The energy of the boron implant is typically 60 to 120 keV.
• Next, as shown inFIG. 9C, the structure is heated to form thick field oxide regions370A and370B in the locations ofopenings354A and354B. Field oxide regions370A and370B could be from 2000 Å to 2 μm in thickness (typically about 0.8 μm). This thermal process also activates the phosphorus and boron dopants and forms an N-type field doping region358A under field oxide region370A and a P-type field doping region358B under field oxide region370B.
• The remains ofnitride layer352 are removed (FIG. 9D), and optionally a sacrificial oxidation may be preformed. Next, as shown inFIG. 9E, a trench374 is etched and oxidized to form anoxide layer371, followed by a dielectric fill with a material such asBPSG372 in the manner described previously. The top surface of the structure is planarized by CMP or etchback, andoxide layer371,BPSG372 and the remains of field oxide regions370A and370B are etched back in the manner described above. A layer of nitride (or another dielectric dissimilar to the material used to fill trench374) is deposited on the top surface, and the surface is then planarized to formprotective caps373.
• This process yields a relatively narrow trench with no field doping which might be used to isolate low-voltage devices, for example, and wide field oxide regions with field doping which might be used to isolate high-voltage CMOS devices, for example. The process gives the designer the ability to form isolation regions of different widths and different field dopings in the same semiconductor substrate, with a flat top surface to simply any further processing. Moreover, the isolation regions can be formed with protective caps, if desired.
• In some embodiments, the material in the trench is protected by a graded dielectric fill in lieu of a discrete trench cap. In such embodiments, the trench is at least partially filled with a mixture of a relatively soft, low stress dielectric and a relatively hard, etch resistant dielectric. The proportion of the relatively hard, etch resistant dielectric in the mixture increases as one approaches the mouth of the trench. For example, a mixture of silicon dioxide and silicon nitride may be deposited in the trench, with the percentage of silicon nitride in the mixture being increased near the mouth of the trench.
• While specific embodiments of this invention have been described, it should be understood that these embodiments are illustrative only, and not limiting. Many additional or alternative embodiments in accordance with the broad principles of this invention will be apparent to those of skill in the art.

Claims (46)

1. A method of forming an isolation structure in a semiconductor substrate comprising:

forming a trench in the semiconductor substrate;

depositing a first dielectric material in the trench;

removing a portion of the first dielectric material such that a surface of the first dielectric material is located at a first level below a second level of a surface of the substrate, thereby forming a recess;

depositing a second dielectric material in the recess; and

removing a portion of the second dielectric material such that a surface of the second dielectric material is substantially coplanar with the surface of the substrate, thereby forming a protective cap in the trench.

2. The method ofclaim 1 wherein the second dielectric material is relatively more resistant to removal by normal semiconductor etch processes as compared with the first dielectric material.

3. The method ofclaim 2 wherein the second dielectric material comprises one or more materials selected from the group consisting of silicon nitride and polyimide.

4. The method ofclaim 2 wherein the first dielectric comprises one or more materials from the group consisting of the doped and undoped silicon oxides and silicate glasses.

5. The method ofclaim 4 wherein the first dielectric material comprises borophosphosilicate glass.

6. The method ofclaim 1 wherein removing a portion of the second dielectric material comprises chemical-mechanical polishing.

7. The method ofclaim 1 wherein removing a portion of the second dielectric material comprises etching.

8. The method ofclaim 1 comprising forming an oxide layer on a wall of the trench after removing a portion of the first dielectric material and before depositing a second dielectric material.

9. The method ofclaim 1 comprising forming an oxide layer on a wall of the trench before depositing a first dielectric material in the trench.

10. The method ofclaim 9 wherein the first dielectric material is doped.

11. The method ofclaim 1 wherein a distance from a bottom of the trench to the bottom of the protective cap is significantly greater than a thickness of the protective cap.

12. The method ofclaim 1 further comprising:

thermally forming a field oxide region at a surface of the semiconductor substrate, the field oxide region extending both above and below the surface of the substrate; and

removing a portion of the field oxide region such that a surface of the field oxide region is substantially coplanar with the surface of the substrate.

13. The method ofclaim 12 wherein removing a portion of the field oxide region comprises chemical-mechanical polishing.

14. The method ofclaim 13 wherein removing a portion of the second dielectric material and removing a portion of the field oxide region are performed in the course of a single chemical-mechanical process.

15. The method ofclaim 12 comprising:

removing a portion of the field oxide region such that the surface of the field oxide region is at a third level below the second level, thereby forming a second recess over a remaining portion of the field oxide region;

depositing the second dielectric material in the second recess; and

removing a portion of the second dielectric material such that a surface of the second dielectric material in the second recess is substantially coplanar with the surface of the substrate, thereby forming a second protective cap over the remaining portion of the field oxide region.

16. A method of forming an isolation structure in a semiconductor substrate comprising:

depositing a first mask layer on the substrate;

depositing a second mask layer on the first mask layer;

patterning the second mask layer to form a first opening having a first width;

etching the first mask layer through the first opening to form a second opening having a width substantially equal to the first width;

etching the substrate through the second opening to form a first trench having a width substantially equal to the first width;

removing the second mask layer;

depositing a third mask layer over a remaining portion of the first mask layer;

patterning the third mask layer to form a third opening having a second width, the second width being unequal to the first width;

etching the first mask layer through the third opening to form a fourth opening having a width substantially equal to the second width;

etching the substrate through the fourth opening to form a second trench having a width substantially equal to the second width;

depositing a layer of a first dielectric material so as to fill the first and second trenches;

removing a portion of the first dielectric material such that surfaces of the first dielectric material in the first and second trenches, respectively, are located at a first level, the first level being no higher than a plane substantially coplanar with a surface of the substrate.

17. The method ofclaim 16 wherein the first level is substantially coplanar with the surface of the substrate.

18. The method ofclaim 16 wherein removing a portion of the first dielectric material comprises removing a portion of the first dielectric material such that surfaces of the first dielectric material in the first and second trenches, respectively, are located below a plane defined by the surface of the substrate, thereby forming a first recess in the first trench and a second recess in the second trench.

19. The method ofclaim 18 comprising;

depositing a second dielectric material in the first and second recesses; and

removing a portion of the second dielectric material such that surfaces of the second dielectric material in the first and second trenches are substantially coplanar with the surface of the substrate, thereby forming a first protective cap in the first trench and a second protective cap in the second trench.

20. The method ofclaim 19 wherein the second dielectric material is relatively more resistant to removal by normal semiconductor processes as compared with the first dielectric material.

21. The method ofclaim 20 wherein the second dielectric material comprises one or more materials selected from the group consisting of silicon nitride and polyimide.

22. The method ofclaim 20 wherein the first dielectric comprises one or more materials from the group consisting of the doped and undoped silicon oxides and silicate glasses.

23. The method ofclaim 22 wherein the first dielectric material comprises borophosphosilicate glass.

24. A method of forming an isolation structure in a semiconductor substrate comprising:

depositing a first mask layer on the substrate;

depositing a second mask layer on the first mask layer;

patterning the second mask layer to form a first opening in the second mask layer;

etching the first mask layer through the first opening to form a second opening in the first mask layer;

implanting a first dopant of a first conductivity type through the second opening to form a first region of the first conductivity type under the second opening;

removing the second mask layer;

heating the substrate so as to form a first field oxide region in the second opening of the first mask layer;

forming a trench in the substrate;

depositing a first dielectric material in the trench;

removing a portion of the first dielectric material such that a surface of the first dielectric material is located at a first level below a second level of a surface of the substrate, thereby forming a first recess over a remaining portion of the first dielectric material;

removing a portion of the first field oxide region such that a surface of the first field oxide region is located at a third level below the second level, thereby forming a second recess over a remaining portion of the first field oxide region;

depositing a second dielectric material in the recesses; and

removing portions of the second dielectric material such that surfaces of the second dielectric material in the recesses are substantially coplanar with a surface of the substrate.

25. The method ofclaim 24 wherein the second dielectric material is relatively more resistant to removal by normal semiconductor etch processes as compared with the first dielectric material.

26. The method ofclaim 25 wherein the second dielectric material comprises one or more materials selected from the group consisting of silicon nitride and polyimide.

27. The method ofclaim 26 wherein the first dielectric comprises one or more materials from the group consisting of the doped and undoped silicon oxides and silicate glasses.

28. The method ofclaim 27 wherein the first dielectric material comprises borophosphosilicate glass.

29. The method ofclaim 1 wherein removing portions of the second dielectric material comprises chemical-mechanical polishing.

30. The method ofclaim 1 wherein removing portions of the second dielectric material comprises etching.

31. An isolation structure formed in a trench in a semiconductor substrate comprising:

a first dielectric material located in a lower portion of the trench;

a second dielectric material located in an upper portion of the trench, the lower portion being larger than the upper portion;

a surface of the second dielectric material being substantially coplanar with a surface of the substrate.

32. The isolation structure ofclaim 31 wherein the second dielectric layer is relatively more resistant to removal by normal semiconductor etch processes as compared with the first dielectric material.

33. The isolation structure ofclaim 31 wherein the second dielectric material comprises one or more materials selected from the group consisting of silicon nitride and polyimide.

34. The isolation structure ofclaim 31 wherein the first dielectric comprises one or more materials from the group consisting of the doped and undoped silicon oxides and silicate glasses.

35. The isolation structure ofclaim 34 wherein the first dielectric material comprises borophosphosilicate glass.

36. The isolation structure ofclaim 31 comprising a first oxide layer along a side wall of the trench, the first oxide layer separating the first dielectric layer from the substrate.

37. The isolation structure ofclaim 36 comprising a second oxide layer along a side wall of the trench, the second oxide layer separating the second dielectric layer from the substrate.

38. A semiconductor substrate comprising:

a first isolation structure comprising a first trench formed in the semiconductor substrate, the first trench being filled with a first dielectric material, a surface of the first dielectric material being substantially coplanar with a surface of the substrate; and

a second isolation structure comprising a second trench formed in the semiconductor substrate, the second trench being filled with a second dielectric material, a surface of the second dielectric material being substantially coplanar with the surface of the substrate,

wherein the first trench is deeper than the second trench and the second trench is wider than the first trench.

39. The semiconductor substrate ofclaim 38 wherein an oxide layer is formed on the walls of each of the first and second trenches.

40. The semiconductor substrate ofclaim 38 wherein the first dielectric material comprises a first layer of a third dielectric material and a second layer of a fourth dielectric material, the second layer being disposed above the first layer in the first trench, a surface of the second layer being substantially coplanar with the surface of the substrate; and wherein the second dielectric material comprises a third layer of the third dielectric material and a fourth layer of the fourth dielectric material, the fourth layer being disposed above the third layer in the second trench, a surface of the fourth layer being substantially coplanar with the surface of the substrate.

41. The semiconductor substrate ofclaim 40 wherein the fourth dielectric material is relatively more resistant to removal by normal semiconductor etch processes as compared with the third dielectric material.

42. The semiconductor substrate ofclaim 41 wherein a first oxide layer lines a wall of the first trench, the first oxide layer separating the first layer from the semiconductor substrate.

43. The semiconductor substrate ofclaim 41 wherein a second oxide layer lines a wall of the second trench, the second oxide layer separating the third layer from the semiconductor substrate.

44. A semiconductor substrate comprising:

a first isolation structure comprising a trench formed in the semiconductor substrate, the trench being filled with a first dielectric material, a surface of the first dielectric material being substantially coplanar with a surface of the substrate; and

a second isolation structure comprising a field oxide region, a surface of the field oxide region being substantially coplanar with the surface of the substrate,

wherein the trench is deeper than the field oxide region and the field oxide region is wider than the trench.

45. A semiconductor substrate comprising:

a first isolation structure comprising a trench, the trench comprising a first layer of a first dielectric material and a second layer of a second dielectric material, the second layer being disposed above the first layer in the trench, a surface of the second layer being substantially coplanar with a surface of the substrate, wherein the second dielectric material is relatively more resistant to removal by normal semiconductor etch processes as compared with the first dielectric material; and

a second isolation structure comprising a field oxide region, a surface of the first oxide region being recessed with respect to the surface of the substrate, and a third layer of a second dielectric material overlying the field oxide region, a surface of the third layer being substantially coplanar with the surface of the substrate, wherein the second dielectric material is relatively more resistant to removal by normal semiconductor etch processes as compared with the field oxide region.

46. An isolation structure formed in a trench in a semiconductor substrate comprising a mixture of a first dielectric material and a second dielectric material, the proportion of the second dielectric material in the mixture increasing with decreasing depth in the trench, wherein the second dielectric material is relatively more resistant to removal by normal semiconductor etch processes as compared with the first dielectric material.

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