US20070117347A1 - Semiconductor constructions - Google Patents

Abstract

The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region of the opening. Subsequently, the opening can be filled with insulative material to form an isolation region. Transistor devices can then be formed on opposing sides of the isolation region, and electrically isolated from one another with the isolation region. The invention also includes semiconductor constructions containing an electrically insulative isolation structure extending into a semiconductor material, with the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.

Description

TECHNICAL FIELD
• The invention pertains to semiconductor processing methods, and to semiconductor constructions.
BACKGROUND OF THE INVENTION
• As the level of integration of integrated circuitry increases, it is becoming an ever greater challenge to maintain electrical isolation between adjacent electrical devices. For instance, the density of dynamic random access memory (DRAM) has been approximately quadrupled every three years by virtue of advances in DRAM technology. As the device dimensions scale down, it is becoming more and more challenging to maintain electrical isolation (especially cell-to-cell isolation) in the memory array region due to reduction of space for isolation structures. A common isolation structure is a trenched isolation structure (such as, for example, a shallow trench isolation structure), and it is becoming increasingly challenging to form and fill the trenches of such isolation structures within the ever-decreasing real estate available for the structures.
• Cell-to-cell isolation is becoming a greater factor in causing failure of integrated circuitry, with such failure frequently being due to leakage around a trenched isolation region. Field implants have been utilized in an attempt to prevent leakage around trenched isolation structures, but such can create problems with refresh.
• Cell-to-cell isolation is already problematically challenging, and is expected to become even more challenging for future generations of devices due to the tighter pitch and smaller space available for isolation structures of the future. Accordingly, it is desirable to develop new isolation structures. It would be particularly desirable for such isolation structures to be suitable for cell-to-cell isolation.
SUMMARY OF THE INVENTION
• In one aspect, the invention includes a semiconductor processing method. A semiconductor material is provided, and an opening is formed to extend into the semiconductor material. An upper periphery of the opening is provided with a liner while at least a portion of a lower periphery of the opening is unlined. Etching is conducted through the unlined portion to form a bulbous extension of the opening, and such bulbous extension is substantially filled with insulative material.
• In one aspect, the invention encompasses a semiconductor processing method. A semiconductor material is provided and an opening is formed to extend into the semiconductor material to a first depth. A periphery of the opening is lined with a protective liner, except for the lower region of the opening. Etching is conducted through the unlined lower region of the opening with an etch that is at least substantially isotropic to form a widened extension of the opening.
• In one aspect, the invention encompasses a semiconductor processing method. A silicon-containing material is provided. An opening is formed to extend into the silicon-containing material. The opening has a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the silicon-containing material. The opening is substantially filled with insulative material. A first transistor device is formed on one side of the opening, with the first transistor device having a pair of first source/drain regions extending into the silicon-containing material. A second transistor device is formed on an opposing side of the opening from the first transistor device, with the second transistor device having a pair of second source/drain regions extending into the silicon-containing material. The insulative material within the opening is utilized to provide electrical isolation between the first and second transistor devices.
• In one aspect, the invention includes a semiconductor construction. The construction comprises a semiconductor material and an electrically insulative structure extending into the semiconductor material. The electrically insulative structure has a bulbous bottom region and a stem extending upwardly from the bottom region to a surface of the semiconductor material. The construction can further include a first transistor device on one side of the electrically insulative structure and a second transistor device on an opposing side of the electrically insulative structure, with the insulative material of the insulative structure providing electrical isolation between the first and second transistor devices.
BRIEF DESCRIPTION OF THE DRAWINGS
• Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
• FIG. 1 is a diagrammatic, cross-sectional view of a semiconductor wafer fragment at a preliminary processing stage of an exemplary aspect of the present invention.
• FIG. 2 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 1.
• FIG. 3 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 2.
• FIG. 4 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 3.
• FIG. 5 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 4.
• FIG. 6 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 5.
• FIG. 7 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 6.
• FIG. 8 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 7.
• FIG. 9 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 8.
• FIG. 10 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 9.
• FIG. 11 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 9 in accordance with an aspect alternative to that ofFIG. 10.
• FIG. 12 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 4 in accordance with an aspect of the invention alternative to that ofFIG. 5.
• FIG. 13 is a view of theFIG. 1 wafer fragment shown at a processing stage subsequent to that ofFIG. 12.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
• The invention includes processes in which bottom regions of openings or trenches are expanded. In particular aspects, the openings having expanded bottom regions are filled with insulative material to create trenched isolation structures. Such isolation structures can provide improvements relative to prior art isolation structures for cell-to-cell isolation in a memory array. Some specific applications of the invention utilize isolation structures formed in accordance with the invention to improve refresh and functionality of devices associated with a memory array relative to the refresh and functionality that would occur in prior art constructions. In some aspects of the invention, the expanded bowl (i.e., expanded bottom region) of an isolation region formed in accordance with the invention is kept relatively far away from channel regions of access devices so that operating parameters of the devices (for example, channel length and drive current) are not adversely impacted by the utilization of the isolation region of the present invention.
• A particular aspect of the invention is described with reference toFIGS. 1-10.
• Referring toFIG. 1, asemiconductor construction10 is illustrated at a preliminary processing stage.Construction10 comprises asubstrate12. The substrate can comprise, consist essentially of, or consist of monocrystalline silicon lightly doped with suitable background dopant, and in particular aspects can comprise, consist essentially of, or consist of monocrystalline silicon lightly background doped with p-type dopant. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
• Although silicon is one exemplary semiconductor material that can be incorporated intosubstrate12, it is to be understood that the substrate can comprise other semiconductor materials, including, for example, germanium.
• Alayer14 comprising, consisting essentially of, or consisting of silicon dioxide is formed oversubstrate12; and alayer16 comprising, consisting essentially of, or consisting of silicon nitride is formed overlayer14. Thelayers14 and16 are together patterned to form a hard mask oversubstrate12. The patterned hard mask has an opening18 extending therethrough to an upper surface ofsubstrate12.Layers14 and16 can be patterned through any suitable processing, including, for example, forming photolithographically patterned photoresist overlayer16, transferring a pattern from the photoresist to theunderlying layers14 and16, and subsequently removing the photoresist.
• Referring toFIG. 2, opening18 is extended into semiconductor material ofsubstrate12. The opening is extended with a suitable anisotropic etch, and can be extended to any suitable depth within the substrate. For instance, if opening18 is ultimately to be used in forming a trenched isolation region, the opening can be extended to a depth approximately equal to that conventionally utilized for trenched isolation regions. The opening can have any suitable shape, and in particular aspects can be a trench extending longitudinally into and out of the page relative to the cross-sectional view ofFIG. 2.
• Theopening18 has a maximumcross-sectional width19 extending transversely across the opening at a widest portion of the opening withinsubstrate12. Such width can be any suitable width, and in particular aspects will be a width of less than or equal to about 100 nanometers.
• Referring next toFIG. 3, aliner20 is formed along a periphery ofopening18. The shown liner extends only alongsemiconductor material substrate12, and not along maskingmaterials14 and16. However, it is to be understood that the invention also encompasses some aspects (not shown) in which the liner extends along exposed surfaces oflayers14 and16, as well as along exposed surfaces ofsemiconductor material substrate12.
• Liner20 can comprise any material suitable for protecting surfaces ofsubstrate12 during a subsequent etch (discussed below). For instance,liner20 can comprise, consist essentially of, or consist of silicon dioxide. In such aspects, the liner can be formed by depositing silicon dioxide within the opening, and/or can be formed by thermal oxidation of exposed surfaces of a silicon-containingsubstrate12 within the opening. Ifsubstrate12 comprises semiconductor materials other than silicon, the oxide formed within the opening asliner20 can be an oxide other than silicon dioxide. The oxidation utilized to formliner20 can, for example, comprise oxidation with an O₂plasma, either in situ or ex situ, and in some aspects chlorine can also be incorporated into the oxidation chemistry.
• In some aspects of the invention,liner20 can comprise, consist essentially of, or consist of a polymeric organic material (or, in other words, an organic polymer). For instance, the liner can comprise, consist essentially of, or consist of a combination of carbon, hydrogen and fluorine. In such aspects, the polymer can be formed from one or more of CHF₃, CH₂F₂, CH₃F, CF₄, CH₄, C₂H₆, C₂H₄, NH₃, and HBr. If the liner comprises an organic polymer, such can be directly on semiconductor material of substrate12 (as shown), or can be over an intervening layer, such as, for example, a thin layer of native oxide.
• The deposition conditions utilized for formingliner20 can comprise moderate to high pressure, and low bias voltage to uniformly deposit the liner withinopening18. If the liner comprises a polymeric organic material, the liner can be deposited over exposed surfaces oflayers14 and16 in addition to being deposited along exposed surfaces ofsemiconductor material substrate12 withinopening18.
• Referring next toFIG. 4,liner20 is subjected to an anisotropic etch which removes the liner from along a lower region of opening18 while leaving the liner along an upper region of the opening. Theliner20 appears to be broken into two separate segments in the shown cross-sectional view ofFIG. 4. It is to be understood, however, that opening18 can have a continuous sidewall if viewed from above, and thatliner20 can thus extend all the way around a lateral periphery of the sidewall at the processing stage ofFIG. 4.
• In some aspects, opening18 can be considered to have an upper periphery and a lower periphery, with the lower periphery including, but not being limited to, a bottom-most portion of the opening. The shown etch has removed the liner from over the bottom-most portion of the opening, and not removed liner from regions above the bottom-most portion. The delineation between the upper periphery of the opening and the lower periphery of the opening can occur at any location within the opening, with the general understanding being that the liner remaining at the processing stage ofFIG. 4 protects an entirety of the upper periphery of the opening, and that at least a portion of the lower periphery of the opening is unlined. The unlined portion of the lower periphery can be the bottom-most portion of the lower periphery, can be a region proximate the bottom-most portion of the lower periphery, or can be some combination of the bottom-most portion of the opening and a region proximate the bottom-most portion of the opening.
• The etch chemistry utilized to removeliner20 from the lower periphery of the opening can be any suitable etch chemistry. For instance, ifliner20 comprises, consists essentially of, or consists of silicon dioxide or an organic polymer, the etch can utilize one or more of CF₄, CHF₃, CH₂F₂, HBr, and Cl₂; and would typically be conducted at low pressure and with a moderate to high bias. The bias can cause the etch to be highly anisotropic.
• The construction ofFIG. 4 can be considered to contain anopening18 extending into semiconductor material ofsubstrate12, with an upper periphery of the opening protected by theliner20 and at least a portion of a lower periphery of the opening being unlined. Alternatively, the unlined portion of the opening can be considered to be an unlined lower region of the opening, and the lined portion of the opening can be considered to be a lined upper region of the opening.
• Referring next toFIG. 5, theliner20 is utilized to protect sidewalls of opening18 while the unlined portion of opening18 is exposed to an etch. The etch is typically isotropic, substantially isotropic, or at least a transition etch between an anisotropic etch and an isotropic etch. The etch widens the lower portion of opening18 to form a widenedextension30 of the opening. In the shown aspect of the invention, the widenedextension30 is a bulbous extension.
• The etch utilized to form widenedextension30 can comprise any suitable etch chemistry, and in particular aspects will comprise substantially isotropic chemistry selective for semiconductor material of substrate12 (such semiconductor material can be silicon, for example) relative to the silicon dioxide oflayer14, the silicon nitride oflayer16, and the material ofliner20. The etch chemistry can, for example, be based on NF₃and/or SF₆, and can also include one or more of HBr, CHF₃, CH₂F₂and O₂as moderating agents (with such moderating agents being specifically included to suppress lateral etching so that thebowl30 ends up being relatively circular in configuration rather than being overly-elongated in lateral directions). The etching can be accomplished utilizing either wet etch or dry etch processes.
• Although the etching utilized to form the widened regions of the opening can be isotropic etching, it is to be understood that the etching would typically be substantially isotropic, rather than absolutely isotropic. In other words, the etch will typically have some minor anisotropic component either purposely or due to, for example, difficulties in creating an absolutely isotropic etch; but will be mostly isotropic. For purposes of interpreting this disclosure and the claims that follow, the phrase “at least substantially isotropic” is to be understood to comprise substantially isotropic conditions and absolutely isotropic conditions.
• The cross-sectional configuration ofFIG. 5 can be considered to comprise anopening18 having a configuration of anarrow stem region34 extending upwardly from a widenedbottom region30. The shown widenedregion30 has relativelysharp corners32 where the widened regions joins with the narrow region of the opening. The sharpness of thecorners32 can be modified by coupling an anisotropic first etch with an isotropic second etch during formation of widenedregion30, as will be discussed in more detail with reference toFIGS. 12 and 13 below. It is to be understood that theopening18 can be in the shape of a trench extending longitudinally into and out of the page relative to the shown cross-sectional view ofFIG. 5.
• Referring toFIG. 6, liner20 (FIG. 5) is removed from within thestem region34 ofopening18. Such removal can be accomplished with any suitable etch chemistry.
• Theopening18 ofFIG. 6 can have any suitable dimensions. In some aspects, the stem region can have a maximumcross-sectional width19 of less than about 100 nanometers, and in particular aspects will have a maximum cross-sectional width of from about 50 nanometers to about 100 nanometers. The widenedregion30 can have a maximumcross-sectional width36 that is at least 10 nanometers greater than thewidth19, and in particular aspects can be from about 20 nanometers greater to about 80 nanometers greater than thewidth19 in the shown cross-sectional view (in other words, can extend from about 10 nanometers to about 40 nanometers laterally outward on either side of the original most-laterally-outward sidewall edges of opening18 in the shown cross-sectional view).
• Referring toFIG. 7, opening18 is filled withmaterial40. In particular aspects of the invention, opening18 is ultimately utilized to form an electrical isolation region extending withinsubstrate12, and accordingly material40 can correspond to an electrically insulative material. In such aspects,material40 can comprise any suitable electrically insulative composition or combination of compositions, and can, for example, comprise, consist essentially of, or consist of silicon dioxide. Although thematerial40 is shown filling an entirety of opening18, it is to be understood that the invention encompasses other aspects (not shown) in which the material only fills a portion ofopening18. For instance,material40 can substantially fill thebulbous extension30 without entirely filling the rest of the opening, or can substantially fill thebulbous region30 and also substantially fill thestem region34 extending upwardly from the bulbous region.
• Although the shown aspect of the invention has the liner removed from within the stem region, it is to be understood that the invention also encompasses aspects in which the liner remains within the stem region as opening18 is filled with various materials. For instance, if the liner comprises silicon dioxide, and the stem region is ultimately going to be filled with silicon dioxide to form an isolation region, the silicon dioxide of the liner can remain within the stem region. However, it can be advantageous to clean the liner from within the stem region in order to remove contaminating materials that may have accumulated on the liner during the processing of forming theopening30, regardless of whether or not the liner otherwise comprises a composition suitable for incorporation into materials that are going to be utilized to fill the opening.
• Referring next toFIG. 8,construction10 is subjected to polishing (such as, for example, chemical-mechanical polishing) to form a planarizedupper surface41 extending acrosslayer16 and across an upper surface ofinsulative material40. The planarization can stop at about an uppermost surface oflayer16, or in some aspects can extend intolayer16.
• Referring toFIG. 9, layers14 and16 (FIG. 8) are removed. The structure comprisinginsulative material40 can, in some aspects, be an isolation structure, and can be considered to correspond to a trenched isolation structure. Such isolation structure has, in the shown cross-sectional view, the widened base30 (which can also be referred to as a bulbous region or bowl region) and thestem34 extending upwardly from such base. Circuit devices can be provided on opposing sides of the isolation structure, and the structure can then be utilized to provide electrical separation between the devices.
• FIG. 10 illustrates an exemplary construction utilizing the isolation structure ofmaterial40 to provide electrical isolation between afirst transistor device50 and asecond transistor device60. The first transistor device is formed on one side of the isolation structure, and the second transistor device is formed on an opposing side of the isolation structure. The first transistor device comprises atransistor gate52 comprising agate dielectric material54, aconductive gate material56, and aninsulative cap58. The gate dielectric can, for example, comprise, consist essentially of, or consist of silicon dioxide. The conductive gate material can comprise any suitable electrically conductive composition or combination of compositions, and in particular aspects will comprise one or more of various metals, metal compositions, and conductively-doped semiconductor material (such as, for example, conductively-doped silicon). Electricallyinsulative cap58 can comprise any suitable electrically insulative composition or combination of compositions, and in particular aspects will comprise one or both of silicon nitride and silicon dioxide.
• A pair of source/drain regions57 areproximate gate52, and are electrically coupled to one another through a channel region beneathgate52 and controlled bygate52. Source/drain regions57 comprise conductively-doped diffusion regions extending intosubstrate12, and can comprise one or both of p-type dopant and n-type dopant. The shown source/drain regions57 comprise lightly-dopedextensions59 and heavily-dopedregions55, as will be recognized by persons of ordinary skill in the art.
• Transistor device50 is shown to comprisesidewall spacers53 beside thegate52. Such sidewall spacers can comprise any suitable composition or combination of compositions, and in particular aspects will comprise, consist essentially of, or consist of one or both of silicon nitride and silicon dioxide.
• Transistor device60 comprises agate62 containinggate dielectric64,conductive gate material66, and aninsulative cap68. Thegate dielectric64,conductive gate material66 andinsulative cap68 can comprise the same compositions as discussed above forgate dielectric54,conductive gate material56, andinsulative cap58.Transistor device60 also comprises source/drain diffusion regions67 extending intosubstrate12, and having lightly-dopedextensions69 and heavily-dopedregions65. In some aspects, source/drain regions57 can be referred to as first source/drain regions, and source/drain region67 can be referred to as second source/drain regions.
• Thesecond transistor device60 comprisessidewall spacers63 which are analogous to thesidewall spacers53, and which can comprise the same compositions discussed previously forsidewall spacers53.
• The cross-sectional view of the construction ofFIG. 10 has the source/drain regions57 and67 entirely abovebulbous region30, and spaced frombulbous region30 bygaps70 between the source/drain regions and the bulbous region. In some aspects of the invention, it can be advantageous to formisolation structure40 with the bulbous region more shallow than that ofFIG. 10 so that source/drain regions of adjacent transistor devices extend to the bulbous region. For instance,FIG. 11 shows a structure similar toFIG. 10, but with the source/drain regions oftransistor devices50 and60 extending tobulbous region30 of the isolation structure. The structures ofFIG. 11 are labeled identically to the structures ofFIG. 10.
• It can be advantageous to form the source/drain regions of adjacent transistor devices to extend down to thebulbous region30 ofisolation structure40 to remove a source of junction leakage. Alternatively, it can be advantageous to form structures of the type shown inFIG. 10 where the source/drain regions are well above thebulbous region30 ofisolation structure40 so that the bulbous region does not impact performance of adjacent transistor devices other than providing better electrical isolation between the devices than can be achieved with prior art isolation regions.
• Although the isolation regions ofFIGS. 10 and 11 have thestem34 extending upwardly above an uppermost surface ofsubstrate12, it is to be understood that the invention encompasses other aspects (not shown) in which the stem is further polished after removal oflayers14 and16 (FIG. 8) so that the stem has an uppermost surface which is approximately coplanar with an uppermost surface ofsubstrate12.
• The aspect of the invention discussed above with reference toFIG. 5 pertained to an embodiment of the invention in which an isotropic etch was conducted immediately after removing the liner from along a bottom portion of theopening18 ofFIG. 4. Another aspect of the invention comprises a first anisotropic etch through the unlined portion of the opening followed by the isotropic etch. Utilization of the first anisotropic etch can enable the corners adjacent the bulbous region (such as, for example, thecorners32 shown inFIG. 5) to have controlled sharpness. The aspect of utilizing the anisotropic etch/isotropic etch combination to control corner sharpness is described with reference toFIGS. 12 and 13.
• Referring initially toFIG. 12,construction10 is shown at a processing stage subsequent to that ofFIG. 4. Identical numbering is utilized in describingFIG. 12 as was used above in describing the embodiment ofFIG. 4. Thus, theconstruction10 is shown to comprise thelayers16 and14 oversubstrate12, and is shown to have theopening18 extending intosubstrate12. The processing stage ofFIG. 12 hasopening18 extended to a greater depth than the opening is at the processing stage ofFIG. 4 due to utilization of an anisotropic etch to extend the opening through the unlined portion ofFIG. 4.
• Referring toFIG. 13, an isotropic etch is subsequently utilized to form thebowl region30 ofopening18. The aspect ofFIG. 13 hassmoother corners32 where the bowl region meets thestem region34 than did the aspect ofFIG. 5. In some applications of the invention, NF₃and HBr are utilized for the isotropic etching ofFIG. 13 as well as for the anisotropic etching ofFIG. 12, and the amount of downward direction of the etch relative to sideward direction of the etch is controlled by the ratio of NF₃to HBr. An isotropic etch will typically etch about 70% downward relative to the amount that it etches laterally, and an etch which does greater than 70% downward relative to the amount that it etches laterally is typically considered to be an anisotropic etch.
• The smoothness of the transition between thebulbous region30 and thestem region34 of opening18 ofFIG. 13 can improve characteristics of an isolation structure formed within the opening relative to the embodiment ofFIG. 5. In some aspects, the transition between the stem region and widenedregion30 can be smoothed by thermal oxidation utilized during formation of insulative material within opening18 in addition to, or alternatively to, utilization of the anisotropic etch through the unlined portion prior to the isotropic etch.
• The various aspects to the invention discussed above with reference toFIGS. 1-13 can be utilized for numerous applications. In some applications, the invention can be utilized for forming new trenched isolation structures (for example, shallow trenched isolation structures) for improving cell-to-cell isolation in memory arrays (for example, dynamic random access memory arrays). The invention incorporates a relatively minor change in standard trench isolation processes, and accordingly can be economically incorporated into conventional processes. By adjusting the isolation region depth, and by adjusting the size of the bowl formed at the bottom of the isolation region, cell side junction leakage can be reduced by shutting down part of a junction leakage path, which can help data retention. The structures of the present invention can be applicable for current and future DRAM generations, and can be incorporated into processing without adding new masks or complicated new processing levels.
• In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (9)

1-26. (canceled)

27: A semiconductor construction, comprising:

a semiconductor material; and

an electrically insulative material structure extending into the semiconductor material, the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.

28: The construction ofclaim 27 wherein the semiconductor material comprises silicon.

29: The construction ofclaim 27 wherein the semiconductor material consists essentially of silicon.

30: The construction ofclaim 29 wherein the insulative material consists essentially of silicon dioxide.

31: The construction ofclaim 27 further comprising:

a first transistor device on one side of the electrically insulative structure, the first transistor device having a pair of first source/drain regions extending into the semiconductor material;

a second transistor device on an opposing side of the electrically insulative structure from the first transistor device, the second transistor device having a pair of second source/drain regions extending into the semiconductor material; and

the insulative material providing electrical isolation between the first and second transistor devices.

32: The construction ofclaim 31 wherein one of the first source/drain regions extends to the bulbous bottom region.

33: The construction ofclaim 32 wherein one of the second source/drain regions extends to the bulbous bottom region.

34: The construction ofclaim 31 wherein the first and second source/drain regions are entirely above the bulbous bottom region.

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