US20070111606A1 - Buffered Thin Module System and Method - Google Patents

Abstract

Multiple fully buffered DIMM circuits or instantiations are presented in a single module. In a preferred embodiment, memory integrated circuits (preferably CSPs) and accompanying AMBs are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete FB-DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

Description

RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 11/007,551 filed Dec. 8, 2004, which is a continuation-in-part of U.S. patent application Ser. No. 10/934,027 filed Sep. 3, ?9004. U.S. patent application Ser. Nos. 11/007,551 and 11/934,027 are incorporated herein by reference.
FIELD
• The present invention relates to systems and methods for creating high density circuit modules.
BACKGROUND
• The well-known DIMM (Dual In-line Memory Module) board has been used for years, in various forms, to provide memory expansion. A typical DIMM includes a conventional PCB (printed circuit board) with memory devices and supporting digital logic devices mounted on both sides. The DIMM is typically mounted in the host computer system by inserting a contact-bearing edge of the DIMM into a card edge connector. Systems that employ DIMMs provide, however, very limited profile space for such devices and conventional DIMM-based solutions have typically provided only a moderate amount of memory expansion.
• As bus speeds have increased, fewer devices per channel can be reliably addressed with a DIMM-based solution. For example, 288 ICs or devices per channel may be addressed using the SDRAM-100 bus protocol with an unbuffered DIMM. Using the DDR-200 bus protocol, approximately 144 devices may be address per channels with the DDR2-400 bus protocol only 72 devices per channel may be addressed. This constraint has led to the development of the fully-buffered DIMM (FB-DIMM) with buffered C/A and data in which 288 devices per channel may be addressed. With the FB-DIMM, not only has capacity increased, pin count has declined to approximately 69 from the approximately 240 pins previously required.
• The FB-DIMM circuit solution is expected to offer practical motherboard memory capacities of up to about 192 gigabytes with six channels and eight DIMMs per channel and two ranks per DIMM using one gigabyte DRAMs. This solution should also be adaptable to next generation technologies and should exhibit significant downward compatibility.
• This great has, however, come with some cost and will eventually be self-limiting. The basic principle of systems that employ FB-DIMM relies upon a point-to-point or serial addressing scheme rather than the parallel multi-drop interface that dictates non-buffered DIMM addressing. That is, one DIMM is in point-to-point relationship with the memory controller and each DIMM is in point-to-point relationship with adjacent DIMMs. Consequently, as bus speeds increase, the number of DIMMs on a bus will decline as the discontinuities caused by the chain of point to point connections from the controller to the “last” DIMM become magnified in effect as speeds increase. Consequently, methods to increase the capacity of a single DIMM find value in contemporary memory and computing systems.
• There are several known methods to improve the limited capacity of a DIMM or other circuit board. In one strategy, for example, small circuit boards (daughter cards) are connected to the DIMM to provide extra mounting space. The additional connection may cause, however, flawed signal integrity for the data signals passing from the DIMM to the daughter card and the additional thickness of the daughter card(s) increases the profile of the DIMM.
• Multiple die packages (MDP) are also used to increase DIMM capacity while preserving profile conformity. This scheme increases the capacity of the memory devices on the DIMM by including multiple semiconductor die in a single device package. The additional heat generated by the multiple die typically requires, however, additional cooling capabilities to operate at maximum operating speed. Further, the MDP scheme may exhibit increased costs because of increased yield loss from packaging together multiple die that are not fully pre-tested.
• Stacked packages are yet another strategy used to increase circuit board capacity. This scheme increases capacity by stacking packaged integrated circuits to create a high-density circuit module for mounting on the circuit board. In some techniques, flexible conductors are used to selectively interconnect packaged integrated circuits. Staktek Group L.P. has developed numerous systems for aggregating CSP (chipscale packaged) devices in space saving topologies. The increased component height of some stacking techniques may alter, however, system requirements such as, for example, required cooling airflow or the minimum spacing around a circuit board on its host system.
• What is needed, however, are methods and structures for increasing the flexibility of the FB-DIMM solution.
SUMMARY
• Multiple fully buffered DIMM circuits or instantiations are combined in a single module to provide on a single module circuitry that is substantially the functional equivalent of two or more FB-DIMMs but avoids some of the drawbacks associated with having two discrete FB-DIMMs In a preferred embodiment, integrated circuits (preferably memory CSPs) and accompanying AMBs are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place at least one FB-DIMM instantiation on each side of the constructed module. In alternative, but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. Other embodiments may connect the constituent devices in a way that creates a FB-DIMM circuit or instantiation with the devices on the upper half of the module while another FB-DIMM instantiation is created with the devices on the lower half of the module. Other embodiments may, for example, combine selected circuitry from one side of the module (memory CSPs for example) with circuitry on the other side of the module (an AMB, for example) in creating one of plural FB-DIMM instantiations on a single module. Other embodiments employ stacks to provide multiple FB-DIMM circuits or instantiations On a low profile module. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a depiction of a preferred embodiment of a module devised in accordance with the present invention.
• FIG. 2 depicts a contact bearing first side of a flex circuit devised in accordance with a preferred embodiment of the present invention.
• FIG. 3 depicts the second side of the exemplar populated flex circuit ofFIG. 2.
• FIG. 4 is a cross-sectional depiction through the devices as populated in an embodiment of the present invention.
• FIG. 5 is an enlarged view of the area marked ‘A’ inFIG. 4.
• FIG. 6 depicts a cross-sectional view of a module devised in accordance with an alternate preferred embodiment of the present invention.
• FIG. 7 depicts the area near an end of a substrate in the embodiment shown inFIG. 6.
• FIG. 8 depicts a cross-sectional view of a module assembly devised in accordance with a preferred embodiment of the present invention.
• FIG. 9 is an enlarged view of a portion of one preferred embodiment.
• FIG. 10 depicts one perspective of an exemplar module devised in accordance with a preferred embodiment of the present invention.
• FIG. 11 is another depiction of the relationship between flex circuitry and asubstrate14 which has been patterned or windowed with cutaway areas.
• FIG. 12 depicts a cross sectional view of an exemplar substrate employed inFIG. 11 before being combined with populated flex circuits.
• FIG. 13 depicts another embodiment of the invention having additional ICs.
• FIG. 14 is a representation of impedance discontinuities in typical FB-DIMM systems.
• FIG. 15 is a representation of impedance discontinuities in an embodiment of the present invention.
• FIG. 16 depicts yet another embodiment of the present invention.
• FIG. 17 presents another embodiment of the present invention.
• FIG. 18 depicts a low profile embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
• FIG. 1 depicts a preferred embodiment devised in accordance with the present invention.Module10 is depicted inFIG. 1exhibiting ICs18 andcircuit19.
• FIG. 2 depicts a first side8 of flex circuit12 (“flex”, “flex circuitry”, “flexible circuit”) used in constructing a module according to an embodiment of the present invention.Flex circuit12 is preferably made from one or more conductive layers supported by one or more flexible substrate layers as further described with reference to later Figs. The construction of flex circuitry is known in the art. The entirety of theflex circuit12 may be flexible or, as those of skill in the art will recognize, theflexible circuit structure12 may be made flexible in certain areas to allow conformability to required shapes or bends, and rigid in other areas to provide rigid and planar mounting surfaces.Preferred flex circuit12 has openings17 for use in aligningflex circuit12 tosubstrate14 during assembly.
• ICs18 onflexible circuit12 are, in this embodiment, chip-scale packaged memory devices of small scale. For purposes of this disclosure, the term chip-scale or “CSP” shall refer to integrated circuitry of any function with an array package providing connection to one or more die through contacts (often embodied as “bumps” or “balls” for example) distributed across a major, surface of the package or die. CSP does not refer to leaded devices that provide connection to an integrated circuit within the package through leads emergent from at least one side of the periphery of the package such as, for example, a TSOP.
• Embodiments of the present invention may be employed with leaded or CSP devices or other devices in both packaged and unpackaged forms but where the term CSP is used, the above definition for CSP should be adopted. Consequently, although CSP excludes leaded devices, references to CSP are to be broadly construed to include the large variety of array devices (and not to be limited to memory only) and whether die-sized or other size such as BGA and micro BGA as well as flip-chip. As those of skill will understand after appreciating this disclosure, some embodiments of the present invention may be devised to employ stacks of ICs each disposed where anIC18 is indicated in the exemplar Figs.
• Multiple integrated circuit die may be included in a package depicted as asingle IC18. While in this embodiment memory ICs are used to provide a memory expansion board or module, and various embodiments may include a variety of integrated circuits and other components. Such variety may include microprocessors, FPGA's, RF transceiver circuitry, digital logic, as a list of non-limiting examples, or other circuits or systems which may benefit from a high-density circuit board or module capability.Circuit19 depicted betweenICs18 may be a memory buffer or controller but in a preferred embodiment is the well known advanced memory buffer or “AMB”.
• The depiction ofFIG. 2 showsflex circuit12 as having first and second fields F1 and F2. Each of fields F1 and F2 have at least one mounting contact array for CSPs such as the one depicted by reference11A. Contact arrays such asarray11 are disposed beneathICs18 andcircuits19. An exemplar contact array11A is shown as isexemplar IC18 to be mounted at contact array11A as depicted. The contact arrays11A that correspond to an IC plurality may be considered a contact array set.
• Field F1 of side8 offlex circuit12 is shown populated with first plurality of CSPs IC_R1and second plurality of CSPs IC_R2while second field F2 of side8 offlex circuit12 is shown populated with first plurality of CSPs IC_R1and second plurality of CSPs IC_R2. Those of skill will recognize that the identified pluralities of CSPs are, when disposed in the configurations depicted, typically described as “ranks”. Between the ranks IC_R2of field F1 and IC_R2of field F2,flex circuit12 bears a plurality of module contacts allocated in this embodiment into two rows (C_R1and C_R2) ofmodule contacts20. Whenflex circuit12 is folded as later depicted, side8 depicted inFIG. 2 is presented at the outside ofmodule10. The opposing side9 offlex circuit12 is on the inside in several depicted configurations ofmodule10 and thus side9 is closer to thesubstrate14 about whichflex circuit12 is disposed than is side8. Other embodiments may have other numbers of ranks and combinations of plural CSPs connected to create the module of the present invention.
• FIG. 3 shows side9 offlex circuit12 depicting the other side of the flex circuit shown inFIG. 2. Side9 offlex circuit12 is shown as being populated withmultiple CSPs18. Side9 includes fields F1 and F2 that each include at least one mounting contact array site for CSPs and, in the depicted case, include multiple contact arrays. Each of fields F1 and F2 include, in the depicted preferred embodiment, two pluralities of ICs identified inFIG. 3 as IC_R1and IC_R2. Thus, each side offlex circuit12 has, in a preferred embodiment, two fields F1 and F2 each of which fields includes two ranks of CSPs IC_R1and IC_R2. In laterFIG. 4, it will be recognized that fields F1 and F2 will be disposed on different sides ofsubstrate14 in a completedmodule10 whenICs18 are identified according to the organizational identification depicted inFIGS. 2 and 3 but those of skill will recognize that the groupings ofICs18 shown inFIGS. 2 and 3 are not dictated by the invention but are provided merely as an exemplar organizational strategy to assist in understanding the present invention.
• Various discrete components such as termination resistors, bypass capacitors and bias resistors, in addition to thebuffers19 shown on side8 offlex circuit12, may be mounted on either or both of sides8 and9 offlex12. Such discrete components are not shown to simplify the drawing.Flex circuit12 may also depicted with reference to its perimeter edges, two of which are typically long (PE_long1and PE_long2) and two of which are typically shorter (PE_short1and PE_short2). Other embodiments may employflex circuits12 that are not rectangular in shape and may be square in which case the perimeter edges would be of equal size or other convenient shape to adapt to manufacturing particulars. Other embodiments may also have fewer or greater numbers of ranks or pluralities of ICs in each field or on a side of a flex circuit.
• FIG. 2 depicts an exemplarconductive trace21 connecting row C_R2ofmodule contacts20 toICs18. Those of skill will understand that there are many such traces in a typical embodiment.Traces21 may also connect to vias that may transit to other conductive layers offlex12 in certain embodiments having more than one conductive layer. In a preferred embodiment, vias connectICs18 on side9 offlex12 tomodule contacts20. An example via is shown asreference23.Traces21 may make other connections between the ICs on either side offlex12 and may traverse the rows ofmodule contacts20 to interconnect ICs. Together the various traces and vias make interconnections needed to convey data and control signals amongst the various ICs and buffer circuits. Those of skill will understand that the present invention may be implemented with only a single row ofmodule contacts20 and may, in other embodiments, be implemented as a module bearing ICs on only one side offlex circuit12.
• FIG. 4 is a cross section views of amodule10 devised in accordance with a preferred embodiment of the present invention.Module10 is populated withICs18 havingtop surfaces18_Tand bottom surfaces18_B. Substrate orsupport structure14 has first and second perimeter edges16A and16Bi appearing in the depiction ofFIG. 4 as ends. Substrate orsupport structure14 typically has first and second lateral sides S₁and S₂. Flex12 is wrapped aboutperimeter edge16A ofsubstrate14, which in the depicted embodiment, provides the basic shape of a common DIMM board form factor such as that defined by JEDEC standard MO-256.
• FIG. 5 is an enlarged view of the area marked ‘A’ inFIG. 4.Edge16A ofsubstrate14 is shaped like a male side edge of an edge, card connector. While a particular oval-like configuration is shown,edge16A may take on other shapes devised to mate with various connectors or sockets. The form and function of various edge card connectors are well know in the art. In many preferred embodiments,flex12 is wrapped aroundedge16A ofsubstrate14 and may be laminated or adhesively connected tosubstrate14 withadhesive30. The depicted adhesive30 andflex12 may vary in thickness and are not drawn to scale to simplify the drawing. The depictedsubstrate14 has a thickness such that when assembled with theflex12 and adhesive30, the thickness measured betweenmodule contacts20 falls in the range specified for the mating connector. In some other embodiments,flex circuit12 may be wrapped aboutperimeter edge16B or bothperimeter edges16A and16B ofsubstrate14. In other instances, multiple flex circuits may be employed or a single flex circuit may connect one or both sets ofcontacts20 to the resident ICs.
• FIG. 6 depicts a cross-sectional view of amodule10 devised in accordance with an alternate preferred embodiment of the present invention with the view taken along a line through two AMBs and selectedICs18 from IC_R1. Themodule10 depicted inFIG. 6 differs from that shown in earlier embodiments in that rather than asingle flex circuit12, the depictedexemplar module10 employs twoflex circuits12A and12B with12A being disposed on one lateral side S1 ofsubstrate14 whileflex circuit12B is employed on lateral side S2 ofsubstrate14.
• FIG. 7 depicts the area nearend16A ofsubstrate14 in the embodiment shown inFIG. 6 that employs two flex circuits identified as12A and12B to implement a module in accordance with an alternate preferred embodiment of the present invention. Each offlex circuits12A and12B are populated withICs18 on one or both of their respective sides8 and9 and each offlex circuits12A and12B employ abuffer circuit19 such as, for example, an advanced buffer circuit or AMB to implement, along with the resident CSPs, multiple FB-DIMM circuits mounted on asingle module10. The area on side9 of each offlex circuits12A and12B opposite the disposition ofbuffer circuit19 disposed along side8 offlex circuits12A and12B is, in the depicted module, filled with aconformal material31 to provide support along the length ofmodule10 where structure is not provided by the bodies of circuits such asICs18 or buffers19.
• FIG. 8 depicts a cross-sectional view of amodule10 devised with asubstrate14 that has cutaway areas into whichICs18 are disposed to reduce the profile ofmodule10. CorrespondingICs18 from each of fields F1 and F2 pass throughwindows250 insubstrate14 as shown in later Figs. in further detail and theinner ICs18 are preferably attached to each other'supper surfaces18_Twith a thermally conductive adhesive30). While in this embodiment, the depicted ICs are attached to flexcircuit12 in opposing pairs, fewer or greater numbers of ICs may be connected in other arrangements such as, for example, staggered or offset arrangements in which they may exhibit preferred thermal characteristics. In a preferred embodiment,ICs18 will be CSPs and typically, memory CSPs. To simplify the drawing, discrete components such as resistors and capacitors typically found on embodiments ofmodule10 are not shown.
• In this embodiment,flex circuit12 hasmodule contacts20 positioned in a manner devised to fit in a circuit board card edge connector or socket and connect to corresponding contacts in the connector (not shown). Whilemodule contacts20 are shown protruding from the surface offlex circuit12, other embodiments may have flush contacts or contacts below the surface level offlex12.Substrate14 supportsmodule contacts20 from behindflex circuit12 in a manner devised to provide the mechanical form required for insertion into a socket. In other embodiments, the thickness or shape ofsubstrate14 in the vicinity ofperimeter edge16A may differ from that in the vicinity ofperimeter edge16B.Substrate14 in the depicted embodiment is preferably made of a metal such as aluminum or copper, as non-limiting examples, or where thermal management is less of an issue, materials such as FR4 (flame retardant type 4) epoxy laminate, PTFE (poly-tetra-fluoro-ethylene) or plastic. In another embodiment, advantageous features from multiple technologies may be combined with use of FR4 having a layer of copper on both sides to provide asubstrate14 devised from familiar materials which may provide heat conduction or a ground plane.
• FIG. 9 is an enlarged view of a portion of one preferred embodiment showinglower IC18₁andupper IC18₂andsubstrate14 having cutaway areas into whichICs18 are disposed. In this embodiment,conductive layer66 offlex circuit12 contains conductive traces connectingmodule contacts20 toBGA contacts63 onICs18₁and18₂. The number of layers may be devised in a manner to achieve the bend radius required in those embodiments that bendflex circuit12 aroundedge16A or16B, for example. The number of layers in any particular portion offlex circuit12 may also be devised to achieve the necessary connection density given a particular minimum trace width associated with the flex circuit technology used. Someflex circuits12 may have three or four or more conductive layers. Such layers may be beneficial to route signals in a FB-DIMM which may have fewer DIMM input/output signals than a registered DIMM, but may have more interconnect traces required among devices on the DIMM, such as, for example, the C/A copy A and C/A copy B (command/address) signals produced by an FB-DIMM AMB.
• In this embodiment, there are three layers offlex circuit12 between the two depictedICs18₁and18₂.Conductive layers64 and66 express conductive traces that connect to the IC's and may further connect to other discrete components (not shown). Preferably, the conductive layers arc metal stick as, for example, copper or alloy110. Vias such as the exemplar vias23 connect the twoconductive layers64 and66 and thereby enable connection betweenconductive layer64 andmodule contacts20. In this preferred embodiment having a three-layer portion offlex circuit12, the twoconductive layers64 and66 may be devised in a manner so that one of them has substantial area employed as a ground plane. The other layer may employ substantial area as a voltage reference plane. The use of plural conductive layers provides advantages and the creation of a distributed capacitance intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize. If more than two conductive layers are employed, additional conductive layers may be added with insulating layers separating conductive layers. Portions offlex circuit12 may in some embodiments be rigid portions (rigid-flex). Construction of rigid-flex circuitry is known in the art.
• With the construction of an embodiment such as that shown inFIG. 9, thermal energy will be urged to move between therespective ICs18₁. Thus, the ICs become a thermal mass sharing the thermal load.Flex circuit12 may be particularly devised to operate as a heat spreader or sink adding to the thermal conduction out ofICs18₁and18₂.
• FIG. 10 depicts one perspective of anexemplar module10 devised in accordance with a preferred embodiment of the present invention. As those of skill will understand, the depiction ofFIG. 10 is simplified to show more clearly the principles of the invention but depictsfewer ICs18 than would typically be presented in embodiments of the present invention.
• The principles of the present invention may, however, be employed where only oneIC18 is resident on a side of aflex circuit12 or where multiple ranks or pluralities of ICS are resident on a side offlex circuit12, or, as will be later shown, wheremultiple ICs18 are disposed one atop the other to give asingle module10 materially greater.
• FIG. 10 depicts a cross sectional view of an exemplar module showing a reduced number ofICs18 to allow a clearer exposition of the principles of the present invention as illustrated by this depicted embodiment. The module shown inFIG. 10 is formed with an exemplar flex circuit such as that depicted inFIGS. 2 and 3. The second side9 offlex circuit12 shown inFIG. 3 is folded aboutsubstrate14 shown inFIG. 10 to placeICs18 into thewindows250 arrayed alongsubstrate14. This results in ICs of ranks IC_R1and IC_R2being disposed back to back withinwindows250. Preferably, a thermally conductive adhesive or glue is used on the upper sides ofICs18 to encourage thermal energy flow as well as provide some mechanical advantages. Those of skill will recognize that in this embodiment, whereFIG. 10 depicts the first or, in this case, the outer side of the flex circuit once combined withsubstrate14, the flex circuit itself will have staggered mounting arrays11A on side8 offlex circuit12 relative to side9 offlex circuit12. This is merely one relative arrangement betweenICs18 on respective sides ofsubstrate14.
• As shown inFIG. 10,ICs18 which are on second side9 (which in this depiction is the inner side with respect to the module10) ofpopulated flex circuit12 are disposed inwindows250 so that theupper surfaces18_TofICs18 of row ICR1 of F1 are in close proximity with theupper surfaces18_tofICs18 of rank ICR1 of F2. Thus, a first group of ICs (CSPs in the depiction) may be considered to be comprised of the ICs of IC_R1from both fields F1 and F2 while a second group of ICs may be considered to be comprised of the ICs of IC_R2from both fields F1 and F2. TheICs18 that are populated along side9 offlex circuit12 are positioned in the cutaway areas of the first and second lateral sides, respectively, ofsubstrate14. In this case, the cutaway areas on each lateral side ofsubstrate14 are in spatial coincidence to createwindows250. Those of skill will recognize that the depiction is not to scale but representative of the interrelationships between the elements and the arrangement results in a profile “PP” formodule10 that is significantly smaller than it would have been withoutfitting ICs18 along inner side9 offlex circuit12 intowindows250. Profile P in this case is approximately the sum of the distances between the upper and lower surfaces ofIC18 plus 4× the diameter of theBGA contacts63 plus 2× the thickness offlex circuit12 in addition to anyadhesive layers30 employed to adhere oneIC18 to another. This profile dimension will vary depending upon whetherBGA contacts63 are disposed below the surface offlex circuit12 to reach an appropriate conductive laver or contacts which typically are a part offlex circuit12.
• FIG. 11 is another depiction of the relationship between flex circuitry and asubstrate14 which has been patterned or windowed with cutaway areas. The view ofFIG. 11 is taken along a line that would intersect the bodies ofICs18. InFIG. 11, twoflex circuits12A and12B are shown populated along their respective sides9 with ICs18 (i.e., CSPs in the depiction). TheICs18 along the inner side9 offlex circuit12A are staggered relative to those that are along inner side9 offlex circuit12B whenmodule10 is assembled andflex circuits12A and12B are combined withsubstrate14. This staggering may result in some construction benefits providing a mechanical “step” forICs18 as they are fitted intosubstrate14 and may further provide some thermal advantages increasing the contact area betweensubstrate14 and the plurality ofICs18. Those of skill will recognize thatflex circuits12A and12B even though depicted as being populated on only one side, may be populated on either or both sides8 and9 just as in those embodiments that employ asingle flex circuit12 may be populated one or both sides offlex circuit12 and may have populated one or both fields or ranks within fields on one or both sides with CSPs or other circuits.
• FIG. 12 depicts a cross sectional view ofexemplar substrate14 employed inFIG. 11 before being, combined withpopulated flex circuits12A and12B as viewed along a line throughwindows250 ofsubstrate14. As depicted inFIG. 12, a number of cutaway areas or pockets are delineated with dotted lines and identified with references250B3 and250B4, respectively. Those areas identified as250B3 correspond, in this example, to the pockets, sites, or cutaway areas on one side ofsubstrate14 into whichICs18 fromflex circuit12A will be disposed whensubstrate14 andflex circuit12A are combined. Those pocket, sites, or cutaway areas identified as references250B4 correspond to the sites into whichICs18 fromflex circuit12B will be disposed.
• For purposes herein, the term window may refer to an opening all the way throughsubstrate14 across span “S” which corresponds to the width or height dimension of packagedIC18 or, it may also refer to that opening where cutaway areas on each of the two sides ofsubstrate14 overlap.
• Where cutaway areas250B3 and250B4 overlap, there are, as depicted, windows all the way throughsubstrate14. In some embodiments, cutaway areas250B3 and2501B4 may not overlap or in other embodiments, there may be pockets or cutaway areas only on one side ofsubstrate14. Those of skill will recognize that cutaway areas such as those identified with references250B3 and250B4 may be formed in a variety of ways depending on the material ofsubstrate14 and need not literally be “cut” away but may be formed by a variety of molding, milling and cutting processes as is understood by those in the field.
• FIG. 13 depicts another embodiment of the invention havingadditional ICs18. In this embodiment, four flex level transitions26 connect to four mountingportions28 offlex circuits12A₁,12A₂,12B₁, and12B₂. In this embodiment, each mountingportion28 hasICs18 on both sides.Flex circuitry12 may also be provided in this configuration by, for example, having a split flex with layers interconnected with vias. As those of skill will recognize, the possibilities for large capacity iterations ofmodule10 are magnified by such strategies and the same principles may be employed where theICs18 on one side ofsubstrate14 are staggered relative to thoseICs18 on the other side ofsubstrate14 or, substrates such as those shown inFIG. 4 that have no cutaway areas may be employed.
• Four flex circuits are employed inmodule10 as depicted inFIG. 13 and, although those embodiments that wrapflex circuit12 aboutend16A ofsubstrate14 present manufacturing efficiencies, in some environments having flex circuitry separate from each other may be desirable.
• In a typical FB-DIMM system employing multiple FB-DIMM circuits, the respective AMB's from one FB-DIMM circuit to another FB-DIMM circuit are separated by what can be conceived of as three impedance discontinuities as represented in the system depicted inFIG. 14 as D1, D2, and D3.FIG. 14 includes twomodules10 and includes a representation of the connection between the two modules. Discontinuity D1 represents the impedance discontinuity effectuated by the connector-socket combination associated with thefirst module10F. Discontinuity D2 represents the impedance perturbation effectuated by the connection between the connector-socket offirst module10F and the connector-socket ofsecond module10S while discontinuity D3 represents the discontinuity effectuated by the connector-socket combination associated with thesecond module10S. The AMB is the new buffer technology particularly for server memory and typically includes a number of features including pass-through logic for reading and writing data and commands and internal serialization capability, a data bus interface, a deserialing and decode logic capability and clocking functions. The functioning of an AMB is the principal distinguishing hard feature of a FB-DIMM module. Those of skill will understand how to implement the connections betweenICs18 andAMB19 in FB-DIMM circuits implemented by embodiments of the present invention and will recognize that the present invention provides advantages in capacity as well as reduced impedance discontinuity that can hinder larger implementations of FB-DIMM systems. Further, those of skill will recognize that various principles of the present invention can be employed to multiple FB-DIMM circuits on a single substrate or module.
• In contrast to the system represented byFIG. 14,FIG. 15 is a schematic representation of the single impedance perturbation DX effectuated by the connection between afirst AMB19 of a first FB-DIMM “FB1” of afirst module10F and asecond AMP19 of a second FB-DIMM “FB2” of the samefirst module10F.
• FIG. 16 depicts another embodiment of the present invention in which amodule10 is devised using stacks to create amodule10 presenting two FB-DIMM circuits. Those of skill will appreciate that using stacks such as depictedstacks40 owned by Staktek Group L.P. allows creating modules that have multiple FB-DIMM circuits on a single module.Stacks40 are just one of several stack designs that may be employed with the present invention.Stacks40 are devised withmandrels42 and stackflex circuits44 as described in U.S. patent application Ser. No. 10/453,395, filed Jun. 6, 2003 which is owned by Staktek Group L.P. and which is hereby incorporated by reference and stacks40 andAMP19 are mounted onflex circuit12 which is disposed aboutsubstrate14.
• FIG. 17 depicts use of stacks in an embodiment of the present invention that exhibits a low profile with use of stacks. Such an embodiment presents at least two FB-DIMM circuits at itscontacts20.
• FIG. 18 illustrates a low profile embodiment of the present invention. The depictedmodule10 has at least two AMBs and associated circuitry such asICs18 which in the preferred mode and as illustrated are CSPs and needed support circuitry to create at least two FB-DIMM circuits or instantiations on a single module with a low profile. It should be understood that the second AMB in addition to the one literally shown can be disposed on either side ofmodule10 but preferably will be disposed closer to lateral side S2 ofsubstrate14 than is the depictedAMB19 but likeAMB19 will be disposed on side8 offlex circuit12. In this embodiment,contacts20 are along side8 offlex circuit12 and proximal to edge E offlex circuit12. The principal circuits that constitute the first FB-DIMM circuitry or instantiation (i.e., the CSPs and AMB) may be disposed in single rank file as shown. They may be allocated to first and second mounting fields of the first and second sides offlex circuit12 as earlier described with reference to earlier Figs. Those of skill will recognize thatcontacts20 may appear on one or both sides ofmodule10 depending on the mechanical contact interface particulars of the application.
• The present invention may be employed to advantage in a variety of applications and environment such as, for example, in computers such as servers and notebook computers by being placed in motherboard expansion slots to provide enhanced memory capacity while utilizing fewer sockets. The two high rank embodiments or the single rank high embodiments may both be employed to such advantage as those of skill will recognize after appreciating this specification.
• One advantageous methodology for efficiently assembling acircuit module10 such as described and depicted herein is as follows. In a preferred method of assembling apreferred module assembly10,flex circuit12 is placed flat and both sides populated according to circuit board assembly techniques known in the art.Flex circuit12 is then folded aboutend16A ofsubstrate14.Flex12 may be laminated or otherwise attached tosubstrate14.
• Although the present invention has been described in detail, it will be apparent to those skilled in the alt that many embodiments taking a variety of specific forms and reflecting changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. Therefore. the described embodiments illustrate but do not restrict the scope of the claims.

Claims (34)

1. A circuit module comprising:

a first side and a second side, between which is disposed a substrate having a first perimeter edge and a second perimeter edge;

a plurality of module contacts comprising

a first row of contacts disposed along the first side of the circuit module proximal to the first perimeter edge of the substrate and

a second row of contacts disposed along the second side of the circuit module proximal to the first perimeter edge of the substrate;

a first FB-DIMM circuit comprising a first memory device and a first AMB, the first FB-DIMM circuit connected by first conductive traces to first selected ones of the plurality of module contacts; and

a second FB-DIMM circuit comprising a second memory device and a second AMB the second FB-DIMM circuit connected by second conductive traces to second selected ones of the plurality of module contacts.

2. The circuit module ofclaim 1 in which the first FB-DIMM circuit is disposed on the first side of the circuit module and the second FB-DIMM circuit is disposed on the second side of the circuit module

3. The circuit module ofclaim 1 in which the first FB-DIMM circuit is disposed proximal to the second perimeter edge of the substrate and the second FB-DIMM circuit is disposed proximal to the first perimeter edge of the substrate.

4. The circuit module ofclaim 1 in which the first memory device and the second memory device each comprises plural memory ICs.

5. The circuit module ofclaim 4 in which the plural memory ICs of the first memory device are arranged in a first field and the plural memory ICs of the second memory device are arranged in a second field.

6. The circuit module ofclaim 4 in which the plural memory ICs of the first memory device and the first AMB are disposed in a first FB-DIIMM row, and the plural memory ICs of the second memory device and the second AMB are disposed in a second FB-DIMM row.

7. The circuit module ofclaim 6 in which the first FB-DIMM row is disposed on the first side of the circuit module and the second FB-DIMM row is disposed on the second side of the circuit module.

8. The circuit module ofclaim 4 in which selected ones of the plural memory ICs of the first memory device are disposed on the first side of the circuit module and the first AMB is disposed on the second side of the circuit module.

9. The circuit module ofclaim 8 in which selected ones of the plural memory ICs of the second memory device are disposed on the second side of the circuit module and the second AMB is disposed on the first side of the circuit module.

10. The circuit nodule ofclaim 4 in which the plural memory ICs are deployed in stacks.

11. The circuit module ofclaim 10 in which the plural memory ICs are CSPs.

12. The circuit module ofclaim 11 in which each stack of CSPs comprises a mandrel.

13. The circuit module ofclaim 4 in which first selected ones of the plural memory ICs are disposed on the first side of the circuit module and second selected ones of the plural memory ICs are disposed on the second side of the circuit module, with each of the first selected ones of the plural memory ICs directly opposed to a respective one of the second selected ones of the plural memory ICs disposed on the opposite side of the substrate.

14. The circuit module ofclaim 4 in which first selected ones of the plural memory ICs are disposed on the first side of the circuit module and second selected ones of the plural memory ICs are disposed on the second side of the circuit module, with the first selected ones of the plural memory ICs offset from the second selected ones of the plural memory ICs disposed on the opposite side of the substrate.

15. A memory module comprising plural FB-DIMM circuits.

16. The memory module ofclaim 15 in which each of the plural FB-DIMM circuits comprises plural memory CSPs.

17. The memory module ofclaim 16 in which selected ones of the plural memory CSPs are stacked.

18. The memory module ofclaim 17 in which selected ones of the stacked plural memory CSPs comprise a mandrel.

19. The memory module ofclaim 15 in which the first AMB is separated from the second AMB by a single impedance perturbation.

20. A memory module comprising:

a support structure having first and second lateral sides and an edge;

a plurality of module contacts disposed adjacent to the edge of the support structure and supported by the first lateral side of the support structure;

a first FB-DIMM instantiation comprising a first memory device and a first AMB; and a second FB-DIMM instantiation comprising a second memory device and a second AMB.

21. The memory module ofclaim 20 in which the first memory device and the second memory device each comprises plural memory ICs.

22. The memory module ofclaim 21 in which the plural memory ICs of the first memory device and the first AMB are disposed in a first row, and the plural memory ICs of the second memory device and the second AMB are disposed in a second row.

23. The memory module ofclaim 22 in which the first row is disposed along the first side of the support structure and the second row is disposed along the second side of the support structure.

24. The memory module ofclaim 21 in which selected ones of the plural memory ICs of the first memory device are disposed along the first side of the support structure and the first AMB is disposed along the second side of the support structure.

25. The memory module ofclaim 24 in which selected ones of the plural memory ICs of the second memory device are disposed along the second side of the support structure and the second AMB is disposed along the first side of the support structure.

26. The memory module ofclaim 21 in which the first memory device and the second memory device each comprises stacks of memory ICs.

27. The memory module ofclaim 26 in which the memory ICs are CSPs.

28. The memory module ofclaim 27 in which each stack of CSPs comprises a mandrel.

29. A circuit module comprising plural FD-DIMM instantiations.

30. The memory module ofclaim 29 in which each of the plural FB-DIMM instantiations comprises plural memory CSPs.

31. The memory module ofclaim 30 in which selected ones of the plural memory CSPs are stacked.

32. The memory module ofclaim 31 in which selected ones of the stacked plural memory CSPs comprise a mandrel.

33. The memory module ofclaim 29 in which the first AMB is separated from the second AMB by a single impedance perturbation.

34. A computer comprising:

a motherboard having a socket and

a circuit module connected to the socket, the circuit module comprising plural FB-DIMM instantiations.

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