US20070108581A1 - Offset integrated circuit package-on-package stacking system - Google Patents

Abstract

An offset integrated circuit package-on-package stacking system is provided including providing a base substrate, forming a contact pad on the base substrate, mounting a first integrated circuit on the base substrate, forming a base package body around the first integrated circuit, providing an offset substrate, mounting a second integrated circuit on the offset substrate, and coupling the offset substrate to the contact pad, including placing the offset substrate on the base package body.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)
• This application claims the benefit of U.S. Provisional Patent Application Ser. number 60/594,884 filed May 16, 2005.
• The present application contains subject matter related to a concurrently filed U.S. Patent Application by Shim et al. entitled “Offset Integrated Circuit Package-on-Package Stacking System”. The related application is assigned to STATS ChipPAC Ltd. and is identified by docket number 27-173.
TECHNICAL FIELD
• The present invention relates generally to integrated circuit package systems, and more particularly to a system for integrated circuit package systems having stacked packages.
BACKGROUND ART
• In order to interface an integrated circuit with other circuitry, it is common to mount it on a lead frame or substrate. Each integrated circuit has bonding pads that are individually connected to the lead frame's lead finger pads using extremely fine gold or aluminum wires. The assemblies are then packaged by individually encapsulating them in molded plastic or ceramic bodies to create an integrated circuit package.
• Integrated circuit packaging technology has seen an increase in the number of integrated circuits mounted on a single circuit board or substrate. The new packaging designs are more compact in form factors, such as the physical size and shape of an integrated circuit, and providing a significant increase in overall integrated circuit density. However, integrated circuit density continues to be limited by the “real estate” available for mounting individual integrated circuits on a substrate. Even larger form factor systems, such as PC's, compute servers, and storage servers, need more integrated circuits in the same or smaller “real estate”. Particularly acute, the needs for portable personal electronics, such as cell phones, digital cameras, music players, PDA's, and location-based devices, have further driven the need for integrated circuit density.
• This increased integrated circuit density, has led to the development of multi-chip packages in which more than one integrated circuit can be packaged. Each package provides mechanical support for the individual integrated circuits and one or more layers of interconnect lines that enable the integrated circuits to be connected electrically to surrounding circuitry. Current multi-chip packages, also commonly referred to as multi-chip modules, typically consist of a PCB substrate onto which a set of separate integrated circuit components is directly attached. Such multi-chip packages have been found to increase integrated circuit density and miniaturization, improve signal propagation speed, reduce overall integrated circuit size and weight, improve performance, and lower costs--all primary goals of the computer industry.
• Multi-chip packages whether vertically or horizontally arranged, can also present problems because they usually must be pre-assembled before the integrated circuit and integrated circuit connections can be tested. Thus, when integrated circuits are mounted and connected in a multi-chip module, individual integrated circuits and connections cannot be tested individually, and it is not possible to identify known-good-die (“KGD”) before being assembled into larger circuits. Consequently, conventional multi-chip packages lead to assembly process yield problems. This fabrication process, which does not identify KGD, is therefore less reliable and more prone to assembly defects.
• Moreover, vertically stacked integrated circuits in typical multi-chip packages can present problems beyond those of horizontally arranged integrated circuit packages, further complicating the manufacturing process. It is more difficult to test and thus determine the actual failure mode of the individual integrated circuits. Moreover the substrate and integrated circuit are often damaged during assembly or testing, complicating the manufacturing process and increasing costs. The vertically stacked integrated circuit problems can be greater than the benefits.
• Thus, a need still remains for improved packaging methods, systems and designs. In view of the shrinking size of consumer electronics and the demand for more sophisticated functions in the restricted space, it is increasingly critical that answers be found to these problems. In view of the ever increasing commercial competitive pressures, increasing consumer expectations, and diminishing opportunities for meaningful product differentiation in the marketplace, it is increasingly critical that answers be found to these problems. Moreover, the ever-increasing need to save costs, improve efficiencies, and meet such competitive pressures adds even greater urgency to the critical necessity that answers be found to these problems.
• Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
• The present invention provides an offset integrated circuit package-on-package stacking system including providing a base substrate, forming a contact pad on the base substrate, mounting a first integrated circuit on the base substrate, forming a base package body around the first integrated circuit, providing an offset substrate, mounting a second integrated circuit on the offset substrate, and coupling the offset substrate to the contact pad, including placing the offset substrate on the base package body.
• Certain embodiments of the invention have other aspects in addition to or in place of those mentioned above. The aspects will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a cross-sectional view of an offset integrated circuit package-on-package stacking system, in an embodiment of the present invention;
• FIG. 2 is a top view of a base package for the offset integrated circuit package-on-package stacking system, in an embodiment of the present invention;
• FIG. 3 is a top view of an assembled package of the offset integrated circuit package-on-package stacking system, in an embodiment of the present invention;
• FIG. 4 is a cross-sectional view of the offset integrated circuit package-on-package stacking system, ofFIG. 3 alongsection line4--4;
• FIG. 5 is a cross-sectional view of the offset integrated circuit package-on-package stacking system, in an alternative embodiment of the present invention;
• FIG. 6 is a top view of the base package for the offset integrated circuit package-on-package stacking system, in an alternative embodiment of the present invention;
• FIG. 7 is a top view of the base package for the offset integrated circuit package-on-package stacking system, in another alternative embodiment of the present invention;
• FIG. 8 is a top view of the base package for the offset integrated circuit package-on-package stacking system, in yet another alternative embodiment of the present invention;
• FIG. 9 is a top view of the base package for the offset integrated circuit package-on-package stacking system, in still another alternative embodiment of the present invention; and
• FIG. 10 is a flow chart of an offset integrated circuit package-on-package stacking system for manufacturing the offset integrated circuit package-on-package stacking system in an embodiment of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
• The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that process or mechanical changes may be made without departing from the scope of the present invention.
• In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail.
• Likewise, the drawings showing embodiments of the device are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGS. In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.
• The term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the package substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “processing” as used herein includes stamping, forging, patterning, exposure, development, etching, cleaning, and/or removal of the material or laser trimming as required in forming a described structure.
• Referring now toFIG. 1, therein is shown a cross-sectional view of an offset integrated circuit package-on-package stacking system100, in an embodiment of the present invention. The cross-sectional view of the offset integrated circuit package-on-package stacking system100 depicts abase package102, such as a ball grid array package, having abase substrate104 with abase top surface106 and abase bottom surface108. A first integratedcircuit110 is mounted on thebase top surface106 with an adhesive112, such as die attach material. The first integratedcircuit110 is coupled to thebase top surface106 byelectrical interconnects114, such as bond wires, solder bumps, solder columns or stud bumps. Abase package body116, such as molding compound, is injection molded around the firstintegrated circuit110, theelectrical interconnects114 and a portion of the basetop surface106. System interconnects118, such as solder balls, solder column interposers or stud bumps, are attached to the basebottom surface108 for attachment to the next level of system (not shown). An array of acontact pad119 is distributed in an area around thebase package body116.
• An offsetpackage120, having an offsetsubstrate122 with atop surface124 and abottom surface126, is mounted in an offset position on thebase package102. The offsetpackage120 has a secondintegrated circuit128 mounted on thetop surface124 with the adhesive112. The secondintegrated circuit128 is coupled to thetop surface124 by theelectrical interconnects114. An offsetpackage body130, such as the molding compound, is injection molded over the secondintegrated circuit128, thetop surface124 and theelectrical interconnects114. The system interconnects118 are attached to thebottom surface126, of the offsetsubstrate122. The offsetpackage120 is mounted on thebase package102, so that thebottom surface126 of the offsetsubstrate122 rests on thebase package body116 and the system interconnects118. This configuration reduces the space required on a printed circuit board (not shown), while maintaining a low profile over a portion of the offset integrated circuit package-on-package stacking system100.
• Referring now toFIG. 2, therein is shown a top view of thebase package102 for the offset integrated circuit package-on-package stacking system100, in an embodiment of the present invention. The top view of thebase package102, ofFIG. 1, depicts thebase package body116, ofFIG. 1, on the basetop surface106, ofFIG. 1, with an array of thecontact pad119, ofFIG. 1, and apassive component204. Anoutline206 indicates the area that will be covered by the offsetpackage120, ofFIG. 1. The array of thecontact pad119 is spaced to align with the system interconnects118, ofFIG. 1, of the offsetpackage120, ofFIG. 1. The non-symmetrical array of thecontact pad119 allows the offsetpackage120 to extend over thebase package body116.
• Referring now toFIG. 3, therein is shown a top view of an assembledpackage300 of the offset integrated circuit package-on-package stacking system100, in an embodiment of the present invention. The top view of the assembledpackage300 depicts the basetop surface106 having thebase package body116, thepassive component204 and the offsetpackage120 mounted thereon. A section line4-4 shows the position of the view inFIG. 4.
• Referring now toFIG. 4, therein is shown a cross-sectional view of the offset integrated circuit package-on-package stacking system100, ofFIG. 3 along the section line4-4. The cross-sectional view of the offset integrated circuit package-on-package stacking system100 depicts thebase package102 with the offsetpackage120 mounted thereon. Thebottom surface126 of the offsetsubstrate122 is on thebase package body116. Thebase package body116 supports the offsetpackage120 during the reflow process preventing collapse of the system interconnects118.
• Referring now toFIG. 5, therein is shown a cross-sectional view of an offset integrated circuit package-on-package stacking system500, in an alternative embodiment of the present invention. The cross-sectional view of the offset integrated circuit package-on-package stacking system500 depicts thebase package102 having the offsetpackage120 coupled electrically through the system interconnects118. Agap filler adhesive502, such as die attach material or epoxy resin, is applied between thebase package body116 and thebottom surface126 of the offsetsubstrate122. The application of thegap filler adhesive502 provides additional mechanical stability to the package structure.
• Referring now toFIG. 6, therein is shown a top view of abase package600 for the offset integrated circuit package-on-package stacking system100, in an alternative embodiment of the present invention. The top view of thebase package600 depicts abase substrate top602 having abase mold cap604, an array of asystem contact606 and anoutline608, indicating the region that would be covered by the addition of the offsetpackage120, ofFIG. 1.
• Referring now toFIG. 7, therein is shown a top view of abase package700 for the offset integrated circuit package-on-package stacking system100, in another alternative embodiment of the present invention. The top view of thebase package700 depicts abase substrate top702, having a base mold cap704 an array of acontact pad706, partially distributed around the base mold cap704. Anoutline708 indicates the region that would be covered by the addition of the offsetpackage120, ofFIG. 1, should it be added. The array of thecontact pad706 provides an electrical interface between thebase package700 and the offsetpackage120.
• Referring now toFIG. 8, therein is shown a top view of abase package800 the offset integrated circuit package-on-package stacking system, in yet another alternative embodiment of the present invention. The top view of thebase package800 depicts abase substrate top802 having abase mold cap804, an array of asystem contact pads806, anactive element808, such as a flipchip integrated circuit, thepassive component204, and an offsetpackage outline810, indicating the region that would be covered by the addition of the offsetpackage120, ofFIG. 1. An overlap region812 indicates the contact area between thebase mold cap804 and the offsetpackage120. The corner of thebase mold cap804 will be covered by the offsetpackage120 which will rest on thebase mold cap804. Theactive element808 is placed beneath the offsetpackage120 and does not contact thebottom surface126, ofFIG. 1, of the offsetsubstrate122, ofFIG. 1.
• Referring now toFIG. 9, therein is shown a top view of abase package900 the offset integrated circuit package-on-package stacking system100, in yet another alternative embodiment of the present invention. The top view of thebase package900 depicts abase substrate top902 having abase mold cap904, an array of asystem contact pads906, theactive element808, ofFIG. 8, such as a small-outline integrated circuit, thepassive component204, and an offsetpackage outline910, indicating the region that would be covered by the addition of the offsetpackage120, ofFIG. 1. The offsetpackage120 will rest on thebase mold cap904 with offset package aligned with the edge of the base mold cap. Theactive element808 may be an active small-outline integrated circuit component that is electrically connected to the circuit within thebase package900, the array of the system contact pads, or a combination thereof Referring now toFIG. 10, therein is shown a flow chart of an offset integrated circuit package-on-package stacking system1000 for manufacturing the offset integrated circuit package-on-package stacking system100, in accordance with an embodiment of the present invention. Thesystem1000 includes providing a base substrate in ablock1002; forming a contact pad on the base substrate in ablock1004; mounting a first integrated circuit on the base substrate in ablock1006; forming a base package body around the first integrated circuit in ablock1008; providing an offset substrate in ablock1010; mounting a second integrated circuit on the offset substrate in ablock1012; and coupling the offset substrate to the contact pad, including placing the offset substrate on the base package body in ablock1014.
• In greater detail, a system to manufacture an offset integrated circuit package-on-package stacking system, according to an embodiment of the present invention, is performed as follows:
• • 1. Providing a base substrate having system interconnects. (FIG. 1)
  • 2. Forming a contact pad on the base substrate. (FIG. 1)
  • 3. Mounting a first integrated circuit on the base substrate, including coupling the first integrated circuit to the contact pad. (FIG. 1)
  • 4. Forming a base package body around the first integrated circuit, including injecting a molding compound. (FIG. 1)
  • 5. Providing an offset substrate including providing the system interconnects. (FIG. 1)
  • 6. Mounting a second integrated circuit on the offset substrate including forming an offset package body over the second integrated circuit. (FIG. 1) and
  • 7. Coupling the offset substrate to the contact pad, including placing the offset substrate on the base package body. (FIG. 1)
• It has been discovered that the present invention thus has numerous aspects.
• It has been discovered that in consumer electronic devices, where space is at a premium, the offset integrated circuit package-on-package stacking system can add more function in a limited space.
• A principle aspect is that the present invention has the flexibility to add additional components on the base substrate without adding additional package size.
• Yet another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
• These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.
• Thus, it has been discovered that the offset integrated circuit package-on-package stacking system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for increasing the integrated circuit density in consumer electronics that have diminished available space. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing offset integrated circuit package-on-package stacked devices fully compatible with conventional manufacturing processes and technologies.
• While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations which fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

Claims (20)

1. An offset integrated circuit package-on-package stacking system comprising:

providing a base substrate;

forming a contact pad on the base substrate;

mounting a first integrated circuit on the base substrate;

forming a base package body around the first integrated circuit;

providing an offset substrate;

mounting a second integrated circuit on the offset substrate; and

coupling the offset substrate to the contact pad, including placing the offset substrate on the base package body.

2. The system as claimed inclaim 1 further comprising mounting a passive component, an active component, or a combination thereof on the base substrate.

3 . The system as claimed inclaim 1 further comprising mounting an offset package on the base substrate with the offset package on the comer of a base mold cap.

4. The system as claimed inclaim 1 further comprising providing a gap filler adhesive between the base package body and the offset substrate.

5. The system as claimed inclaim 1 further comprising mounting an offset package on the base substrate with the offset package aligned with one edge of a base mold cap.

6. An offset integrated circuit package-on-package stacking system comprising:

providing a base substrate having system interconnects;

forming a contact pad on the base substrate;

mounting a first integrated circuit on the base substrate, including coupling the first integrated circuit to the contact pad;

forming a base package body around the first integrated circuit, including injecting a molding compound;

providing an offset substrate including providing the system interconnects;

mounting a second integrated circuit on the offset substrate including forming an offset package body over the second integrated circuit; and

coupling the offset substrate to the contact pad, including placing the offset substrate on the base package body.

7. The system as claimed inclaim 6 further comprising mounting a passive component, an active component, or a combination thereof on the base substrate, including coupling the passive component, the active component, or the combination thereof to the first integrated circuit, or the contact pads.

8. The system as claimed inclaim 6 further comprising mounting an offset package on the base substrate with the offset package on the corner of a base mold cap, including providing an overlap region.

9. The system as claimed inclaim 6 further comprising providing a gap filler adhesive between the base package body and the offset substrate, including providing a die attach material.

10. The system as claimed inclaim 6 further comprising mounting an offset package on the base substrate with the offset package aligned with one edge of a base mold cap under the offset substrate.

11. An offset integrated circuit package-on-package stacking system comprising:

a base substrate;

a contact pad formed on the base substrate;

a first integrated circuit mounted on the base substrate;

a base package body molded around the first integrated circuit;

an offset substrate;

a second integrated circuit mounted on the offset substrate; and

the offset substrate coupled to the contact pad, includes the offset substrate placed on the base package body.

12. The system as claimed inclaim 11 further comprising a passive component, an active component, or a combination thereof mounted on the base substrate.

13. The system as claimed inclaim 11 further comprising an offset package mounted on the base substrate with the offset package on the comer of a base mold cap.

14. The system as claimed inclaim 11 further comprising a gap filler adhesive between the base package body and the offset substrate.

15. The system as claimed inclaim 11 further comprising an offset package mounted on the base substrate with the offset package aligned with one edge of a base mold cap.

16. An offset integrated circuit package-on-package stacking system comprising:

system interconnects on the base substrate;

the first integrated circuit coupled to the contact pad;

a molding compound injected around the first integrated circuit;

the system interconnects on the offset substrate; and

an offset package body formed over the second integrated circuit.

17. The system as claimed inclaim 16 further comprising a passive component, an active component, or a combination thereof mounted on the base substrate, includes the passive component, the active component, or the combination thereof coupled to the first integrated circuit, or the contact pads.

18. The system as claimed inclaim 16 further comprising a base mold cap under the offset package mounted on the base substrate, with the offset package on the corner of the base mold cap, includes an overlap region.

19. The system as claimed inclaim 16 further comprising a gap filler adhesive between the base package body and the offset substrate, comprises a die attach material.

20. The system as claimed inclaim 16 further comprising a base mold cap under the offset package mounted on the base substrate with the offset package aligned with one edge of the base mold cap.

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