US20070087506A1 - Method of forming a semiconductor device - Google Patents

Abstract

In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxidation. In a preferred embodiment, these steps are clustered and transportation between the clustered process chambers takes place in a controlled environment such as nitrogen or a vacuum. In some embodiments, the method provides an oxide layer to be used as part of the device, such as a tunnel oxide for a flash-EEPROM, or as a general gate oxide. Alternatively, the steps can be used to sculpt through oxidation various levels of a substrate, thereby allowing for embedded memory architecture. Cleaning between oxidation steps offers the advantage of providing a more defect-free oxide layer or providing access to a more defect-free level of substrate.

Description

RELATED APPLICATIONS
• This application is a divisional of application Ser. No. 10/133,132, filed Apr. 25, 2002; which is a divisional of application Ser. No. 09/652,723, filed Aug. 31, 2000, now U.S. Pat. No. 6,589,877; which is a divisional of application Ser. No. 09/017,453, filed Feb. 2, 1998, now U.S. Pat. No. 6,475,927.
TECHNICAL FIELD
• The present invention relates to the formation of semiconductor devices. More particularly, the present invention relates to the formation of an oxide layer as part of a device or as used in the fabrication of the device.
BACKGROUND OF THE INVENTION
• In the semiconductor industry, oxide films are used in a variety of applications. Oftentimes they are used for scratch protection and passivation purposes. Oxide films are also used as a dielectric or insulative layer, electrically separating various regions or structures. For example, an oxide film can be used as a dielectric between different levels of metal in a semiconductor device. Such a film could also be used for field isolation. Moreover, an oxide film can serve as a gate oxide, wherein the film is provided above an area, such as a semiconductor substrate, having a source region, a drain region, and an interposing channel region. A gate, in turn, is formed on the oxide film. As a result, the voltage applied to the gate must reach a particular threshold before overcoming the insulative effects of the oxide and allowing current to flow through the channel. When used as field isolation, an oxide is formed in order to electrically insulate one device, such as a transistor, from another.
• Whether for field isolation purposes or for application in the gate stack of a transistor, providing the oxide typically begins by exposing designated oxide regions of a substrate to an oxidizing ambient through a patterned mask. The mask may be made, for example, of silicon nitride. For purposes of explaining the current invention, it is assumed that the substrate represents the surface of a wafer and is comprised generally of silicon. Nevertheless, this invention is understood to cover devices having a substrate comprising any construction made of semiconductive material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon) and semiconductive material layers (either alone or in assemblies comprising other materials). Upon exposure to the oxidizing ambient, the unprotected portions of the silicon substrate oxidize into silicon dioxide (SiO₂). The silicon at and below the surface of the substrate that oxidizes is often referred to as having been “consumed.” It follows that the amount of silicon consumed can indicate the depth of SiO₂beneath the substrate's original surface. As a result, greater consumption allows for a greater depth of SiO₂and, thus, greater electrical isolation between devices or between active areas within a device.
• The consuming effect of oxide films on silicon serves other purposes as well. For example, greater consumption in a particular area of the wafer allows access to a lower level of silicon within the substrate. Accordingly, removing the oxide results in a wafer topography having different elevations of silicon, depending upon the amount of prior oxidation in each area. This is particularly helpful in embedded dynamic random access memory (DRAM) processing, wherein the memory cell array should be embedded deeper within the wafer than other memory elements.
• Oxidizing the exposed substrate, as discussed above, is often referred to as “growing” the oxide. Oxides can be grown in a “dry” process using oxygen (O₂) or in a “wet” process using steam as the oxidizing agent. As an alternative to growing, oxides can be deposited on the substrate with techniques such as sputter deposition or chemical vapor deposition (CVD).
• Oxide layers have a large impact on device performance due to their role in isolating active device regions and in establishing voltage thresholds for devices. Thus, there is always a need in the art for high quality oxide films. Further, as the dimensions of semiconductor devices are scaled down to enhance circuit density and speed, the oxide films must advance accordingly. Therefore, those skilled in the art are constantly striving to provide oxide films that are thinner and that have a high dielectric constant.
• However, during the deposition or growth of oxides, defects in the oxide can occur due to the presence of certain constituents within the layer, such as contaminants exposed to the oxide. For example, particulate matter in the process atmosphere is one source of contamination. Even when the oxide or other layers are developed in a “clean room” environment, wherein filters and other techniques attempt to remove particles from the environment, particles that are too small for these techniques to handle may nevertheless end up within the oxide layer. Further attempts at reducing defects have been made by clustering together the chambers for several wafer processes in an environment isolated from and even more controllable than the clean room atmosphere. Transferring the wafers between the clustered chambers can involve the use of a wafer carrier capable of maintaining a vacuum or a nitrogen atmosphere. See, for example, U.S. Pat. Nos. 5,613,821 and 5,344,365. Nonetheless, there is a constant need in the art for further lowering the number of defects in oxide films, including a need for methods of handling contaminants that find their way to the wafer despite the controlled environment.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a process flow diagram of one exemplary embodiment of the present invention.
• FIGS. 2athrough2eillustrates a prior art process for forming an embedded DRAM.
• FIGS. 3athrough3cdepicts a second exemplary embodiment of the current invention.
• FIGS. 4athrough4edemonstrates a third exemplary embodiment of the current invention.
• FIG. 5 shows a portion of a flash-electrically erasable programmable read only memory.
• FIG. 6 illustrates an in-process semiconductor device that is electrically isolated using a shallow trench isolation process.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• As seen inFIG. 1, at least one embodiment of the current invention comprises acleaning stage20, a stage involving forming an oxide (or an oxynitride)22, and a stage of forming astructure24. These basic stages,20,22, and24, further comprise more detailed steps. For example,cleaning stage20 includes a vapor clean20b. In many cases this vapor clean20bis performed in at least five seconds and occurs at a temperature ranging between 50° and 75° C. This vapor clean20bmay take the form of an ultraviolet-chlorine clean, wherein ultraviolet light excites and dissociates a gas containing chlorine. As a result, chlorine radicals are generated. These chlorine radicals act as gettering agents, penetrating the oxide layer and bonding with constituents therein, such as contaminants. These radicals are particularly useful in neutralizing the harm caused by metallic constituents within an oxide layer. This ultraviolet-chlorine clean generally takes between ten and sixty seconds and may occur at pressures less than, greater than, or equal to 760 torr. The temperature for this process is generally between 50° and 150° C. but is preferably between 60° and 80° C.
• Alternatively, the vapor clean20bmay comprise an HF vapor clean. As one example of the parameters needed for an HF vapor clean, the pressure should be 1 mtorr, the temperature should be less than 200° C., and the exposure to HF should last five to ten seconds. The pH can be established at any level between 1 and 10. Still other alternatives include using tetramethylammonium hydroxide (TMAH) in the vapor clean process to assist in cleaning. For purposes of explaining the current invention, the TMAH is assumed to have a pH of 3, although one of ordinary skill in the art can appreciate that the pH level can vary according to the particular passivation requirements of a given embodiment. Also for purposes of explanation, it is assumed that a wafer is undergoing the methods of the current invention, although this is not required to practice the invention, as individual devices could also be processed. In general, the cleaning stage helps to remove residue from etches executed earlier in the device-formation process.
• As a part of thecleaning stage20, an optional wet clean20amay be performed in addition to the vapor clean20b. Preferably, the wet clean20ais performed before the vapor clean20b. This wet clean step20amay be an RCA clean, which involves cleaning solutions developed by RCA. These solutions employ hydrogen peroxide chemistry, the two most common solutions being “standard clean 1” (SC-1) and “standard clean 2” (SC-2). The solution SC-1 typically comprises ammonium hydroxide, hydrogen peroxide, and deionized water in the following volume ratio: 1 NH₄OH: 1 H₂O₂: 5 H₂O. The solution SC-2 generally has the following composition: 6 H₂O: 1 H₂O₂: 1 HCl. Typically wafers are immersed in the RCA cleaning solutions for 10 minutes at 20° to 80° C. for each solution, with deionized water rinses between immersions. There is also a final deionized water rinse after all immersions. The wet clean20aserves to passivate the wafer by allowing for a termination of the silicon surface with hydrogen atoms. In this way, a hydrophilic or a hydrophobic surface can be prepared.
• Once the wafer surface has been cleaned, it is ready for oxide or oxynitride formation, as indicated bystage22. In many embodiments, thisstage22 initially involves growing an oxide on the wafer surface22c, which consumes the silicon down to a particular level within the substrate. However, the current invention includes embodiments wherein oxide is deposited22bat the initiation of thisstage22.
• In at least one embodiment, oxide growth can be accomplished through a rapid thermal oxidation (RTO) process22dat a temperature generally ranging from 800° to 1100° C. This RTO process22dis carried out until it has produced an oxide thickness of at least generally 10 angstroms.
• In addition to this initial step of growing an oxide, there are additional steps which may take place to enhance theoxide formation stage22. For instance, after the vapor clean20bhas been performed, yet before the RTO process22dbegins, it may be beneficial to induce chemical oxide growth on the wafer through an ultraviolet-ozone treatment22a, wherein ultraviolet radiation is used to enhance the oxidation rate of the silicon substrate in an ozone environment. This treatment22ais preferably carried out long enough to provide a high-quality oxide layer having a thickness generally ranging from 10 to 15 angstroms. Regardless of whether the oxide is provided in one step or a plurality of steps, it is preferable to have approximately 30 to 40 angstroms of oxide once step22dhas been completed.
• Once the ultraviolet-ozone treatment22aand the RTO process22dhave been performed, there is an option to provide additional amounts of oxide22g. Further growth22kfrom the consumption of silicon may be used to provide oxide similar to that resulting from the initial growth. Alternatively, an oxide, such as Ta₂O₅(22h), could be deposited. Regardless of the precise methods of providing oxides in these steps22d,22a, and22g, they are understood to cooperate in achieving a given thickness of oxide at the end of theoxide formation stage22. Thus, a greater oxide contribution in one step may relieve the need to produce more oxide in other steps. This “given thickness” of oxide varies depending on the structures formed, as one skilled in the art can appreciate. Exemplary thicknesses are discussed below.
• Achieving this given thickness of oxide is further aided by an optional additional cleaning step22e, such as a second vapor clean22fperformed after an oxidation step and, preferably, interposed between oxidation steps such as22dand22g. As a result of this vapor clean22f, some or all of the oxide present may be removed. If a gate dielectric such as Ta₂O₅is deposited, some of the oxide provided in a prior step should remain to act as an adhesion layer between the substrate and the gate dielectric. In addition to curing any problems that might result from an inadvertent overgrowth of oxide, this second vapor clean22falso serves to remove defects that would otherwise exist in the finished device. Defective oxides can arise if there are certain constituents, such as contaminants, in the silicon from which the oxide grows. As the silicon is consumed in steps such as22dand22a, the resulting oxide may retain those contaminants. By removing all or part of this grown oxide, the second vapor clean22falso removes those contaminants associated with the removed oxide.
• While the amount of oxide at the end of thisstage22 may have a generally constant thickness, such a limitation is not necessary for the present invention. In fact, providing for variations in oxide thickness is actually desired in certain circumstances, such as in providing the topography needed for embedded DRAM memory devices.FIG. 2 illustrates how this topography is achieved in the prior art. As seen inFIG. 2a, a thin layer ofSiO₂30 is grown on thesilicon substrate32.FIG. 2bindicates that the SiO₂layer30 is then covered with amask layer34, such as one made of silicon nitride. Themask layer34 is patterned to expose anarea36 where further oxide growth is desired. Additional oxide growth is then carried out inFIG. 2c, resulting in more silicon being consumed in the exposedarea36, while most of the SiO₂layer30 under thesilicon nitride mask34 retains its original thickness. InFIG. 2d, themask34 and SiO₂layer30 are removed, leaving behind a bi-level topography for thesubstrate32. It is preferred that the resulting levels be parallel, but differences in slopes are allowable to the extent that the devices would still be functional. Further oxidation and masking steps are carried out to form structures such as the fieldoxide isolation regions38 andgate oxide regions40 and41 depicted inFIG. 2e. This prior art method, however, depends on the higher levels of thesubstrate32 being relatively free of constituents such as contaminants. Should thesubstrate32 be contaminated in an area under themask layer34, then thegate oxide40 formed by consuming silicon in that area will also be contaminated.
• At least one embodiment of the current invention is free of such dependency.FIG. 3adepicts theunoxidized substrate32 havingcontaminants42. Some of thesecontaminants42 become part of the grown SiO₂layer30 after oxidation, as depicted inFIG. 3b. The effect of the second vapor clean step22f, shown inFIG. 1, can be seen inFIG. 3c, wherein the SiO₂layer30, along with its associatedcontaminants42, is removed. Subsequent oxidation, masking, and removal steps may then be taken to achieve the bi-level topography needed for embedded DRAM devices. Assuming somecontaminants42 remain in thesubstrate32, the subsequent oxidation and removal steps will preferably eliminate most if not all of thesecontaminants42.
• Moreover, it is not necessary to completely remove the initial SiO₂layer30, as shown in the embodiment depicted inFIGS. 4athrough4e.FIG. 4aonce again shows thesubstrate32 with the SiO₂layer30 grown on top.FIG. 4bdepicts the in-process wafer after the second vapor clean22f, wherein only part of the SiO₂layer30 has been removed as a result of that cleaning. Preferably, this partial oxide removal or subsequent oxide removals will eliminate most if not all of any existing contaminants or other undesired constituents within the SiO₂layer. Assuming an exemplary embedded memory topography is desired, it is preferred that approximately 40 angstroms of the SiO₂layer30 remain after the second vapor clean22f. Themask layer34 is then provided and patterned to expose thearea36. If desired, further cleaning steps could be taken to remove more of the exposed SiO₂layer30 before additional oxide is grown. Alternatively, one may retain the existing SiO₂layer and continue to grow more oxide, as demonstrated inFIG. 4d. Regardless of whether this latest cleaning is performed, it is preferred that the final thickness of the SiO₂layer30 in the exposedarea36 be within a range of approximately 70 to 90 angstroms for this exemplary embedded memory structure. Removing the SiO₂layer30 and themask layer34 reveals the bi-level topography of the wafer ofFIG. 4e. Field oxide regions and gate oxide regions may then be formed by the oxidation/cleaning steps described in the above embodiments or by a method known in the art.
• If an oxynitride layer is desired, then a nitridation step22j(seen inFIG. 1) may be performed on the oxide layer. One possible way to carry out this step22jinvolves rapid thermal nitridation (RTN), wherein ammonia (NH₃) is introduced to the wafer environment and heated with a source, such as a halogen lamp, to a temperature generally ranging from 850° to 1050° C. As a result of this process, the oxide film is rapidly changed to an oxynitride film.
• Regardless of the particular devices being developed on the wafer, once the correct amount of oxide or oxynitride is present, an optional conditioning step22imay be performed. In at least one embodiment, this conditioning step22icomprises hardening the oxide in a nitridizing ambient, such as NO or N₂O. In other embodiments, particularly those involving high dielectric constant materials such as Ta₂O₅, the conditioning step can alternatively include exposure to an ambient comprised of NH₃; dichlorosilane (SiCl₂H₂) and NH₃; an oxygen environment, such as ozone; N₂; Ar; or H₂. This exposure would last for at least ten seconds at preferably five to fifteen atmospheres and at a temperature generally between 500° to 750° C. Another conditioning alternative involves steam oxidation, wherein the dielectric is exposed to a mixture of H₂and O₂. Those skilled in the art understand that such a mixture may be generated by using a plasma torch. The current invention, however, also includes a conditioning step wherein a plasma torch is not used; rather, H₂and O₂are brought together within the process chamber at a pressure of generally one atmosphere or lower and at a temperature generally ranging from 500° to 900° C.
• If an embodiment of the current invention is used to provide a gate oxide, one advantage will be to reduce the current leakage of a device or, at least, counteract factors that could increase the leakage. Moreover, the cleaning, oxidizing, and conditioning steps described above have uses in addition to altering the topography of the silicon substrate and to providing some form of gate oxide. These steps, for example, can be used to form thetunnel oxide44 of aflash memory cell46 depicted inFIG. 5, as well as theentire oxide48 for thatcell46. Theflash memory cell46 pictured is more specifically a flash-electrically erasable programmable read only memory (flash-EEPROM) cell formed in a p-type substrate50 having n-type source and drainregions52,54. Over thesubstrate50, a floatinggate56 is provided within theoxide48. Acontrol gate58 is also withinoxide48 and is located over the floatinggate56. The floatinggate56 is separated from the substrate by thetunnel oxide44. Thistunnel oxide44 is a relatively thin oxide layer; while it can be as thin as thirty to forty angstroms, it is preferably closer to seventy to one hundred angstroms thin. Thetunnel oxide44 is so named because memory programming and erasing is accomplished by way of Fowler-Nordheim tunneling through thistunnel oxide44. Thus, through an embodiment of the current invention, thetunnel oxide44 could be provided through an initial oxidation step with a cleaning to reduce the oxide to a desired thickness. Alternatively, the oxide could be completely cleaned away, allowing a subsequent oxidation step to form thetunnel oxide44 at a lower level of thesubstrate50. The rest of theoxide48 could be formed by an additional oxidation step or by still more oxidation/cleaning cycles.
• As another example, these cleaning, oxidizing, and conditioning steps can be used to provide a gate oxide for devices isolated using a shallow trench isolation (STI) process. Such a device in-progress appears inFIG. 6, wherein an etchedsubstrate60 definestrenches62 that electrically isolate one cell site from another. After providing atrench fill64, thegate oxide66 is grown in a high-pressure oxidation environment using the steps described above. For instance, thegate oxide66 could be grown at a pressure generally ranging from five to fifteen atmospheres.
• Given these varying environments for the oxide, the specific steps taken within the stage of forming astructure24 will depend in part on the context in which the oxide is formed—such as whether it is formed for a gate in an embedded DRAM or to sculpt the substrate to accommodate such a gate, for a floating gate in a tunnel oxide, for a gate in an STI cell, or for other structures. many instances, the stage of forming astructure24 will involve a step of forming a gate24awhich, in turn, is often formed by depositing a polysilicon film. Moreover, a silicon-germanium film may be provided as an option by doping the polysilicon film with germanium, wherein the germanium concentration may generally range from 2% to 25%. Other alternatives to depositing polysilicon include depositing tantalum nitride, titanium nitride, and tungsten nitride.
• Once the stage of forming astructure24 has been completed, the wafer may undergo further processing, such as steps taken to form word lines. It should also be noted that, in a preferred embodiment, it is desirable to cluster the steps from the first vapor clean20bto the stage involving forming astructure24. Of course, in an even more preferred embodiment, every step would be clustered. This would serve to further reduce the constituents such as contaminants that might appear in an oxide as well as other layers.
• In general, this documents discusses, among other things, methods for providing an oxide layer during the processing of a semiconductor device. One exemplary embodiment relates to a method wherein an oxide is provided on a substrate surface and is then subjected to a cleaning process, followed by a provision of still more oxide. The oxide in either step could be grown or deposited. Moreover, the cleaning step may be used to remove all or some of the first provision of oxide. This embodiment has the advantage of removing any oxide that may carry constituents such as contaminants that were part of the underlying substrate. Thus, this embodiment can be used to provide a more contaminant-free oxide for a semiconductor device. Alternatively, this embodiment can be used to selectively consume portions of a substrate, thereby allowing memory structures such as embedded memories to be formed within the lower elevations of the substrate.
• Another exemplary embodiment allows for providing a gate dielectric having a high dielectric constant. Such dielectrics include oxides such as tantalum pentoxide (Ta₂O₅), or layers produced through rapid thermal nitridation (RTN), such as oxynitrides. In this embodiment, a layer of oxide or oxynitride serves as an adhesion layer between the substrate and the subsequently deposited Ta₂O₅. A cleaning step between providing the adhesion layer and providing the Ta₂O₅layer is optional. One advantage of this embodiment is that leakage current can be improved.
• Yet another exemplary embodiment covers a range of steps for processing the semiconductor device, including a vapor clean, an initial oxide growth or deposition, a subsequent oxide growth or deposition, an optional second vapor clean between the two oxide steps, an oxide hardening, and the formation of an electrode over the second oxide. In a more preferred version of this embodiment, these steps are clustered, wherein transportation between the various processes are performed in a common controlled environment, such as a nitrogen atmosphere or a vacuum. The cluster process environment lowers the amount of contaminants having access to the in-process semiconductor device, and the cleaning steps help to negate the effects of any contaminants that appear within the device despite the attempts to control the environment.
• Finally, one skilled in the art can appreciate that, although specific embodiments of this invention have been described above for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. For example, providing oxide under the current invention is not limited to at most two oxidation steps; any number of oxidation steps and cleaning steps as needed are covered, as shown by the arrow inFIG. 1 looping from step22gback to22e. Further, any masking steps that might be needed to allow oxidation and cleaning in selected areas are also included. Accordingly, the invention is not limited except as stated in the claims.

Claims (23)

1. A method for developing a topography in a substrate, comprising:

growing a first layer of oxide from the substrate;

cleaning the first layer; and

growing a second layer of oxide from the substrate.

2. The method ofclaim 1, wherein cleaning the first layer comprises removing at least a portion of the first layer.

3. The method ofclaim 2, further comprising removing the second layer.

4. The method ofclaim 3, wherein removing the at least the portion of the first layer comprises removing all of the first layer.

5. The method ofclaim 2, wherein growing the second layer comprises growing the second layer of oxide in an embedded site of the substrate.

6. A method for forming a tunnel oxide of an in-process memory cell, comprising:

removing contaminants from an area of the in-process memory cell;

oxidizing the area for a first time; and

oxidizing the area for a second time.

7. The method ofclaim 6, wherein removing the contaminants comprises:

performing a pre-oxidation cleaning; and

performing an inter-oxidation cleaning.

8. The method ofclaim 7, wherein performing the inter-oxidation cleaning comprises:

cleaning after oxidizing the area for the first time; and

cleaning before oxidizing the area for the second time.

9. A method of forming a wafer, comprising:

sculpting a portion of the wafer using an oxidation/cleaning cycle; and

forming an oxide layer on the wafer using the oxidation/cleaning cycle.

10. The method ofclaim 9, wherein sculpting the portion of the wafer using the oxidation/cleaning cycle comprises:

oxidizing the wafer;

cleaning away an oxidized material; and

repeating the oxidizing and the cleaning until a particular thickness of the oxidized material remains.

11. The method ofclaim 10, wherein sculpting the portion of the wafer comprises sculpting a substrate of the wafer.

12. The method ofclaim 11, wherein forming the oxide layer on the wafer comprises forming an oxide layer over the portion.

13. The method ofclaim 12, wherein sculpting the portion of the wafer comprises sculpting along a plane within the wafer generally parallel to a surface of the substrate.

14. The method ofclaim 10, wherein repeating the oxidizing and the cleaning comprises repeating the oxidizing and the cleaning until no thickness of the oxidized material remains.

15. A conditioning method, comprising:

providing a process device defining a process chamber;

providing an object within the process chamber; and

mixing H₂and O₂within the process chamber.

16. The method ofclaim 15, wherein providing the process device comprises providing a rapid thermal process device.

17. The method ofclaim 16, wherein mixing H₂and O₂comprises mixing H₂and O₂at a pressure of at most generally one atmosphere.

18. The method ofclaim 17, wherein mixing H₂and O₂comprises mixing H₂and O₂at a temperature generally ranging from 500° C. to 900° C.

19. The method ofclaim 18, wherein providing the object comprises providing an object having a film exposed to the process chamber.

20. The method ofclaim 19, wherein providing the object comprises providing an object having a grown film.

21. A method for affecting a leakage factor of a gated device, comprising:

providing a process area;

controlling clean-room-contaminant access to the process area; and

operating on a wafer within the process area, further comprising:

cleaning the wafer,

providing a gate oxide on the wafer, and

nitridizing the gate oxide within the process area.

22. The method ofclaim 21, wherein nitridizing the gate oxide comprises rapidly thermally nitridizing the gate oxide.

23. The method ofclaim 22, wherein providing the gate oxide comprises:

growing at least one oxide layer; and

cleaning the at least one oxide layer.

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