US20070085213A1 - Selective electroless-plated copper metallization - Google Patents

Abstract

Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate to a thickness of less than 15 nanometers (nm). A number of via holes is defined above the seed layer. A layer of copper is deposited over the seed layer using electroless plating to fill the via holes to a top surface of the patterned photoresist layer. The method can be repeated any number of times, forming second, third and fourth layers of copper. The photoresist layers along with the seed layers in other regions can then be removed, such as by oxygen plasma etching, such that a chemical mechanical planarization process is avoided.

Description

RELATED APPLICATIONS
• This application is a Continuation of U.S. application Ser. No. 10/929,251, filed Aug. 30, 2004, which is a Divisional of U.S. application Ser. No. 09/483,881, filed Jan. 18, 2000, both of which are incorporated herein by reference.
• This application is related to the following co-filed and commonly assigned applications; U.S. application Ser. No. 09/488,098, filed Jan. 18, 2000, now U.S. Pat. No. 6,429,120 and U.S. application Ser. No. 09/484,303, filed Jan. 18, 2000, both of which are hereby incorporated by reference.
FIELD OF THE INVENTION
• The present invention relates generally to integrated circuits. More particularly, it pertains to structures and methods for selective electroless-plated copper metallization.
BACKGROUND OF THE INVENTION
• The rapid progress in miniaturization of integrated circuits (IC) is leading to denser and finer pitched chips with ever increasing performance. In order to enhance the performance of advanced ICs, the interconnect systems are gradually migrating from aluminum-based metallurgy to higher-conductivity and more electromigration-resistant copper. Of the several schemes proposed for fabricating copper interconnects, the most promising method appears to be the Damascene process. Using this method, the trenches and vias are patterned in blanket dielectrics, and then metal is deposited into the trenches and holes in one step, followed by chemical mechanical polishing (CMP) to remove the unwanted surface metal. This leaves the desired metal in the trenches and holes, and a planarized surface for subsequent metallization. During the CMP process, especially for the via holes, more than 99% of the deposited copper is removed, and this is a very wasteful and expensive process, which includes a high usage of consumables such as pads and slurry. Furthermore, the disposition of used materials is a very important environmental issue. Therefore it is highly desirable to accomplish the copper metallization without CMP.
• One approach to the formation of copper vias and metal lines includes the electroless deposition of copper. Electroless deposition of copper is used in printed circuit boards to manufacture copper lines and through holes where the line and hole dimensions are in the several tens to hundreds of microns. The is, of course, much larger than the sub-micron design rules for integrated circuit fabrication on silicon wafers. In this approach, Palladium (Pd) is often used as the activated base metal for electroless copper plating. Several different groups have shown the success of the same. For example, an article published by Bhansali and D. K. Sood, entitled, “A novel technique for fabrication of metallic structure on polyimide by selective electroless copper plating using ion implantation,” Thin Solid Films, vol. 270, p. 489-492, 1995, successfully used palladium ion implantation into polyimide to seed an electroless plated copper film on the polyimide surface. An ion dose range of 1.5×10¹⁵to 1.2×10¹⁷ions/cm²was used. They also reported on the successfull use of copper implantation into silicon to seed the electroless plating using a dose range of 5×10¹⁴to 6.4×10¹⁶ions/cm². (See, Bhansali, S. et al, “Selective electroless copper plating on silicon seeded by copper ion implantation”, Thin Solid Films, vol. 253, no. 1-2, p. 391-394, 1994). An article published by M.-H. Kiang, et al, entitled, “Pd/Si plasma immersion ion implantation for selective electroless copper plating on SiO₂, Applied Physics Letters, vol. 60, no. 22, p. 2767-2769, 1992, demonstrated selective deposition of copper in SiO₂trenches using Pd/Si plasma immersion ion implantation and electroless copper plating. An article published by J.-Y. Zhang et al, entitled, “Investigations of photo-induced decomposition of palladium acetate for electroless copper plating”, Thin Solid Films, vol. 318, p. 234-238, 1998, illustrates photo-induced palladium decomposition of acetate performed by using argon and xenon excimer vacuum ultraviolet sources in the formation of palladium, which acted as a catalyst for subsequent copper plating by means of an electroless bath for selective copper deposition. An article published by M.-H. Bernier et al, entitled, “Laser processing of palladium for selective electroless copper plating”, SPEE Proc., vol. 2045, p. 330-337, 1993 demonstrated that the direct writing of palladium features by the Ar⁺ laser-induced pyrolytic decomposition of an organometallic palladium resins on polyimide and Si₃N₄led to active Pd sites which were selectively copper plated. Also, as described in an article published by J.-L. Yeh et al, entitled, “Selective Copper Plating of Polysilicon surface Micromachined Structures”, Technical digest of 1998 Solid-State Sensor and Actuator Workshop, Transducer Research Foundation Catalog No. 98TRF-0001, p. 248-251, 1998, Yeh et al. exposed polycrystalline silicon structures to a palladium solution that selectively activated the polysilicon structure, but not the silicon oxide or nitride layers. Upon immersion into a copper plating solution at a temperature between 55 and 80° C., the copper nuclei were initially formed on the Pd+ activated polysilicon surface. After the formation of a thin-layer copper, copper started to deposit on this thin initiated copper film. Recently, an article published by V. M. Dubin et al, entitled, “Selective and Blanket Electroless Copper Deposition for Ultralarge Scale Integration”, J. Electrochem. Soc., vol. 144, no. 3, p. 898-908, 1997, disclosed a novel seeding method for electroless copper deposition on sputtered copper films with an aluminum protection layer. This seeding method consisted of (I) deposition of Cu seed layer by sputtering or evaporation, (ii) deposition of a sacrificial thin aluminum layer without breaking vacuum, (iii) etching the aluminum layer in the electroless Cu plating bath, followed by electroless Cu deposition.
• Here, Dubin et al. designed and constructed a single-wafer electroless copper deposition tool with up to 200 mm wafer capability, and an electroless copper deposition process was developed. Electroless Cu films deposited at high plating rate (up to 120 nm/min) in solutions with optimized plating chemical environment exhibited low resistivity (<2 μ ohm cm for as deposited films), low surface roughness, and good electrical uniformity.
• All of these above described methods are rather complex which means that the number of process steps involved in integrated circuit fabrication increases. The problem associated with these methods is that an increase in the number of process steps makes integrated circuit fabrication more costly. Further, none of the above described methods address or provide a resolution to the costly excess expenditure of materials and the environmental concerns when such processes are implemented to form sub-micron vias and metal lines on wafers in a conventional CMP fabrication process.
• For the reasons stated above and for others which will become apparent from reading the following disclosure, structures and methods are needed which alleviate the problems associated with via and metal line fabrication processes. These structures and methods for via and metal line fabrication must be streamlined and accommodate the demand for higher performance in integrated circuits even as the fabrication design rules shrink.
BRIEF DESCRIPTION OF THE DRAWINGS
• The following detailed description of the preferred embodiments can best be understood when read in conjunction with the following drawings, in which:
• FIGS. 1A-1B illustrate an embodiment of the various processing steps for forming vias and metal lines according to the teachings of the prior art;
• FIGS. 2A-2K illustrate an embodiment of the various processing steps for a selective electroless-plated copper metallization according to the teachings of the present invention.
• FIG. 3 is an illustration of an integrated circuit formed according to the teachings of the present invention.
DETAILED DESCRIPTION
• In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
• The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Substrate includes doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term insulator is defined to include any material that is less electrically conductive than the materials generally referred to as conductors by those skilled in the art. The following detailed description is, therefore, not to be taken in a limiting sense.
• FIGS. 1A-1B illustrate an embodiment of the various processing steps for forming vias and metal lines according to the teachings of the prior art. As shown inFIG. 1A, a number of vias101-1 and101-2 are formed in aninsulator material103, e.g. silicon dioxide (SiO₂), contacting with asubstrate100. As one of ordinary skill in the art will recognize, any number of semiconductor devices can be formed in the substrate to which the number of vias101-1 and101-2 make electrical contact.
• Conventionally, to form vias and aluminum wire metal lines, fabricators use a dual-damascene metallization technique, which takes its name from the ancient Damascene metalworking art of inlaying metal in grooves or channels to form ornamental patterns. The dual-damascene technique entails covering the components on a wafer with aninsulative layer103, etching small holes in theinsulative layer103 to expose portions of the components underneath insubstrate100, and subsequently etching shallow trenches from hole to hole to define a number of metal lines. Fabricators then blanket the entire insulative layer with a layer of aluminum or other conductive material and polish off the excess, leaving behind conductive vias, or contact plugs, in the holes and conductive lines in the trenches.
• As shown in the prior art ofFIG. 1A, a layer ofcopper104 can be deposited in the holes and trenches using an electroplated copper deposition technique. As shown inFIG. 1A, thecopper layer104 fills the holes and the trenches, but also covers all of the surfaces features such theinsulator material103 used in the dual damascene process.
• FIG. 1B illustrates the structure after the excess copper has been removed through a chemically mechanical planarization (CMP) process step. As shown in the prior artFIG. 1B, the CMP process step polishes the deposited layer ofcopper104 down to and level with the top surface of theinsulator layer103 to form the copper vias101-1 and101-2 as well as copper metal lines105-1 and105-2. One of ordinary skill in the art will understand, upon viewing the fabrication process illustrated inFIGS. 1A and 1B, the wastefulness in the amount of copper which is discarded in the CMP process step.
METHOD OF THE PRESENT INVENTION
• FIGS. 2A through 2K illustrate a novel methodology for a selective electroless-plated copper metallization according to the teachings of the present invention. Specifically,FIG. 2A through 2K illustrate a method for forming a multilayer copper (Cu) wiring structure on a substrate. The methodology of the present invention avoids the need for a chemical mechanical planarization (CMP) process step in forming the same. As shown inFIG. 2A, a seed layer, or first seed layer,202 is deposited on asubstrate200. In one embodiment, depositing thefirst seed layer202 on thesubstrate200 includes depositing a thin film of Palladium (Pd) on thesubstrate200. In another embodiment, depositing thefirst seed layer202 on thesubstrate200 includes depositing a thin film of Copper (Cu) on the substrate. Theseed layer202 is deposited to have a thickness of less than 15 nanometers (nm). In one exemplary embodiment, theseed layer202 is deposited to form a barely continuous film in the thickness range of 3 to 10 nm. In another exemplary embodiment, theseed layer202 is deposited such that the seed layer possesses a discontinuous island structure in the thickness range of 3 to 10 nm. In one embodiment, theseed layer202 is deposited using a physical vapor deposition process. For example, in one embodiment, theseed layer202 is deposited using a sputtering deposition technique. In another embodiment, theseed layer202 is deposited using an evaporation deposition technique. One of ordinary skill in the art will understand, upon reading this disclosure, the manner in which such physical vapor deposition processes can be performed to form theseed layer202 described herein.
• FIG. 2B illustrates the structure following the next sequence of processing steps. InFIG. 2B, a photolithography technique is used to define a number of via holes, or openings,206-1,206-2, . . . ,206-N, above theseed layer202 on thesubstrate200. As one of ordinary skill in the art will understand upon reading this disclosure, using a photolithography technique to define a number of holes206-1,206-2, . . . ,206-N, includes patterning aphotoresist layer208 to define the number via holes, or openings,206-1,206-2, . . . ,206-N over theseed layer202. One of ordinary skill in the art will also understand upon reading this disclosure, the manner of forming the patterned photoresist layer, or first patterned photoresist layer,208. For example, a photoresist layer can be deposited over theseed layer202 using any suitable technique, e.g. by spin coating. Then the photoresist can be masked, exposed, and washed to define the number of via holes, or openings,206-1,206-2, . . . ,206-N to theseed layer202. One of ordinary skill in the art will further understand, upon reading this disclosure, that the thickness of thephotoresist layer202 is scalable. That is, the deposition of thephotoresist layer208 is controllable such that the photoresist thickness can be set at a predetermined height (h1). Thus, the scalable thickness of thephotoresist layer208 determines a height (h1), or depth (h1) for the number of via holes, or openings,206-1,206-2, . . . ,206-N. The structure is now as appears inFIG. 2B.
• FIG. 2C illustrates the structure following the next sequence of processing steps. InFIG. 2C, a layer of copper, first layer of copper, or first level ofcopper vias210 is deposited over theseed layer202 using electroless plating. One of ordinary skill in the art will understand upon reading this disclosure the various manner in which the layer of copper, first layer of copper, or first level ofcopper vias210 can be deposited over theseed layer202 using electroless plating. According to the teachings of the present invention, the layer of copper, first layer of copper, or first level ofcopper vias210 is formed in the number of via holes, or openings,206-1,206-2, . . . ,206-N. Forming layer of copper, first layer of copper, or first level ofcopper vias210 includes filling the number of via holes, or openings,206-1,206-2, . . . ,206-N to atop surface214 of the firstpatterned photoresist layer208. According to the teachings of the present invention depositing the layer of copper, first layer of copper, or first level ofcopper vias210 over theseed layer202 is such that the layer of copper, first layer of copper, or first level ofcopper vias210 form on theseed layer202 but not on the patternedphotoresist layer208. The structure is now as appears inFIG. 2C.
• FIG. 2D illustrates the structure following the next sequence of processing steps. InFIG. 2D, another seed layer, or second seed layer,216 is deposited on the first layer of copper, or first level ofcopper vias210 and thetop surface214 of the firstpatterned photoresist layer208. In one embodiment, depositing thesecond seed layer216 on the first layer of copper, or first level ofcopper vias210 and thetop surface214 of the firstpatterned photoresist layer208 includes depositing a thin film of Palladium (Pd). In another embodiment, depositing thesecond seed layer216 on the first layer of copper, or first level ofcopper vias210 and thetop surface214 of the firstpatterned photoresist layer208 includes depositing a thin film of Copper (Cu). As before, thesecond seed layer216 is deposited to have a thickness of less than 15 nanometers (nm). In one exemplary embodiment, thesecond seed layer216 is deposited to form a barely continuous film in the thickness range of 3 to 10 nm. In another exemplary embodiment, thesecond seed layer216 is deposited such that thesecond seed layer216 possesses adiscontinuous island structure216 having an island thickness in the range of 3 to 10 nm.
• In one embodiment, thesecond seed layer216 is deposited using a physical vapor deposition process. For example, in one embodiment, thesecond seed layer216 is deposited using a sputtering deposition technique. In another embodiment, thesecond seed layer216 is deposited using an evaporation deposition technique. One of ordinary skill in the art will understand, upon reading this disclosure, the manner in which such physical vapor deposition processes can be performed to form thesecond seed layer216 described herein.
• A secondpatterned photoresist layer218 is deposited above thesecond seed layer216, which defines a number of conductor line openings220-1,220-2, . . . ,220-N. In one embodiment, depositing the secondpatterned photoresist layer218 which defines a number of conductor line openings220-1,220-2, . . . ,220-N, or first level metal line openings220-1,220-2, . . . ,220-N. In one embodiment, the number of conductor line openings220-1,220-2, . . . ,220-N are defined to form a number of conductor line openings220-1,220-2, . . . ,220-N having a near minimum width and spacing. As one of ordinary skill in the art will understand upon reading this disclosure, this insures a sufficient space in the structure for a subsequent removal of the photoresist layers, e.g. first patternedphotoresist layer208, on lower levels. This consideration is described in greater detail in a co-pending, co-filed application, application Ser. No. 09/584,157, filed May 31, 2000, now U.S. Pat. No. 6,674,167, issued on Jan. 6, 2004, entitled, “A Multilevel Copper Interconnect with Double Insulation for ULSI.” One of ordinary skill in the art will understand upon reading this disclosure, the manner of forming the secondpatterned photoresist layer218. For example, a photoresist layer can be deposited over thesecond seed layer216 using any suitable technique, e.g. by spin coating. Then the photoresist can be masked, exposed, and washed to define the number of conductor line openings220-1,220-2, . . . ,220-N to thesecond seed layer216. One of ordinary skill in the art will further understand, upon reading this disclosure, that the thickness of the secondpatterned photoresist layer218 is scalable. That is, the deposition of thephotoresist layer218 is controllable such that the photoresist thickness can be set at a predetermined height (h2). Thus, the scalable thickness of the secondpatterned photoresist layer218 determines a height (h2), or depth (h2) for the number of conductor line openings220-1,220-2, . . . ,220-N. According to the teachings of the present invention, depositing the secondpatterned photoresist layer218 includes depositing the secondpatterned photoresist layer218 to have a thickness (h2) which is less than a thickness (h1) of the firstpatterned photoresist layer208. That is, the thickness (h2) of the secondpatterned photoresist layer218, and consequently a depth (h2) of the number of conductor line openings220-1,220-2, . . . ,220-N, is thinner than a depth (h1) of the first level ofcopper vias210 defined by the thickness (h1) of the firstpatterned photoresist layer208. The structure is now as appears inFIG. 2D.
• FIG. 2E illustrates the structure following the next sequence of processing steps. InFIG. 2E, another layer of copper, second layer of copper, or first level ofconductor lines224 is deposited or formed in the number of conductor line openings220-1,220-2, . . . ,220-N using electroless plating. One of ordinary skill in the art will understand upon reading this disclosure the various manner in which this next layer of copper, second layer of copper, or first level ofconductor lines224 can be deposited in the number of conductor line openings220-1,220-2, . . . ,220-N using electroless plating. According to the teachings of the present invention, forming this next layer of copper, second layer of copper, or first level ofconductor lines224 includes filling the number of conductor line openings220-1,220-2, . . . ,220-N to atop surface226 of the secondpatterned photoresist layer218. According to the teachings of the present invention depositing this next layer of copper, second layer of copper, or first level ofconductor lines224 over thesecond seed layer216 is such that this next layer of copper, second layer of copper, or first level ofconductor lines224 form on thesecond seed layer216 but not on the secondpatterned photoresist layer218. The structure is now as appears inFIG. 2E.
• FIG. 2F illustrates the structure after the following sequence of processing steps. InFIG. 2F, according to the teachings of the present invention, the firstpatterned photoresist layer208 and the secondpatterned photoresist layer218 are removed. In one exemplary embodiment, removing the firstpatterned photoresist layer208 and the secondpatterned photoresist layer218 includes removing the firstpatterned photoresist layer208 and the secondpatterned photoresist layer218 using an oxygen plasma etching. According to the teachings of the present invention, the method further includes removing the first and second seed layers202 and216 with the photoresist layers208 and218 from areas on thesubstrate200 which are not beneath the number ofcopper vias210 or between theconductive metal lines224 and thevias210. As one of ordinary skill in the art will understand from reading this disclosure, this is due the present inventions novel methodology where the seed layers,202 and216, are deposited to have a thickness of less than 15 nanometers (nm), thus forming a barely continuous thin film and/or discontinuous island structure. Other suitable techniques for removing the firstpatterned photoresist layer208 and the secondpatterned photoresist layer218 can similarly be employed.
• At this point, athin diffusion barrier228 can be formed on the exposed first level ofcopper vias210 and first level ofconductor lines224 as well as the remaining, exposed first and second seed layers,202 and216 respectively, located between the substrate, vias, and metal lines. According to the teachings of the present invention, forming athin diffusion barrier228 includes forming a thin diffusion barrier of Tungsten Silicon Nitride (WSi_xN_y)228 having a thickness of less than 8 nanometers (nm). In one embodiment, according to the teachings of the present invention, forming a thin diffusion barrier of Tungsten Silicon Nitride (WSi_xN_y)228 having a thickness of less than 8 nanometers (nm) includes forming a graded composition of WSi_x, where x varies from 2.0 to 2.5, and nitriding the graded composition of WSi_x. The details of forming athin diffusion barrier228, as presented above, are further described in detail in a co-filed, co-pending application; application Ser. No. 09/484,303, filed Jan. 18, 2000, entitled, “Method for Making Copper Interconnects in Integrated Circuits,” which is hereby incorporated by reference. The structure is now as appears inFIG. 2F.
• As one of ordinary skill in the art will understand upon reading this disclosure, forming additional or subsequent layer/levels of conductive vias and metallization lines are also included within the scope of the present invention. In this scenario, the removal of the firstpatterned photoresist layer208 and the secondpatterned photoresist layer218 can be delayed until these subsequent layer are completed, the invention is not so limited. That is, if subsequent layers are to be fabricated, the steps illustrated inFIG. 2F will be delayed and the process will repeat the sequence provided inFIG. 2A-2E.
• FIG. 2G illustrates the forming of subsequent via and metallization layers prior to the process steps ofFIG. 2F and continuing in sequence after the number of process steps completed inFIG. 2E. For example,FIG. 2G shows that in forming subsequent conductive via and metallization layers, another seed layer, or third seed layer,229 is deposited on the second layer of copper, or first level ofconductor lines224 and thetop surface226 of the secondpatterned photoresist layer218. In one embodiment, depositing thethird seed layer229 on the second layer of copper, or first level ofconductor lines224 and thetop surface226 of the secondpatterned photoresist layer218 includes depositing a thin film of Palladium (Pd). In another embodiment, depositing thethird seed layer229 on the second layer of copper, or first level ofconductor lines224 and thetop surface226 of the secondpatterned photoresist layer218 includes depositing a thin film of Copper (Cu). As before, thethird seed layer229 is deposited to have a thickness of less than 15 nanometers (nm). In one exemplary embodiment, thethird seed layer229 is deposited to form a barely continuous film in the thickness range of 3 to 10 nm. In another exemplary embodiment, thethird seed layer229 is deposited such that thethird seed layer229 possesses adiscontinuous island structure229 having an island thickness in the range of 3 to 10 nm.
• In one embodiment, thethird seed layer229 is deposited using a physical vapor deposition process. For example, in one embodiment, thethird seed layer229 is deposited using a sputtering deposition technique. In another embodiment, thethird seed layer229 is deposited using an evaporation deposition technique. One of ordinary skill in the art will understand, upon reading this disclosure, the manner in which such physical vapor deposition processes can be performed to form thethird seed layer229 described herein.
• InFIG. 2G, a thirdpatterned photoresist layer230 is deposited above thethird seed layer229, which defines a number of via holes, or openings,232-1,232-2, . . . ,232-N to thethird seed layer229. One of ordinary skill in the art will understand upon reading this disclosure, the manner of forming the thirdpatterned photoresist layer230. For example, a photoresist layer can be deposited over thethird seed layer229 using any suitable technique, e.g. by spin coating. Then the photoresist can be masked, exposed, and washed to define the number of via holes, or openings,232-1,232-2, . . . ,232-N to thethird seed layer229. One of ordinary skill in the art will further understand, upon reading this disclosure, that the thickness of the secondpatterned photoresist layer218 is scalable. That is, the deposition of thephotoresist layer230 is controllable such that the photoresist thickness can be set at a predetermined height (h3). Thus, the scalable thickness of the secondpatterned photoresist layer230 determines a height (h3) for the number of via holes, or openings,232-1,232-2, . . . ,232-N. The structure is now as appears inFIG. 2G.
• FIG. 2H illustrates the structure continuing on from the process steps included inFIG. 2G. InFIG. 2H, another layer of copper, third layer of copper, or second level ofcopper vias234 is deposited or formed over thethird seed layer229 using electroless plating. One of ordinary skill in the art will understand upon reading this disclosure the various manner in which the third layer of copper, or second level ofcopper vias234 can be deposited over thethird seed layer229 using electroless plating. According to the teachings of the present invention, the third layer of copper, or second level ofcopper vias234 is formed in the number of via holes, or openings,232-1,232-2, . . . ,232-N to thethird seed layer229. Forming the third layer of copper, or second level ofcopper vias234 includes filling the number of via holes, or openings,232-1,232-2, . . . ,232-N to atop surface236 of the thirdpatterned photoresist layer230. According to the teachings of the present invention, depositing third layer of copper, or second level ofcopper vias234 over thethird seed layer229 is such that the third layer of copper, or second level ofcopper vias234 form on thethird seed layer229 but not on the thirdpatterned photoresist layer230. The structure is now as appears inFIG. 2H.
• FIG. 2I illustrates the structure following the next sequence of processing steps. InFIG. 2I, another seed layer, or fourth seed layer,238 is deposited on the third layer of copper, or second level ofcopper vias234 and thetop surface236 of the thirdpatterned photoresist layer230. In one embodiment, depositing thefourth seed layer238 on the third layer of copper, or second level ofcopper vias234 and thetop surface236 of the thirdpatterned photoresist layer230 includes depositing a thin film of Palladium (Pd). In another embodiment, depositing thefourth seed layer238 on the third layer of copper, or second level ofcopper vias234 and thetop surface236 of the thirdpatterned photoresist layer230 includes depositing a thin film of Copper (Cu). As before, thefourth seed layer238 is deposited to have a thickness of less than 10 nanometers (nm). In one exemplary embodiment, thefourth seed layer238 is deposited to form a barely continuous film in the thickness range of 3 to 10 nm. In another exemplary embodiment, thefourth seed layer238 is deposited such that thefourth seed layer238 possesses adiscontinuous island structure238 having an island thickness in the range of 3 to 10 nm.
• In one embodiment, thefourth seed layer238 is deposited using a physical vapor deposition process. For example, in one embodiment, thefourth seed layer238 is deposited using a sputtering deposition technique. In another embodiment, thefourth seed layer238 is deposited using an evaporation deposition technique. One of ordinary skill in the art will understand, upon reading this disclosure, the manner in which such physical vapor deposition processes can be performed to form thefourth seed layer238 described herein.
• A fourthpatterned photoresist layer240 is deposited above thefourth seed layer238, which defines a number of conductor line openings242-1,242-2, . . . ,242-N. In one embodiment, depositing the fourthpatterned photoresist layer240 which defines a number of conductor line openings242-1,242-2, . . . ,242-N includes defining a number of second level metal line openings242-1,242-2, . . . ,242-N. In one embodiment, the second number of conductor line openings242-1,242-2, . . . ,242-N are defined to form a number of conductor line openings242-1,242-2, . . . ,242-N having a near minimum width and spacing. As one of ordinary skill in the art will understand upon reading this disclosure, this insures a sufficient space in the structure for a subsequent removal of the photoresist layers, e.g. first, second, and thirdpatterned photoresist layer208,218, and230 on lower levels. This consideration is described in greater detail in a co-pending, co-filed application, application Ser. No. 09/584,157, filed May 31, 2000, now U.S. Pat. No. 6,674,167, issued on Jan. 6, 2004, entitled, “A Multilevel Copper Interconnect with Double Insulation for ULSI.” One of ordinary skill in the art will understand upon reading this disclosure, the manner of forming the fourthpatterned photoresist layer240. For example, a photoresist layer can be deposited over thefourth seed layer238 using any suitable technique, e.g. by spin coating. Then the photoresist can be masked, exposed, and washed to define the number of conductor line openings242-1,242-2, . . . ,242-N to thefourth seed layer238. One of ordinary skill in the art will further understand, upon reading this disclosure, that the thickness of the fourthpatterned photoresist layer240 is scalable. That is, the deposition of the fourthpatterned photoresist layer240 is controllable such that the photoresist thickness can be set at a predetermined height (h4). Thus, the scalable thickness of the fourthpatterned photoresist layer240 determines a height (h4) for the number of conductor line openings242-1,242-2, . . . ,242-N. According to the teachings of the present invention, depositing the fourthpatterned photoresist layer240 includes depositing the fourthpatterned photoresist layer240 to have a thickness (h4) which is less than a thickness (h3) of the thirdpatterned photoresist layer230. That is, the thickness (h3) of the thirdpatterned photoresist layer230 is thinner than a depth (h3) of the second level ofcopper vias234 defined by the thickness (h3) of the thirdpatterned photoresist layer230. The structure is now as appears inFIG. 2I.
• FIG. 2J illustrates the structure following the next sequence of processing steps. InFIG. 2E, another layer of copper, fourth layer of copper, or second level ofconductor lines244 is deposited or formed in the number of conductor line openings242-1,242-2, . . . ,242-N using electroless plating. One of ordinary skill in the art will understand upon reading this disclosure the various manner in which this fourth layer of copper, or second level ofconductor lines244 can be deposited in the number of conductor line openings242-1,242-2, . . . ,242-N using electroless plating. According to the teachings of the present invention, forming this fourth layer of copper, or second level ofconductor lines244 includes filling the number of conductor line openings242-1,242-2, . . . ,242-N to atop surface246 of the fourthpatterned photoresist layer240. According to the teachings of the present invention depositing this fourth layer of copper, or second level ofconductor lines244 over thefourth seed layer238 is such that this fourth layer of copper, or second level ofconductor lines244 form on thefourth seed layer238 but not on the fourthpatterned photoresist layer240. The structure is now as appears inFIG. 2J.
• FIG. 2K illustrates the structure after the following sequence of processing steps. InFIG. 2K, according to the teachings of the present invention, the first, second, third, and fourth patterned photoresist layers208,218,230, and240 are removed. In one exemplary embodiment, removing the first, second, third, and fourth patterned photoresist layers208,218,230, and240 includes removing the first, second, third, and fourth patterned photoresist layers208,218,230, and240 using an oxygen plasma etching. According to the teachings of the present invention, the method further includes removing the first, second, third, and fourth seed layers,202,216,229 and238 respectively, with the photoresist layers from areas on the substrate which are not beneath the number of copper vias or between the conductive metal lines and the vias. As one of ordinary skill in the art will understand from reading this disclosure, this is due the present inventions novel methodology where the seed layers,202,216,229 and238, are deposited to have a thickness of less than 15 nanometers (nm), thus forming a barely continuous thin film and/or discontinuous island structure. Other suitable techniques for removing the first, second, third, and fourth patterned photoresist layers208,218,230, and240 can similarly be employed. As one of ordinary skill in the art will further understand upon reading this disclosure, the first, second, third, and fourth patterned photoresist layers208,218,230, and240 can be removed at earlier or later stages of a fabrication process, as described herein, depending on the number of via and metal levels to be formed.
• At this point, or as could equally be performed at an earlier or later stage depending on when the photoresist layers are removed, athin diffusion barrier248 can be formed on the exposed first and second level ofcopper vias210,234 and the exposed first and second level ofconductor lines224,244 as well as the remaining, exposed first, second, third, and fourth seed layers,202,216,229 and238 respectively, located between the substrate, vias, and metal lines. According to the teachings of the present invention, forming athin diffusion barrier248 includes forming a thin diffusion barrier of Tungsten Silicon Nitride (WSi_xN_y)248 having a thickness of less than 8 nanometers (nm). In one embodiment, according to the teachings of the present invention, forming a thin diffusion barrier of Tungsten Silicon Nitride (WSi_xN_y)248 having a thickness of less than 8 nanometers (nm) includes forming a graded composition of WSi_x, where x varies from 2.0 to 2.5, and nitriding the graded composition of WSi_x. The details of forming athin diffusion barrier228, as presented above, are further described in detail in a co-filed, co-pending application; application Ser. No. 09/484,303, filed Jan. 18, 2000, entitled, “Method for Making Copper Interconnects in Integrated Circuits,” which is hereby incorporated by reference. The structure is now as appears inFIG. 2K.
• Structure
• FIG. 3 is an illustration of anintegrated circuit300 formed according to the teachings of the present invention. According to the teachings of the present invention, theintegrated circuit300 includes a multilayer copper wiring structure. As shown inFIG. 3, theintegrated circuit300 includes at least onesemiconductor device301 formed in asubstrate302. A first number of seed layers304-1,304-2, . . . ,304-N are formed on a number of portions305-1,305-2, . . . ,305-N of the at least one semiconductor device. As one of ordinary skill in the art will understand upon reading this disclosure the number of portions305-1,305-2, . . . ,305-N of the at least onesemiconductor device301 include the number of portions305-1,305-2, . . . ,305-N of asemiconductor device301 which require electrical contact to subsequent integrated circuit layers formed above thesemiconductor device301. For example, the at least onesemiconductor device301 can include at least onetransistor301 which has a source and a drain region. In this scenario, the number of portions305-1,305-2, . . . ,305-N of asemiconductor device301 which require electrical contact to subsequent integrated circuit layers formed above thesemiconductor device301 include the source and the drain regions305-1,305-2, . . . ,305-N.
• As shown inFIG. 3, a number of copper vias307-1,307-2, . . . ,307-N, or first level of copper vias307-1,307-2, . . . ,307-N, are formed above and contact with the first number of seed layers304-1,304-2, . . . ,304-N. According to the teachings of the present invention, the first number of seed layers304-1,304-2, . . . ,304-N include a thin film of Palladium (Pd) or Copper. Further, the first number of seed layers304-1,304-2, . . . ,304-N have a thickness of less than 15 nanometers (nm). In one embodiment, the first number of seed layers304-1,304-2, . . . ,304-N includes a first number of seed layers304-1,304-2, . . . ,304-N having a discontinuous island structure with an island thickness in the range of 3 to 10 nanometers.
• A second number of seed layers309-1,309-2, . . . ,309-N are formed on the number of copper vias307-1,307-2, . . . ,307-N. According to the teachings of the present invention, the second number of seed layers309-1,309-2, . . . ,309-N include a thin film of Palladium (Pd) or Copper. Further, the second number of seed layers309-1,309-2, . . . ,309-N have a thickness of less than 15 nanometers (nm). In one embodiment, the second number of seed layers309-1,309-2, . . . ,309-N includes a second number of seed layers309-1,309-2, . . . ,309-N having a discontinuous island structure with an island thickness in the range of 3 to 10 nanometers.
• A number of conductor metal lines311-1,311-2, . . . ,311-N, or first level of conductor metal lines311-1,311-2, . . . ,311-N, are formed above and contact with the second number of seed layers309-1,309-2, . . . ,309-N. In one embodiment, the first level of conductor metal lines311-1,311-2, . . . ,311-N includes a number of copper metal lines311-1,311-2, . . . ,311-N. In one embodiment, as shown inFIG. 3, theintegrated circuit300 further includes athin diffusion barrier315 covering the number of copper vias307-1,307-2, . . . ,307-N, the number of conductor metal lines311-1,311-2, . . . ,311-N, and the first and the second number of seed layers,304-1,304-2, . . . ,304-N, and309-1,309-2, . . . ,309-N respectively. According to the teachings of the present invention, thethin diffusion barrier315 has a thickness of less than 8.0 nanometers (mm). In one embodiment, the thin diffusion barrier has a thickness in the range of 2.0 to 6.0 nanometers. In one embodiment, thethin diffusion barrier315 includes a graded composition of Tungsten Silicon Nitride (WSi_xN_y), and wherein x varies from 2.0 to 2.5.
• In one embodiment, as shown inFIG. 3, the integrated circuit, or multilayercopper wiring structure300 includes a third number of seed layers317-1,317-2, . . . ,317-N, including a thin film of Palladium (Pd) or Copper, are formed on the first level of copper metal lines311-1,311-2, . . . ,311-N, or first level of conductor metal lines311-1,311-2, . . . ,311-N. Further, the third number of seed layers317-1,317-2, . . . ,317-N have a thickness of less than 15 nanometers (nm). In one embodiment, the third number of seed layers317-1,317-2, . . . ,317-N includes a third number of seed layers317-1,317-2, . . . ,317-N having a discontinuous island structure with an island thickness in the range of 3 to 10 nanometers. A second level of copper vias319-1,319-2, . . . ,319-N are formed above and contacting the third number of seed layers317-1,317-2, . . . ,317-N. A fourth number of seed layers321-1,321-2, . . . ,321-N, including a thin film of Palladium (Pd) or Copper, are formed on the second level of copper vias319-1,319-2, . . . ,319-N. In one embodiment, the fourth number of seed layers321-1,321-2, . . . ,321-N includes a fourth number of seed layers321-1,321-2, . . . ,321-N having a discontinuous island structure with an island thickness in the range of 3 to 10 nanometers. A second level of copper metal lines323-1,323-2, . . . ,323-N, or second level of conductor metal lines323-1,323-2, . . . ,323-N, are formed above and contacting fourth number of seed layers321-1,321-2, . . . ,321-N.
• In one embodiment, as shown inFIG. 3, thethin diffusion barrier315 further covers the second level of copper vias319-1,319-2, . . . ,319-N, the second level of copper metal lines323-1,323-2, . . . ,323-N, and the third, and fourth number of seed layers,317-1,317-2, . . . ,317-N and321-1,321-2, . . . ,321-N respectively.
CONCLUSION
• Thus, structures and methods have been shown which include a selective electroless copper metallization. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper which will not require chemical mechanical planarization (CMP). Thus, the present invention is streamlined and significantly reduces the amount of deposited conductive material, e.g. copper, which is ultimately discarded according to conventional processes. This also alleviates important environmental concerns regarding the disposition of used materials. Further, by avoiding the need for a CMP process step the usage of consumables such as pads and slurry is conserved.
• The above mentioned problems associated with integrated circuit size and performance, the via and metal line formation process, and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Structures and methods are provided which include a selective electroless copper metallization. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which will not require chemical mechanical planarization (CMP). Thus, the present invention significantly reduces the amount of deposited conductive material, e.g. copper, which is ultimately discarded according to conventional processes. This alleviates important environmental concerns regarding the disposition of used materials. Further, by avoiding the need for a CMP process step, the usage of consumables such as pads and slurry is conserved.
• In particular, an illustrative embodiment of the present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate. The seed layer is deposited to a thickness of less than 15 nanometers (nm). A photolithography technique is used to define a number of via holes above the seed layer. In one embodiment, using a photolithography technique includes forming a patterned photoresist layer to define the number of via holes above the seed layer. A layer of copper is deposited over the seed layer using electroless plating filling the number of via holes to a top surface of the patterned photoresist layer. The method can be repeated any number of times depositing a second seed layer, depositing another patterned photoresist layer defining a number of conductor line openings above the second seed layer, and forming a second layer of copper using electroless plating which fills the number of conductor line openings to a top surface of the second patterned photoresist layer. The photoresist layers along with the seed layers in other regions can then be removed by ashing and a chemical mechanical planarization process is avoided. Structures formed by this novel process are similarly included within the scope of the present invention.
• These and other embodiments, aspects, advantages, and features of the present invention are set forth in part in the description, and in part will become apparent to those skilled in the art by reference to the description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
• Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (33)

1. An electronic circuit, comprising:

a plurality of individual electrical devices interconnected by a plurality of metallic conductor lines;

a plurality of electrical contact areas on a top surface of the plurality of individual electric devices;

each of the plurality of electrical contact areas in contact with a first metallic layer;

the metallic layer in contact with a plurality of substantially vertical metal columns;

a top surface of the substantially vertical metal columns in contact with at least one of a second metallic layer and a portion of a bottom surface of a plurality of substantially horizontal metal lines; and

a diffusion barrier layer covering substantially the entirety of a top surface, side surfaces and all portions of the bottom surface not in contact with the top surface of the vertical metal columns of the plurality of substantially horizontal metal lines, and the diffusion barrier layer covering substantially the entirety of sidewalls of the vertical metal columns.

2. The electronic circuit ofclaim 1, wherein the plurality of substantially vertical metal columns are separated from each other by a gas, forming air bridges.

3. The electronic circuit ofclaim 1, wherein the diffusion barrier layer has a thickness of less than 8.0 nanometers (nm).

4. The electronic circuit ofclaim 1, wherein the first and second metallic layers have a thickness of less than 15 nanometers (nm).

5. The electronic circuit ofclaim 1, wherein the first and second metallic layers have a thickness of less than 5 nanometers (nm).

6. The electronic circuit ofclaim 1, wherein the first and second metallic layers includes a discontinuous island structure having islands less than 50 nanometers (nm) in diameter.

7. The electronic circuit ofclaim 1, wherein the substantially vertical metal columns and the substantially horizontal metal lines include copper.

8. The electronic circuit ofclaim 1, wherein the first and second metallic layers are formed of a material selected from a list consisting of palladium (Pd), copper (Cu), aluminum (Al), platinum (Pt), and combinations thereof.

9. The electronic circuit ofclaim 1, wherein the first metallic layer only contacts the plurality of electrical contact areas on the top surface of the individual electric devices.

10. The electronic circuit ofclaim 1, wherein the plurality of electronic devices are disposed in a substrate.

11. The electronic circuit ofclaim 10, wherein the substrate is a semiconducting material and the electronic circuit is an integrated circuit.

12. The electronic circuit ofclaim 1, wherein each of the plurality of substantially vertical metal columns is directly above one of the plurality of electrical contact areas on a top surface of the plurality of individual electrical devices.

13. The electronic circuit ofclaim 1, wherein the diffusion barrier layer comprises tungsten, silicon and nitrogen.

14. An integrated circuit, comprising:

a substrate including a plurality of transistors each having electrical contact areas;

individual ones of the plurality of transistors electrically interconnected by air bridge conductors comprising:

a plurality of metallic regions formed on the electrical contact areas of the plurality of transistors including a layer comprising at least one of palladium (Pd) and copper (Cu) having a thickness of less than 15 nanometers (nm);

each of the plurality of metallic regions contacting a vertical copper via formed above and contacting a bottom portion of one of a plurality of horizontal copper interconnect line; and

a diffusion barrier layer comprising surrounding the vertical copper vias and the horizontal copper interconnect except for the top and bottom surfaces of the vertical copper vias and the bottom contact points between the horizontal copper interconnect lines and the top surface of the vertical copper vias.

15. The integrated circuit ofclaim 14, wherein the diffusion barrier has a thickness of less than 8.0 nanometers (nm).

16. The integrated circuit ofclaim 15, wherein the diffusion barrier includes a graded composition of Tungsten Silicon Nitride (WSixNy), and wherein x varies from 2.0 to 2.5.

17. The integrated circuit ofclaim 14, wherein the metallic regions formed on the electrical contact areas of the plurality of transistors comprises unconnected islands of palladium between the lower surface of the vertical copper vias and the contact regions of the plurality of transistors.

18. An integrated circuit, comprising:

a plurality of devices formed in a semiconductor substrate;

a dielectric layer disposed over the semiconductor substrate including a plurality of contact holes;

a first metallic layer contacting portions of a surface of the semiconductor substrate exposed by the plurality of contact holes in the dielectric layer;

each of the plurality of contact holes including a substantially vertical metal column contacting the first metallic layer and extending above a top surface of the dielectric layer;

a second metallic layer contacting a top portion of the substantially vertical metal columns;

a plurality of substantially horizontal metal lines formed above and contacting the second metallic layer proximate to the top of the substantially vertical metal columns;

a diffusion barrier covering substantially the entirety of a top surface, a side surface and portions of a bottom surface of the substantially horizontal metal lines not in contact with the second metallic layer; and

the diffusion barrier covering substantially the entirety of portions of a sidewall of the substantially vertical metal columns not in contact with the dielectric layer.

19. The integrated circuit ofclaim 18, wherein the first and second metallic layers include at least one of palladium (Pd) and copper (Cu).

20. The integrated circuit ofclaim 18, wherein the first and second metallic layers have a barely continuous web within the contact holes, with a thickness from of 3 to 5 nanometers.

21. The integrated circuit ofclaim 18, wherein the first metallic layer comprises a discontinuous layer within each of the contact holes.

22. The integrated circuit ofclaim 21, wherein the first metallic layer comprises a plurality of non-connected islands within each of the contact holes.

23. The integrated circuit ofclaim 18, wherein the substantially vertical metal columns comprise copper.

24. The integrated circuit ofclaim 18, wherein the diffusion barrier comprises tungsten silicon nitride.

25. The integrated circuit ofclaim 18, wherein the diffusion barrier has a thickness of less than 8.0 nanometers.

26. The integrated circuit ofclaim 25, wherein the diffusion barrier comprises a graded composition of (WSixNy), and wherein x varies from 2.0 to 2.5.

27. An integrated circuit, comprising:

a plurality of devices formed in a semiconductor substrate;

a dielectric layer disposed over the semiconductor substrate including a plurality of contact holes;

a first metallic layer contacting portions of a surface of the semiconductor substrate exposed by the plurality of contact holes in the dielectric layer;

each of the plurality of contact holes including a substantially vertical metal column contacting the first metallic layer and extending above a top surface of the dielectric layer to form a first plurality of substantially vertical metal columns;

a second metallic layer contacting a top portion of each of the first plurality of substantially vertical metal columns;

a first plurality of substantially horizontal metal lines formed above and contacting the second metallic layer proximate to the top of the first plurality of substantially vertical metal columns;

a third metallic layer contacting a portion of a top surface of the first plurality of substantially horizontal metal lines;

a second plurality of substantially vertical metal columns disposed contacting the third metallic layer and the top surface of the substantially horizontal metal lines;

a fourth metallic layer contacting a top portion of each of the second plurality of substantially vertical metal columns;

a second plurality of substantially horizontal metal lines formed above and contacting the fourth metallic layer proximate to the top of the second plurality of substantially vertical metal columns; and

a diffusion barrier covering substantially the entirety of any portion of the first and second plurality of substantially vertical columns not in directly contact with the dielectric layer or the first or second substantially horizontal metal lines, and the diffusion barrier covering substantially the entirety of any portion of the first and second substantially horizontal metal lines not in contact with the first and second substantially vertical columns.

28. The integrated circuit ofclaim 27, wherein each of the metallic layers comprise palladium (Pd) or copper (Cu), and have a thickness in the range of 3 to 10 nanometers.

29. The integrated circuit ofclaim 28, wherein the first metallic layer is confined within the contact holes and comprises a discontinuous layer.

30. The integrated circuit ofclaim 27, wherein the first and second substantially vertical metal columns comprise copper.

31. The integrated circuit ofclaim 27, wherein the diffusion barrier comprises tungsten silicon nitride.

32. The integrated circuit ofclaim 27, wherein the diffusion barrier has a thickness of about 2.0-8.0 nanometers.

33. The integrated circuit ofclaim 27, wherein the diffusion barrier comprises a graded composition of (WSixNy), wherein x varies from 2.0 to 2.5.

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