US20070076502A1 - Daisy chain cascading devices - Google Patents

Abstract

A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO). Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device in the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device's SI is passed through the device and output from the device via the device's SO. The information is then transferred to the later device's SI via the connection from the earlier device's SO and the later device's SI.

Description

RELATED APPLICATION(S)
• This application is a continuation in part of U.S. patent application Ser. No. 11/324,023 filed Dec. 30, 2005 which claims the benefit of U.S. Provisional Application No. 60/722,368, filed on Sep. 30, 2005 and this application claims the benefit of U.S. Provisional Application No. 60/787,710, filed on Mar. 28, 2006. The entire teachings of the above applications are incorporated herein by reference.
BACKGROUND OF THE INVENTION
• Today computer-based systems can be found most everywhere and have made inroads into many devices that are used by society everyday, such as cell phones, handheld computers, automobiles, medical devices, personal computers and so on. In general, society has placed much reliance on computer-based systems to handle everyday tasks such as simple tasks like balancing checkbooks to relatively complex tasks such as predicting the weather. As technology improves, more and more tasks are migrated to computer-based systems. This, in turn, causes society to become more and more reliant on these systems.
• A typical computer-based system comprises a system board and optionally one or more peripheral devices, such as display units, storage units and the like. The system board may contain one or more processors, a memory subsystem and other logic, such as serial device interfaces, network device controllers, hard disk controllers and the like.
• The type of processors that are employed on a particular system board usually depends on the type of tasks performed by the system. For example, a system that performs a limited set of tasks, such as monitor emissions generated by an automobile engine and adjust an air/fuel mixture to ensure the engine is burning fuel completely may employ a simple specialized processor that is tailored to performing these tasks. On the other hand, a system that performs many different tasks, such as managing many users and running many different applications, may employ one or more complex processors that are general purpose in nature, configured to perform high-speed calculations and manipulate data to minimize the response time to servicing the users' requests.
• The memory subsystem is a storage that holds information (e.g., instructions, data values) used by the processors. The memory subsystem typically comprises controller logic and one or more memory devices. The controller logic typically is configured to interface the memory devices with the processors and enable the processors to store and retrieve information to and from the memory devices. The memory devices hold the actual information.
• Like the processors, the type of devices employed in a memory subsystem is often driven by the type of tasks performed by the computer system. For example, a computer system may have the task of having to boot without the assistance of a disk drive and execute a set of software routines that do not change often. Here, the memory subsystem may employ non-volatile devices, such as flash memory devices, to store the software routines. Other computer systems may execute very complex tasks that require a large high-speed data store to hold large portions of information. Here, the memory subsystem may employ high-speed high-density Dynamic Random Access Memory (DRAM) devices to store large portions of information.
• Devices in a memory subsystem are often interconnected using a parallel interconnection scheme. This scheme involves interconnecting the devices in a manner such that address and data information and control signals are coupled to the devices in a parallel fashion. Each device may incorporate multiple inputs/outputs to accommodate the parallel transfer of the data and address information as well as control signals to the devices.
SUMMARY OF THE INVENTION
• One shortcoming associated with utilizing parallel interconnections in a memory subsystem is that they tend to require a large number of interconnections between the devices in order to transfer information and signals to the devices in parallel. This adds to the complexity of boards that implement these subsystems. Moreover, undesirable effects associated with large numbers of interconnections, such as crosstalk, tend to limit the performance of these subsystems. In addition, the number of devices incorporated in these subsystems may be limited due to propagation delay of signals carried by the interconnections.
• The techniques described herein overcome the above shortcomings by providing a technique for coupling devices in a serial daisy chain cascading arrangement that employs fewer and shorter connections than parallel interconnection implementations. Configuring devices in the daisy chain arrangement may allow the devices to be operated at higher speeds than parallel interconnection implementations because utilizing fewer and shorter interconnections makes the overall implementation less vulnerable to undesirable effects, such as propagation delay and crosstalk. Moreover, fewer and shorter connections tend to reduce the complexity of the implementation. This reduced complexity further enables a subsystem containing the devices to be implemented in a smaller area thus allowing the subsystem to occupy a smaller footprint.
• According to aspects of the techniques described herein, devices are coupled in a daisy chain cascade arrangement such that outputs of an earlier device in the daisy chain cascade are coupled to inputs of the next device later in the daisy chain to accommodate the transfer of information (e.g., data, address and command information) and control signals (e.g., enable signals) from the earlier device to the latter device.
• In an embodiment of the techniques, each device in the daisy chain cascade comprises a serial input (SI) and a serial output (SO). Information is input to a device via its SI. Likewise, the information is output from the device via its SO. The SO of a device in the daisy chain cascade is coupled to the SI of the next device in the daisy chain cascade. Circuitry is provided in the devices to enable information input to an earlier device in the daisy chain cascade via its SI to be passed through the device and output from the device via its SO. The information is then transferred to the SI of the next device in the daisy chain cascade via the connection between the earlier device's SO and the next device's SI. The transferred information may then be inputted to the next device via its SI.
• In addition, a clock signal is coupled to the devices in the daisy chain cascade. The clock signal is used by the devices to accommodate the transfer of the information from one device to the next device in the daisy chain cascade.
• In accordance with other aspects of the techniques described herein, control signals (e.g., enable signals) that are utilized by the devices to, e.g., enable data to be input to the device via the SI and output from the device via the SO are transferred between devices in the daisy chain cascade, as described above. Here, circuitry is provided to enable control signals input to an earlier device in the daisy chain cascade to be propagated through the device and transferred from the device via an output to an input of a next device in the daisy chain cascade. The transferred signals are then input to the next device via the input.
BRIEF DESCRIPTION OF THE DRAWINGS
• The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.
• FIG. 1 is a block diagram of an exemplary device configuration comprising a plurality of single port devices configured in a serial daisy chain cascade arrangement.
• FIG. 2 is a block diagram of an exemplary device configuration comprising a plurality of single port devices configured in a serial daisy chain cascading arrangement having a cascaded clock.
• FIG. 3 is a block diagram of an exemplary device configuration comprising a plurality of dual port devices configured in a serial daisy chain cascade arrangement.
• FIG. 4 is a block diagram of an exemplary device configuration comprising a plurality of single port devices configured in a serial daisy chain arrangement having inputs and outputs for various enable signals.
• FIG. 5 is a block diagram of an exemplary device configuration comprising dual port devices configured in a serial daisy chain arrangement having inputs and outputs configured for various enable signals.
• FIG. 6 is a block diagram of an exemplary device configuration comprising a plurality of devices having multiple parallel inputs and multiple parallel outputs which are configured in a serial daisy chain cascading arrangement.
• FIG. 7 is a timing diagram illustrating timing associated with a read operation performed on a single device configured and a plurality of devices configured in a serial daisy chain cascade arrangement.
• FIG. 8 is a timing diagram illustrating timing associated with information transferred between devices configured in a serial daisy chain cascade arrangement.
• FIG. 9 is a high-level block diagram of exemplary serial output control logic for a single ported device.
• FIG. 10 is a high-level block diagram of exemplary serial output control logic for a dual ported device.
• FIG. 11 is a detailed block diagram of exemplary serial output control logic for a device.
• FIG. 12 is a block diagram of an exemplary configuration of devices configured in a serial daisy chain cascading arrangement and containing exemplary serial output control logic.
• FIG. 13 is a timing diagram illustrating timing associated with inputs and outputs of the devices comprising exemplary serial output control logic.
• FIG. 14 is a block diagram of exemplary serial output control logic that may be used to transfer data from memory contained in a first device in a daisy chain cascade to a second device in the daisy chain cascade.
• FIG. 15 is a timing diagram illustrating timing associated with transferring data contained in memory of a first device in a daisy chain cascade to a second device in the daisy chain cascade using exemplary serial output control logic.
DETAILED DESCRIPTION OF THE INVENTION
• A description of preferred embodiments of the invention follows.
• FIG. 1 is a block diagram of an exemplary device configuration comprising a plurality of single port devices110a-econfigured in a serial daisy chain cascade arrangement. The devices110a-eare illustratively memory devices each of which contains a memory (not shown) which may comprise Dynamic Random Access Memory (DRAM) cells, Static Random Access Memory (SRAM) cells, flash memory cells and the like. Each device110 comprises a serial input (SI), a serial output (SO), a clock (SCLK) input and a chip select (CS#) input.
• The SI is used to transfer information (e.g., command, address and data information) into the device110. The SO is used to transfer information from the device110. The SCLK input is used to provide an external clock signal to the device110 and the CS# input is used to provide a chip select signal to the device110. An example of a device that may be used with the techniques described herein is a Multiple Independent Serial Link (MISL) Memory device described in previously incorporated U.S. patent application Ser No. 11/324,023.
• The SI and SO are connected between devices110 in the daisy chain cascade arrangement such that the SO of a device110 earlier in the daisy chain cascade is coupled to the SI of the next device110 in the daisy chain cascade. For example, the SO ofdevice110ais coupled to the SI ofdevice110b.The SCLK input of each device110 is fed with a clock signal from, e.g., a memory controller (not shown). The clock signal is distributed to each device110 via a common link. As will be described further below, SCLK is used to, inter alia, latch information input to the device110 at various registers contained in the device110.
• Information input to the devices110 may be latched at different times of the clock signal fed to the SCLK input. For example, in a single data rate (SDR) implementation, information input to the device110 at the SI may be latched at either the rising or falling edge of the SCLK clock signal. Alternatively, in a double data rate (DDR) implementation, both the rising and falling edges of the SCLK clock signal may be used to latch information input at the SI.
• The CS# input of each device is a conventional chip select that selects the device. This input is coupled to a common link which enables a chip select signal to be asserted to all of the devices110 concurrently and consequently selects all of the devices110 simultaneously.
• FIG. 2 is a block diagram of an exemplary device configuration comprising a plurality of single port devices210a-econfigured in a serial daisy chain cascading arrangement having a cascaded clock. Each device210 comprises a SI, SO, SCLK input and CS# input, as described above. In addition, each device210 comprises a clock output (SCLKO). The SCLKO is an output that outputs the SCLK signal input to the device210.
• Referring toFIG. 2, the SI and SO of the devices210 are coupled in a daisy chain cascade arrangement, as described above. In addition, the SCLK input and SCLKO of the devices are also coupled in a daisy chain cascade arrangement such that the SCLKO of an earlier device210 in the daisy chain cascade is coupled to the SCLK input of the next210 device in the daisy chain cascade. Thus, for example, the SCLKO ofdevice210ais coupled to the SCLK input ofdevice210b.
• Note that the clock signal may incur a delay as it propagates through the daisy chain cascaded devices. An internal delay compensation circuit, such as a delay locked loop (DLL) circuit, may be employed to obviate this delay.
• FIG. 3 is a block diagram of an exemplary device configuration comprising a plurality of dual port devices310a-econfigured in a serial daisy chain cascading arrangement. Each device310 comprises an SI and SO for each port, an SCLK input and CS# input, as described above. Referring toFIG. 3, the SI for the first port on the device310 is labeled “SI0” and the SI for the second port is labeled “SI1”. Likewise, the SO for the first port is labeled “SO0” and for the second port “SO1”. The SI and SO for each port are connected between devices310 as described above. Thus, for example, the SO ofport0 ondevice310ais fed to the SI ofport0 ondevice310band so on. Likewise, the SO ofport1 ondevice310ais fed to the SI ofport1 ondevice310band so on.
• FIG. 4 is a block diagram of an exemplary device configuration comprising a plurality of single port devices configured in a serial daisy chain arrangement having inputs and outputs for various enable signals. Each device410 comprises an SI, SO, CS# input, SCLK input, as described above. In addition, each device410 comprises an input port enable (IPE) input, output port enable (OPE) input, input port enable output (IPEQ) and output port enable output (OPEQ). The IPE input is used to input an IPE signal to the device. The IPE signal is used by the device to enable the SI such that when IPE is asserted information may be serially input to the device410 via the SI. Likewise, the OPE input is used to input an OPE signal to the device. The OPE signal is used by the device to enable the SO such that when OPE is asserted information may be serially output from the device410 via the SO. The IPEQ and OPEQ are outputs that output the IPE and OPE signals, respectively, from the device. The CS# input and SCLK inputs are coupled to separate links which distribute the CS# and SCLK signals, respectively, to the devices410a-d,as described above.
• The SI and SO are coupled from one device to the next in a daisy chain cascade arrangement, as described above. Moreover, the IPEQ and OPEQ of an earlier device410 in the daisy chain cascade are coupled to the IPE input and OPE input, respectively, of the next device410 in the daisy chain cascade. This arrangement allows IPE and OPE signals to be transferred from one device410 to the next in a serial daisy chain cascade fashion.
• FIG. 5 is a block diagram of an exemplary device configuration comprising dual port devices510a-dconfigured in a serial daisy chain arrangement having inputs and outputs for various enable signals. Each device510 comprises a CS# input, SCLK input, and an SI, SO, IPE, OPE, IPEQ and OPEQ for each port, as described above. The SI, SO, IPE, OPE, IPEQ and OPEQ forport1 andport2 are designated SI1, SO1, IPE1, OPE1, IPEQ1 and OPEQ1, and SI2, SO2, IPE2, OPE2, IPEQ2 and OPEQ2, respectively.
• The CS# input for each device510 is coupled to a single link to simultaneously select all devices510, as described above. Likewise, the SCLK for each device510 is coupled to a single link which is configured to simultaneously distribute a clock signal to all devices510, as described above. Also, as described above, the SI, SO, IPE, OPE, IPEQ and OPEQ are coupled between devices such that the SO, IPEQ and OPEQ of an earlier device in the daisy chain cascade are coupled to the SI, IPE and OPE of a later device in the daisy chain cascade. For example, the SO1, S02, IPEQ1, IPEQ2, OPEQ1 and OPEQ2 ofdevice510aare coupled to the SI1, SI2, IPE1, IPE2, OPE1 and OPE2, respectively, ofdevice510b.
• The SI, IPE and OPE signals that are input to the SI, IPE and OPE inputs ofdevice510a, respectively, are provided to thedevice510afrom, e.g., a memory controller (not shown).Device510dprovides data and control signals back to the memory controller via the SO, IPEQ and OPEQ outputs ofdevice510d.
• FIG. 6 is a block diagram of an exemplary device configuration comprising a plurality of devices610a-dhaving multiple serial inputs (SI0 to SIn) and multiple serial outputs (SO0 to SOn) which are configured in a serial daisy chain cascading arrangement. In addition, each device610 has an SCLK input and CS# input, as described above.
• The serial inputs (SI0 to SIn) and serial outputs (SO0 to SOn) employed for each device610 enable information to be input to and output from the device610, respectively, in a serial fashion. Each input may be assigned a specific role to input certain types of information (e.g., address, command, data) and/or signals (e.g., enable signals) to the device610. Likewise, each output may be assigned a specific role to output certain types of information and signals from the device610. For example, one or more inputs may be assigned a role to enable address information to be input to the device610. Likewise, for example, one or more outputs may be assigned a role to output the address information from the device610.
• The number of serial inputs and serial outputs for each device610 typically depends on certain factors, such as the number of address lines, command size and data width size. These factors may be influenced by how the device is used in a particular system application. For example, a system application that requires a data store that is used to store a small amount of information may employ a device that has fewer address and data lines, and hence fewer inputs/outputs, than a system application that requires a data store for a large amount of information.
• FIG. 7 is a timing diagram illustrating timing associated with a read operation performed on a single device, and a plurality of devices configured in a serial daisy chain cascade arrangement. Referring toFIG. 7, CS# is asserted to select all of the devices. The read operation begins by asserting IPE and clocking information associated with the read operation into the device via SI. Illustratively, this information includes a command (CMD) indicating a read operation is to be performed and a column address (Col. ADD) and row address (Row ADD) that indicate a starting location in memory where the data is read.
• At time “tR”, the requested data is read from memory and placed in a special internal data buffer contained in the device. The length of tR is typically determined by characteristics of cells that comprise the memory. After time tR, OPE is asserted to enable the serial transfer of data from the internal data buffer via the SO to the next device in the daisy chain cascade. The data is serially outputted from the internal buffer at the SO output, illustratively, at the rising edge of SCLK. Data output from a device in the daisy chain cascade is delayed as much as one clock cycle to control latency, e.g., associated with propagating control signals, such as IPE and OPE. As will be described further below, latency control is performed using a clock synchronized latch.
• FIG. 8 is a timing diagram illustrating timing associated with information transferred between devices configured in a serial daisy chain cascade arrangement. As above, CS# is asserted to select the devices. Information is input to the first device in the daisy chain cascade by asserting IPE and clocking data into the device on successive rising edges of SCLK. IPE is propagated through the first device to the second device in less than a cycle. This enables information to be clocked from the SO of the first device into the SI of the second device at one cycle after the information was clocked into the first device. This is repeated for successive devices in the daisy chain cascade. Thus, for example, the information is inputted to the third device in the serial daisy chain cascade at the third rising edge of SCLK from the latch point of the data at the first device. Control signals IPE and OPE are synchronized with the rising edge of SCLK in order to ensure a proper setup time for these signals at the next device in the daisy chain cascade.
• FIG. 9 is a block diagram of exemplary serialoutput control logic900 for a single ported device.Logic900 comprises an input buffer forIPE902, input buffer for SI (SIP)904, input buffer forOPE906,input latch control908, serial-to-parallel register910,output latch control912, data register914,address register916,command interpreter918,selector920,page buffer924, logical ORgate926,output buffer928,selector930 andmemory950.
• Input buffer902 is a conventional low-voltage transistor-to-transistor logic (LVTTL) buffer configured to buffer the state of an IPE signal fed to the device at the input ofbuffer902. The output ofbuffer902 is fed to inputlatch control908 which latches the state of the IPE signal and provides a latched state of the IPE signal to inputbuffer904 andselector920.Input buffer904 is a LVTTL buffer configured to buffer information fed to the device via the SI input.Input buffer904 is enabled by the output ofinput latch control908. When enabled, information provided to the SI input is fed by thebuffer908 to the serial-to-parallel register910 and an input ofselector930. Theinput buffer904 is enabled when the latched state of the IPE signal fed from theinput latch control908 indicates that the IPE signal is asserted. Information fed to the serial-to-parallel register910 is converted by theregister910 from a serial form to a parallel form. Outputs of the serial-to-parallel register910 are fed to data register914,address register916 andcommand interpreter918.
• The data register914 and address register916 hold data and address information, respectively, that is fed to the device via the SI. Thecommand interpreter918 is configured to interpret commands input to the device via the SI. These commands are used to further control the operation of the device. For example, a “write memory” command may be used to cause the device to write data contained in the data register914 tomemory950 contained in the device at an address specified by theaddress register916.
• Theinput buffer906 is a LVTTL buffer configured to buffer an OPE signal that is fed to the OPE input of the device. The output ofbuffer906 is transferred to anoutput latch control912 which latches the state of the OPE signal. Output latch control outputs the latched OPE signal state to ORgate926. ORgate926 is a conventional logic OR gate whose output is used to enable/disable the output ofoutput buffer928.
• Selector920 is a conventional 2-to-1 multiplexer that outputs one of two inputs as selected by the signal DAISY_CHAIN. As noted above, one of these inputs is the latched state of IPE frominput latch control908. The other input is set to a logical low condition. The signal DAISY_CHAIN indicates whether the device is coupled to one or more other devices in a serial daisy chain cascade arrangement. Illustratively, this signal is asserted if the device is coupled to one or more devices in a serial daisy chain cascade arrangement. Asserting the DAISY_CHAIN signal causes the latched state of the IPE signal fed to theselector920 to be output from theselector920. When DAISY_CHAIN is not asserted, the logic low condition input to theselector920 is output from theselector920.
• Page buffer924 is a conventional data buffer that is configured to hold information read frommemory950.Selector930 is a conventional 2-to-1 multiplexer that outputs one of two inputs as selected by the signal ID_MATCH. One input toselector930 is fed from the output of thepage buffer924 and the other input is fed from the output of theSI input buffer904. The output ofselector930 is fed tooutput buffer928. The signal ID_MATCH indicates whether a particular command sent to the device via SI is addressed to the device. If the command is addressed to the device, ID_MATCH is asserted causing the output from thepage buffer924 to be output from theselector930. If ID_MATCH is not asserted, the output from the SI buffer904 (i.e., the state of the SI signal input to the device) is output fromselector930.
• Memory950 is a conventional memory configured to hold data.Memory950 may be a random access memory (RAM) comprising cells, such as static RAM (SRAM), dynamic RAM (DRAM) or flash memory cells, that are addressable using an address that is input to the device via the SI.
• Operationally, an asserted IPE signal is buffered byinput buffer902 and transferred to inputlatch control908 which latches the asserted state of IPE. This latched state is fed toselector920 and to inputbuffer904 to enable thisbuffer904. Command, address and data information input to inputbuffer904 are then transferred to the serial-to-parallel register910 which converts the information from a serial form to a parallel form and feeds the command, address and data information to thecommand interpreter918,address register916 and data register914, respectively. The output ofbuffer904 is also fed toselector930. If ID_MATCH is not asserted, the output of thebuffer904 is present at the output ofselector930 which is fed to the input ofoutput buffer928. If DAISY_CHAIN is asserted, the latched state of IPE is present at the output ofselector920 and fed to a first input of ORgate926. ORgate926 passes the state of IPE tooutput buffer928 to enable theoutput buffer928. This, in turn, allows the information input to the SI input to be output from the device at SO.
• Data from thepage buffer924 are output from the device by asserting OPE and ID_MATCH. Specifically, the asserted state of OPE is fed to inputbuffer906 which in turn feeds the state tooutput latch control912 which latches the state. The latched asserted state is fed to a second input of ORgate926 which outputs a signal to enableoutput buffer928. Asserting ID_MATCH enables the output ofpage buffer924 to be present at the output ofselector930. The output ofselector930 is fed to the enabledoutput buffer928 which outputs the data from the device at the device's SO output.
• Note that, if DAISY_CHAIN is not asserted,output buffer928 is only enabled by the OPE. This allows the device to be used in non-daisy chain serial cascade configurations.
• FIG. 10 is a block diagram of exemplary serialoutput control logic1000 for a dual ported device. For each port, the input and controlpath logic1000 comprises an IPE input buffer1002, SI input buffer1004, OPE input buffer1006, input latch control1008, serial-to-parallel register1010, output latch control1012, data register1014, address register1016, command interpreter1018, selector1020, page buffer1024, logical OR gate1026, output buffer1028 and selector1030 which are identical to the above describedIPE input buffer902,SIP input buffer904,OPE input buffer906,input latch control908, serial-to-parallel register910,output latch control912, data register914,address register916,command interpreter918,selector920,page buffer924, logical ORgate926,output buffer928 andselector930, respectively.
• FIG. 11 is a detailed block diagram of another embodiment of serialoutput control logic1100 that may used with the techniques described herein.Logic1100 comprises anSI input buffer1104, anIPE input buffer1106, anOPE input buffer1108, anSCLK input buffer1110, logical ANDgates1112 and1114, latches1116,1118,1120 and1122,selectors1124 and1130, logical ORgate1126 and anSO output buffer1128.Buffers1104,1106,1108 and1110 are conventional LVTTL buffers configured to buffer SI, IPE, OPE and SCLK signals, respectively, that are inputted to the device.
• ANDgate1112 is configured to output the information input to the SI to latch1116 when IPE is asserted.Latch1116 is configured to latch the information when a clock signal (SCLK) is provided bybuffer1110. DATA_OUT represents the state of data read from a memory (not shown) contained in the device. ANDgate1114 is configured to output a state of DATA_OUT when OPE is asserted. The output of ANDgate1114 feeds latch1118 which is configured to latch the state of DATA_OUT when a clock signal is provided bybuffer1110.Buffer1106 is configured to buffer the IPE signal fed to the device. The output ofbuffer1106 is latched bylatch1120. Likewise,buffer1108 is configured to buffer the OPE signal fed to the device.Latch1122 is configured to latch the state of OPE as output bybuffer1108.Selectors1124 and1130 are conventional 2-to-1 multiplexers each comprising two inputs. The inputs forselector1124 are selected for output from theselector1124 by the above-described ID_MATCH signal. One input is fed with the latched state of DATA_OUT as maintained bylatch1118. This input is selected for output fromselector1124 when ID_MATCH is asserted. The other input is fed with the latched state of SI as maintained bylatch1116. This input is selected for output from theselector1124 when ID_MATCH is not asserted.
• The inputs forselector1130 are selected for output from theselector1130 by the above-described DAISY_CHAIN signal. One input toselector1130 is fed with the latched state of IPE as maintained bylatch1120 and the other input is tied to a logical zero. The latched state of IPE is selected for output from theselector1130 when DAISY_CHAIN is asserted. Likewise, when DAISY_CHAIN is not asserted, logical zero is selected for output from theselector1130.
• ORgate1126 is a conventional logical OR gate configured to provide an enable/disable signal tooutput buffer1128. ORgate1126 is fed with the output ofselector1130 and the latched state of OPE, as maintained bylatch1122. Either of these outputs may be used to provide an enable signal to buffer1128 to enable the buffer's output.Buffer1128 is a conventional buffer that buffers output signal SO. As noted above,buffer1128 is enabled/disabled by the output ofOR gate1126.
• Operationally, when IPE is asserted, information that is input to the device via SI is fed to latch1116.Latch1116 latches this information illustratively at the first upward transition of SCLK after IPE is asserted. Likewise,latch1120 latches the state of IPE at this SCLK transition. Assuming ID_MATCH is not asserted, the output oflatch1116 is fed to buffer1128 viaselector1124. Likewise, the asserted IPE is transferred frombuffer1106 to latch1120 where it is also illustratively latched by the first upward transition of SCLK. Assuming DAISY_CHAIN is asserted, the latched state of IPE is provided at the output ofselector1130 and transferred to ORgate1126 to provide an enable signal to buffer1128. The latched state of SI is then transferred from the device viabuffer1128 as output SO.
• When DAISY_CHAIN is not asserted, the logical zero input toselector1130 is selected which outputs a logical zero fromselector1130. This effectively disables IPE from enablingbuffer1128.
• Illustratively, at the next upward transition of SCLK after OPE is asserted, the asserted state of OPE is latched at1122 and the state of DATA_OUT is latched atlatch1118. Assuming ID_MATCH is asserted, the latched state of DATA_OUT is selected byselector1124 and applied to the input ofbuffer1128. Simultaneously, the latched asserted state of OPE fromlatch1122 passes through ORgate1126 to enablebuffer1128 which causes the latched state of DATA_OUT to be output from the device as output SO.
• FIG. 12 is a block diagram of an exemplary configuration of devices configured in a serial daisy chain cascading arrangement and containing exemplary serial output control logic. The arrangement comprises three devices1210 configured such that outputs of an earlier device in the daisy chain cascade are coupled to inputs of the next device in the daisy chain cascade, as described above. The transfer of information and data from one device to the next is described with reference toFIG. 13 below.
• FIG. 13 is an exemplary timing diagram illustrating timing associated with inputs and outputs of devices illustrated inFIG. 12. Specifically, the diagram illustrates the operation of the serialoutput control logic1100 in each device with respect to passing information input at the SI input of each device1210 to the SO output of the device1210.
• Referring toFIGS. 11, 12 and13, assume DAISY_CHAIN is asserted. When IPE is asserted atdevice1210a, information at the device's SI input is passed through the device's serialoutput control logic1100, as described above, to the SO output of thedevice1210a. Specifically, data is clocked intodevice1210aillustratively at each rising edge of SCLK after IPE is asserted. The information and state of IPE propagates through thelogic1100, as described above, and exits thedevice1210aat the device's SO and IPEQ outputs, respectively. These outputs are represented in the diagram as S1 and P1, respectively. These outputs are fed to the SI and IPE inputs ofdevice1210b, pass through the serialoutput control logic1100 of thedevice1210b, as described above, and are output fromdevice1210bat the device's SO and IPEQ outputs one clock cycle later. These outputs are represented in the diagram as S2 and P2, respectively. Likewise, the SO and IPEQ outputs ofdevice1210bare fed to the SI and IPE inputs ofdevice1210c, respectively, pass through the serialoutput control logic1100 ofdevice1210cand are output from thedevice1210cat the device's SO and IPEQ outputs, respectively, one clock cycle later. These outputs are represented in the diagram as S3 and P3, respectively.
• In the daisy chain cascade arrangements described above, the output latency of signals in the daisy chain cascade for SDR operation may be determined using the following formula:
  output_latency=N*clock_cycle_time
• where:
• “output_latency” is the output latency of the data,
• “N” is the number of devices in the daisy chain cascade arrangement and
• “clock_cycle_time” is the clock cycle time at which the clock (e.g., SCLK) operates.
• For example, assume the clock_cycle_time for the daisy chain cascade illustrated inFIG. 12 is 10 nanoseconds. The total output latency for the data at the SO ofdevice1210cis 3*10 nanoseconds or 30 nanoseconds.
• In the case of DDR operation, the output latency may be determined as follows:
  output_latency=N*(clock_cycle_time/2)
• In DDR operation both edges of the clock may act as latch points of input data and change points of output data. Thus, the total latency is half the latency for SDR operation.
• Note that in the above description, the information input to a device1210 is output one clock cycle later for SDR operation and one half cycle later for DDR operation. This delay is introduced to accommodate the time it takes to activate theoutput buffer1128.
• FIG. 14 is a block diagram oflogic1400 that may be used to transfer data contained in memory of afirst device1450ain a daisy chain cascade to asecond device1450bin the daisy chain cascade.Logic1400 comprises adata output register1402, anOPE input buffer1404, anSCLK input buffer1406, an ANDgate1408, adata output latch1410, anOPE state latch1412, aselector1414, anSO output buffer1416 and anOPEQ output buffer1418.
• Thedata output register1402 is a conventional register configured to store data read from memory contained in the device1450. Theregister1402 is illustratively a parallel-to-serial data register that loads data in parallel from memory and serially transfers the data to an input ofgate1408. SCLK provides clocks that are used byregister1402 to transfer the data togate1408. As illustrated, data register1402 is configured to hold a byte of data comprising bits D0 through D7 where D0 is the least-significant bit (LSB) of the byte and bit D7 is the most-significant bit (MSB) of the byte. Theregister1402 is loaded in parallel with a byte's worth of data from memory. The data is then shifted from the register and serially fed bit-by-bit to the input ofgate1408 starting with the MSB.
• Buffers1404 and1406 are conventional LVTTL buffers used to buffer input signals OPE and SCLK, respectively. The OPE signal is transferred from the output of buffer1404 (OPEI) togate1408. The SCLK signal is transferred from the output ofbuffer1406 todata output register1402 and, latches1410 and1412 to provide a clock to these components.
• Gate1408 is a conventional logic AND gate which is configured to transfer the output of the data output register1402 (DATA_OUT) to latch1410 when OPE is asserted. The output ofgate1408 is designated as “DBIT”.Latches1410 and1412 are conventional latches configured to latch the state of DBIT and the OPE signal, respectively.Selector1414 is a conventional two input 2-to-1 multiplexer that is controlled by the signal ID_MATCH. One of the data inputs is fed with the latched state of DBIT. This state is output from theselector1414 when ID_MATCH is asserted. The other input is fed with serial information (SI0) inputted to thedevice1450avia its SI. This information is outputted by theselector1414 when ID_MATCH is not asserted.
• Buffers1416 and1418 are conventional buffers configured to buffer the output ofselector1414 andlatch1406, respectively. The output ofbuffer1416 exits thedevice1450aas SO (SO0) and the output ofbuffer1418 exits thedevice1450aas OPEQ (OPEQ0).
• FIG. 15 is a timing diagram illustrating timing associated with transferring a byte's worth of data from memory contained indevice1450atodevice1450busing logic1400. Referring toFIGS. 14 and 15, OPEI is asserted shortly after OPE is fed to thedevice1450aatinput buffer1404. OPEI is fed togate1408 to enable the data present in D7 of thedata output register1402 to be latched atlatch1410 at the next rising edge of SCLK. In addition, this next rising edge of SCLK causes data to be right-shifted indata output register1402 such that data in D6 is shifted into D7, data in D5 is shifted into D6 and so on. The output oflatch1410 is presented toselector1414 which, assuming ID_MATCH is asserted, outputs the latched state of the data to buffer1416.Buffer1416 outputs this latched state from thedevice1450aas SO0 which is fed to the SI input (SI1) of thenext device1450bof the daisy chain cascade. Meanwhile, also at the rising edge of the first clock after OPE is asserted, the state of OPE is latched atlatch1412. The output oflatch1412 is transferred to buffer1418 which outputs the latched state of OPE from thedevice1450aas OPEQ (OPEQ0) which is fed to the OPE input (OPE1) of thenext device1450bin the daisy chain cascade. This process is repeated for bits D6 through D0.
• While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims (20)

1. An apparatus having a plurality of devices configured in a daisy chain cascade arrangement, the apparatus comprising:

a first memory device having:

(a) memory,

(b) a first input for receiving address information associated with a memory location in the memory,

(c) a first output configured to output data contained in the memory location from the first device; and

a second memory device having:

(a) a first input coupled to the first output of the first device and configured to receive the data outputted from the first device.

2. An apparatus as defined inclaim 1 wherein the data is serially transferred from the first output of the first memory device to the first input of the second memory device.

3. An apparatus as defined inclaim 1 wherein the first memory device further has:

(a) a second input for receiving an enable signal that is used to enable the first input of the first memory device to receive the address information, and

(b) a second output for outputting the enable signal.

4. An apparatus as defined inclaim 3 wherein the second memory device has a second input coupled to the second output of the first memory device for receiving the enable signal at the second memory device.

5. An apparatus as defined inclaim 1 wherein the first memory device has:

a second input for receiving an enable signal that is used to enable the data to be output on the first output of the first memory device; and

a second output for outputting the enable signal from the first memory device.

6. An apparatus as defined inclaim 5 wherein the second memory device has a second input that is coupled to the second output of the first memory device for receiving the enable signal at the second memory device.

7. An apparatus as defined inclaim 1 wherein the first memory device and second memory device each have a second input for receiving a clock signal that is used by the first and second memory devices to accommodate the transfer of the accessed data from the first output of the first memory device to the first input of the second memory device.

8. An apparatus as defined inclaim 7 wherein the first memory device has a second output coupled to the second input of the second memory device for transferring the clock signal from the first memory device to the second memory device.

9. A method comprising:

inputting, into a first input of a first memory device, address information associated with a memory location of memory contained in the first memory device;

accessing data in memory contained in the first memory device at the memory location; and

coupling a first output of the first device to a first input of a second memory device to allow the accessed data to be transferred from the first memory device to the second memory device.

10. A method as defined in claim.9 further comprising:

coupling a clock signal to the first memory device and the second memory device, the clock signal being used by the first memory device and second memory device to accommodate the transfer of the accessed data from the first memory device to the second memory device.

11. A method as defined inclaim 10 wherein the clock signal is coupled to a second input of the second memory device from a second output of the first memory device.

12. A method as defined inclaim 9 further comprising:

inputting into a second input of the first memory device an enable signal that is used to enable the address information to be input to the first input of the first memory device;

outputting the enable signal from a second output of the first memory device; and

coupling the second output of the first memory device to a second input of the second memory device to allow the enable signal to be transferred from the first memory device to the second memory device.

13. A method as defined inclaim 9 further comprising:

inputting, into a second input of the first memory device, an enable signal that is used to enable the accessed data to be output from the first memory device;

outputting the enable signal from a second output of the first memory device; and

coupling the second output of the first memory device to a second input of the second memory device to allow the enable signal to be transferred from the first memory device to the second memory device.

14. A method as defined inclaim 9 wherein the accessed data is serially transferred from the first output of the first memory device to the first input of the second memory device.

15. An apparatus comprising:

means for inputting, into a first input of a first memory device, address information associated with a memory location of memory contained in the first memory device;

means for accessing data in memory contained in the first memory device at the memory location; and

means for coupling a first output of the first device to a first input of a second memory device to allow the accessed data to be transferred from the first memory device to the second memory device.

16. An apparatus as defined inclaim 15 further comprising:

means for coupling a clock signal to the first memory device and the second memory device, the clock signal being used by the first memory device and second memory device to accommodate the transfer of the accessed data from the first memory device to the second memory device.

17. An apparatus as defined inclaim 16 wherein the clock signal is coupled to a second input of the second memory device from a second output of the first memory device.

18. An apparatus as defined inclaim 15 further comprising:

means for inputting into a second input of the first memory device an enable signal that is used to enable the address information to be input to the first input of the first memory device;

means for outputting the enable signal from a second output of the first memory device; and

means for coupling the second output of the first memory device to a second input of the second memory device to allow the enable signal to be transferred from the first memory device to the second memory device.

19. An apparatus as defined inclaim 15 further comprising:

means for inputting, into a second input of the first memory device, an enable signal that is used to enable the accessed data to be output from the first memory device;

means for outputting the enable signal from a second output of the first memory device; and

means for coupling the second output of the first memory device to a second input of the second memory device to allow the enable signal to be transferred from the first memory device to the second memory device.

20. An apparatus as defined inclaim 15 wherein the accessed data is serially transferred from the first output of the first memory device to the first input of the second memory device.

Images