US20070047364A1 - Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices - Google Patents
Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devicesDownload PDFInfo
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- US20070047364A1 US20070047364A1US11/216,666US21666605AUS2007047364A1US 20070047364 A1US20070047364 A1US 20070047364A1US 21666605 AUS21666605 AUS 21666605AUS 2007047364 A1US2007047364 A1US 2007047364A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
Definitions
- the present inventionrelates generally to techniques for varying a voltage by a diode voltage in various integrated circuits and, more particularly, to techniques for providing a variable diode voltage using independently controlled asymmetrical double-gate devices.
- FIG. 1is a circuit diagram of a conventional CMOS circuit 100 having an integrated circuit 150 , such as logic or memory elements, a power-gating switch 110 and a diode clamp 120 .
- FIG. 2is a schematic cross-section of a bulk-Si (or SOI) field effect transistor (FET) 200 . As shown in FIG.
- a large reverse well/body bias 220causes an exponential increase in the reverse junction leakage including band-to-band tunneling current, while a forward well/body bias 210 results in an exponential increase in the forward diode leakage.
- V T modulation effectdiminishes with device scaling due to a low body factor in the scaled, low V T transistor.
- the distributed RC for the well/body contactlimits the viable operating frequency.
- FIG. 3is a schematic cross-section of an asymmetrical double-gate nFET 300 .
- the front gate 310typically uses n+ polysilicon and the back gate 320 typically consists of p+ polysilicon.
- a p+ polysilicon gatewould be used for the front-gate and an n+ polysilicon gate would be used for the back-gate.
- the predominant front-channelhas a significantly lower V T and much larger current drive compared with the “weak” back-channel.
- the disclosed asymmetrical double-gate devicescouple the front gate and back gate using a connection 330 .
- the threshold voltage, V Tis a function of the fixed back gate voltage.
- the disclosed asymmetrical double-gate devicescannot be used to provide a variable V T diode and thereby control the virtual V DD or virtual Ground in the integrated circuit 100 of FIG. 1 .
- an integrated circuitis provided that is controlled by one or more of a supply voltage and a reference voltage.
- the integrated circuitcomprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage.
- the independent controlmay comprise, for example, a back gate bias.
- the asymmetrical double-gate devicecomprises a p+ polysilicon gate for a first gate; and an n+ polysilicon gate for a second gate, wherein the threshold voltage, V T , is independently controlled by a bias of the first or second gates.
- a plurality of voltage islandsmay be provided in an integrated circuit that each provide a different voltage level.
- Each voltage islandcomprises an independently controlled asymmetrical double-gate device to provide one of the different voltage levels.
- a power gating circuitis provided that comprises at least one integrated circuit; and an independently controlled asymmetrical double-gate device that provides a variable threshold voltage, V T .
- the power gating circuitmay also comprise an asymmetrical double-gate device to serve as a power switch.
- the independently controlled asymmetrical double-gate device of the present inventionmay also be employed in static RAM devices having a plurality of memory cells. Each memory cell has an independently controlled asymmetrical double-gate device that provides a variable threshold voltage, V T .
- a processor unitcomprises: (i) an oscillator; (ii) at least one independently controlled asymmetrical double-gate device that provides a variable threshold voltage, V T ; (iii) a phase detector to compare an output of the oscillator to a reference signal; and (iv) a charge pump to adjust a back-gate bias of the at least one independently controlled asymmetrical double-gate device based on the comparison.
- FIG. 1is a circuit diagram of a CMOS circuit
- FIG. 2is a schematic cross-section of a bulk-Si (or SOI) field effect transistor
- FIG. 3is a schematic cross-section of an asymmetrical double-gate nFET employed by the present invention
- FIG. 4is a circuit diagram of a CMOS circuit incorporating features of the present invention.
- FIG. 5illustrates a plurality of voltage islands incorporating one or more independently controlled asymmetrical double-gate devices of the present invention
- FIG. 6illustrates a power gating structure incorporating one or more independently controlled asymmetrical double-gate devices of the present invention
- FIG. 7illustrates the relevant portions of an SRAM incorporating one or more independently controlled asymmetrical double-gate devices in each cell according to the present invention
- FIG. 8illustrates a column based dynamic V DD scheme for Read/Write operations in an SRAM using one or more independently controlled variable diode-drop asymmetrical double-gate devices
- FIG. 9depicts an “on-the-fly” virtual supply regulator that optimizes the power-performance of a processor unit using the independently controlled variable diode-drop asymmetrical double-gate device of the present invention.
- the present inventionprovides techniques for varying a supply voltage or a reference voltage using one or more independently controlled asymmetrical double-gate devices.
- the present inventionrecognizes that the front-channel V T (and current) of the asymmetrical double-gate devices can be modulated using independent control, such as back-gate biasing, through gate-to-gate coupling.
- This V T modulation mechanismis significantly stronger than the existing well/body bias in bulk CMOS and PD/SOI devices, as discussed above in conjunction with FIG. 2 .
- the effectimproves with device scaling due to stronger gate-to-gate coupling in thinner film or thinner gate oxides (or both), and the frequency is only limited by the gate RC, in the same manner as core logic.
- FIG. 4is a circuit diagram of a CMOS circuit 400 incorporating features of the present invention.
- the CMOS circuit 400comprises an integrated circuit 450 , such as logic or memory elements, and one or more asymmetrical double-gate nFET devices 410 , for example, associated with the virtual ground (footer) or virtual supply voltage (header), or both.
- the virtual ground (VGND)is clamped by the diode connected front gate of an asymmetrical double-gate nFET device 410 that uses an n+ polysilicon gate for the front-gate and a p+ polysilicon gate for the back-gate.
- the drain terminal of the asymmetrical double-gate nFET device 410is coupled to the front gate, as shown in FIG. 4 .
- the back gate of the asymmetrical double-gate device 410is used to independently control the voltage drop across the MOS diode 420 , using a bias signal, VGND control.
- circuit 415is an equivalent representation of the asymmetrical double-gate NFET device 410 .
- the diode 420represents the strong current associated with the front gate of the asymmetrical double-gate NFET device 410
- the open circuit 430represents the very small current associated with the back gate of the asymmetrical double-gate nFET device 410 .
- VVDDvirtual VDD
- VVDDvirtual VDD
- an independently controlled asymmetrical double-gate pFET devicethat uses a p+ polysilicon gate for the front-gate and an n+ polysilicon gate for the back-gate.
- the back gate of the asymmetrical double-gate device 410would be used to independently control the voltage drop across the MOS diode 420 , using a bias signal, VVDD control.
- the exemplary back-gate biasing of the asymmetrical double-gate device 410is used to modulate the front-gate V T through gate-to-gate coupling. Since the diode drop (V d ) is physically associated with V T and the V T modulation effect is significant, the disclosed independently controlled asymmetrical double-gate devices 410 can provide a wide range of diode voltage for clamping VGND or VVDD (or both).
- the disclosed asymmetrical double-gate devicesare scalable as the gate-to-gate coupling effect improves with device scaling (for thin silicon film and thin gate dielectric).
- the operating frequencyis only limited by the gate RC (in a similar manner to the core logic.
- the disclosed asymmetrical double-gate devicesare area efficient since a single device is used for the diode and tuning.
- the diodecan also serve as the power switch, thus further improving the area, density, power, and performance.
- the back-gate biasdoes not increase the junction leakage, while well-body bias can cause significant increase in reverse/forward junction leakage and band-to-band tunneling leakage.
- the burden of charge movement to charge/discharge of voltage rail capacitanceis smaller than that of an equivalent parallel pass gate voltage switch. As a result, the virtual supply settling time can be shorter in design.
- the wide tuning range for the diode voltagemakes the present invention useful for the following applications:
- the present inventionis well suited for emerging asymmetrical double-gate technologies including planar double-gate devices, FinFETs, and TriGate technologies.
- the present inventionis also applied to fully depleted SOI devices with back-gating capability.
- FIG. 5illustrates an integrated circuit 500 having a plurality of voltage islands 510 - 1 through 510 - 3 incorporating one or more independently controlled asymmetrical double-gate devices 520 of the present invention.
- individual independently controlled diode-connected asymmetrical double-gate pFETs 520 - 1 through 520 - 3each with different back-gate biases, bias I through bias III, are used to provide different virtual V DD s for corresponding individual voltage islands 510 - 1 through 510 - 3 .
- each sub-circuit 530 - 1 through 530 - 3may need a different supply voltage, provided by a corresponding voltage island 510 .
- FIG. 6illustrates a power gating structure 600 incorporating one or more independently controlled asymmetrical double-gate devices 610 of the present invention.
- the power gating structure 600 of FIG. 6improves the speed, relative to the implementation of FIG. 4 .
- two transistorsare employed to provide higher currents and faster speed.
- the power switches 605are embodied as front gate to back gate coupled asymmetrical double-gate devices 300 ( FIG. 3 ).
- the corresponding power switch 605is ON and the back gate is ON.
- the power switch 605shunts the diode and the virtual GND is close to GND (and the virtual V DD is close to V DD ).
- the power switch 605is OFF, and the back-gates are biased to provide the proper diode voltages to clamp the virtual GND and virtual V DD at the desired levels. It is noted that due to the capability of wide range diode voltage provided by the present invention, the power switches 605 can actually be removed. With the back-gate biased at full V DD to the footer or at full “0” to the header, the diode voltage drops are negligible, and the diodes themselves can serve as the power switches as well.
- FIG. 7illustrates the relevant portions of an SRAM 700 incorporating one or more independently controlled diode-connected asymmetrical double-gate devices 710 according to the present invention in one or more cells 720 - 1 through 720 -n.
- the independently controlled diode-connected asymmetrical double-gate devices 710serve both as the power switches and the variable diode-voltage clamps. In a standby mode, the diode voltages can be tuned to maintain adequate voltage across the cells for state retention and to reduce the leakage current.
- FIG. 7illustrates the levels for VGND control and the levels for VVDD control would be complementary, as would be apparent to a person of ordinary skill.
- the disclosed back-gate controlled variable diode-drop schemecan be applied to a dynamic Read/Write supply voltage for SRAM.
- a dynamic Read/Write supply voltage for SRAMAs previously indicated, for SRAMs in scaled technologies, it is desirable to have a higher supply voltage during a read operation, to maintain an adequate noise margin, and a lower supply voltage during a write operation, to facilitate writing.
- FIG. 8illustrates a column based dynamic V CC scheme for Read/Write operations in an SRAM 800 using one or more independently controlled variable diode-drop asymmetrical double-gate devices 810 .
- the implementation shown in FIG. 8has the following advantages:
- the virtual supply control lineonly needs to charge/discharge the back-gate capacitance, and the voltage rail is charged/discharged by the front-gate current.
- the virtual supply settling timeis shorter (conventional techniques require the drain of the pass transistors to be connected directly to the virtual supply line, hence a large amount of charges have to be moved to charge/discharge the voltage rail capacitance).
- FIG. 9depicts an “on-the-fly” virtual supply regulator 900 that optimizes the power-performance of a processing unit 950 using the back-gate controlled variable diode-drop asymmetrical double-gate device 910 of the present invention.
- an oscillator (OSC) 960is designed to match the unit cycle time within a predefined margin.
- the output of the oscillator 960goes through a level shifter 920 , and is then compared with a clock signal CLKG through a phase detector 930 . If the output of the oscillator 960 is slower than CLKG, the charge pump 940 will lower the back-gate bias for the pFET header diode to speed up the unit. If the output of the oscillator 960 is faster than CLKG, the charge pump 940 will raise the back-gate bias to slow it down.
- the unit 950will maintain its required performance at the lowest supply voltage (hence lowest power).
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Abstract
Description
- This invention was made with Government support under Contract No. NBCH3039004 awarded by Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in this invention.
- The present invention relates generally to techniques for varying a voltage by a diode voltage in various integrated circuits and, more particularly, to techniques for providing a variable diode voltage using independently controlled asymmetrical double-gate devices.
- A number of techniques have been proposed or suggested for containing power/leakage, improving performance, and extending scaling, including voltage islands, dynamic VDD, and separate supplies for logic and SRAM. For example, one commonly used technique drops the supply voltage (or raises the Ground voltage) through a metal oxide semiconductor (MOS) diode by one threshold voltage, VT. MOS diodes are also widely used in power-gating structures for logic and static random access memories (SRAM) to clamp the virtual VDDor virtual Ground (or both) to maintain adequate voltage across the memory elements for proper state retention, as illustrated in
FIG. 1 .FIG. 1 is a circuit diagram of aconventional CMOS circuit 100 having anintegrated circuit 150, such as logic or memory elements, a power-gating switch110 and a diode clamp120. - It is desirable to have a variable VTdiode to compensate for process variations, VTfluctuations or both. Furthermore, in SRAM applications, it is desirable to have a higher supply voltage during a read operation to maintain adequate noise margin, and a lower supply voltage during a write operation to facilitate writing. While well/body bias in bulk CMOS or PD/SOI devices have been proposed for used in modulating the threshold voltage, VT, the effect, in general, is quite limited.
FIG. 2 is a schematic cross-section of a bulk-Si (or SOI) field effect transistor (FET)200. As shown inFIG. 2 , a large reverse well/body bias 220 causes an exponential increase in the reverse junction leakage including band-to-band tunneling current, while a forward well/body bias 210 results in an exponential increase in the forward diode leakage. Furthermore, it is known that the VTmodulation effect diminishes with device scaling due to a low body factor in the scaled, low VTtransistor. Finally, the distributed RC for the well/body contact limits the viable operating frequency. - E. Nowak et al., “Turning Silicon on its Edge,”IEEE Circuits Devices Mag.20-31 (January/February, 2004), incorporated by reference herein, discloses a VTmodulation technique that employs double-gate devices. The disclosed VTmodulation technique uses asymmetrical gates, where the two gate electrodes consist of materials of differing work functions.
FIG. 3 is a schematic cross-section of an asymmetricaldouble-gate nFET 300. As shown inFIG. 3 , thefront gate 310 typically uses n+ polysilicon and theback gate 320 typically consists of p+ polysilicon. For an asymmetrical pFET, a p+ polysilicon gate would be used for the front-gate and an n+ polysilicon gate would be used for the back-gate. In such an implementation, the predominant front-channel has a significantly lower VTand much larger current drive compared with the “weak” back-channel. - As shown in
FIG. 3 , the disclosed asymmetrical double-gate devices couple the front gate and back gate using aconnection 330. The threshold voltage, VT, is a function of the fixed back gate voltage. Thus, the disclosed asymmetrical double-gate devices cannot be used to provide a variable VTdiode and thereby control the virtual VDDor virtual Ground in the integratedcircuit 100 ofFIG. 1 . A need exists for improved techniques for variable VTmodulation. A further need exists for techniques for varying a supply voltage or a reference voltage (or both) using independently controlled asymmetrical double-gate devices. - Generally, methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. According to one aspect of the invention, an integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. In a pMOS implementation, the asymmetrical double-gate device comprises a p+ polysilicon gate for a first gate; and an n+ polysilicon gate for a second gate, wherein the threshold voltage, VT, is independently controlled by a bias of the first or second gates.
- According to another aspect of the invention, a plurality of voltage islands may be provided in an integrated circuit that each provide a different voltage level. Each voltage island comprises an independently controlled asymmetrical double-gate device to provide one of the different voltage levels. According to yet another aspect of the invention, a power gating circuit is provided that comprises at least one integrated circuit; and an independently controlled asymmetrical double-gate device that provides a variable threshold voltage, VT. The power gating circuit may also comprise an asymmetrical double-gate device to serve as a power switch. The independently controlled asymmetrical double-gate device of the present invention may also be employed in static RAM devices having a plurality of memory cells. Each memory cell has an independently controlled asymmetrical double-gate device that provides a variable threshold voltage, VT.
- In addition, the adjusted back-gate bias can be employed in a processing unit to improve power and performance of the processing unit. A processor unit according to the present invention comprises: (i) an oscillator; (ii) at least one independently controlled asymmetrical double-gate device that provides a variable threshold voltage, VT; (iii) a phase detector to compare an output of the oscillator to a reference signal; and (iv) a charge pump to adjust a back-gate bias of the at least one independently controlled asymmetrical double-gate device based on the comparison.
- A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
FIG. 1 is a circuit diagram of a CMOS circuit;FIG. 2 is a schematic cross-section of a bulk-Si (or SOI) field effect transistor;FIG. 3 is a schematic cross-section of an asymmetrical double-gate nFET employed by the present invention;FIG. 4 is a circuit diagram of a CMOS circuit incorporating features of the present invention;FIG. 5 illustrates a plurality of voltage islands incorporating one or more independently controlled asymmetrical double-gate devices of the present invention;FIG. 6 illustrates a power gating structure incorporating one or more independently controlled asymmetrical double-gate devices of the present invention;FIG. 7 illustrates the relevant portions of an SRAM incorporating one or more independently controlled asymmetrical double-gate devices in each cell according to the present invention;FIG. 8 illustrates a column based dynamic VDDscheme for Read/Write operations in an SRAM using one or more independently controlled variable diode-drop asymmetrical double-gate devices; andFIG. 9 depicts an “on-the-fly” virtual supply regulator that optimizes the power-performance of a processor unit using the independently controlled variable diode-drop asymmetrical double-gate device of the present invention.- The present invention provides techniques for varying a supply voltage or a reference voltage using one or more independently controlled asymmetrical double-gate devices. The present invention recognizes that the front-channel VT(and current) of the asymmetrical double-gate devices can be modulated using independent control, such as back-gate biasing, through gate-to-gate coupling. This VTmodulation mechanism is significantly stronger than the existing well/body bias in bulk CMOS and PD/SOI devices, as discussed above in conjunction with
FIG. 2 . Furthermore, the effect improves with device scaling due to stronger gate-to-gate coupling in thinner film or thinner gate oxides (or both), and the frequency is only limited by the gate RC, in the same manner as core logic. - According to one aspect of the invention, a variable threshold voltage, VT, is provided using independently controlled asymmetrical double-gate devices.
FIG. 4 is a circuit diagram of aCMOS circuit 400 incorporating features of the present invention. As shown inFIG. 4 , theCMOS circuit 400 comprises anintegrated circuit 450, such as logic or memory elements, and one or more asymmetricaldouble-gate nFET devices 410, for example, associated with the virtual ground (footer) or virtual supply voltage (header), or both. - In the exemplary embodiment of
FIG. 4 , the virtual ground (VGND) is clamped by the diode connected front gate of an asymmetricaldouble-gate nFET device 410 that uses an n+ polysilicon gate for the front-gate and a p+ polysilicon gate for the back-gate. In addition, the drain terminal of the asymmetricaldouble-gate nFET device 410 is coupled to the front gate, as shown inFIG. 4 . The back gate of the asymmetricaldouble-gate device 410 is used to independently control the voltage drop across theMOS diode 420, using a bias signal, VGND control. - It is noted that the
circuit 415 is an equivalent representation of the asymmetricaldouble-gate NFET device 410. Thediode 420 represents the strong current associated with the front gate of the asymmetricaldouble-gate NFET device 410, and theopen circuit 430 represents the very small current associated with the back gate of the asymmetricaldouble-gate nFET device 410. - Although not shown in
FIG. 4 , the virtual VDD (VVDD) can also be clamped by an independently controlled asymmetrical double-gate pFET device that uses a p+ polysilicon gate for the front-gate and an n+ polysilicon gate for the back-gate. The back gate of the asymmetricaldouble-gate device 410 would be used to independently control the voltage drop across theMOS diode 420, using a bias signal, VVDD control. - As previously indicated, the exemplary back-gate biasing of the asymmetrical
double-gate device 410 is used to modulate the front-gate VTthrough gate-to-gate coupling. Since the diode drop (Vd) is physically associated with VTand the VTmodulation effect is significant, the disclosed independently controlled asymmetricaldouble-gate devices 410 can provide a wide range of diode voltage for clamping VGND or VVDD (or both). - Among other benefits, the disclosed asymmetrical double-gate devices are scalable as the gate-to-gate coupling effect improves with device scaling (for thin silicon film and thin gate dielectric). In addition, the operating frequency is only limited by the gate RC (in a similar manner to the core logic. The disclosed asymmetrical double-gate devices are area efficient since a single device is used for the diode and tuning. Moreover, in power-gating applications, the diode can also serve as the power switch, thus further improving the area, density, power, and performance. The back-gate bias does not increase the junction leakage, while well-body bias can cause significant increase in reverse/forward junction leakage and band-to-band tunneling leakage. Finally, in dynamic VDDapplications, the burden of charge movement to charge/discharge of voltage rail capacitance is smaller than that of an equivalent parallel pass gate voltage switch. As a result, the virtual supply settling time can be shorter in design.
- As discussed hereinafter, the wide tuning range for the diode voltage makes the present invention useful for the following applications:
- (1) Dynamic VDD;
- (2) Voltage islands;
- (3) Power gating;
- (4) Separate VDDfor logic and SRAM;
- (5) Dynamic VDDfor SRAM Read/Write (High VDDfor Read; low VDDfor Write); and
- (6) Compensation for process variations and VTfluctuation.
- The present invention is well suited for emerging asymmetrical double-gate technologies including planar double-gate devices, FinFETs, and TriGate technologies. The present invention is also applied to fully depleted SOI devices with back-gating capability.
- Voltage Islands
FIG. 5 illustrates anintegrated circuit 500 having a plurality of voltage islands510-1 through510-3 incorporating one or more independently controlled asymmetrical double-gate devices520 of the present invention. As shown in the exemplary embodiment ofFIG. 5 , individual independently controlled diode-connected asymmetrical double-gate pFETs520-1 through520-3, each with different back-gate biases, bias I through bias III, are used to provide different virtual VDDs for corresponding individual voltage islands510-1 through510-3. For example, each sub-circuit530-1 through530-3 may need a different supply voltage, provided by a corresponding voltage island510.- Power Gating
FIG. 6 illustrates apower gating structure 600 incorporating one or more independently controlled asymmetrical double-gate devices610 of the present invention. Thepower gating structure 600 ofFIG. 6 improves the speed, relative to the implementation ofFIG. 4 . Generally, two transistors are employed to provide higher currents and faster speed. The power switches605 are embodied as front gate to back gate coupled asymmetrical double-gate devices300 (FIG. 3 ).- In an active mode, the corresponding power switch605 is ON and the back gate is ON. The power switch605 shunts the diode and the virtual GND is close to GND (and the virtual VDDis close to VDD). In a standby mode, the power switch605 is OFF, and the back-gates are biased to provide the proper diode voltages to clamp the virtual GND and virtual VDDat the desired levels. It is noted that due to the capability of wide range diode voltage provided by the present invention, the power switches605 can actually be removed. With the back-gate biased at full VDDto the footer or at full “0” to the header, the diode voltage drops are negligible, and the diodes themselves can serve as the power switches as well.
- Separate VDDfor Logic and SRAM
FIG. 7 illustrates the relevant portions of anSRAM 700 incorporating one or more independently controlled diode-connected asymmetricaldouble-gate devices 710 according to the present invention in one or more cells720-1 through720-n. In the implementation shown inFIG. 7 , the independently controlled diode-connected asymmetricaldouble-gate devices 710 serve both as the power switches and the variable diode-voltage clamps. In a standby mode, the diode voltages can be tuned to maintain adequate voltage across the cells for state retention and to reduce the leakage current.FIG. 7 illustrates the levels for VGND control and the levels for VVDD control would be complementary, as would be apparent to a person of ordinary skill.- Dynamic VDDfor SRAM Read/Write
- According to another aspect of the invention, the disclosed back-gate controlled variable diode-drop scheme can be applied to a dynamic Read/Write supply voltage for SRAM. As previously indicated, for SRAMs in scaled technologies, it is desirable to have a higher supply voltage during a read operation, to maintain an adequate noise margin, and a lower supply voltage during a write operation, to facilitate writing.
FIG. 8 illustrates a column based dynamic VCCscheme for Read/Write operations in anSRAM 800 using one or more independently controlled variable diode-drop asymmetricaldouble-gate devices 810. The implementation shown inFIG. 8 has the following advantages:- (a) only one regular supply is required and the back-gate bias is used to control/change the voltage across the SRAM cells (conventional techniques require two external power supplies, or the use of on-chip voltage generator/regulator to provide the extra supply level);
- (b) requires only a header diode or a footer diode (conventional techniques require two pass transistors to perform the MUX function);
- (c) it is only necessary to route either the virtual GND control line or the virtual VDDcontrol line (conventional techniques require routing two supply lines); and
- (d) the virtual supply control line only needs to charge/discharge the back-gate capacitance, and the voltage rail is charged/discharged by the front-gate current. Thus, the virtual supply settling time is shorter (conventional techniques require the drain of the pass transistors to be connected directly to the virtual supply line, hence a large amount of charges have to be moved to charge/discharge the voltage rail capacitance).
FIG. 9 depicts an “on-the-fly”virtual supply regulator 900 that optimizes the power-performance of aprocessing unit 950 using the back-gate controlled variable diode-drop asymmetricaldouble-gate device 910 of the present invention. When a whole processor unit is gated, an oscillator (OSC)960 is designed to match the unit cycle time within a predefined margin. As shown inFIG. 9 , the output of theoscillator 960 goes through alevel shifter 920, and is then compared with a clock signal CLKG through aphase detector 930. If the output of theoscillator 960 is slower than CLKG, thecharge pump 940 will lower the back-gate bias for the pFET header diode to speed up the unit. If the output of theoscillator 960 is faster than CLKG, thecharge pump 940 will raise the back-gate bias to slow it down. Thus, theunit 950 will maintain its required performance at the lowest supply voltage (hence lowest power).- It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.
Claims (20)
1. An integrated circuit controlled by one or more of a supply voltage and a reference voltage, comprising:
an independently controlled asymmetrical double-gate device to adjust one or more of said supply voltage and said reference voltage.
2. The integrated circuit ofclaim 1 , wherein said independent control comprises a back gate bias.
3. The integrated circuit ofclaim 1 , wherein said asymmetrical double-gate device is a pMOS device comprising:
a p+ polysilicon gate for a first gate; and
an n+ polysilicon gate for a second gate, wherein a threshold voltage, VT, is independently controlled by a bias of said first or second gates.
4. The integrated circuit ofclaim 1 , wherein said reference voltage is a ground voltage.
5. The integrated circuit ofclaim 1 , wherein said integrated circuit is a CMOS circuit.
6. The integrated circuit ofclaim 1 , wherein said independently controlled asymmetrical double-gate device employs a second gate to control a diode voltage.
7. An integrated circuit controlled by one or more of a supply voltage and a reference voltage, comprising:
a back-gate controlled fully depleted Silicon-On-Insulator (SOI) device to adjust one or more of said supply voltage and said reference voltage.
8. An integrated circuit comprising:
a plurality of voltage islands each providing a different voltage level, each voltage island comprising:
an independently controlled asymmetrical double-gate device to provide one of said different voltage levels.
9. The integrated ofclaim 8 , wherein each of said of said different voltage levels are obtained using a corresponding back-gate bias.
10. A power gating circuit, comprising:
at least one integrated circuit; and
an independently controlled asymmetrical double-gate device that provides a variable threshold voltage, VT.
11. The power gating circuit ofclaim 10 , further comprising an asymmetrical double-gate device to serve as a power switch.
12. The power gating circuit ofclaim 11 , wherein in an active mode, said power switch is ON and said independently controlled asymmetrical double-gate device is ON.
13. The power gating circuit ofclaim 11 , wherein in a standby mode, said power switch is OFF, and said independently controlled asymmetrical double-gate device is biased to provide a diode voltage to clamp virtual GND and virtual VDDat predefined levels.
14. A static RAM device, comprising:
a plurality of memory cells, each having an independently controlled asymmetrical double-gate device that provides a variable threshold voltage, VT.
15. The static RAM device ofclaim 14 , wherein said independently controlled asymmetrical double-gate devices serve as a power switch and a variable diode-voltage clamp.
16. The static RAM device ofclaim 14 , wherein in a standby mode, diode voltages of said independently controlled asymmetrical double-gate devices can be tuned to compensate for one or more process variations or VTfluctuation and to reduce leakage currents.
17. The static RAM device ofclaim 14 , wherein a back-gate bias on said independently controlled asymmetrical double-gate devices is used to control a voltage across said plurality of cells.
18. A processor unit, comprising:
an oscillator;
at least one independently controlled asymmetrical double-gate device that provides a variable threshold voltage, VT;
a phase detector to compare an output of said oscillator to a reference signal; and
a charge pump to adjust a back-gate bias of said at least one independently controlled asymmetrical double-gate device based on said comparison.
19. The processor unit ofclaim 18 , wherein said adjusted back-gate bias improves a power performance of said processing unit.
20. The processor unit ofclaim 18 , wherein said adjusted back-gate bias maintains a required performance with a reduced supply voltage.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/216,666US20070047364A1 (en) | 2005-08-31 | 2005-08-31 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
| US12/511,658US7952422B2 (en) | 2005-08-31 | 2009-07-29 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
| US12/511,666US9076509B2 (en) | 2005-08-31 | 2009-07-29 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/216,666US20070047364A1 (en) | 2005-08-31 | 2005-08-31 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
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| US12/511,666DivisionUS9076509B2 (en) | 2005-08-31 | 2009-07-29 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
| US12/511,658DivisionUS7952422B2 (en) | 2005-08-31 | 2009-07-29 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
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| US20070047364A1true US20070047364A1 (en) | 2007-03-01 |
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| US11/216,666AbandonedUS20070047364A1 (en) | 2005-08-31 | 2005-08-31 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
| US12/511,666Expired - Fee RelatedUS9076509B2 (en) | 2005-08-31 | 2009-07-29 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
| US12/511,658Expired - Fee RelatedUS7952422B2 (en) | 2005-08-31 | 2009-07-29 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
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| US12/511,666Expired - Fee RelatedUS9076509B2 (en) | 2005-08-31 | 2009-07-29 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
| US12/511,658Expired - Fee RelatedUS7952422B2 (en) | 2005-08-31 | 2009-07-29 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20090303778A1 (en) | 2009-12-10 |
| US7952422B2 (en) | 2011-05-31 |
| US20090302929A1 (en) | 2009-12-10 |
| US9076509B2 (en) | 2015-07-07 |
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