US20070023904A1 - Electro-optic interconnection apparatus and method - Google Patents

Abstract

A construction for attaching an optical fiber to an electro-optic chip is described. The construction includes support for the optical fiber, optionally provided by an aperture in a supporting copper sheet. High density interconnection circuits are fabricated on the copper sheet. Pillar-in-well connections are used between the electro-optic chip and the interconnection circuits, with electrical connections for signals and power, and thermal connections at increased density for cooling the chip. An electronic subsystem employing stacked modules is described, with optical ports at each of the modules.

Description

• This application claims priority to U.S. provisional patent application Ser. No. 60/704,721 filed Aug. 1, 2005, the entire contents of which are hereby incorporated herein by reference.
FIELD OF THE INVENTION
• This invention relates to interconnections between optical devices and electronic systems, and more particularly to methods for connecting an electro-optic device in an electronic subsystem with high rate cooling in selected areas.
DESCRIPTION OF THE RELATED ART
• Over the last 40 years transistor density in silicon integrated circuit (IC) chips has increased by a factor greater than 100,000; this phenomenon is known as Moore's Law. Meanwhile, the ability to integrate silicon chips into systems has progressed relatively slowly. Package development can be traced from printed circuit boards (PCBs) having plated through holes (PTHs) around 1970. Surface mount technology (SMT) has followed, also multi-chip modules (MCMs), and systems in package (SIPs). The slow rate of development of integration methods compared with silicon fabrication has resulted in an integration gap; this gap has dimensions of cost, performance, cooling, and scalability.
• The 2003 International Technology Roadmap for Semiconductors (ITRS) shows packaging costs for microprocessor circuits exceeding chip costs in 2010. Digital IC chips can now operate at signaling rates of 10 Gbps while many packages do not support speeds greater than around 200 Mpbs. Cooling has become critical. Modern servers typically have bulky finned aluminum heat sinks surrounding each of the processors. This increases the volume of the server units with attendant cost increases and performance decreases. Recent microprocessor chips dissipate as much as 150 W each. Cooling costs for a 30,000 square foot data center are reported at $8 million per year. Scalability has not been much discussed at the system level, apart from providing servers in a blade form factor for higher packaging density and user convenience. Generally, system or subsystem scalability is difficult if multiple component types and packages are employed.
• Electrical connections to an IC chip have typically occurred on the front side of the chip where the active circuits and bonding pads are located, while cooling has been provided at the back side. Thermal interface materials (TIMs) such as thermal grease have been used between the back side of the die and its heat sink. When thermal grease is used, it is typically the highest impedance element in the thermal path.
SUMMARY OF THE INVENTION
• Methods for interfacing optical fibers to electronic systems or subsystems are described. An electro-optic chip having a flip chip interface comprising a mixed array of signal bumps and heat bumps is attached to an interconnection circuit on a copper substrate. The heat bumps can provide cooling of 160 W/cm²in the assembly described, and optional copper slugs can provide cooling of hot spots at over 1000 W/cm². Methods for aligning and attaching an optical fiber with an optical path through the copper substrate are also described.
BRIEF DESCRIPTION OF THE DRAWINGS
• The foregoing and other objects of the invention will be more clearly understood from the accompanying drawings and description of the invention:
• FIG. 1 is a cross-sectional view of a stacked subsystem of the current invention, including embedded cooling channels.
• FIG. 2A is an enlarged cross-sectional view of region A ofFIG. 1.
• FIG. 3 is a cross-sectional view corresponding to section AA ofFIG. 2.
• FIG. 4 is similar toFIG. 3, except some solder balls have been replaced with fiber optic connections.
• FIG. 5 shows an expanded cross-sectional view of a fiber optic connector ofFIG. 4.
• FIG. 6 shows in cross-section a further expanded view of a fiber optic connector that employs both heat bumps and I/O bumps.
• FIG. 7 depicts in cross-section a fiber optic connection that does not require a glass window.
• FIG. 8 shows in cross-section a stack of subsystems, with a fiber optic connection to each subsystem.
• FIG. 9 illustrates in cross-section the use of a semiconductor plug device in a module.
• FIG. 10 shows an expanded schematic cross-sectional view of the plug device ofFIG. 9.
• FIG. 11 is a schematic view of section BB ofFIG. 2, showing an interface between a chip and a substrate that includes a mixed array of I/O bumps and heat bumps.
• FIG. 12 is an expanded cross-sectional view of section CC ofFIG. 11.
• FIG. 13 is a further expanded cross-sectional view of Detail D ofFIG. 12.
• FIG. 14 is an expanded cross-sectional view showing the use of a damping layer.
• FIG. 15 is a top view of a square copper panel showing a layout of multiple copper substrates on a circular copper wafer to be separated from the square panel.
• FIG. 16A-16F depicts in cross-section a series of process steps for fabricating a hermetic copper substrate of the current invention having glass-isolated copper feedthroughs.
• FIG. 17A-17P depicts in cross-section a series of process steps for fabricating a 5-layer interconnection circuit plus and a well layer on the copper substrate ofFIG. 15D, and also forming a solder ball at each feed through, and assembling a chip on the interconnection circuit.
• FIG. 18 shows a subsystem stack in cross-section, including a directed source of hot inert gas for removing a defective module.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• Various embodiments of the present invention are described hereinafter with reference to the figures. It should be noted that the figures are only intended to facilitate the description of specific embodiments of the invention. They are not intended as an exhaustive description of the invention or as a limitation on the scope of the invention. In addition, an aspect described in conjunction with a particular embodiment of the present invention is not necessarily limited to that embodiment and can be practiced in any other embodiments. For instance, the preferred embodiment describes cooling of the high power laser diodes in the electro-optic chip using heat bumps at the front face of the chip. However, additional cooling may be applied through the back face of the chip, using a thicker chip or a copper slug, as described relative to other circuit elements of the current invention.
• A preferred embodiment of the current invention is a stacked system or subsystem employing modules comprising copper substrates and arrays of flipped chips, with inter-stack cooling channels provided between each pair of modules in the stack. Conventional system components such as PCBs and discrete packages are eliminated. The system is assembled from semiconductor chips and copper substrates having interconnection circuits fabricated thereon. Preferably all of the integrated circuit types including digital, analog, RF, integrated passives, optical, and electro-optical are provided on IC chips that attach using the same type of PIW connector.
• The PIW connector employs a pillar or a bump inserted into a well filled with conductive material. It is described in U.S. Pat. No. 6,881,609 for the case of gold stud bumps and solder as the conductive material in the wells. The bumps are usually provided on the IC chips and the wells are provided on the substrate to which the chips are attached, although the reverse can also be employed. The current description of PIW employs a flexible copper pillar for the bump instead of a gold stud bump. The pillar is formed by electro-deposition as a thin wire-like element having flexibility for relieving stress at the interface between chip and substrate. By providing this stress relief using flexible pillars, columns, mesas, or bumps, the typical requirement for an epoxy under layer is avoided; this makes easy rework possible. Testing of known good die (KGD) can be accomplished at full power and full speed by filling the wells with a conductive dry powder. Modules including multiple chips can be assembled and tested in this temporary form of the final assembly, with convenient replacement of any chips that prove defective. For production units, a semi-permanent connection is made by heating the dry powder to form solder; this can be accomplished in one step for an entire subsystem assembly. Even the melted solder connections can be reworked if necessary. This is done be selectively applying heat to melt the solder attaching a defective component. The defective component is withdrawn from the wells, the remaining solder is sucked out of the wells, the wells are refilled and a replacement chip is attached. By using these temporary and semi-permanent connections, complex assemblies with 100 or more chips can be assembled with 100% assembly yield. This avoids rejection of modules or subsystems due to imperfect yield of the component chips. Thus a cost benefit is achieved for modules having up to approximately 6 chips where the compound yield is satisfactory, and an enabling technology is achieved for extending module complexity to modules having 100 chips or more, for example.
• For complex flip chip assemblies it is difficult or impossible to test them at full power and full speed through a cable to an external test box. Use of a typical test connector and cable tends to negate the miniaturization advantages of flip chip. Also, it is difficult to drive and sense high speed signals through conventional cables and connectors due to their parasitic inductance and capacitance, particularly as chip technology progresses toward lower power supplies and reduced noise margins. For the systems described herein it is preferable to provide test chips resident in the modules; they will include high speed sampling circuits and comparators and an interface to a test support computer. This testing approach is described in co-pending U.S. patent application Ser. No. 10/448,611, and is incorporated herein in its entirety by reference.
• The current invention provides an option for providing a mixed array of flip chip connectors at the interface between each chip and its underlying substrate. The mixed array provides both input/output (I/O) capabilities and heat sinking capabilities on the active (front) side of the IC chip. A regular array of bumps (pillars) can be formed in rows and columns to create a sea of bumps, of which selected ones are used for I/O, and the others are used for heat-sinking. Modern microprocessor chips may require 2,000 leads or more, combining both signal and power pins. The PIW connectors can be configured in a small size that will support digital signaling rates of around 20 Gbps.
• FIG. 1 shows a stacked electronic assembly (subsystem)10 of the current invention.Subsystem10 includeshermetic modules11 containing IC chips12.Modules111 at different levels in the stack may be similar to perform a similar function, or may be different to perform different functions.Modules11 are preferably built oncopper substrates14 and are preferably separated byinter-stack cooling channels15 through which a coolant may flow.Modules11 andcooling channels15 are preferably hermetically sealed (hermetic), to prevent any moisture reaching IC chips12 as well as to contain the coolant without leakage. As examples, the coolant fluid may be air or water or liquid metal.Cooling channels15 may be provided between each pair ofmodules11, or may be selectively included between high power modules, and not included between low power modules.Subsystem10 may interface with a PCB or other electronic component usingsolder balls16 arranged to form a ball grid array (BGA). The BGA interface provides power and signal I/O to stackedassembly10, and thestacked BGA connectors17 provide distribution throughoutsubsystem10. PIW connectors may be used in place of the BGA connectors, although a sealing type of connection is required to contain the coolant in coolingchannels15, and this is typically achieved using solder. Thus, a hybrid of PIW electrical connectors combined with solder-type sealing connections may be employed. Atypical height H18 forsubsystem10 including sixteenmodules11 is 60 mm with a typicalwidth dimension W19 of 50 mm. Anexample subsystem10 may be a 64-way computer server wherein eachmodule111 contains around 80 IC chips and implements a 4-way server. The suite of IC chips withinmodule11 may include processors, I/O and legacy controllers, memory chips of various types (flash and DDR RAM for example), power distribution chips, one or more test chips, and integrated passives. Compared with servers that are currently available in a blade format (like the IBM HS40 which is a 4-way blade server),modules11 are smaller and lighter by a factor of more than 100. As will be further explained,modules11 andsubsystem10 are also testable and repairable, including repair of any chip in any module.
• Subsystem10 will be more reliable than conventional subsystems because of its electrical, mechanical, and thermal design. This is briefly described here in the context ofFIG. 1 and further elaborated in the following paragraphs. A new type of flip chip connector (the PIW connector) is used to attach each of the I/O chips such as12. A similar PIW connector is used for both I/O and for heat extraction. The PIW connector includes a slender copper column (bump) that is flexible enough to relieve shear stresses at the chip/substrate interface. The flexibility (compliance) of the copper column eliminates reliability issues such as cracking of the solder joints due to thermally induced mechanical stress. Also, epoxy under fill is not required and this is an important enabler of an effective rework strategy, for replacing a component that proves to be defective. The copper base plates provide a rugged mechanical design, yet compliance in the flexible copper bumps makes the modules resistant to vibration and shock damage. The thermal design includes options for cooling high thermal fluxes, to be further described. Tight control of junction temperatures leads to increased circuit reliability which is a strong function of peak operating temperature. Finally, by eliminating conventional cables and connectors, subsystem reliability is further improved.
• The scalability ofsubsystem10 is apparent from its modular construction; the stacking unit is a 4-way server in the preferred embodiment. It can be envisaged that a 256-way server would comprise a stack having four times the height ofsubsystem10, for example. It is anticipated that such a 256-way server would require more I/O than a 64-way server; in this case the footprint may be increased, accommodating more I/O at the BGA interface. Since solder bumps and copper feedthroughs have high current capacity, the number of BGA connectors needed for distributing power may not need to increase, allowing the additional pins to be used for I/O. As an alternative solution that will accommodate high bandwidth signals, fiber optic communication ports will be described in reference toFIG. 4 throughFIG. 8.
• Compared with a typical electronic subsystem of today, the usual printed circuit boards and discrete packages have been eliminated.Subsystem10 has been assembled from IC chips and copper substrates with interconnection circuits that will be further described. This requires that all circuit components be provided in the form of IC chips, including integrated devices like computing cores, memory chips, power distribution chips, and integrated passives, as well as discrete devices such as resistors, capacitors, inductors, power diodes and power transistors. It also requires innovations in test, assembly and rework, as will be further described. However, elimination of conventional packages and boards reduces cost. The board of the current invention can be viewed as the combination of a high density interconnection (HDI) circuit and a heat dissipation device. Other manufacturing cost advantages are achievable using new testing and rework methods, to be further described.
• Because of their small size, the I/O connectors will have a low inductance of approximately 0.1 nH, and this will enable digital signaling rates of around 20 Gbps as well as RF connections operating at frequencies up to around 10 GHz.
• FIG. 2 is an expanded cross-sectional view of region A ofFIG. 1. It details a portion ofmodule11, employingcopper substrates14. Coolingchannel15 is shown, andsolder ball16 of a BGA interface.Copper feedthrough21 is isolated fromcopper substrate14 by aglass seal22, to be further described. IC chips such as12bare mounted using a flip chip attachment tointerconnection circuit23a, to be further described. If the backside of a chip requires a bias voltage, it can be provided using awire bond24 to a corresponding pad oninterconnection circuit23a.Solder elements25aand25bare lines of solder that provide a hermetic seal at the edges ofcoolant channel15. Similarly,solder elements26aand26bare lines of solder that seal at the outer edges of coolant channel layers, thus keeping feedthroughs like27adry.Solder elements26cand26dare also lines of solder; in this case their function is to keep the interior ofmodule11 dry. Feedthroughs like27bwithinmodule11 have a slightly different structure from feedthrough27a.Solder bump28 connects between two copper feedthroughs with no interconnection circuit present. Conversely,solder bump29 connects to a trace oninterconnection circuit23bthrough acopper pad30 embedded in the interconnection circuit. Note that interconnection circuits of the current invention include polymer dielectric layers that are not impervious to water; thus they are not present at the hermetic sealing elements.
• FIG. 3 corresponds to section AA ofFIG. 2.Copper base plate14 is shown, together with solder features25,26, and28 defined inFIG. 2. Coolant flow is unobstructed in the direction shown,31.
• FIG. 4 shows a variation ofFIG. 3 wherein some of the solder bumps have been replaced with optical connections to increase the I/O bandwidth ofmodule11 ofsubsystem10.Optical fibers41aand41bare shown. For example,circuit42 may implement an optical receiver andcircuit43 may implement an optical transmitter. Again,coolant flow31 is unobstructed.
• FIG. 5 illustrates in cross-section an expanded view ofoptical circuit42 ofFIG. 4, includingoptical fiber41aandlight path51. Electro-optic chip12cis directly attached tointerconnection circuit23cusing PIWflip chip connectors52, to be further described. For improved heat dissipation,chip12cmay be increased in height to provide cooling through the back face of the die tocopper substrate14b, or alternatively, a copper slug like20 ofFIG. 1 may be employed. Aclear glass window53 is provided incopper substrate14afor transmittinglight signal51.Glass window53 is sealed insubstrate14ausing aglass seal54, to be further described. Analignment cap55 is used to position the end offiber optic cable41ain proper relation to electro-optic chip12c.Hermetic structure56aseals an edge ofcoolant channel15, andhermetic structure56bseals the complement of chips provided insubsystem11b.Filler materials57aand57bare used to stabilize the structures after assembly; they are non-conducting and preferably good thermal conductors. A disadvantage ofmodule11bcompared withmodule11 ofFIG. 1 is increased difficulty of rework, owing to the presence offiller57b. Another disadvantage is the lack of a hermetic environment for electro-optic chip12c. However, providing high bandwidth optical connections is important enough that these disadvantages may be acceptable.
• Optical alignment oflight path51 with electro-optic chip12ccan be accomplished in two steps. First, the basic alignment accuracy of the PIW connectors is around ±5 μm. A performance parameter of the optical link (such as signal to noise ratio, SNR) is monitored while the solder is melted and the fine positioning of the chip attachment is optimized for link performance. The initial alignment and the fine-tuning feature depend on features of the PIW connector, to be further described.
• FIG. 6 is a further expanded cross-sectional view of a preferred direct chip attachment of electro-optic chip12cwithinterconnection circuit23c. InFIG. 6 this attachment includes a combination of heat bumps61 and input/output (I/O) bumps62 as shown. The heat bumps are densely packed for maximum heat conduction and the I/O bumps are spaced apart to create separate electrical connections, to be further described. Heat bumps61 terminate on acopper pedestal63 while I/O bumps62 terminate ininterconnection circuit23c.
• FIG. 7 shows a variation on the fiber optic attachment depicted inFIG. 6. A precisely located and alignedhole71 is provided incopper substrate14bfor capturing the end ofoptical fiber41awhile providing good alignment oflight path51 as it enters or exits from electro-optic chip12c. As will be further described, the process used tomachine copper substrate14bcan createalignment hole71 with a placement accuracy of around ±1 μm using available milling machines. Using this placement accuracy together with a process for fine-tuning the optical alignment, as described in reference toFIG. 5, good optical alignment can be achieved while avoiding the cost of fabricating theclear glass window53 shown inFIG. 6.
• FIG. 8 shows astacked subsystem architecture80 of the current invention wherein each of the modules in the stack has afiber optic connection81 for increased I/O bandwidth.
• FIG. 9 illustrates the use of asemiconductor plug91 for communicating high bandwidth signals betweeninterconnection circuits23dand23eofmodule11c.Chips12dand12eare thinned to approximately one half of the thickness ofplug91 so that the different chips fit well together inmodule11cas shown.
• FIG. 10 is a schematic representation ofplug91 including copper bump (pillar)element100, andfeedthrough element101. Various methods are known in the art for creatingfeedthrough element101 using either polysilicon or copper as the feedthrough conductor. Detailed features ofbump element100 will be further described.
• FIG. 11 corresponds to section BB ofFIG. 2; it is a cross-section representing an interface between a chip and a substrate. Abackground array111 of heat bumps is shown; it is comprised of copper columns that are closely spaced for maximum heat conduction and bend individually to relieve stress at the interface. I/O bumps are arrayed in rows and columns like112; the I/O bumps are spaced apart and connect to substrate nodes individually, as will be further described. The layout shown inFIG. 11 represents a default or starting condition; it can be adjusted as required in response to routing issues and thermal issues. Note that the default layout shown inFIG. 11 provides a signal connector within a millimeter or two of any location on the chip; this means that signal path lengths can be short, aiding high frequency operation.
• FIG. 12 is an expanded cross-sectional view corresponding to section CC ofFIG. 11. Heat bumps61 and I/O bumps62 are shown. Heat bumps61 terminate at the substrate in acommon well63 filled with conductive material. I/O bumps62 terminate at the substrate inindividual wells64 filled with conductive material.
• FIG. 13 is a further expanded cross-sectional view corresponding to Detail D ofFIG. 12. Both heat bumps61 and I/O bumps62 are slender copper pillars that can flex to relieve stress at the interface. The bumps are anchored onpads135 located on the front face (active side) ofchip12f. A preferred height-to-width ratio for both kinds of bumps is 5-10. A preferred height is 100 μm, because calculations show that around 32 μm of lateral translation is required at the edge of a large chip undergoing typical temperature cycles during manufacture; a height of 100 μm provides enough extension and flexibility to accomodate this motion. In addition to the lateral motion, about 6 μm of vertical translation is also required to relieve the interface stress, allowing an attached chip to remain flat; the columns are preferably flexible enough that they will bend or buckle as required to relieve this stress in the vertical direction. A preferred pitch for the I/O connectors is 80 μm, providing over 15,000 connectors per square centimeter. This density provides enough connectors for good localized power distribution. The extra connectors can also help to lower signal cross-talk, by surrounding each signal connector with a set of nearest-neighbor GND or DC power connections. A preferred pitch for the heat bumps is 30 μm, providing over 100,000 bumps per square centimeter. A suitable plating resist for achieving these geometries is Clariant Exp 100XT. It is a positive resist that is easily stripped after the copper columns are formed. The resist can be patterned with essentially vertical sidewalls at 100 μm thickness.
• Common well63 is provided for terminating the heat bumps at the substrate surface, and anindividual well64 for each I/O bump is shown. An example of aninterconnection circuit23fis shown. The well layer is shown as133. Heat bumps61 thermally connect with acopper pedestal134 for maximum heat conduction fromIC chip12ftocopper substrate14. As will be further described, each bump originates at a pad like135 on the chip. Note that bumps61 and62 combine mechanical, electrical, and thermal functions. Mechanically they provide structural support, stress relief, and compliant resistance to vibration and shock. Electrically they provide low inductance connectors estimated at 0.1 nH per bump/well combination; thus they will support digital signaling at around 20 Gbps and RF circuits operating at multi-gigahertz frequencies. Thermally they can dissipate heat flux ranging from 9 W/cm²for signal bumps alone, to 160 W/cm²for densely packed heat bumps, and to over 1,000 W/cm²when copper slugs like20 inFIG. 1 are employed. These calculations assume a liquid coolant temperature of 10° C. and a maximum junction temperature of 85° C. Without resorting to the use of copper plugs, or using them only sparingly, subsystems like10 ofFIG. 1 can dissipate over 10 kW, while running efficiently and reliably. This multi-function performance can enable a new technology platform wherein digital and RF components are integrated using the same PIW connector. The preferred technology platform also includes copper substrates and high density interconnection circuits and test chips, to be further described.
• FIG. 14 shows the use of a dampinglayer135 of dielectric material such as polyimide, fabricated onchip12fand substantially filling the space aroundpillars61 and62, except for ends of the pillars that are inserted into the wells. Dampinglayer135 provides a compliant support structure that does not substantially interfere with the stress-relieving properties of the compliant pillars, yet provides additional protection against shock and vibration, and adds another thermally conductive path to aid in transporting heat betweenchip12fandsubstrate14.
• This disclosure will now describe manufacturing processes for building the preferred modules and subsystems, along with a test method and a rework method for the stacked architecture.
• FIG. 15 is a top view of asquare copper panel140, preferably measuring 305×305×0.8 mm. Inscribed onpanel140 is acircular copper wafer141 that is 300 mm in diameter. Inscribed withinwafer141 are seventeencopper substrates14 measuring 50×50 mm. These dimensions take advantage of available fabrication equipment for processing 300 mm semiconductor wafers; however, any practical size ofpanel140,wafer141, andsubstrate14 are included in the current invention. Alignment marks142 are also provided; along with the wafer and substrate outlines they are inscribed (machined) into the copper surface during milling steps to be described.
• FIG. 16A-16F illustrates a process sequence for fabricating isolated copper feedthroughs, starting withcopper panel140.FIG. 16A shows a vacuum hold-down surface161 of a milling machine such as an H100 available from LPKF Laser and Electronics, Wilsonville, Oreg., USA. This machine spins the cutting tool at 100,000 RPM and is capable of milling tracks as narrow as 0.0031 inches or 80 μm. It also has a repetition accuracy of ±1 μm.Copper panel140 ofFIG. 15 is affixed tovacuum surface161 using two mounting tapes that are pre-applied to the copper panel. The first tape is preferably a thermal release tape such as Revalpha available from Nitto Denko, Tokyo, Japan. It has a thermal release temperature of 150° C. for example. After removing its liner, this tape includes thermal release layer162 (which is adhesive) andbase polyester layer163. The second applied tape has anadhesive layer164 and aporous backing layer165. After mountingcopper panel140 tovacuum surface161 using the two mounting tapes, the milling tool is programmed to cut cylindrical cavities such as166aand166bthat penetrate intoporous layer165 but do not interfere withvacuum surface161. The preferred thickness ofpanel140 is 0.8 mm and the preferred cavity width,w167, is 0.1 mm.
• FIG. 16B shows the effect of screening aglass frit material170 into the machined cavities. This process is preferably performed using a vacuum table171, which will help fill the cavities to the bottom.
• FIG. 16C shows the result of activating the thermal release layer and removing both of the tapes from the back side ofcopper panel140. The stiffness of the screened frit material is adequate to holdcopper feedthroughs21 in position while both mounting tapes are released using a hotplate.
• FIG. 16D shows the result of firing the glass frit to form glass seals22 aroundcopper feedthroughs21, as first defined inFIG. 2. An inert atmosphere is used for this firing at around 550° C., to prevent excessive oxidation ofbase copper panel140. The screened frit material will reduce in volume when fired, forming acupped surface172 as shown.Copper wafer141bwill be separated from thecopper panel140 using the milling tool, employing alignment marks142 previously described in reference toFIG. 15. Chemical mechanical polishing (CMP) will be applied as is known in the art, to polish the separated copper wafer to a final preferred thickness of 0.6 mm.
• FIG. 16E shows an under bump metallization (UBM)173 applied to the copper feedthroughs as shown. UBMs are known in the art; a typical formulation includes a thin titanium layer for adhesion, nickel as a diffusion barrier, and gold to provide a solder wetting surface.
• FIG. 16F showscopper substrate14 withsolder balls16 formed onUBM layer173. Since the solder balls would prevent vacuum hold-down on chucks used for processing the interconnection circuits oncopper wafer141b, process steps described in relation toFIGS. 16E and 16F are delayed until the interconnection circuits are completed. The solder balls may be formed using wafer level stencil printing, jetting processes, or electroforming, all known in the art. When the deposited solder alloy is heated to melting, it is pulled into a spherical shape by surface tension. After bumpingwafer141bwith solder balls, it can be separated intoindividual module substrates14 using the milling tool previously described.
• FIG. 17A-17P illustrates a process sequence for fabricating interconnection circuits and a well layer on a copper wafer.FIG. 17A-17E teaches the base processes for fabricating a single dual damascene copper layer, of which five are included in the preferred embodiment of the current invention. For visual reference inFIG. 17A-17P anedge172 is shown, although this edge is not created until wafer processing is completed andsubstrates14 are separated fromwafer141c.
• FIG. 17A shows the result of spincoating copper wafer141cwith a preferred spin-on dielectric (SOD)material171 called BCB (benzocyclobutene), which is well known in the industry. Polyimide may be used in place of BCB. The preferred thickness is approximately 8 μm.
• InFIG. 17B,layer171 of BCB has been patterned using dual damascene processes, forming viafeatures173aand173b, and also trace features174. Either photolithographic methods or the imprinting method may be used to achieve this result; both are known in the art.
• FIG. 17C shows the result of sputter deposition of a seed layer ofcopper175, typically using a thin layer of titanium for adhesion to the underlying BCB.
• InFIG. 17D, the copper seed layer has been electroplated, terminating in anuneven surface176.
• FIG. 17E shows the result of polishing the surface ofwafer141cusing CMP methods known in the art.Power trace layer177 is complete, includingvias178 and179, also traces180. In the preferred embodiment, this layer provides GND plus two power supplies, delivered using via/trace179 and traces180aand181arespectively. These power traces repeat across the substrate surface, and trace181bdelivers the same voltage as181a. For the special case of thepower trace layer177 depicted inFIG. 17E, embedded capacitance may be valuable for bypassing each power supply to GND. Consequently, a high dielectric material may be used forlayer171 instead of BCB or polyimide. This embedded capacitance technique is also known in the art.
• FIG. 17F shows that anew layer184 of SOD material has been applied towafer141c, in preparation for fabrication of a second dual damascene copper interconnect layer.
• FIG. 17G shows completedsecond layer185 which is a GND layer, to support a transmission line structure for the subsequent signal layer, as is known in the art.Layer185 includesground conductors186 andfeedthrough vias187.
• FIG. 17H depictsfirst signal layer188, includingtraces189 that preferably run in the x-direction. Signal traces are routed around the power and GND vias.
• FIG. 171 shows second signal layer194, including traces like195 that preferably run in the y-direction.
• FIG. 17J illustrates layer196, includingvias197 that will connect with wells, to be fabricated next.
• FIG. 17K illustrates a patterneddielectric layer201, preferably around 20 μm thick, forming the well shapes for a well layer,200a.
• InFIG. 17L, well layer200bincludes sputter deposited Ti/Au202 that physically and electrically connects with the underlying copper structures. An outer covering of gold is required for compatibility with the preferred 80Au20Sn solder paste. For reliable solder connections, the Au layer must be at least 1000 Angstroms thick.
• FIG. 17M shows the result of CMP to remove the Ti/Au thin films infield areas203, providing electrical isolation between the wells inlayer200c.
• InFIG. 17N, layer200dshows that the wells have been filled with fineconductive particles204. The preferred particles are made from a gold-tin alloy, 80Au20Sn. The preferred particle diameter is smaller than 4 μm, for easy filling of thewells64. 80Au20Sn alloy is lead-free, and has a successful history as a high-reliability solder. Any oxide tarnish on the particles can be removed by dipping in dilute hydrochloric acid; thus providing a flux-free solder. The wells are filled by pouring the conductive powder over the substrate surface to fill all of the wells, then applying and removing a sheet of adhesive to the substrate surface to remove loose particles adhering toareas203 between the wells.
• FIG. 17O shows the result of aligning anIC chip12gwith the substrate containing the wells, bringing them together, and pushing gently onchip12gso that thepillars62 penetrate the powder in the wells. For fragile chips such as ones using delicate low-k dielectrics, it may be desirable to apply ultrasonic shaking, so that the pillars enter the powder in the wells using only gravity as a pushing force. The alignment process is known in the art: a precision flip chip aligner using split beam optics can achieve alignment accuracy of around ±2 μm. 80Au20Sn is reported to have tensile strength and shear strength of 40,000 PSI, the highest of commonly available solders. This strength is advantageous for capturing the ends of copper bumps62 inwells64 firmly under mechanical stress conditions such as occur during temperature cycling or shock conditions.
• FIG. 17P shows the result of melting and flowing the 80Au20Sn solder at approximately 320° C.; the volume of solder shrinks slightly.
• In the event that a large subsystem like10 ofFIG. 1 begins to fail, some disassembly may be required. The resident test chips can be used to isolate which of the modules is defective and needs replacement or repair.FIG. 18 shows schematically how the nozzles of a rework device can direct jets of hot inert gas selectively at a particular set of feedthroughs in the stack. Soldered joints at the chosen level in the stack will melt, allowing disassembly. This process may be aided by flowing hot inert gas throughadjacent cooling channels15. It is preferable to suck out any solder remaining at the interface and replace it with new solder on the replacement parts. The new solder is reflowed to semi-permanently install the replacement module. Defective modules can be repaired by re-working defective chips using the process previously described in relation to PIW connectors.
• A stacked 3D electronic subsystem has been described with optical ports for high bandwidth signals. It can achieve a miniaturization factor of over 100 compared with equivalent assemblies using current technology, yet it can be well-tested, repairable, and adequately-cooled. The described methods can be applied to increase performance and reduce cost, in assemblies as small as cell phones and as large as supercomputers.

Claims (19)

1. An electro-optic assembly comprising:

a substrate;

an electro-optic chip;

an optical fiber carrying signals in communication with said electro-optic chip;

interconnection circuits fabricated in or on said substrate; and,

a flip chip interface between said electro-optic chip and said interconnection circuits.

2. The electro-optic assembly ofclaim 1 wherein said flip chip interface includes a mixed array of signal pillars carrying signals or power, and closely spaced heat pillars.

3. The electro-optic assembly ofclaim 2 wherein each of said signal pillars is inserted into a matching well filled with conductive material in said interconnection circuit.

4. The electro-optic assembly ofclaim 3 wherein said heat pillars are provided in a background array, and said signal pillars are located wherever necessary for electrical connections.

5. The electro-optic assembly ofclaim 1 wherein said substrate includes a sheet of copper or an alloy of copper.

6. The electro-optic assembly ofclaim 5 wherein said copper sheet includes an aperture for positioning said optical fiber in relation to said electro-optic chip.

7. The electro-optic assembly ofclaim 1 wherein the back side of said electro-optic chip is thermally coupled to a heat sink.

8. The electro-optic assembly ofclaim 7 wherein said thermal coupling includes a copper slug between said back side of said electro-optic chip and said heat sink.

9. A method for aligning an optical fiber to an electro-optic chip comprising the following steps:

a) providing a substrate;

b) attaching said electro-optic chip to said substrate;

c) drilling an aperture in said substrate corresponding to the desired entry or exit point of light signals interacting with said electro-optic chip; and,

d) positioning an end of said optical fiber in said aperture.

10. The method ofclaim 9 and further including the following steps;

e) establishing a communication link through said fiber to said electro-optic chip; and,

f) optimizing the performance of said link while adjusting said attachment of said electro-optic chip to said substrate.

11. The method ofclaim 10 wherein said attachment includes pillars at input/output pads of said electro-optic chip, said pillars are inserted in conductive material in matching wells in interconnection circuits on said substrate, and said adjusting includes small movements of said pillars in said wells.

12. A stacked electronic subsystem having optical communication ports comprising: stackable circuit modules;

cooling channels provided between selected ones of said circuit modules; and,

one or more of said optical communication ports in each of said circuit modules.

13. The stacked electronic subsystem ofclaim 12 wherein said modules are interconnected using ball grid arrays.

14. The stacked electronic subsystem ofclaim 12 wherein said modules are interconnected using pillar-in-well connectors.

15. The stacked electronic subsystem ofclaim 12 wherein each of said modules is hermetically sealed.

16. The stacked electronic subsystem ofclaim 12 wherein said modules are enclosed between sheets of copper or copper alloy.

17. The stacked electronic subsystem ofclaim 16 wherein a coolant fluid is circulated in each of said cooling channels.

18. The stacked electronic subsystem ofclaim 16 wherein each of said communication ports includes an optical fiber capable of carrying signals that communicate with said electronic subsystem.

19. The stacked electronic subsystem ofclaim 18 wherein each of said optical fibers is positioned in an aperture provided in one of said copper sheets.

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