US20070010055A1 - Non-volatile memory and fabricating method thereof - Google Patents

Abstract

A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive: layers are formed between two neighboring first dielectric layers in the same row.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to a memory device and fabricating method thereof. More particularly, the present invention relates to a non-volatile memory and fabricating method thereof.
• 2. Description of The Related Art
• Non-volatile memory is a type of memory that allows writing, reading and erasing data for multiple times, and the stored data will be retained even after power supplied to the device is off. Furthermore, non-volatile memory also has the advantages of small size, fast access speed and low power consumption. In addition, data can be erased in a block-by-block fashion so that the operating speed is further enhanced. With these advantages, non-volatile memory has become one of the most widely adopted memory devices for personal computers and electronic equipments.
• A typical non-volatile memory comprises an array of memory cells. The horizontally laid memory cells are serially connected through a word line and the vertically laid memory cells are serially connected through a bit line. In general, the control gate of the memory cell serves as the word line, while the source region or drain region of the memory is electrically connected with bit line through the source contact or the drain contact. However, in the process of forming such contacts, misalignment between the contacts and the source regions or the drain regions occurs easily, which would reduce device reliability. Although the misalignment can be corrected through an increased width of the source regions or the drain regions, the size of each device would be enlarged as well. Hence, in view of device integration; a better solution is desired.
SUMMARY OF THE INVENTION
• Accordingly, at least one objective of the present invention is to provide a method of fabricating a non-volatile memory capable of resolving the misalignment problem in the conventional contact fabricating process.
• At least a second objective of the present invention is to provide a non-volatile memory having a smaller device dimension so that overall level of integration of the memory can be increased.
• To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a non-volatile memory. First, a substrate is provided. A plurality of columns of isolation structures are formed on the substrate. Thereafter, a plurality of rows of stacked gate structures are formed on the substrate. The stacked gate structures cross over the isolation structures, and each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate. After that, a plurality of doping regions are formed in the substrate, between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures between two neighboring rows of stacked gate structures. Wherein, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. Then, a plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.
• The present invention also provides a non-volatile memory. The non-volatile memory comprises a substrate, a plurality of columns of isolation structures, a plurality of rows of stacked gate structures, a plurality of stripes of spacers, a plurality of first dielectric layers, a plurality of first conductive layers and a plurality of doping regions. The isolation structures are located on the substrate. The stacked gate structures are located on the substrate, and cross over the isolation structures. Also, each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate. The spacers are located on the sidewalls of the stacked gate structures. The first dielectric layers are located on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. The first conductive layers are located between two neighboring first dielectric layers in the same row, and between two spacers in opposite sides. The doping regions are located in the substrate beneath the first conductive layers.
• Because contacts (the first conductive layers) are formed in the first dielectric layers on the isolation structures, misalignment between contacts and the source region or the drain region is minimized in the process of forming contacts, and the process window can be increased.
BRIEF DESCRIPTION OF THE DRAWINGS
• The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
• FIGS. 1A through 1C are top views showing the steps for fabricating a non-volatile memory according to one embodiment of the present invention.
• FIGS. 2A through 2D are schematic cross-sectional views along line I-I′ ofFIG. 1A showing the steps for fabricating a non-volatile memory.
• FIGS. 3A through 3D are schematic cross-sectional views along line II-II′ ofFIG. 1A showing the steps for fabricating a non-volatile memory.
• FIGS. 4A through 4D are schematic cross-sectional views along line III-III′ ofFIG. 1A showing the steps for fabricating a non-volatile memory.
DESCRIPTION OF THE EMBODIMENTS
• Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
• FIGS. 1A through 1C are top views showing the steps for fabricating a non-volatile memory according to one embodiment of the present invention;FIGS. 2A through 2D are schematic cross-sectional views along line I-I′ ofFIG. 1A;FIGS. 3A through 3D are schematic cross-sectional views along line II-II′ ofFIG. 1A; andFIGS. 4A through 4D are schematic cross-sectional views along line III-III′ ofFIG. 1A.
• First, as shown inFIGS. 1A, 2A,3A and4A, asubstrate100 is provided. Thesubstrate100 can be a silicon substrate. Then, a plurality of columns ofisolation structures102 are formed on thesubstrate100. Wherein,isolation structures102 are shallow trench isolation structures, for example, which can be formed by performing a conventional shallow trench isolation structure fabricating process.
• Thereafter, a plurality of rows of stackedgate structures104 are formed on thesubstrate100. Also, thestacked gate structures104 cross over theisolation structures102, and eachstacked gate structure104 comprises abottom dielectric layer106, acharge storage layer108, atop dielectric layer110 and acontrol gate layer112 sequentially disposed over thesubstrate100. Wherein, thestacked gate structures104 are defined by amask layer114, while thecontrol gate layer112 can serve as a bit line. In an embodiment, thebottom dielectric layer106 is a tunneling layer fabricated using silicon oxide material, for example. Thecharge storage layer108 is a charge-trapping layer fabricated using silicon nitride material, for example. Thetop dielectric layer110 is a charge barrier layer fabricated using silicon oxide material, for example. The control gate layer is a doped polysilicon layer, for example.
• After that, a plurality ofdoping regions116 are formed in thesubstrate100 between two neighboring stackedgate structures104. Thedoping regions116 can serve as source regions and drain regions, which can be formed by performing an ion implantation process.
• Then, as shown inFIGS. 2B, 3B and4B, a plurality of stripes ofspacers118 are formed on the sidewalls of the stackedgate structures104. The material of thespacers118 can be, for example, silicon nitride, which can be fabricated by forming a spacer material layer over the substrate, and then performing an anisotropic etching process.
• In an embodiment, after formingspacers118, the method further comprises forming heavy doping regions in thesubstrate100 by using the stackedgate structures104 and thespacers118 as a mask.
• Thereafter, dielectric material layers120 and122 are sequentially formed over thesubstrate100 to cover thestacked gate structures104,isolation structures102 andsubstrate100. In addition, the etching selectivities of the dielectric material layers120 and122 are different, so that thedielectric material layer120 can serve as an etching stop layer. In an embodiment, the material of thedielectric material layer120 can be silicon nitride, while that of thedielectric material layer122 can be silicon oxide, for example. In another embodiment, only thedielectric material layer122 is formed, and the material of thedielectric material layer122 can be silicon oxide.
• Then, as shown inFIGS. 2C, 3C and4C, the dielectric material layers120 and122 are patterned to formdielectric layers120aand122aon a portion of theisolation structures102 adjacent to two rows of stackedgate structures104, andopenings124 are formed. Also, oneisolation structure102 is disposed between two neighboringdielectric layers122ain the same row, while two neighboring rows comprising the dielectric layer112aandisolation structure102 are arranged in an interlacing manner (as shown inFIG. 1B). In addition, in an embodiment, the formeddielectric layers120aand122aextend in two sides to cover a portion of thestacked gate structure104.
• It is noted that self-aligned contact openings (openings124) can be formed between two neighboring stackedgate structures104 under the protection of thespacers118. Therefore, misalignment of contact openings is minimized, and the process window can be increased.
• Then,conductive layers126 are formed between two neighboringdielectric layers120aand122a(in openings124) in the same row. Wherein, the formedconductive layers126 can be self-aligned contacts. The material of theconductive layers126 can be tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material, for example, which can be made by forming a conductive material layer over thesubstrate100 to cover thedielectric layers120aand122a, stackedgate structures104 andsubstrate100, and then removing the conductive material layer outside theopening124 to expose the top surfaces of thedielectric layers122a, wherein the removing method can be a chemical mechanical polishing process. At this time, the conductive material layer cover all of thesubstrate100, and only the top surfaces of thedielectric layers122aare exposed. In an embodiment, before forming theconductive layers126, the method further comprises forming a conductive barrier layer to increase the adhesion of theconductive layers126.
• Thereafter, as shown inFIGS. 2D, 3D and4D, a portion of theconductive layers126, thedielectric layers120aand122ais removed on thestacked gate structures104 to expose the top surfaces of the stackedgate structures104. The removing method can be a chemical mechanical polishing process, for example.
• After that, adielectric layer128 with a plurality ofopenings130 is formed over thesubstrate100 to cover the entire structure, and eachopening130 exposes a partial region of theconductive layer126a. The material of thedielectric layer128 can be, for example, silicon oxide. Thedielectric layer128 is made by forming a dielectric material layer over thesubstrate100 to cover the entire structure, and then performing a patterning process to form theopenings130. It is noted that the size of theconductive layers126aunder the dielectric material layer is bigger, so that the process window is big during the patterning process to formopenings130, and thus misalignment can be avoided. In addition, in an embodiment, before forming the dielectric material layer, the method further comprises forming anotherdielectric layer132 to serve as an etching stop layer.
• Then, a plurality ofconductive layers134 are formed in the openings130 (as shown inFIG. 1C). Theconductive layers134 can serve as contacts, and electrically connect with theconductive layers126a. The material of theconductive layers134 can be, for example, tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material and is formed by forming a conductive material layer over thesubstrate100 to cover the entire structure, and then removing the conductive material layer outside theopenings130, wherein the removing method can be a chemical mechanical polishing process. In an embodiment, before forming theconductive layers134, the method further comprises forming a conductive barrier layer to increase the adhesion of theconductive layers134.
• Thereafter, a plurality of columns ofbit line136 are formed on thedielectric layer128, and eachbit line136 connects with theconductive layers134 in the same column.
• In the following, the structure fabricated in the above method is described. As shown inFIGS. 1C, 2D,3D and4D, the non-volatile memory comprises asubstrate100, a plurality of columns ofisolation structures102, a plurality of rows of stackedgate structures104, a plurality of stripes ofspacers118, a plurality of dielectric layers112a, a plurality ofconductive layers126aand a plurality ofdoping regions116. In an embodiment, the non-volatile memory further comprisesdielectric layers120aand128 and bit lines136.
• Theisolation structures102 are located on thesubstrate100, and theisolation structures102 can be shallow trench isolation structures. Thestacked gate structures104 are located on thesubstrate100, and cross over theisolation structures102. Also, eachstacked gate structure104 comprises abottom dielectric layer106, acharge storage layer108, atop dielectric layer110 and acontrol gate layer112 sequentially disposed over thesubstrate100.
• Thespacers118 are located on the sidewalls of the stackedgate structures104. Thedielectric layers122aare located on a portion of theisolation structures102 between two neighboring rows of stackedgate structures104. Also, oneisolation structure102 is disposed between two neighboringdielectric layers122ain the same row, while two neighboring rows comprising the dielectric layer112aand theisolation structure102 are arranged in an interlacing manner.
• Theconductive layers126aare located between two neighboringdielectric layers122ain the same row. The material of theconductive layers126acan be, for example, tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material. Thedoping regions116 are located in thesubstrate100 beneath theconductive layers126a.
• Eachdielectric layer120ais located between thedielectric layer122aand theisolation structure102, and between thedielectric layer122aandspacer118. The etching selectivities of thedielectric layers120aand122aare different. In an embodiment, the material of thedielectric layers120acan be silicon nitride, while that of thedielectric layers122acan be silicon oxide, for example.
• Thedielectric layer128 with a plurality ofopenings130 covers a portion of theconductive layers126a, thedielectric layers122aand thestacked gate structures104, and eachopening130 exposes a partial region of theconductive layer126a. Theconductive layers134 are located in theopenings130, wherein the material of theconductive layers134 can be tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material. The bit lines136 are located on thedielectric layer128, and eachbit line136 connects with theconductive layers134 in the same column.
• Accordingly, in the present invention, self-aligned contacts can be formed between two neighboring stacked gate structures by thespacers118 and the dielectric layers on the isolation structures. Therefore, misalignment of contacts is minimized, and the process window can be increased.
• It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (11)

1. A method of fabricating a non-volatile memory, comprising:

providing a substrate;

forming a plurality of columns of isolation structures on the substrate;

forming a plurality of rows of stacked gate structures, wherein the stacked gate structures cross over the isolation structures, and each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate;

forming a plurality of doping regions in the substrate between two neighboring stacked gate structures;

forming a plurality of stripes of spacers on the sidewalls of the stacked gate structures;

forming a plurality of first dielectric layers on a portion of the isolation structures adjacent to two rows of stacked gate structures, wherein one isolation structure is between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and isolation structure are arranged in an interlacing manner; and

forming a plurality of first conductive layers between two neighboring first dielectric layers in the same row.

2. The method according toclaim 1, after the step of forming the first conductive layers, the method further comprising:

forming a second dielectric layer with a plurality of openings over the substrate, wherein each opening exposes a partial region of the first conductive layer;

forming a plurality of second conductive layers in the openings; and

forming a plurality of columns of bit lines on the second dielectric layer, each bit line connecting with the second dielectric layers in the same column.

3. The method according toclaim 2, wherein a material of the second conductive layers comprises tungsten, polysilicon, doped polysilicon, copper or aluminum.

4. The method according toclaim 1, wherein each formed first dielectric layer extends in two sides to cover a portion of the stacked gate structure.

5. The method according toclaim 4, wherein the step of forming the first conductive layers comprises:

forming a conductive material layer over the substrate to cover the first dielectric layers, the stacked gate structures and the substrate;

removing a portion of the conductive material layer to expose the top surfaces of the first dielectric layers; and

removing a portion of the conductive material layer and the first dielectric layers on the stacked gate structures to expose the top surfaces of the stacked gate structures.

6. The method according toclaim 1, wherein the step of forming the first dielectric layers comprises:

forming a first dielectric material layer over the substrate to cover the stacked gate structures, the isolation structures and the substrate; and

patterning the first dielectric material layer.

7. The method according toclaim 6, further comprising forming a second dielectric material layer over the substrate before forming the first dielectric material layer.

8. The method according toclaim 7, wherein the etching selectivities of the first dielectric material layer and the second dielectric material layer are different.

9. The method according toclaim 1, wherein a material of the first conductive layers comprises tungsten, polysilicon, doped polysilicon copper or aluminum.

10. The method according toclaim 1, wherein the control gate layer serves as a bit line.

11-17. (canceled)

Images