US20060261397A1 - Lanthanide oxide/hafnium oxide dielectric layers - Google Patents

Abstract

Dielectric layers are provided configured with a layer of lanthanide oxide and a layer of hafnium oxide, where the layer of hafnium oxide is structured as one of more monolayers of hafnium oxide. In an embodiment, a dielectric layer may be arranged as a nanolaminate of hafnium oxide and a lanthanide oxide, with the layer of hafnium oxide structured as one of more monolayers of hafnium oxide.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This application is a divisional of U.S. application Ser. No. 10/931,343, filed 31 Aug. 2004, which is a divisional of U.S. application Ser. No. 10/602,323, filed 24 Jun. 2003, which applications are incorporated herein by reference in their entirety.
• This application is related to the following commonly assigned U.S. patent applications, which are herein incorporated by reference in their entirety:
• U.S. application Ser. No. 10/602,315, entitled “Lanthanide Oxide/Hafnium Oxide Dielectrics,” filed 24 Jun. 2003, now issued as U.S. Pat. No. 7,049,192;
• U.S. application Ser. No. 10/137,058, entitled: “Atomic Layer Deposition and Conversion,” filed 2 May 2002;
• U.S. application Ser. No. 10/137,168, entitled: “Methods, Systems, and Apparatus for Atomic-Layer Deposition of Aluminum Oxides in Integrated Circuits,” filed 2 May 2002; and
• U.S. application Ser. No. 09/797,324, entitled: “Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions,” filed 1 Mar. 2001, now issued as U.S. Pat. No. 6,852,167.
TECHNICAL FIELD
• This application relates generally to semiconductor devices and device fabrication and, more particularly, to dielectric layers and their method of fabrication.
BACKGROUND
• The semiconductor device industry has a market driven need to improve speed performance, improve its low static (off-state) power requirements, and adapt to a wide range of power supply and output voltage requirements for its silicon based microelectronic products. In particular, there is continuous pressure to reduce the size of devices such as transistors. The ultimate goal is to fabricate increasingly smaller and more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).
• Currently, the semiconductor industry relies on the ability to reduce or scale the dimensions of its basic devices, primarily, the silicon based metal-oxide-semiconductor field effect transistor (MOSFET). A common configuration of such a transistor is shown inFIG. 1. While the following discussion usesFIG. 1 to illustrate a transistor from the prior art, one skilled in the art will recognize that the present invention could be incorporated into the transistor shown inFIG. 1 to form a transistor according to the present invention. Atransistor100 is fabricated in asubstrate110 that is typically silicon.Transistor100 has asource region120 and adrain region130. Abody region132 is located betweensource region120 anddrain region130, wherebody region132 defines a channel of the transistor with achannel length134. A gate dielectric140 is located onbody region132 with agate150 located over gate dielectric140. Gate dielectric140 is typically an oxide, and is commonly referred to as a gate oxide. Gate150 may be fabricated from polycrystalline silicon (polysilicon), or other conducting materials such as metal may be used.
• In fabricating transistors to be smaller in size and reliably operate on lower power supplies, one design criteria is gate dielectric140. The mainstay for forming the gate dielectric has been silicon dioxide, SiO₂. A thermally grown amorphous SiO₂layer provides an electrically and thermodynamically stable material, where the interface of the SiO₂layer with underlying Si provides a high quality interface as well as superior electrical isolation properties. However, increased scaling and other requirements in microelectronic devices have created the need to use other dielectric materials as gate dielectrics.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 shows a configuration of a transistor having a gate dielectric containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to various embodiments of the present invention.
• FIG. 2A depicts an atomic layer deposition system for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide, according to various embodiments of the present invention.
• FIG. 2B depicts a gas-distribution fixture of an atomic layer deposition system for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide, according to various embodiments of the present invention.
• FIG. 3 depicts an electron beam evaporation system for processing a layer of lanthanide oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide, according to various embodiments of the present invention.
• FIG. 4 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
• FIG. 5 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
• FIG. 6 depicts an embodiment of a dielectric layer including a nanolaminate of a hafnium oxide layer and a lanthanide oxide layer, according to the present invention.
• FIG. 7 shows an embodiment of a configuration of a transistor having a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
• FIG. 8 shows an embodiment of a configuration of a capacitor having a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
• FIG. 9 is a simplified block diagram for an embodiment of a memory device with a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
• FIG. 10 illustrates a block diagram for an embodiment of an electronic system having devices with a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
DETAILED DESCRIPTION
• The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.
• The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC). The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
• The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
• In various embodiments, a dielectric layer includes a hafnium oxide layer and a lanthanide oxide layer, where the hafnium oxide layer is formed by atomic layer deposition (ALD) and the lanthanide oxide layer is formed by electron beam evaporation. The lanthanide oxide can be selected from Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃. In an embodiment, a dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate.
• The term “nanolaminate” means a composite film of ultra thin layers of two or more materials in a layered stack, where the layers are alternating layers of materials of the composite film. Typically, each layer in a nanolaminate has a thickness of an order of magnitude in the nanometer range. Further, each individual material layer of the nanolaminate can have a thickness as low as a monolayer of the material. A nanolaminate of hafnium oxide and a lanthanide oxide includes at least one thin layer of hafnium oxide, and one thin layer of the lanthanide oxide, which can be written as a nanolaminate of hafnium oxide/lanthanide oxide. Further, a hafnium oxide/lanthanide oxide nanolaminate is not limited to alternating one lanthanide layer after a hafnium oxide layer, but can include multiple thin layers of a lanthanide oxide alternating with multiple thin layers of hafnium oxide. Further, the number of thin layers of lanthanide oxide and the number of thin layers of hafnium oxide can vary independently within a nanolaminate structure. Additionally, a hafnium oxide/lanthanide oxide nanolaminate can include layers of different lanthanide oxides, where each layer is independently selected from Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃. A dielectric layer containing alternating layers of a lanthanide oxide and a hafnium oxide has an effective dielectric constant related to the series combination of the layers of lanthanide oxide and hafnium oxide, which depends on the relative thicknesses of the lanthanide oxide layers and the hafnium oxide layers. Thus, a dielectric containing a hafnium oxide/lanthanide oxide nanolaminate can be engineered to effectively provide a selected dielectric constant.
• Agate dielectric140 ofFIG. 1, when operating in a transistor, has both a physical gate dielectric thickness and an equivalent oxide thickness (t_eq). The equivalent oxide thickness quantifies the electrical properties, such as capacitance, of agate dielectric140 in terms of a representative physical thickness. The equivalent oxide thickness, t_eq, is defined as the thickness of a theoretical SiO₂layer that would have the same capacitance density as a given dielectric, ignoring leakage current and reliability considerations.
• A SiO₂layer of thickness, t, deposited on a Si surface as a gate dielectric will have a t_eqlarger than its thickness, t. This t_eqresults from the capacitance in the surface channel on which the SiO₂is deposited due to the formation of a depletion/inversion region. This depletion/inversion region may result in t_eqbeing from 3 to 6 Angstroms (Å) larger than the SiO₂thickness, t. Thus, with the semiconductor industry driving to scale the gate dielectric equivalent oxide thickness to under 10 Å, the physical thickness for a SiO₂layer used for a gate dielectric would be need to be approximately 4 to 7 Å.
• Additional characteristics for a SiO₂layer depend on the gate electrode used in conjunction with the SiO₂gate dielectric. Using a conventional polysilicon gate results in an additional increase in t_eqfor the SiO₂layer. This additional thickness could be eliminated by using a metal gate electrode, though metal gates are not currently used in typical complementary metal-oxide-semiconductor field effect transistor (CMOS) technology. Thus, future devices would be designed towards a physical SiO₂gate dielectric layer of about 5 Å or less. Such a small thickness for a SiO₂oxide layer creates additional problems.
• Silicon dioxide is used as a gate dielectric, in part, due to its electrical isolation properties in a SiO₂—Si based structure. This electrical isolation is due to the relatively large bandgap of SiO₂(8.9 eV) making it a good insulator from electrical conduction. Signification reductions in its bandgap would eliminate it as a material for a gate dielectric. As the thickness of a SiO₂layer decreases, the number of atomic layers, or monolayers of the SiO₂decreases. At a certain thickness, the number of monolayers will be sufficiently small that the SiO₂layer will not have a complete arrangement of atoms as in a larger or bulk layer. As a result of incomplete formation relative to a bulk structure, a thin SiO₂layer of only one or two monolayers will not form a full bandgap. The lack of a full bandgap in a SiO₂gate dielectric could cause an effective short between an underlying Si channel and an overlying polysilicon gate. This undesirable property sets a limit on the physical thickness to which a SiO₂layer may be scaled. The minimum thickness due to this monolayer effect is thought to be about 7-8 Å. Therefore, for future devices to have a t_eqless than about 10 Å, dielectrics other than SiO₂need to be considered for use as a gate dielectric.
• For a typical dielectric layer used as a gate dielectric, the capacitance is determined as one for a parallel plate capacitance: C=κε₀A/t, where κ is the dielectric constant, ε₀is the permittivity of free space, A is the area of the capacitor, and t is the thickness of the dielectric. The thickness, t, of a material is related to its t_eqfor a given capacitance, with SiO₂having a dielectric constant κ₀=3.9, as
  t=(κ/κ_ox)t_eq=(κ/3.9)t_eq.
  Thus, materials with a dielectric constant greater than that of SiO₂, 3.9, will have a physical thickness that may be considerably larger than a desired t_eq, while providing the desired equivalent oxide thickness. For example, an alternate dielectric material with a dielectric constant of 10 could have a thickness of about 25.6 Å to provide a t_eqof 10 Å, not including any depletion/inversion layer effects. Thus, a reduced t_eqfor transistors may be realized by using dielectric materials with higher dielectric constants than SiO₂. The thinner t_eqfor lower transistor operating voltages and smaller transistor dimensions may be realized by a significant number of materials, but additional fabricating characteristics makes determining a suitable replacement for SiO₂difficult.
• The current view for the microelectronics industry is still for Si based devices. Thus, the gate dielectric employed will grow on a silicon substrate or silicon layer, which places significant restraints on the substitute dielectric material. During the formation of the dielectric on the silicon layer, there exists the possibility that a small layer of SiO₂could be formed in addition to the desired dielectric. The result would effectively be a dielectric layer consisting of two sublayers in parallel with each other and the silicon layer on which the dielectric is formed. In such a case, the resulting capacitance would be that of two dielectrics in series. As a result, the t_eqof the dielectric layer would be the sum of the SiO₂thickness and a multiplicative factor of the thickness of the dielectric being formed, written as
  t_eq=t_SiO2+(κ_ox/κ)t.
  Thus, if a SiO₂layer is formed in the process, the t_eqis again limited by a SiO₂layer. Thus, use of an ultra-thin silicon dioxide interface layer should be limited to significantly less than ten angstroms. In the event that a barrier layer is formed between the silicon layer and the desired dielectric in which the barrier layer prevents the formation of a SiO₂layer, the t_eqwould be limited by the layer with the lowest dielectric constant. However, whether a single dielectric layer with a high dielectric constant or a barrier layer with a higher dielectric constant than SiO₂is employed, the layer interfacing with the silicon layer must provide a high quality interface to maintain a high channel carrier mobility.
• One of the advantages for using SiO₂as a gate dielectric has been that the formation of the SiO₂layer results in an amorphous gate dielectric. Having an amorphous structure for a gate dielectric is advantageous because grain boundaries in polycrystalline gate dielectrics provide high leakage paths. Additionally, grain size and orientation changes throughout a polycrystalline gate dielectric may cause variations in the layer's dielectric constant. Many materials having a high dielectric constant relative to SiO₂also have a disadvantage of a crystalline form, at least in a bulk configuration. Thus, the best candidates for replacing SiO₂as a gate dielectric are those with high dielectric constant, a relatively large bandgap, and are able to be fabricated as a thin layer with an amorphous form.
• Materials such as Ta₂O₃, TiO₂, A₂O₃, HfO₂, HfSi_xO_y, HfSi_xO_y, and barium strontium titanate (BST) have been proposed as replacements for SiO₂as gate dielectric materials. Additional materials have been proposed to not only provide a material layer with a dielectric constant greater than silicon dioxide, but also to provide adjustment to the insulating properties of the material. Such materials can be provided as nanolaminates, for example, Ta₂O₅/HfO₂, ZrO₂/HfO₂, Ta₂O₅/HfO₂nanolaminates. Providing dielectric layers configured as nanolaminates can provide a dielectric layer with relatively low leakage current properties.
• An embodiment for a method for forming a dielectric layer containing a hafnium oxide and a lanthanide oxide includes forming a layer of the hafnium oxide by atomic layer deposition and forming a layer of the lanthanide oxide by electron beam evaporation. The layer of hafnium oxide is adjacent to and in contact with the layer of lanthanide oxide. In an embodiment, a dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate having an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer.
• Dielectric layers containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer have a larger dielectric constant than silicon dioxide. Such dielectric layers provide a significantly thinner equivalent oxide thickness compared with a silicon oxide layer having the same physical thickness. Alternately, such dielectric layers provide a significantly thicker physical thickness than a silicon oxide layer having the same equivalent oxide thickness. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, and methods for forming such structures.
• In an embodiment of the present invention, a dielectric film having an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide allows for the engineering of a dielectric layer with a dielectric constant significantly higher than that of silicon dioxide and a relatively low leakage current characteristic. Using layers of atomic layer deposited HfO₂in various embodiments, provides layers, as compared to ZrO₂, that have a stronger tendency to form a single phase structure, a higher refractive index when deposited at low temperatures, a larger band gap, higher band offsets on silicon, and better thermal stability against silicide formation. Additionally, amorphous lanthanide oxides provide high oxide capacitance, low leakage current, and high thermal stability. Other considerations for selecting the material and method for forming a dielectric layer for use in electronic devices and systems concern the suitability of the material for applications requiring a dielectric layer to have an ultra-thin equivalent oxide thickness, form conformally on a substrate, and/or be engineered to specific thickness and elemental concentrations.
• Another consideration concerns the roughness of the dielectric layer on a substrate. Surface roughness of the dielectric layer has a significant effect on the electrical properties of the gate oxide, and the resulting operating characteristics of the transistor. Leakage current through a physical 1.0 nanometer gate oxide has been found to be increased by a factor of 10 for every 0.1 increase in the root-mean-square (RMS) roughness.
• During a conventional sputtering deposition process stage, particles of the material to be deposited bombard the surface at a high energy. When a particle hits the surface, some particles adhere, and other particles cause damage. High-energy impacts remove body region particles creating pits. The surface of such a deposited layer may have a rough contour due to the rough interface at the body region.
• In an embodiment, a hafnium oxide layer having a substantially smooth surface relative to other processing techniques is formed on a substrate using atomic layer deposition. Further, the ALD deposited hafnium oxide layer provides a conformal coverage on the substrate surface on which it is deposited. A lanthanide oxide layer is then formed on the hafnium oxide layer, where the lanthanide oxide layer is formed by electron beam evaporation.
• ALD, also known as atomic layer epitaxy (ALE), was developed in the early 1970's as a modification of chemical vapor deposition (CVD) and is also called “alternatively pulsed-CVD.” In ALD, gaseous precursors are introduced one at a time to the substrate surface mounted within a reaction chamber (or reactor). This introduction of the gaseous precursors takes the form of pulses of each gaseous precursor. Between the pulses, the reaction chamber is purged with a gas, which in many cases is an inert gas, and/or evacuated.
• In a chemisorption-saturated ALD (CS-ALD) process, during the first pulsing phase, reaction with the substrate occurs with the precursor saturatively chemisorbed at the substrate surface. Subsequent pulsing with a purging gas removes precursor excess from the reaction chamber.
• The second pulsing phase introduces another precursor on the substrate where the growth reaction of the desired layer takes place. Subsequent to the layer growth reaction, reaction by-products and precursor excess are purged from the reaction chamber. With favourable precursor chemistry where the precursors adsorb and react with each other on the substrate aggressively, one ALD cycle may be performed in less than one second in properly designed flow type reaction chambers. Typically, precursor pulse times range from about 0.5 sec to about 2 to 3 seconds.
• In ALD, the saturation of all the reaction and purging phases makes the growth self-limiting. This self-limiting growth results in large area uniformity and conformality, which has important applications for such cases as planar substrates, deep trenches, and in the processing of porous silicon and high surface area silica and alumina powders. Thus, ALD provides for controlling layer thickness in a straightforward manner by controlling the number of growth cycles.
• ALD was originally developed to manufacture luminescent and dielectric layers needed in electroluminescent displays. Significant efforts have been made to apply ALD to the growth of doped zinc sulfide and alkaline earth metal sulfide layers. Additionally, ALD has been studied for the growth of different epitaxial II-V and II-VI layers, nonepitaxial crystalline or amorphous oxide and nitride layers and multilayer structures of these. There also has been considerable interest towards the ALD growth of silicon and germanium layers, but due to the difficult precursor chemistry, this has not been very successful.
• The precursors used in an ALD process may be gaseous, liquid or solid. However, liquid or solid precursors must be volatile. The vapor pressure must be high enough for effective mass transportation. Also, solid and some liquid precursors need to be heated inside the reaction chamber and introduced through heated tubes to the substrates. The necessary vapor pressure must be reached at a temperature below the substrate temperature to avoid the condensation of the precursors on the substrate. Due to the self-limiting growth mechanisms of ALD, relatively low vapor pressure solid precursors may be used though evaporation rates may somewhat vary during the process because of changes in their surface area.
• There are several other characteristics for precursors used in ALD. The precursors must be thermally stable at the substrate temperature because their decomposition would destroy the surface control and accordingly the advantages of the ALD method that relies on the reaction of the precursor at the substrate surface. A slight decomposition, if slow compared to the ALD growth, may be tolerated.
• The precursors have to chemisorb on or react with the surface, though the interaction between the precursor and the surface as well as the mechanism for the adsorption is different for different precursors. The molecules at the substrate surface must react aggressively with the second precursor to form the desired solid layer. Additionally, precursors should not react with the layer to cause etching, and precursors should not dissolve in the layer. Using highly reactive precursors in ALD contrasts with the selection of precursors for conventional CVD.
• The by-products in the reaction must be gaseous in order to allow their easy removal from the reaction chamber. Further, the by-products should not react or adsorb on the surface.
• In a reaction sequence ALD (RS-ALD) process, the self-limiting process sequence involves sequential surface chemical reactions. RS-ALD relies on chemistry between a reactive surface and a reactive molecular precursor. In an RS-ALD process, molecular precursors are pulsed into the ALD reaction chamber separately. The metal precursor reaction at the substrate is typically followed by an inert gas pulse to remove excess precursor and by-products from the reaction chamber prior to pulsing the next precursor of the fabrication sequence.
• By RS-ALD, layers can be layered in equal metered sequences that are all identical in chemical kinetics, deposition per cycle, composition, and thickness. RS-ALD sequences generally deposit less than a full layer per cycle. Typically, a deposition or growth rate of about 0.25 to about 2.00 Å per RS-ALD cycle may be realized.
• The characteristics of RS-ALD include continuity at an interface, conformality over a substrate, use of low temperature and mildly oxidizing processes, freedom from first wafer effects and chamber dependence, growth thickness dependent solely on the number of cycles performed, and ability to engineer multilayer laminate layers with resolution of one to two monolayers. RS-ALD allows for deposition control on the order on monolayers and the ability to deposit monolayers of amorphous layers.
• Herein, a sequence refers to the ALD material formation based on an ALD reaction of a precursor or a precursor with its reactant precursor. For example, forming a metal layer from a precursor containing the metal forms an embodiment of a metal sequence. Additionally, forming a layer of metal oxide from a precursor containing the metal and from an oxygen containing precursor as its reactant precursor forms an embodiment of a metal/oxygen sequence, which may be referred to as the metal oxide sequence. A cycle of a metal sequence includes pulsing a precursor containing the metal and pulsing a purging gas for the precursor. Further, a cycle of a metal oxide sequence includes pulsing a precursor containing the metal, pulsing a purging gas for the precursor, pulsing a reactant precursor, and pulsing a purging gas for the reactant precursor. Additionally, a cycle for a compound metal oxide includes pulsing a precursor containing a first metal, pulsing a purging gas for this precursor, pulsing a reactant precursor for the first metal precursor, pulsing a purging gas for the reactant precursor, pulsing a precursor containing a second metal, pulsing a purging gas for this precursor, pulsing a reactant precursor for the second metal precursor, and pulsing a purging gas for this reactant precursor. The order of the metal precursors can depend on the tendency of the metals to allow diffusion of atoms through the metal to the underlying substrate. The order employed can limit the amount of unwanted atomic diffusion to the substrate surface.
• In an embodiment, a hafnium oxide layer is formed on a substrate mounted in a reaction chamber by ALD using precursor gases individually pulsed into the reaction chamber. Alternately, solid or liquid precursors may be used in an appropriately designed reaction chamber.
• FIG. 2A depicts an embodiment of an atomiclayer deposition system200 for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide. The elements depicted are those elements necessary for discussion of embodiments of the present invention such that those skilled in the art may practice various embodiments of the present invention without undue experimentation. A further discussion of the ALD reaction chamber can be found in co-pending, commonly assigned U.S. patent application: entitled “Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions,” Ser. No. 09/797,324, filed 1 Mar. 2001, incorporated herein by reference.
• InFIG. 2A, asubstrate210 is located inside areaction chamber220 ofALD system200. Also located withinreaction chamber220 is aheating element230, which is thermally coupled tosubstrate210 to control the substrate temperature. A gas-distribution fixture240 introduces precursor gases to thesubstrate210. Each precursor gas originates from individual gas sources251-254 whose flow is controlled by mass-flow controllers256-259, respectively. Each gas source,251-254, provides a precursor gas either by storing the precursor as a gas or by providing a location and apparatus for evaporating a solid or liquid material to form the selected precursor gas. Furthermore, additional gas sources may be included, one for each metal precursor employed and one for each reactant precursor associated with each metal precursor.
• Also included in the ALD system are purginggas sources261,262, each of which is coupled to mass-flow controllers266,267, respectively. Furthermore, additional purging gas sources may be constructed inALD system200, one purging gas source for each precursor gas. For a process that uses the same purging gas for multiple precursor gases less purging gas sources are used inALD system200.
• Gas sources251-254 and purging gas sources261-262 are coupled by their associated mass-flow controllers to a common gas line orconduit270, which is coupled to the gas-distribution fixture240 insidereaction chamber220.Gas conduit270 is also coupled to vacuum pump, or exhaust pump,281 by mass-flow controller286 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence fromgas conduit270.
• Vacuum pump, or exhaust pump,282 is coupled by mass-flow controller287 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence fromreaction chamber220. For convenience, control displays, mounting apparatus, temperature sensing devices, substrate maneuvering apparatus, and necessary electrical connections as are known to those skilled in the art are not shown inFIG. 2A.
• FIG. 2B depicts an embodiment of a gas-distribution fixture240 of atomiclayer deposition system200 for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide. Gas-distribution fixture240 includes a gas-distribution member242, and agas inlet244.Gas inlet244 couples gas-distribution member242 togas conduit270 ofFIG. 2A. Gas-distribution member242 includes gas-distribution holes, or orifices,246 and gas-distribution channels248. In the illustrated embodiment, holes246 are substantially circular with a common diameter in the range of 15-20 microns, gas-distribution channels248 have a common width in the range of 20-45 microns. Thesurface249 ofgas distribution member242 having gas-distribution holes246 is substantially planar and parallel tosubstrate210 ofFIG. 2A. However, other embodiments use other surface forms as well as shapes and sizes of holes and channels. The distribution and size of holes may also affect deposition thickness and thus might be used to assist thickness control.Holes246 are coupled through gas-distribution channels248 togas inlet244. ThoughALD system200 is well suited for practicing embodiments of the present invention, other ALD systems commercially available may be used.
• Those of ordinary skill in the art of semiconductor fabrication understand the use, construction and fundamental operation of reaction chambers for deposition of material layers. Embodiments of the present invention may be practiced on a variety of such reaction chambers without undue experimentation. Furthermore, one of ordinary skill in the art will comprehend the necessary detection, measurement, and control techniques in the art of semiconductor fabrication upon reading and studying this disclosure.
• The elements ofALD system200 may be controlled by a computer. To focus on the use ofALD system200 in the various embodiments of the present invention, the computer is not shown. Those skilled in the art can appreciate that the individual elements such as pressure control, temperature control, and gas flow withinALD system200 may be under computer control. In an embodiment, a computer executes instructions stored in a computer readable medium to accurately control the integrated functioning of the elements ofALD system200 to form a hafnium oxide layer for a dielectric layer containing a hafnium oxide layer and a lanthanide oxide layer. In an embodiment, following the ALD formation of a hafnium oxide layer, a layer of a lanthanide oxide is formed by electron beam evaporation.
• FIG. 3 depicts an electronbeam evaporation system300 for processing a layer of lanthanide oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide.Evaporation system300 includes areaction chamber305 in which is located asubstrate310 having asurface312 that is to be processed.Substrate310 rests onsubstrate holder315 and its temperature can be raised above room temperature using aheater320 with its associatedreflector325.Evaporation system300 also includes anelectron gun device330 regulated byelectron gun controller335 for depositing material onsubstrate surface312.
• Material evaporated usingelectron gun device330 travels tosubstrate310 through anionizer ring345 andshutter350.Ionizer ring345 provides supplemental oxygen for processes that require additional oxygen due to lost of oxygen in the evaporation of target materials. For target materials substantially void of oxygen,ionizer ring345 provides initial oxygen to a film deposited onsubstrate surface312 that is to undergo a subsequent oxidation process.Shutter350 is used in conjunction with the control ofelectron gun device330 to control the growth rate of a film onsubstrate310. The growth rate is determined using quartz crystal monitors355,360. The quartz crystal monitors355,360 are coupled to a thickness/rate control365, typically located outsidereaction chamber305.
• Also located outsidereaction chamber305 is anoxygen gas source370 including a mass-flow controller375. In an embodiment, the oxygen gas source is ozone gas. Mass-flow controller375 controls the flow of the oxygen source intoreaction chamber305. Further, avacuum pump380 withmass flow controller385 maintains the overall atmosphere ofevaporation system300 at desired levels prior to, during, and after evaporation.
• Electron gun device330 can include an electron gun and receptacle for a target material that is to be evaporated. Target material placed in the target receptacle ofelectron gun device330 is heated by impact from an electron beam from its associated electron gun. The electron beam is generated with an intensity and duration with which to evaporate the material in the target receptacle ofelectron gun device330. The evaporated material then distributes throughout thereaction chamber305. The evaporated material and pre-evaporation contaminants are prevented from depositing onsubstrate surface312 in an unwanted manner byshutter350. Further, electron gun device can be realized using commercially available devices as are known to those skilled in the art.
• Ionizer ring345 provides oxygen necessary to compensate for loss of oxygen in the evaporated target material, or to add initial oxygen for subsequent oxidation processing. In one embodiment, it includes a ring with a center axis. The ring has a plurality of openings adapted to direct oxygen flowing toionizer ring345 fromoxygen gas source370 towardssubstrate surface312. Oxygen is uniformly distributed tosubstrate surface312 byionizer ring345 positioned generally parallel tosubstrate310.
• Theevaporation chamber300 can be included as part of an overall processing system includingALD system200 ofFIG. 2A, 2B. To avoid contamination of the surface of a layer formed by atomic layer deposition,evaporation chamber300 can be connected toALD system200 using sealable connections to maintain the substrate, which issubstrate210 inFIG. 2 andsubstrate310 ofFIG. 3, in an appropriate environment between ALD processing of a hafnium oxide layer and electron beam evaporation of a lanthanide oxide layer. Other means as are known to those skilled in the art can be employed for maintaining an appropriate environment between different processing procedures.
• FIG. 4 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer. This embodiment includes forming a layer of hafnium oxide by atomic layer deposition, atblock410, and forming a layer of a lanthanide oxide by electron beam evaporation, atblock420, where the layer of hafnium oxide is adjacent to and in contact with the lanthanide oxide layer. The lanthanide oxide can be selected from Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃. In an embodiment the method includes forming the layer of hafnium oxide on a substrate and forming the layer of lanthanide oxide on the layer of hafnium oxide. Alternately, a layer of lanthanide oxide is formed on a substrate and a layer of hafnium oxide is formed on the layer of lanthanide oxide. In an embodiment, the method includes controlling the forming of the layer of hafnium oxide and the layer of the lanthanide oxide to form a lanthanide oxide/hafnium oxide nanolaminate. The nanolaminate may have multiple layers of different lanthanide oxides selected from Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃. For a dielectric layer having a hafnium oxide layer and one or more layers of a lanthanide oxide, the combined thickness of lanthanide oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. Also, for a dielectric layer having a lanthanide oxide layer and one or more layers of hafnium oxide, the combined thickness of hafnium oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. In an embodiment, hafnium oxide layers are limited to between 2 nanometers and 5 nanometers. In an embodiment, a dielectric layer includes a hafnium oxide layer and multiple layers of lanthanide oxide, where each layer of lanthanide oxide is limited to a thickness between about 2 nanometers and about 10 nanometers.
• Performing each atomic layer deposition includes pulsing one or more precursors into a reaction chamber for a predetermined period. The predetermined period is individually controlled for each precursor pulsed into the reaction chamber. Further the substrate is maintained at a selected temperature for each pulsing of a precursor, where the selected temperature is set independently for pulsing each precursor. Additionally, each precursor may be pulsed into the reaction under separate environmental conditions. Appropriate temperatures and pressures are maintained dependent on the nature of the precursor, whether the precursor is a single precursor or a mixture of precursors.
• Using atomic layer deposition, the pulsing of the precursor gases is separated by purging the reaction chamber with a purging gas following each pulsing of a precursor. In an embodiment, nitrogen gas is used as the purging gas following the pulsing of each precursor used in a cycle to form a hafnium oxide layer. Additionally, the reaction chamber may also be purged by evacuating the reaction chamber.
• FIG. 5 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer. In an embodiment, the method depicted inFIG. 5 can be used to form a gate dielectric layer for a transistor. This embodiment may be implemented with the atomiclayer deposition system200 ofFIG. 2A, B, and the electron beam evaporation system ofFIG. 3.
• Atblock505,substrate210 is prepared.Substrate210 used for forming a transistor is typically a silicon or silicon containing material. In other embodiments, germanium, gallium arsenide, silicon-on-sapphire substrates, or other suitable substrates may be used. This preparation process may include cleaning ofsubstrate210 and forming layers and regions of the substrate, such as drains and sources of a metal oxide semiconductor (MOS) transistor, prior to forming a gate dielectric. In an embodiment, the substrate is cleaned to provide an initial substrate depleted of its native oxide. In an embodiment, the initial substrate is cleaned to provide a hydrogen-terminated surface. In an embodiment, a silicon substrate undergoes a final hydrofluoric acid, HF, rinse prior to ALD processing to provide the silicon substrate with a hydrogen-terminated surface without a native silicon oxide layer.
• In an embodiment,substrate210 is prepared as a chemical oxide-terminated silicon surface prior to forming a hafnium oxide by atomic layer deposition. This preparation allows for forming an interface layer to provide a structure that may further aid in reducing the leakage current through the dielectric layer.
• The sequencing of the formation of the regions of the transistor being processed follows typical sequencing that is generally performed in the fabrication of a MOS transistor as is well known to those skilled in the art. Included in the processing is the masking of substrate regions to be protected during the gate dielectric formation, as is typically performed in MOS fabrication. In this embodiment, the unmasked region may include a body region of a transistor; however one skilled in the art will recognize that other semiconductor device structures may utilize this process. Additionally,substrate210 in its ready for processing form is conveyed into a position inreaction chamber220 for ALD processing.
• Atblock510, a hafnium-containing precursor is pulsed intoreaction chamber220. In an embodiment, HfI₄is used as a precursor. In other embodiments, a hafnium-containing precursor includes but is not limited to HfCl₄, and Hf(NO₃)₄. The HfI₄precursor is pulsed intoreaction chamber220 through the gas-distribution fixture240 tosubstrate210. Mass-flow controller256 regulates the flow of the HfI₄fromgas source251, where the HfI₄gas is held at a temperature ranging from about 185° C. to about 195° C. In an embodiment, the substrate temperature is maintained between about 500° C. and about 750° C. In an embodiment, the substrate temperature is maintained at about 300° C. In other embodiments, the substrate may be held at lower temperatures lower than 300° C. The HfI₄reacts with the surface of thesubstrate210 in the desired region defined by the unmasked areas of thesubstrate210.
• Atblock515, a first purging gas is pulsed intoreaction chamber220. In an embodiment, nitrogen with a purity of about 99.999% is used as a purging gas. Mass-flow controller266 regulates the nitrogen flow from the purginggas source261 into thegas conduit270. Using the pure nitrogen purge avoids overlap of the precursor pulses and possible gas phase reactions.
• A first oxygen-containing precursor is pulsed ontosubstrate210, atblock520. In an embodiment, molecular oxygen is used as a precursor. In other embodiments, an oxygen-containing precursor for a hafnium/oxygen sequence includes but is not limited to H₂O, H₂O₂, an H₂O—H₂O₂mixture, alcohol (ROH), N₂O, or O₃. The molecular oxygen precursor is pulsed intoreaction chamber220 through the gas-distribution fixture240 onsubstrate210. Mass-flow controller257 regulates the flow of the water vapor fromgas source252. In an embodiment, the substrate temperature is maintained between about 100° C. and about 150° C. The water vapor reacts with at the surface ofsubstrate210 in the desired region defined by the unmasked areas of thesubstrate210.
• After pulsing the first oxygen-containing precursor, a second purging gas is pulsed, at block,525. In an embodiment, nitrogen is used as the second purging gas. Excess precursor gas and reaction by-products are removed from the system by the purge gas in conjunction with the exhausting ofreaction chamber220 usingvacuum pump282 through mass-flow controller287, and exhausting of thegas conduit270 by thevacuum pump281 through mass-flow controller286. With the conclusion of the second purging gas pulse, a cycle. for forming an atomic layer deposited hafnium oxide is completed.
• In an embodiment using a HfI₄/O₂sequence, the substrate may be held between about 500° C. and about 750° C. by theheating element230. In an embodiment, the substrate may be held at 300° C. In other embodiments, the substrate may be held at lower temperatures lower than 300° C. The HfI₄precursor can be pulsed for about 2.0 s. After the HfI₄pulse, the hafnium/O₂sequence continues with a purge pulse followed by a O₂pulse followed by a purge pulse. In an embodiment, the O₂pulse time is about 2.0 sec, and the two nitrogen purging pulse times are each at about 2.0 sec.
• Atblock530, a determination is made as to whether a desired number of cycles has been performed, that is, whether the number of completed cycles is equal to a predetermined number. The predetermined number corresponds to a predetermined thickness for the ALD hafnium oxide layer. The thickness of the hafnium oxide layer is determined by a fixed growth rate for the pulsing periods and precursors used, set at a value such as N nm/cycle. In an embodiment, a hafnium oxide layer may be grown at a rate ranging from about 0.07 nm/cycle to about 0.12 nm/cycle for an oxygen pressure ranging from about 0.1 Torr to about 0.3 Torr. For a desired dielectric layer thickness, t, the ALD process is repeated for t/N total cycles. Once the t/N cycles have completed, no further ALD processing for the current hafnium oxide layer is performed.
• If the number of completed cycles is less than the predetermined number, the hafnium-containing precursor is pulsed intoreaction chamber220, atblock510, and the process continues. If the total number of cycles to form the desired thickness for the hafnium oxide layer has been completed, a determination is made as to whether the dielectric layer being formed contains the desired number of layers of a lanthanide oxide, atblock535. If the desired number of layers of a lanthanide oxide have been made, a determination is made as to whether the desired number of layers of hafnium oxide have been processed, atblock545. Such a case may occur in embodiments for a dielectric layer having hafnium oxide formed as consecutive layers on a lanthanide oxide layer. If more layers of hafnium oxide are required for the given application, the overall process continues as an atomic layer deposition with the pulsing of a hafnium-containing precursor, atblock510.
• If it is determined, atblock535, that the desired number of layers of a lanthanide oxide have not been formed, then a layer of lanthanide oxide is formed onsubstrate210, atblock540, which may include hafnium oxide layers and other lanthanide oxide layers.Substrate210 in the ALD system, as illustrated inFIG. 2, is moved into the evaporation system depicted inFIG. 3, where thesubstrate210, with its formed layers, becomessubstrate310 ofFIG. 3. To avoid contamination of the surface of a layer formed by atomic layer deposition,evaporation chamber300 can be connected toALD system200 using sealable connections to maintain the substrate in an appropriate environment between ALD processing of a hafnium oxide layer and electron beam evaporation of a lanthanide oxide layer. Other means as are known to those skilled in the art can be employed for maintaining an appropriate environment between different processing procedures.
• Substrate310, suitably masked for the given application and process procedures, is moved intoevaporation chamber305.Electron gun330 contains a receptacle for a source target on which an electron beam is directed.Electron gun controller335 regulates the rate of evaporation of material from the target source. Alternatively,evaporation chamber305 can include multiple electron guns, where each electron gun is directed to different targets containing sources to form selected lanthanide oxides to be used at different times in the process.
• In an embodiment, the target source ofelectron gun330 contains a ceramic Pr₆O₁₁source, which is evaporated due to the impact of the electron beam. The evaporated material is then distributed throughout thechamber305. A dielectric layer of Pr₂O₃is grown onsurface312 ofsubstrate310, which is maintained at a temperature ranging from about 100° C. to about 150° C. The growth rate can vary with a typical rate of 0.1 Å/s. In an embodiment in which a lanthanide is first formed on a substrate prior to forming a hafnium oxide layer, a Pr₂O₃layer may include a thin amorphous interfacial layer separating a crystalline layer of Pr₂O₃from the substrate on which it is grown. This thin amorphous layer may be beneficial in reducing the number of interface charges and eliminating any grain boundary paths for conductance from the substrate. Other source materials can be used for forming a Pr₂O₃layer, as are known to those skilled in the art.
• Alternately, the lanthanide oxide layer formed by electron beam evaporation for a dielectric layer containing an atomic layer deposited hafnium oxide and a lanthanide oxide can be an oxide selected from Nd₂O₃, Sm₂O₃, Gd₂O₃, or Dy₂O₃. Further, a dielectric layer may include a number of hafnium oxide layers and a number of lanthanide oxide layers, where the lanthanide oxide layers are different lanthanide oxides. The different lanthanide oxides can be selected from Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃. The source material for the particular lanthanide oxide is chosen from commercial materials for forming the lanthanide oxide by electron bean evaporation, as is known by those skilled in the art.
• After forming the layer of lanthanide oxide, atblock540, a determination is made as to whether the desired number of hafnium oxide layers has been formed, atblock545. If the desired number of hafnium oxide layers has not been formed,substrate310 is moved back into atomiclayer deposition system200 and a hafnium-containing precursor is pulsed, atblock510 and the process continues. If it is determined that the desired number of hafnium oxide layers have been formed, atblock545, it is then determined whether the desired number of layers of a lanthanide oxide have been formed, atblock550. If the desired number of lanthanide oxide layers has not been formed, a layer of lanthanide oxide is formed by electron beam evaporation, atblock540, and the process continues. If is determined that the desired number of lanthanide oxide layers have been formed, atblock550, and if the desired number of hafnium oxide layers have been formed, then the substrate is further processed to complete device processing, atblock555.
• If the dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide has been formed to have the desired thickness, the growth of the dielectric layer is complete. The dielectric layer may be annealed. To avoid the diffusion of oxygen during annealing to the semiconductor substrate surface, annealing may be performed in an oxygen-free environment for short periods of time. An embodiment of an annealing environment may include a nitrogen atmosphere. In addition to limiting or avoiding oxygen diffusion to the semiconductor substrate, the relatively low processing temperatures employed by atomic layer deposition of the hafnium oxide layers and by electron beam evaporation of the lanthanide layers allows for the formation of an amorphous dielectric layer.
• Atblock555, after forming the dielectric film containing atomic layer deposited hafnium oxide and electron beam deposited lanthanide oxide, processing the device having this dielectric layer is completed. In an embodiment, completing the device includes completing the formation of a transistor. In an embodiment, completing the device includes completing the formation of a capacitor. In an embodiment, completing the process includes completing the construction of a memory device having an array with access transistors formed with gate dielectrics containing atomic layer deposited hafnium oxide and electron beam deposited lanthanide oxide. In an embodiment, completing the process includes the formation of an electronic system including an information handling device that uses electronic devices with transistors formed with dielectric layers having an atomic layer deposited hafnium oxide and an electron beam deposited lanthanide oxide.
• Upon reading and comprehending this disclosure, it can be appreciated by those skilled in the art that the elements of a method for forming a dielectric layer containing atomic layer deposited hafnium oxide and electron beam deposited lanthanide oxide in the embodiment ofFIG. 5 may be performed under various environmental conditions, including various pressures and temperatures, and pulse periods depending on the dielectric layer to be formed for a given application and the systems used to fabricate such a dielectric layer. Determination of the environmental conditions, precursors used, purging gases employed, pulse periods for the precursors and purging gases, and electron beam target materials may be made without undue experimentation.
• The elements for a method for forming a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam deposited lanthanide oxide as illustrated inFIG. 5 can vary and include numerous permutations. In an embodiment, an atomic layer deposited hafnium oxide layer is formed on a substrate and an electron beam evaporated lanthanide oxide layer is formed on the hafnium oxide layer. Alternately, an electron beam evaporated lanthanide oxide layer is formed on a substrate and an atomic layer deposited hafnium oxide layer is deposited on the lanthanide oxide layer. A hafnium oxide layer may be formed as multiple layers of atomic layer deposited hafnium oxide. Similarly, a lanthanide oxide layer may be formed as multiple layers of an electron beam evaporated lanthanide oxide. Additionally, a dielectric layer may contain multiple layers of lanthanide oxide, where two or more layers contain different lanthanide oxides selected from Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃.
• In an embodiment, a dielectric containing hafnium oxide and lanthanide oxide is formed as a nanolaminate. The nanolaminate may have multiple layers of different lanthanide oxides selected from Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃. For a dielectric layer having a hafnium oxide layer and one or more layers of a lanthanide oxide, the combined thickness of lanthanide oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. Also, for a dielectric layer having a lanthanide oxide layer and one or more layers of hafnium oxide, the combined thickness of hafnium oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. In an embodiment, hafnium oxide layers are limited to between 2 nanometers and 5 nanometers. In an embodiment, a dielectric layer includes a hafnium oxide layer and multiple layers of lanthanide oxide, where each layer of lanthanide oxide is limited to a thickness between about 2 nanometers and about 10 nanometers. In an embodiment, a dielectric layer includes a lanthanide oxide layer and multiple layers of hafnium oxide, where each layer of hafnium oxide is limited to a thickness between about 2 nanometers and about 10 nanometers. In an embodiment, a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electron beam evaporated lanthanide oxide layer has a thickness ranging from about 2 nanometers to about 20 nanometers.
• A dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam deposited lanthanide oxide may be processed in an atomic layer deposition system such asALD system200 andevaporation system300 under computer control to perform various embodiments, and operated under computer-executable instructions to perform these embodiments. Instructions stored in a computer readable medium are executed by a computer to accurately control the integrated functioning of the elements of atomiclayer deposition system200 andevaporation system300 to form a dielectric layer containing hafnium oxide and a lanthanide oxide, according to various embodiments. The computer-executable instructions may be provided in any computer-readable medium. Such computer-readable medium may include, but is not limited to, floppy disks, diskettes, hard disks, CD-ROMS, flash ROMS, nonvolatile ROM, and RAM.
• Dielectric layers containing hafnium oxide layers and lanthanide oxide layers can have a wide range of dielectric constants determined by the series configuration and relative thickness of the hafnium oxide layers and the lanthanide oxide layers. In bulk form, HfO₂has a dielectric constant of about 25. Bulk Pr₂O₃has a dielectric constant of about 31, while the dielectric constants for Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃, in bulk form, are generally also in the range of 25-30. Consequently, a dielectric layer containing bulk layers of hafnium oxide and lanthanide oxide could be expected to have a dielectric constant engineered in the range from about 25 to about 31. Such a dielectric layer would have a t_eqthat is about one-sixth to one-eight smaller than a silicon oxide layer of the same thickness.
• However, a thin dielectric layer with an interfacial layer formed between the surface of the substrate and the first layer of a hafnium oxide or a lanthanide oxide will have a t_eqthat is based on an interfacial layer physically in parallel with the dielectric layer equivalently forming a series configuration of electrical structures. Thus, the dielectric layer formed having an interfacial layer between it and the substrate on which it is grown can have an effective dielectric constant considerably less than a dielectric constant associated with the combination of hafnium oxide and lanthanide oxide layers.
• Effective dielectric constants associated with thin layers of Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃oxides on silicon have been reported to have dielectric constants in the range of 11 to 15 with interfacial regions having a thickness in the of about 0.5 nm to about 1.1 nm. See J. Sanghun et al.,Technical Digest of International Electron Devices Meetings2001, pp. 471-474 (2001). Similarly, HfO₂also has been reported to have an effective dielectric constant reduced from its bulk value to a value in the range of 12 to 16 when formed as a thin layer on a silicon substrate with an interfacial layer. See K. Kukli et al.,Journal of Applied Physics,vol. 92: no. 10, pp. 5698-5703 (2002). The effective dielectric constants for thin dielectric layers containing any of these materials and/or combinations of these materials may be reduced from their bulk value depending on the thickness and material composition of any interfacial layer that may be formed.
• Further, for those cases in which a dielectric layer containing hafnium oxide and lanthanide oxide is formed with little or no interfacial layer, the dielectric layer may be subject to a thin film effect related to the abrupt termination of the film. A planar bulk or thick film can be considered as a bulk region with two surface regions. Due to the termination of the thick film, the properties of the two surface regions can vary from that of the bulk region. In a thick film, the effective properties of the film are dominated by the bulk region. In a thin film, including nanolaminates, the properties of the thin film are effectively controlled by two surface regions. See K. Natori et al.,Applied Physics Letters,vol. 73: no. 5, pp. 632-634 (1998). Thus, thin films of hafnium oxide and lanthanide oxide may have effective dielectric constants reduced from their bulk values without being formed in a structure with interfacial regions. Without a size effect, dielectric layers containing hafnium oxide and lanthanide oxide may have a dielectric constant in the range of about 25 to about 31. With a size effect, dielectric layers containing hafnium oxide and lanthanide oxide may have dielectric constants in the range from about 11 to about 16.
• The embodiments described herein provide a process for growing a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide having a wide range of useful equivalent oxide thickness, t_eq. The relatively large dielectric constant for such a dielectric layer ranges from about 11 to about 31, depending on the presence of an interfacial layer and/or on a size effect. Forming a dielectric layer according to various embodiments with a thickness ranging from 2 nanometers to 20 nanometers allows for the engineering of dielectric layers achieving a t_eqin the range of about 0.7 nanometers to about 7 nanometers. Without an interfacial layer and without a size effect, the t_eqfor such a dielectric layer may range from about 0.25 nanometers to about 2.5 nanometers. A dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide may be formed for applications with a t_eqbetween 10 Å and 20 Å, or less than 10 Å.
• Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide using embodiments of the present invention may be engineered with various structures and compositions including an amorphous structure. Embodiments using low processing temperatures tend to provide an amorphous structure, which is better suited for reducing leakage current than structures exhibiting a polycrystalline structure or a partial polycrystalline structure.
• FIG. 6 depicts ananolaminate structure600 for an embodiment of a dielectric structure including atomic layer deposited hafnium oxide and electron beam evaporated lanthanide oxide.Nanolaminate structure600 includes a plurality of layers605-1 to605-N, where each layer contains atomic layer deposited hafnium oxide or electron beam evaporated lanthanide oxide. The sequencing of the layers depends on the application. The effective dielectric constant associated withnanolaminate structure600 is that attributable to N capacitors in series, where each capacitor has a thickness defined by the thickness of the corresponding electron beam evaporated lanthanide oxide or atomic layer deposited hafnium oxide layer. By selecting each thickness and the composition of each layer, electron beam evaporated lanthanide oxide or atomic layer deposited hafnium oxide layer, a nanolaminate structure can be engineered to have a predetermined dielectric constant.
• Embodiments for forming a dielectric layer including ALD processing of a hafnium oxide and processing of an lanthanide oxide by electron beam evaporation may be implemented to form transistors, capacitors, memory devices, and other electronic systems including electro-optic devices, microwave devices, and information handling devices. With careful preparation and engineering of the dielectric layer limiting the size of interfacial regions, a t_eqless than about 10 Å for these devices is anticipated.
• Atransistor100 as depicted inFIG. 1 may be constructed by forming asource region120 and adrain region130 in a silicon basedsubstrate110 where source and drainregions120,130 are separated by abody region132.Body region132 defines a channel having achannel length134. A dielectric layer is disposed onsubstrate110 formed as a layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide. The resulting dielectric layer formsgate dielectric140.
• Agate150 is formed overgate dielectric140. Typically, forminggate150 may include forming a polysilicon layer, though a metal gate may be formed in an alternative process. Aninterfacial layer133 may form betweenbody region132 andgate dielectric140.Interfacial layer133 may be limited to a thickness less than 1 nanometer, or to a thickness significantly less than 1 nanometer as to be effectively eliminated. Forming the substrate, the source and drain regions, and the gate is performed using standard processes known to those skilled in the art. Additionally, the sequencing of the various elements of the process for forming a transistor is conducted with standard fabrication processes, also as known to those skilled in the art.
• The method for forming a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in various embodiments may be applied to other transistor structures having dielectric layers.FIG. 7 shows an embodiment of a configuration of atransistor700 having a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide.Transistor700 includes a silicon basedsubstrate710 with asource720 and adrain730 separated by abody region732.Body region732 betweensource720 and drain730 defines a channel region having achannel length734. Located abovebody region732 is astack755 including agate dielectric740, a floatinggate752, a floatinggate dielectric742, and acontrol gate750.Gate dielectric740 includes a dielectric containing an atomic layer deposited hafnium oxide layer and an electron beam evaporated lanthanide oxide layer as described herein with the remaining elements of thetransistor700 formed using processes known to those skilled in the art. Alternately, bothgate dielectric740 and floatinggate dielectric742 may be formed as dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in various embodiments as described herein. Aninterfacial layer733 may form betweenbody region732 andgate dielectric740.Interfacial layer733 may be limited to a thickness less than 1 nanometer, or to a thickness significantly less than 1 nanometer as to be effectively eliminated.
• The embodiments of methods for forming dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide may also be applied to forming capacitors in various integrated circuits, memory devices, and electronic systems. In an embodiment for forming acapacitor800 illustrated inFIG. 8, a method includes forming a first conductive layer810, forming adielectric layer820 containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide on first conductive layer810, and forming a secondconductive layer830 ondielectric layer820. Aninterfacial layer815 may form between first conductive layer810 anddielectric layer820.Interfacial layer815 may be limited to a thickness less than 1 nanometer, or to a thickness significantly less than1 nanometer as to be effectively eliminated.
• Transistors, capacitors, and other devices dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide using methods described herein may be implemented into memory devices and electronic systems including information handling devices. Such information devices may include wireless systems, telecommunication systems, and computers. It will be recognized by one skilled in the art that several types of memory devices and electronic systems including information handling devices utilize embodiments of the present invention.
• FIG. 9 is a simplified block diagram of amemory device900 using an embodiment of a dielectric containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide.Memory device900 includes an array ofmemory cells902,address decoder904,row access circuitry906,column access circuitry908,control circuitry910, and Input/Output (I/O)circuit912. The memory is operably coupled to anexternal microprocessor914, or memory controller for memory accessing.Memory device900 receives control signals fromprocessor914, such as WE*, RAS* and CAS* signals, which can be supplied on a system bus.Memory device900 stores data that is accessed via I/O lines. Each memory cell in a row ofmemory cell array902 is coupled to a common word line. The word line is coupled to gates of individual transistors, where at least one transistor has a gate coupled to a gate dielectric containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in accordance with the methods and structure previously described herein. Additionally, each memory cell in a column is coupled to a common bit line. Each cell inmemory array902 may include a storage capacitor and an access transistor as is conventional in the art. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device ofFIG. 9 has been simplified to focus on embodiments of the present invention.
• It will be understood that the above description of a memory device is intended to provide a general understanding of the memory and is not a complete description of all the elements and features of a specific type of memory, such as DRAM (Dynamic Random Access Memory). Further, embodiments are equally applicable to any size and type of memory circuit and are not intended to be limited to the DRAM described above. Other alternative types of devices include SRAM (Static Random Access Memory) or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs and other emerging DRAM technologies.
• FIG. 10 illustrates a block diagram for anelectronic system1000 having devices with an embodiment for a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide.Electronic system1000 includes acontroller1005, abus1015, and anelectronic device1025, wherebus1015 provides electrical conductivity betweencontroller1005 andelectronic device1025. In various embodiments,controller1005 and/orelectronic device1025 include an embodiment for a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide as previously discussed herein. In an embodiment,electronic system1000 includes a plurality of electronic devices using an embodiment for a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide according to the present invention.Electronic system1000 may include, but is not limited to, information handling devices, wireless systems, telecommunication systems, fiber optic systems, electro-optic systems, and computers.
CONCLUSION
• A dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide, using methods described herein, provides a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO₂. Forming dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in relatively low processing temperatures may allow for dielectric layers that are amorphous and conformally layered on a substrate surface. Further, the formation of these dielectric layers provides for enhanced dielectric and electrical properties relative to those attained with an amorphous SiO₂layer. These properties of dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide allow for application as dielectric layers in numerous devices and systems.
• Capacitors, transistors, electro-optic devices, higher level ICs or devices, and electronic systems are constructed utilizing various embodiments for forming a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide structured to provide an ultra thin equivalent oxide thickness, t_eq. Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide are formed having a dielectric constant substantially higher than that of silicon dioxide, where such dielectric layers are capable of a t_eqthinner than 10 Å, thinner than the expected limit for SiO₂gate dielectrics. The thinner t_eqof these dielectric layers allows for a higher capacitance than SiO₂gate dielectrics, which provides further effective scaling for microelectronic devices and systems. At the same time, the physical thickness of the dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide is much larger than the SiO₂thickness associated with the t_eqlimit of SiO₂. Forming the larger thickness aids in the manufacturing process for gate dielectrics and other dielectric layers.
• Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the present invention includes any other applications in which the above structures and fabrication methods are used. The scope of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (37)

1. An electronic device comprising:

a first conductive region disposed on a substrate;

a dielectric layer disposed on the first conductive region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and

a first conductive region disposed on the dielectric layer, wherein the first conductive region, the dielectric layer, and the second conductive region are structured in a capacitor or in a transistor.

2. The electronic device ofclaim 1, wherein the lanthanide oxide layer is disposed as an electron beam evaporated lanthanide oxide layer.

3. The electronic device ofclaim 1, wherein the hafnium oxide layer and the lanthanide oxide layer are arranged as a hafnium oxide/lanthanide oxide nanolaminate.

4. The electronic device ofclaim 1, wherein the lanthanide oxide layer has a thickness essentially between 2 nanometers and 10 nanometers.

5. The electronic device ofclaim 1, wherein the lanthanide oxide layer includes Pr₂O₃.

6. The electronic device ofclaim 1, wherein the dielectric layer includes Nd₂O₃.

7. The electronic device ofclaim 1, wherein the dielectric layer includes Sm₂O₃.

8. The electronic device ofclaim 1, wherein the dielectric layer includes Gd₂O₃.

9. The electronic device ofclaim 1, wherein the dielectric layer includes Dy₂O₃.

10. A capacitor, comprising:

a first conductive layer disposed on a substrate;

a dielectric layer disposed on the first conductive layer, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide, the hafnium oxide layer and lanthanide oxide layer disposed in a hafnium oxide/lanthanide oxide nanolaminate, the nanolaminate having one or more lanthanide oxide layers; and

a second conductive layer disposed on the dielectric layer, wherein the lanthanide layers of the nanolaminate have a combined thickness ranging from about 2 nanometers to about 10 nanometers.

11. The capacitor ofclaim 10, wherein the lanthanide oxide layer includes an electronic beam evaporated lanthanide oxide layer.

12. The capacitor ofclaim 10, wherein the hafnium oxide layer is disposed in contact with the first conductive layer.

13. The capacitor ofclaim 10, wherein hafnium oxide/lanthanide oxide nanolaminate includes an electron beam evaporated lanthanide oxide layer disposed in contact with the first conductive layer.

14. The capacitor ofclaim 10, wherein the lanthanide oxide layer includes one or more of Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, or Dy₂O₃.

15. A transistor comprising:

a body region in a substrate between a source region and a drain region;

a dielectric layer disposed on the body region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and

a gate coupled to the dielectric layer.

16. The transistor ofclaim 15, wherein the lanthanide oxide layer dielectric layer includes an electron beam evaporated lanthanide oxide layer.

17. The transistor ofclaim 15, wherein the hafnium oxide layer and the lanthanide oxide layer are layers in a lanthanide oxide/hafnium oxide nanolaminate.

18. The transistor ofclaim 15, wherein the dielectric layer contains multiple electron beam evaporated lanthanide oxide layers with a combined thickness of the multiple electron beam evaporated lanthanide oxide layers ranging from about 2 nanometers and about 10 nanometers.

19. The transistor ofclaim 15, wherein the dielectric layer contains multiple hafnium oxide layers, the hafnium oxide layers structured as one or more monolayers of hafnium oxide, the multiple hafnium oxide layers having a combined thickness of the multiple hafnium oxide layers ranging from about 2 nanometers and about 10 nanometers.

20. The transistor ofclaim 15, wherein the hafnium oxide layer and the lanthanide oxide layer are layers in a lanthanide oxide/hafnium oxide nanolaminate having multiple layers of lanthanide oxide, each layer of lanthanide oxide limited to a thickness of between about 2 nanometers and about 10 nanometers.

21. The transistor ofclaim 15, wherein the lanthanide oxide layer includes a combination of lanthanide oxides, the oxides selected from the group of Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, and Dy₂O₃.

22. A memory comprising:

a number of transistors, each transistor including a gate coupled to a dielectric layer, the dielectric layer disposed on a body region in a substrate between a source region and a drain region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and

a number of bit lines, each bit line coupled to one of the number of transistors.

23. The memory ofclaim 22, wherein the dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate such that a combined thickness of the lanthanide oxide layers in the nanolaminate ranges from a thickness of 2 nanometers to 10 nanometers.

24. The memory ofclaim 22, wherein the transistor is a transistor in a flash memory and the dielectric layer is an inter-gate dielectric of the transistor.

25. The memory ofclaim 22, wherein the dielectric layer is structured as a nanolaminate.

26. The memory ofclaim 22, wherein the dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate having a combined thickness of hafnium oxide layers ranging from about 2 nanometers to about 10 nanometers.

27. The memory ofclaim 22, wherein the lanthanide oxide layer includes an electron beam evaporated lanthanide oxide layer having one or more Pr₂O₃, Nd₂O₃, Sm₂O₃, Gd₂O₃, or Dy₂O₃.

28. An electronic system comprising:

a controller; and

an electronic device coupled to the controller, wherein at least one of the controller and the electronic device includes a dielectric layer, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide.

29. The electronic system ofclaim 28, where the lanthanide oxide layer includes an electron beam evaporated lanthanide oxide layer.

30. The electronic system ofclaim 28, wherein the hafnium oxide layer and the lanthanide oxide layer are layers in a lanthanide oxide/hafnium oxide nanolaminate.

31. The electronic system ofclaim 28, wherein the dielectric layer contains multiple electron beam evaporated lanthanide oxide layers with a combined thickness of the multiple electron beam evaporated lanthanide oxide layers ranging from about 2 nanometers and about 10 nanometers.

32. The electronic system ofclaim 28, wherein the dielectric layer contains multiple hafnium oxide layers with a combined thickness of the multiple hafnium oxide layers ranging from about 2 nanometers and about 10 nanometers.

33. The electronic system ofclaim 28, wherein the lanthanide oxide layer includes Pr₂O₃.

34. The electronic system ofclaim 28, wherein the lanthanide oxide layer includes one or more of Nd₂O₃or Sm₂O₃.

35. The electronic system ofclaim 28, wherein the lanthanide oxide layer includes one or more of Gd₂O₃or Dy₂O₃.

36. The electronic system ofclaim 28, wherein the electronic system includes an information handling device.

37. The electronic system ofclaim 28, wherein the electronic system includes a wireless system.

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