US20060244045A1 - MOS Transistor Gates with Doped Silicide and Methods for Making the Same - Google Patents

Abstract

Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.

Description

FIELD OF INVENTION
• The present invention relates generally to semiconductor devices and more particularly to doped silicide MOS transistor gates and fabrication methods for making the same.
BACKGROUND OF THE INVENTION
• Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a gate contact or electrode is energized to create an electric field in a channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel. A gate dielectric or gate oxide is formed over the channel, and a gate electrode or gate contact is formed over the gate dielectric. The gate dielectric and gate electrode layers are then patterned to form a gate structure overlying the channel region of the substrate.
• In operation of the resulting MOS transistor, the threshold voltage (Vt) is the gate voltage value required to render the channel conductive by formation of an inversion layer at the surface of the semiconductor channel. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-channel and p-channel (NMOS and PMOS) transistors are used to fabricate logic and other circuitry. For enhancement-mode (e.g., normally off) devices, the threshold voltage Vt is positive for NMOS and negative for PMOS transistors. The threshold voltage is dependent upon the flat-band voltage, where the flat-band voltage depends on the work function difference between the gate and the substrate materials, as well as on surface charge.
• The work function of a material is a measure of the energy required to move an electron in the material outside of a material atom from the Fermi level, and is usually expressed in electron volts (eV). For CMOS products, it is desirable to provide predictable, repeatable, and stable threshold voltages for the NMOS and PMOS transistors. To establish Vt values, the work functions of the PMOS and NMOS gate contact and the corresponding channel materials are independently tuned or adjusted through gate and channel engineering, respectively.
• Channel engineering typically involves shallow dopant implants to the prospective channel regions of the semiconductor body, sometimes referred to as threshold adjust (Vt adjust) implants, where the implanted impurities behave as a sheet of fixed charge located under the gate oxide. A Vt adjust implant for the NMOS devices introduces boron or other p-type impurities into the NMOS channel region to raise the channel work function (sometimes referred to as a VTN implant), and a Vt adjust implant for the PMOS devices introduces arsenic, phosphorus, or other n-type impurities to lower the PMOS channel work function (VTP implant). In this manner, the Vt for the channels can be separately adjusted for NMOS and PMOS devices. Channel engineering typically includes multiple implants, for example, a Vt adjust implant, a punch-thru implant to suppress punch-through, and a channel stop implant, for each of the NMOS and PMOS devices.
• Gate engineering is employed in combination with channel engineering to adjust the work function of the gate contact materials, where different gate work function values are set for PMOS and NMOS gates. The need to independently adjust PMOS and NMOS gate work functions has made poly-silicon attractive for use as gate contact material in CMOS processes, since the work function of poly-silicon can be easily raised or lowered by doping the poly-silicon with p-type or n-type impurities, respectively. The PMOS poly-silicon gates are doped with p-type impurities and NMOS gate poly-silicon is doped with n-type dopants, typically during implantation of the respective source/drain regions following gate patterning. In this way, the final gate work functions are typically near the Si conduction band edge for NMOS and near the valence band for PMOS. The provision of dopants into the poly-silicon also has the benefit of increasing the conductivity of the gate contact. Poly-silicon has thus far been widely using in the fabrication of CMOS devices, wherein the gate engineering (e.g., implants) are conventionally tuned to provide a desired gate contact conductivity (e.g., sheet resistance value), and the threshold voltage fine tuning is achieved by tailoring the Vt adjust implants to change the channel work function.
• FIG. 1 illustrates conventionalCMOS fabrication process10 beginning at12, in which front end processing is performed at14, including well formation and isolation processing. At16 and18, channel engineering is performed (e.g., Vt adjust, punch-thru, and channel stop implants) for PMOS and NMOS regions, respectively. A thin gate dielectric and an overlying poly-silicon are formed at20 and22, respectively, and the poly-silicon is patterned at24 to form gate structures for the prospective NMOS and PMOS transistors. The gate structures are then encapsulated at26, typically through oxidation and highly-doped drain (HDD) implants are performed at28 to provide p-type dopants to prospective source/drains of the PMOS regions and n-type dopants to source/drains of the NMOS regions, using the patterned gate structures and isolation structures as an implantation mask. Sidewall spacers are then formed at30 along the lateral sidewalls of the gate structures.
• At32, the PMOS source/drain regions and the PMOS poly-silicon gate structures are implanted with p-type dopants to further define the PMOS source/drains, and to render the PMOS gates conductive. Similarly, the NMOS source/drain regions and the NMOS poly-silicon gate structures are implanted at34 with n-type dopants, further defining the NMOS source/drains and to rendering the NMOS gates conductive. Thereafter, the source/drains and poly-silicon gates are silicided at36 and back end processing (e.g., interconnect metalization, etc.) is performed at38, before theprocess10 ends at40. In theconventional process10, the channel engineering implants at16 and18 shift the work functions of the PMOS and NMOS channel regions, respectively, to compensate for the changes in the PMOS and NMOS poly-silicon gate work functions resulting from the source/drain implants at32 and34, respectively. In this manner, the desired work function difference between the gates and channels, and hence the desired threshold voltages, may be achieved for the resulting PMOS and NMOS transistors.
• The gate dielectric or gate oxide between the channel and the gate contact is an insulator material, typically SiO₂or other dielectric, that operates to prevent large currents from flowing from the gate contact into the channel when a voltage is applied to the gate electrode. The gate dielectric also allows an applied gate voltage to establish an electric field in the channel region in a controllable manner. Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface.
• However, there are electrical and physical limitations on the extent to which SiO₂gate dielectrics can be made thinner. These include gate leakage currents tunneling through the thin gate oxide, limitations on the ability to form very thin oxide films with uniform thickness, and the inability of very thin SiO₂gate dielectric layers to prevent dopant diffusion from the gate poly-silicon into the underlying channel. Accordingly, recent scaling efforts have focused on high-k dielectric materials having dielectric constants greater than that of SiO₂, which can be formed in a thicker layer than scaled SiO₂, and yet which produce equivalent field effect performance. A thicker high-k dielectric layer can thus be formed to avoid or mitigate tunneling leakage currents, while still achieving the required electrical performance equivalent (e.g., capacitance value) of a thinner SiO₂.
• Another shortcoming of scaled CMOS devices having poly-silicon gate contacts is known as poly-silicon depletion. Poly-silicon depletion occurs when annealing or other thermal back-end processing following the implants at32 and34 is insufficient to drive the implanted impurities down the entire depth of the poly-silicon gate structures. In this situation, a bottom portion of the poly-silicon gate contact near the gate dielectric is “depleted” of charges, and acts as an insulator. The depleted portion of the gate contact and the gate dielectric operate as series connected capacitors, resulting in a reduced effective gate capacitance, which reduces the drive current capability of the device. Consequently, poly-silicon depletion causes reduction in device performance which leads to poor unscalable devices. Simply increasing the implant energy and/or anneal time to combat poly-silicon depletion has adverse results, in that the corresponding depths of the concurrently implanted source/drain regions are increased.
• With the relatively thick gate dielectrics and gate contact structures of the past, poly depletion was not critical to achieve desired device performance. However, as gate dielectrics and gate contacts continue to become smaller through scaling, the poly-silicon depletion problem is more pronounced, wherein poly-silicon depletion regions of 2 to 4 angstroms become a significant fraction of the overall effective gate capacitance. Thus, while poly-silicon gate contacts have previously offered flexibility in providing dual work functions for CMOS processes, the future viability of conventional poly-silicon gate technology is lessened as scaling efforts continue. Accordingly, attention has recently been directed again to the possibility of using metal gate contacts in CMOS products, where the metal gate materials conceivably do not need doping for conductivity improvement. Although this approach presumably avoids poly-silicon depletion issues with respect to gate capacitance, there remains a need for dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes. In this regard, metal work functions are not shifted as easily by the same amounts as was the case for poly-silicon. Accordingly, there is a need for improved CMOS transistor gate designs and fabrication techniques by which the benefits of scaling can be achieved while avoiding or mitigating the poly-silicon depletion degradation found in conventional devices.
SUMMARY OF THE INVENTION
• The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
• The invention relates to semiconductor devices and fabrication methods, wherein transistor gate structures are created using doped metal silicide materials. A first metal silicide is formed above a gate dielectric and the silicide is doped with n-type impurities for NMOS gates or with p-type impurities for PMOS gates. The inventors have appreciated that the gate work function of the resulting NMOS and PMOS transistors can be successfully adjusted through appropriate doping the gate silicide, thereby facilitating elimination or simplification of channel engineering. The doped first metal silicide may comprise a refractory metal such as molybdenum, tungsten, tantalum, titanium, or others having a high melting temperature, and may be formed by direct silicide deposition or through reacting metal and silicon deposited above the gate dielectric. In this regard, a single starting material may be employed to form both PMOS and NMOS gate structures, thus avoiding process integration problems associated with using different gate materials. Dopants may be added to the first silicide through any means, such as direct implantation into a reacted or deposited silicide or implantation into unreacted metal and/or unreacted silicon followed by annealing to concurrently diffuse the dopants into the metal and to create the resulting metal silicide, where the dopants can be introduced before or after gate patterning.
• The gate structures include a second upper metal silicide located above the doped first metal silicide. A silicon material may be provided between the first and second metal silicides, or the second metal silicide may overlie the doped first metal silicide thereby forming a silicide bilayer above the gate dielectric. In order to facilitate controlled dopant distribution within the doped first metal silicide for setting the gate work function (e.g., particularly at the gate dielectric interface), the first metal silicide may be relatively thin, wherein the provision of the upper silicide and/or the intervening silicon can advantageously reduce the gate contact sheet resistance. In one example, the first metal silicide is doped MoSi₂where poly-silicon is formed over the doped metal silicide. The poly-silicon may also be doped, for example, via source/drain or other implantations, to render the poly-silicon conductive. A second silicide is then formed over the poly-silicon, wherein the poly-silicon may be reacted with a deposited second metal (e.g., nickel) to form the upper silicide. The upper silicide and the remaining poly-silicon may thus be of lower resistivity than the first metal silicide. In another example, the entire poly-silicon is reacted (e.g., consumed) in forming the upper silicide, whereby the gate stack includes a metal silicide bilayer.
• In accordance with an aspect of the invention, a method is provided for fabricating PMOS and NMOS gate structures in a semiconductor device. The method comprises forming a gate dielectric, forming an n-doped first metal silicide above the gate dielectric in an NMOS region, and forming a p-doped first metal silicide above the gate dielectric in the PMOS region. The method further comprises forming a second metal silicide above the doped first metal silicide in the NMOS and PMOS regions. The first and second metal silicides may be different, for example, where the lower silicide includes a refractory metal (e.g., molybdenum, tungsten, tantalum, titanium, etc.) and the upper silicide includes nickel, and the method may further comprise forming silicon between the first and second metal silicides in the NMOS and PMOS regions.
• Another aspect of the invention provides a semiconductor device comprising NMOS and PMOS gate structures. The NMOS gate structure comprises a gate dielectric above a semiconductor body, an n-doped first metal silicide structure above the gate dielectric, and a second metal silicide above the n-doped first metal silicide. The PMOS gate structure comprises a gate dielectric above a semiconductor body, a p-doped first metal silicide structure above the gate dielectric, and a second metal silicide above the p-doped first metal silicide. In one implementation, the device further comprises silicon between the first and second metal silicides in the NMOS and PMOS gate structures. Yet another aspect of the invention provides a transistor gate structure, comprising a gate dielectric formed above a semiconductor body, a first metal silicide above the gate dielectric, the first metal silicide being doped with n or p-type impurities, and a second metal silicide above the first metal silicide.
• The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a simplified flow diagram illustrating a conventional poly-silicon gate CMOS fabrication process including channel engineering for both PMOS and NMOS transistors;
• FIGS. 2A and 2B are partial side elevation views in section illustrating exemplary MOS transistors having gate structures with first and second metal silicides in accordance with one or more aspects of the present invention;
• FIG. 3 is a flow diagram illustrating an exemplary method of fabricating semiconductor devices having PMOS and NMOS gate structures in accordance with the invention;
• FIG. 4 is a partial flow diagram illustrating several techniques for forming MOS transistor gate structures with doped first metal silicide in the fabrication method ofFIG. 3, wherein the first metal silicide is formed through deposition or reaction prior to introducing dopants therein;
• FIGS. 5A-5L are partial side elevation views in section illustrating exemplary NMOS and PMOS transistors undergoing CMOS processing in accordance with the invention at various stages of fabrication to form gate structures with first and second metal silicides and an intervening poly-silicon;
• FIGS. 5M-5O are partial side elevation views in section illustrating exemplary NMOS and PMOS transistors undergoing CMOS processing at various stages of fabrication to form gate structures with first and second metal silicides in a silicide bilayer with no intervening silicon in accordance with the invention;
• FIG. 6 is a partial flow diagram illustrating other techniques for forming MOS transistor gate structures with doped first metal silicide in the fabrication method ofFIG. 3, in which one or both of a first metal and a first silicon are doped prior to annealing to form the first metal silicide;
• FIGS. 7A-7L are partial side elevation views in section illustrating exemplary NMOS and PMOS transistors undergoing processing at various stages of fabrication to form gate structures with first and second metal silicides and an intervening silicon in accordance with the invention; and
• FIGS. 7M-7O are partial side elevation views in section illustrating exemplary NMOS and PMOS transistors undergoing CMOS processing at various stages of fabrication to form gate structures with first and second metal silicides in a silicide bilayer with no intervening silicon.
DETAILED DESCRIPTION OF THE INVENTION
• One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The invention relates to semiconductor devices, as well as MOS transistor gate structures and fabrication methods therefor, in which first and second metal silicides are formed in a gate structure and the first metal silicide is doped.
• FIGS. 2A and 2B illustrate exemplaryCMOS semiconductor devices50 and52, withNMOS transistors58aand58b,respectively, having gate structures in accordance with the invention. Thedevices50,52 are fabricated in or on asilicon substrate54, although the invention may be carried out in association with SOI wafers, epitaxial silicon layers formed over silicon wafers, and any other semiconductor body. N-wells, p-wells, and/or buried layers (not shown) may be formed in thesubstrate54, and thesubstrate54 may be initially doped with p-type or other impurities. Thetransistors58aand58binclude field oxide (FOX)isolation structures56, and n-doped source/drains60.
• In accordance with an aspect of the invention, thedevices50 and52 include MOS transistor gate structures, comprising agate dielectric layer62 formed above a channel region of thesubstrate54, an n-dopedfirst metal silicide64 above thegate dielectric62 having a thickness of about 100 Å or less, and asecond metal silicide66 above thefirst metal silicide64, wherein the exemplary gate structures ofFIGS. 2A and 2B have a total thickness on the order of about 1000 Å or less. The gate structures have sidewalls over which an encapsulation oxide orother material70 is formed, and along which sidewall spacers72 are formed. Silicide source/drain contacts74 are formed over the source/drains60. Thetransistor58binFIG. 2B provides a gate structure having a bilayer metal silicide with thesecond silicide66 situated over the dopedfirst silicide64.
• The transistor58aofFIG. 2A further includes asilicon layer68 between the first andsecond metal silicides64 and66. The interveningsilicon68 may be doped to increase the conductivity thereof, and to thereby reduce the sheet resistance of the gate, wherein a portion of thesilicon68 may be reacted with nickel or other metal in forming thesecond silicide66. In this regard, a poly-silicon (not shown) may be deposited above thefirst silicide64 in thedevice52, the entirety of which is consumed in forming thesecond silicide66, leaving the bilayer silicide gate stack shown inFIG. 2B. The provision of silicon above thefirst silicide64 advantageously provides protection for thefirst silicide64 in fabrication processing, for example, to integrate the creation of the gate structures of the invention into existing CMOS process flows tailored for poly-silicon being present during gate etch processes to define the gate structures for NMOS and PMOS transistors. For instance, poly-silicon coverage may be desirable for a case in which thefirst silicide64 comprises titanium silicide, which is reactive to hydrogen fluoride used in wet etch steps or other processing following formation of thefirst silicide64.
• In the illustrateddevices50 and52, the first andsecond metal silicides64 and66, respectively, are different, wherein thefirst metal silicide64 comprises a refractory metal such as molybdenum, tungsten, tantalum, titanium, or others, while the second metal silicide comprises nickel. Alternatively, the first andsecond metal silicides64 and66 can be the same type and/or can comprise any suitable metal within the scope of the invention. However, the inventors have appreciated that the use of refractory metal silicides, such as MoSi₂or others comprising W, Ti, Ta, etc., for thefirst silicide64 provides high melting temperatures to withstand fabrication processing. In this regard, nickel or othersecond silicides66 provide low resistivity, wherein thesecond silicide66 may be formed later in a fabrication flow, and thus only be exposed to relatively lower temperature back-end processing.
• While NMOS transistors58 are illustrated inFIGS. 2A and 2B, the aspects of the invention are also applicable to PMOS structures, as described further below with respect toFIGS. 5A-5O and7A-7O. The dopants in thefirst metal silicide64 of NMOS and PMOS transistor gate structures can be separately tailored for setting the respective gate work functions, thereby facilitating threshold voltage tuning while simplifying or eliminating channel engineering steps and avoiding poly depletion troubles of conventional CMOS devices. A single type of doped metal silicide can be employed in both the NMOS and PMOS regions of a device, thus simplifying subsequent patterning and other processing steps. N and p-type dopants are separately introduced into thelower metal silicide64 to provide differentiated work functions for NMOS and PMOS transistors, respectively, either before or after gate patterning.
• Another aspect of the invention provides methods for fabricating PMOS and NMOS transistors in a semiconductor device. In the examples below, an n-doped first metal silicide is formed above a gate dielectric in an NMOS region of a semiconductor device, a p-doped first metal silicide is formed above the gate dielectric in a PMOS region, and a second metal silicide is formed above the doped first metal silicide in the NMOS and PMOS regions. In accordance with the invention, the n-doped and p-doped first silicides can be formed by separate processes for the NMOS and PMOS regions, respectively. However, the invention also advantageously provides for forming the doped first silicides using a common starting material in both NMOS and PMOS regions. In one example, a single starting first metal silicide is deposited above the gate dielectric and then selectively doped in the NMOS and PMOS regions. In another implementation, a common first metal and a first silicon are deposited in both regions, and are subsequently annealed to form the first silicide, either before, or after selective doping of the NMOS and PMOS regions. Thereafter, a second or upper silicide, doped or undoped, is formed above the first silicide, and an optional silicon layer may be formed between the first and second silicides.
• FIG. 3 illustrates an exemplary semiconductor device fabrication process100 in accordance with the invention, andFIG. 4 illustrates various exemplary techniques for forming MOS transistor gate structures with doped first metal silicide in the fabrication method ofFIG. 3, in which the first metal silicide is formed through deposition or reaction prior to introducing dopants therein.FIGS. 5A-5O illustrate fabrication of an exemplary CMOS device according to the processing examples ofFIGS. 3 and 4.FIG. 6 illustrates other techniques for forming MOS transistor gate structures with doped first metal silicide in the fabrication method ofFIG. 3, in which one or both of a first metal and a first silicon are doped prior to annealing to form the first metal silicide.FIGS. 7A-7O illustrate fabrication of an exemplary CMOS device according to the processing examples ofFIGS. 3 and 6.
• Although the exemplary method100 ofFIGS. 3, 4, and6 is illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Further, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures and devices not illustrated.
• The method100 begins at102 inFIG. 3, wherein front end processing is performed at104. Any front end processing may be performed within the scope of the invention, wherein the processing at104 may include, for example, formation of n and p wells using diffusion, implantation, or other suitable processing steps, as well as formation of isolation structures in field regions of a device wafer, using LOCOS, STI, or any suitable isolation processing. The front-end processing104 may also comprise channel doping (e.g., channel engineering) to adjust the work function of a channel portion of the semiconductor body in prospective NMOS and/or PMOS active regions. Such channel engineering may include, for example, a shallow Vt adjust implant to introduce boron or other p-type dopants into the NMOS channel regions with the PMOS regions masked to raise the NMOS channel work function. In addition, a boron punch-thru implant may be performed to suppress punch-through, along with a somewhat deeper boron channel stop implant in the NMOS regions. Similar channel engineering may be performed to provide n-type dopants (e.g., arsenic, phosphorus, etc.) to the PMOS regions with the NMOS regions masked.
• At106, a gate dielectric is formed in the NMOS and PMOS regions using any suitable materials, material thicknesses, and processing steps, including a single thermal oxidation or deposition or combinations thereof to form a gate dielectric above the semiconductor body. The invention may be employed in conjunction with any gate dielectric material, such as SiO₂, SiON, high-k dielectrics, and stacks or combinations thereof, including but not limited to binary metal oxides including aluminum oxide (Al₂O₃), zirconium oxide (ZrO₂), hafnium oxide (HfO₂), lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃), titanium oxide (TiO₂), as well as their silicates and aluminates; metal oxynitrides including aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), as well as their silicates and aluminates such as ZrSiON, HfSiON, LaSiON, YSiON, etc.; and perovskite-type oxides including a titanate system material such as barium titanate, strontium titanate, barium strontium titanate (BST), lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium lanthanum titanate, barium zirconium titanate; a niobate or tantalate system material such as lead magnesium niobate, lithium niobate, lithium tantalate, potassium niobate, strontium aluminum tantalate and potassium tantalum niobate; a tungsten-bronze system material such as barium strontium niobate, lead barium niobate, barium titanium niobate; and bilayered perovskite system material such as strontium bismuth tantalate, bismuth titanate and others. Separate processing may optionally be employed to form different gate dielectrics in the NMOS and PMOS regions within the scope of the invention. In the examples illustrated and described herein, a single thermal oxidation is performed at106 to create a thin SiO₂or gate oxide overlying the substrate in the NMOS and PMOS regions.
• Gate structures are then formed at110, with the general gate fabrication principles being illustrated inFIG. 3, and several exemplary gate fabrication implementations being illustrated inFIGS. 4 and 6. An n-doped first metal silicide is formed above the gate dielectric in the NMOS region at112 inFIG. 3, and a p-doped first metal silicide is formed above the gate dielectric in the PMOS region at114. The silicide may be formed by any suitable techniques in accordance with the invention, including but not limited to deposition of a metal silicide, or formation of metal and silicon layers and reaction thereof to form the first metal silicide. N-type and p-type dopants are selectively introduced into the first metal silicide of the NMOS and PMOS regions using any suitable techniques, including but not limited to implantation and/or diffusion, wherein the dopants may be introduced before and/or after silicidation of a first metal with silicon in the case of reacted silicide.
• A silicon layer is formed at116 above the first metal silicide in the NMOS and PMOS regions, some or all of which may subsequently be consumed in forming a second metal silicide above the first metal silicide, wherein the silicon may, but need not, be n-doped or p-doped in the NMOS and PMOS regions, respectively. Any suitable formation techniques may be employed to create the silicon at116, for example, chemical vapor deposition (CVD) processes, etc. The silicon may be formed at116 directly over the first metal silicide or may be formed over one or more intervening material layers within the scope of the invention. The silicon and first metal silicide are patterned at118 to form NMOS and PMOS gate structures using any suitable techniques, for example, such as masked etching.
• At120, the gate structures are optionally encapsulated using any suitable materials and processing steps. Highly-doped drain (HDD) implants are performed at122 to introduce p-type dopants (e.g., boron, etc.) into prospective PMOS source/drains and to provide n-type dopants (e.g., arsenic, phosphorus, etc.) to prospective NMOS source/drains, using any suitable processing steps and operational parameters, wherein the patterned gate structures and isolation structures operate as implantation masks. The HDD implants at122 also provide n-type dopants to the silicon in the NMOS regions and p-type dopants to the silicon in the PMOS regions in the illustrated example, although the gate silicon layers can alternatively be masked during the implantation operations at122. Sidewall spacers are formed at124 along the lateral sidewalls of the patterned gate structures, using any suitable process techniques and materials, for example, by depositing and etching SiO₂, Si₃N₄, etc.
• Source/drain implants are then performed at126 and128 to further dope the PMOS and NMOS source/drain regions of the semiconductor body, wherein n-type dopants may also be implanted into the silicon in the NMOS regions and p-type dopants may be implanted into the silicon in the PMOS regions. In the illustrated implementation, a PMOS source/drain implant is performed at126, to introduce boron or other p-type impurities into the PMOS region of the semiconductor body and into the PMOS gate silicon with the NMOS region masked. Any suitable implantation technique, operational settings, and implant species may be employed at126 to render the PMOS gate silicon conductive and to further define the PMOS source/drains in the semiconductor body.
• An NMOS source/drain implant is performed at128 to introduce arsenic, phosphorus, or other suitable n-type impurities to the NMOS region of the semiconductor body and to the NMOS gate silicon with the PMOS region masked. Any suitable implantation technique, operational settings, and implant species may be employed at128 to render the NMOS gate silicon conductive and to further define the NMOS source/drains, wherein the implants at126 and128 may be performed in any order. In addition, activation anneal operations may be performed following one or both of the source/drain implants126,128, wherein such annealing may also operate to diffuse dopants in the first silicide.
• A self-aligned silicide process is performed at130 to silicide the source/drains and the gate silicon, wherein silicidation of the gate silicon creates a second metal silicide above the first metal silicide of the gate stacks in the exemplary implementation. In one example, nickel or other metal is deposited at130 over the gate silicon and over the semiconductor body in the prospective source/drain regions, and the wafer is annealed to react the gate silicon and the source/drain region silicon of the semiconductor body with the deposited nickel to form nickel silicide. By this technique, the second silicide of the gate stack may be formed above the doped first metal silicide concurrently with formation of source/drain silicide contacts, although separate silicide formation techniques (e.g., reaction or deposition and etching) may be employed to form the second metal silicide of the gate structures. In one implementation (e.g.,FIG. 2A above), a portion of the doped silicon remains unreacted after the silicidation at130. In another example, substantially all of the silicon is consumed at130 in creating the second silicide, leaving a silicide bilayer gate structure as shown inFIG. 2B above.
• The second silicide can be formed anywhere above the first metal silicide of the gate structure within the scope of the invention. For example, the second silicide may be formed directly over the first metal silicide, directly over an intervening silicon, or one or more other layers may be situated between the second silicide and the first silicide or the silicon. As discussed above, the second silicide may be the same or may comprise different metal than the first silicide. For example, the second silicide may advantageously comprise nickel (e.g., low resistivity, lower melting temperature), where the first metal silicide comprises a refractory metal (e.g., molybdenum, tungsten, tantalum, titanium, etc.) having a higher melting temperature. In this manner, the second silicide may provide improved (e.g., lower) gate sheet resistance, whereas the first silicide is able to withstand relatively higher processing thermal budget between the first silicide formation at112 and the back-end processing at132. In addition, the provision of the intervening silicon over the first metal silicide (e.g., whether fully consumed at130 or not) may advantageously protect the first metal silicide during fabrication processing. Back end processing (e.g., interconnect metalization, etc.) is performed at132, before the exemplary method100 ends at134.
• Referring now toFIGS. 3, 4, and5A-5O, anexemplary CMOS device302 is illustrated inFIGS. 5A-5O at various stages of fabrication processing generally according to the method100 above. In this example, the gate fabrication for the NMOS and PMOS transistors (e.g.,110 in method100) is illustrated in further detail inFIG. 4, in which a first metal silicide (e.g.,MoSi₂312 in the exemplary device302) is formed through deposition or reaction prior to introduction of n or p-type dopants therein.FIGS. 5A-5L illustrate exemplary NMOS and PMOS transistors in thedevice302 undergoing processing at various stages of fabrication in accordance with the invention to form gate structures with first andsecond metal silicides312 and344 and an intervening poly-silicon324. InFIGS. 5M-5O, analternative device302ais illustrated having gate structures with first and second metal silicides in a silicide bilayer with no intervening silicon in accordance with the invention.
• As illustrated inFIG. 5A, theCMOS device302 includes a siliconsubstrate semiconductor body304 with a p-well306 formed in an NMOS region and an n-well308 formed in a PMOS region, as well as field oxide (FOX)isolation structures310, where thewells306,308 and thefield oxide310 are formed during front-end processing (e.g., at104 inFIG. 3). Agate dielectric316 is then formed (e.g., at106 inFIG. 3) over the surface of thesubstrate304 in NMOS and PMOS active regions of thedevice302 between theFOX isolation structures310, for example, a thermally grown SiO₂oxide316 or any other dielectric material formed by any suitable technique in the illustrateddevice302.FIG. 4 illustrates various alternative gate structure fabrication approaches wherein a first metal silicide is formed over thegate dielectric316 through deposition or silicide reaction of metal and silicon (e.g., “DEP” or “REACT” at200), and wherein poly-silicon is formed above the first metal silicide either before or after doping (e.g., “POLY FIRST” or “DOPE FIRST” at204).
• In theexemplary device302, thefirst metal silicide312 is formed through deposition (e.g., “DEP” at200). InFIG. 5B, a refractory metal silicide312 (molybdenum disilicide, MoSi₂) is deposited (e.g.,202 ofFIG. 4) over thegate dielectric316 in NMOS and PMOS regions of thedevice302 via adeposition process314, for example, sputtering, CVD, ALD, or other suitable deposition technique. Thefirst metal silicide312 may be deposited or otherwise formed to any suitable thickness within the scope of the invention, wherein thesilicide312 in theexemplary device302 has a thickness of about 100 Å or less. Compared with reacting the first metal silicide (e.g.,230-234 below), deposition of thefirst metal silicide312 through sputtering, CVD, etc., may allow tighter control over the final silicide composition.
• A layer ofsilicon324 is then deposited inFIG. 5C over thefirst metal silicide312 before doping (e.g., “POLY FIRST” at204) using a CVD deposition process326 (206 inFIG. 4). Thesilicon324 may be formed to any desired thickness within the scope of the invention. Alternatively, dopants may be directly implanted into the first metal silicide prior to silicon deposition (e.g.,216-220 below). InFIG. 5D, amask321 is formed to cover the PMOS regions and expose the NMOS regions, and n-type dopants (e.g., P, As, etc.) are introduced via animplantation process323 into the exposed silicon in the NMOS regions, thus creating n-doped poly-silicon324aover the first metal silicide in the NMOS regions (208 inFIG. 4). The range of the implantation can also be adjusted to dope the poly-silicon near to the metal silicide, or to dope the silicide layer itself.
• Themask321 is then removed and amask320 is formed inFIG. 5E to cover the NMOS regions and expose the PMOS regions. Animplantation process322 is performed to provide boron or other p-type dopants to the poly-silicon in the PMOS region (210 inFIG. 4), thereby creating p-doped poly-silicon324bover thefirst silicide312 in the PMOS region, after which themask320 is removed. Alternatively, thefirst silicide312 and the poly-silicon324 can be patterned before the implantations at208 and210. Thereafter inFIG. 5F, ananneal process325 is performed (212 inFIG. 4) to diffuse n and p-type dopants from the NMOS and PMOS poly-silicon324aand324b,respectively, into the underlyingfirst metal silicide312 in the NMOS and PMOS regions, thereby creating n and p-dopedfirst metal silicide312aand312bin the NMOS and PMOS regions, respectively.
• InFIG. 5G, amask328 is formed, and the n and p-doped poly-silicon324aand324b,respectively, as well as the doped first metal silicide are patterned (214 inFIG. 4) via anetch process330 to define patterned NMOS and PMOS gate structures. InFIG. 5H, themask328 is removed and the patterned gate structures are encapsulated (120 inFIG. 3) by forming a single ormulti-layer encapsulation structure332 along the sidewalls and top of the gate structures. Following encapsulation,HDD implants334 are performed (122 inFIG. 3) to introduce p-type dopants into prospective PMOS source/drains336 and to introduce n-type dopants into prospective NMOS source/drains338, with thefield oxide310 and patterned gate structures operating as an implantation mask.
• InFIG.5I sidewall spacers340 are formed (e.g.,124 inFIG. 3) along the lateral sidewalls of the patterned gate structures. Amask320 is formed over the NMOS region, and a p-type source/drain implant342ais performed (126 inFIG. 3) to implant boron or other p-type impurities into the PMOS region, which further defines the PMOS source/drains336 and provides additional dopants to the PMOS gate stack poly-silicon324b.Themask320 is removed inFIG. 5J, and amask327 is formed over the PMOS region. An n-type source/drain implant342bis performed (128 inFIG. 3) to implant arsenic, phosphorus or other n-type impurities into the NMOS region, thus further defining the NMOS source/drains338 and providing additional dopants to the NMOS gate stack poly-silicon324a.
• InFIGS. 5K and 5L, asecond metal silicide344ais formed (130 inFIG. 3) above thefirst metal silicide312 and the poly-silicon324, and source/drain silicide contacts344bare formed over the source drains336 and338. In the illustrated example, a layer ofnickel341 is deposited over thedevice302 inFIG. 5K, whereby thenickel341 overlies the poly-silicon324 of the patterned gate stacks and also overlies the doped source/drains336 and338 of thesubstrate304. Athermal anneal343 is performed to react thenickel341 with the poly-silicon324 of the gate stacks, thereby forming asecond metal silicide344aabove the remaining poly-silicon324 as seen inFIG. 5L. In addition, theanneal343 concurrently reacts thenickel341 with the source/drain silicon336 and338 to form nickel silicide source/drain contacts344b,after which any remaining (e.g., unreacted)nickel341 is removed. Interconnect metalization and other back-end processing (not shown) may thereafter be performed to complete the fabrication of the device302 (132 inFIG. 3). Thesecond metal silicide344aand the source/drain silicide contacts344bmay alternatively be formed by separate processes within the scope of the invention.
• FIGS. 5M-5O illustrate analternative device302ain accordance with the invention, having MOS gate structures comprising first andsecond metal silicides312 and344ain a silicide bilayer with no intervening poly-silicon. InFIG. 5M, a relatively thickfirst metal silicide312 is formed over the gate dielectric316 (e.g., MoSi₂having a thickness greater than about 100 Å) and somewhat thinner poly-silicon324 is deposited over thefirst metal silicide312. Following gate stack and source/drain fabrication as described above,FIG. 5N illustrates deposition ofnickel341 over the patterned NMOS and PMOS gate structures and the source/drains336,338. Ananneal process343 is performed to react thenickel341 with the poly-silicon324 of the gate stacks, thereby forming asecond metal silicide344aand concurrently forming silicide source/drain contacts344b.In thedevice302a,the relative deposited thicknesses of thefirst silicide312, the poly-silicon324, and thenickel341 are selected such that the anneal causes thesilicide344ato consume substantially all of the poly-silicon324 in the gate structures, as seen inFIG. 5O. Thus, a bilayer (e.g., first andsecond silicides312 and344a) is provided in the gates above thegate dielectric316. As with the above example, a single silicide process may be used to concurrently form thesecond metal silicide344aof the gate structures as well as the source/drain contacts344b,or these may be formed by separate processes within the scope of the invention.
• In the above example ofFIGS. 4 and 5A-5O, the dopedfirst metal silicide312 is formed by depositing firstmetal silicide material312 above the gate dielectric in the NMOS and PMOS regions, introducing n-type dopants into the firstmetal silicide material312 in the NMOS region, and introducing p-type dopants into the firstmetal silicide material312 in the PMOS region. However, alternative implementations are possible where the first (e.g., lower)metal silicide312 is formed prior to introduction of dopants therein, some of which are illustrated inFIG. 4. In one alternative, thefirst metal silicide312 may be formed by reaction of deposited silicon and metal (e.g., “REACT” at200). In this case, a metal (e.g., refractory or other suitable first metal material) is deposited over the gate dielectric at230 to any thickness using any suitable process. A first silicon is then deposited at232 over the deposited metal, and an anneal is performed at234 to form thefirst metal silicide312.
• This reacted silicide can then be provided with dopants through diffusion from an overlying doped poly-silicon (e.g., at206-212 as described above), or be directly implanted prior to poly-silicon formation. In this case (“DOPE FIRST” at204), the first metal silicide of the NMOS region is implanted at216 with n-type dopants and the first metal silicide of the PMOS region is implanted with p-type dopants at218, using appropriate masks. Thereafter an anneal may optionally be performed to diffuse the implanted dopants, and poly-silicon is deposited over the doped first metal silicide at220. As one alternative, the silicon deposition at220 (e.g., CVD deposition) may provide suitable thermal heating to diffuse the dopants to the desired depth, concentration, profile, etc. within the first metal silicide, whereby an extra (e.g., dedicated) anneal may not be required. Thereafter, the gate structures are patterned at214 as described above. In the various implementations illustrated and described herein, the gate structures can alternatively be patterned at other points in the fabrication process, for example, prior to implantation and/or diffusion of dopants into the first metal silicide. Other possible alternatives include forming poly-silicon over undoped first metal silicide (reacted or deposited), and implanting dopants through the poly-silicon and into the underlying first metal silicide, with or without subsequent diffusion annealing.
• Referring now toFIGS. 3, 6, and7A-7O, another possible implementation involves doping one or both of a first metal and a first silicon prior to annealing to form the first metal silicide. This approach may advantageously facilitate location of dopants at a desired concentration at the bottom of the first metal silicide near the interface with the gate dielectric. For example, one exemplary implementation illustrated and described below provides for formation of a doped silicon overlying a deposited metal, where an anneal process concurrently diffuses dopants from the silicon into the metal while reacting the metal with the silicon to form the first metal silicide over the gate dielectric. In another alternative implementation, dopants are implanted through the silicon and into the underlying metal, after which a post-implant anneal is performed to react the metal and the silicon and thereby form the first silicide. The gate structures may be patterned at any suitable point in these implementations, such as before or after the anneal steps.
• FIGS. 7A-7L illustrate anotherexemplary CMOS device502 at various stages of fabrication processing generally according to the method100 above. Fabrication of the NMOS and PMOS gate structures in the device502 (e.g.,110 inFIG. 3) is illustrated in further detail inFIG. 6. A first metal511 (e.g., refractory metal such as Mo, W, Ti, Ta, etc.) is deposited over the gate dielectric, along with anoverlying silicon524, wherein dopants are introduced into one or both of these materials prior to or concurrently with silicidation thereof. The completed transistor gates include first andsecond metal silicides512 and544aand an interveningsilicon524.FIGS. 7M-7O illustrate analternate device502ahaving gate structures with first and second metal silicides in a silicide bilayer with no intervening silicon in accordance with the invention.
• The device502 (FIG. 7A) includes a siliconsubstrate semiconductor body504 with a p-well506, an n-well508, and fieldoxide isolation structures510 formed during front-end processing (104 inFIG. 3). Agate dielectric516 is then formed (106 inFIG. 3) over the surface of thesubstrate504 in NMOS and PMOS active regions of thedevice502, which can be a thermally grown SiO₂oxide516 or any other dielectric material formed by any suitable technique. Gate fabrication then proceeds in accordance with processing indicated generally as110binFIG. 6. InFIG. 7B, a refractory metal511 (e.g., Mo, W, Ti, Ta, etc.) is deposited (e.g.,402 ofFIG. 6) over thegate dielectric516 in NMOS and PMOS regions of thedevice502 via a deposition process514, for example, sputter deposition or other suitable process. Thefirst metal511 can alternatively be a non-refractory metal and may be deposited or otherwise formed to any suitable thickness within the scope of the invention. InFIG. 7C, a layer ofsilicon524 is deposited over thefirst metal511 using a CVD deposition process526 (404 inFIG. 6) to any desired thickness. In one possible implementation, thedeposition process526 is preferably adjusted such that themetal layer511 and the depositedsilicon layer524 do not react to form a silicide layer at this process step.
• Doping of the ultimately formed first metal silicide may be accomplished using any suitable technique within the scope of the invention, including direct implantation or diffusion (“DIRECT IMPLANT” or “DIFFUSION” at406 inFIG. 6). In theexemplary device502, diffusion is employed (e.g.,408-414 inFIG. 6). InFIG. 7D, a mask521 is formed covering the PMOS regions and exposing the NMOS regions, and animplantation process523 provides n-type dopants to the NMOS silicon, thereby creating n-dopedsilicon524aover the first metal511 (408 inFIG. 6). InFIG. 7E, the mask521 is removed and amask520 is formed to cover the NMOS regions and expose the PMOS regions. An implantation process522 is performed to introduce p-type dopants into the silicon in the PMOS region (410 inFIG. 6), thus creating p-dopedsilicon524bover thefirst metal511 in the PMOS region and themask520 is then removed. InFIG. 7F, ananneal process525 is performed (412 inFIG. 6) to diffuse n and p-type dopants from the NMOS andPMOS silicon524aand524b,respectively, into the underlyingfirst metal511, and to concurrently react thesilicon524 and themetal511 to form doped first metal silicide512 in the NMOS and PMOS regions. As a result, n and p-dopedfirst metal silicides512aand512bare created in the NMOS and PMOS regions, respectively, as shown inFIG. 7F.
• Amask528 is formed inFIG. 7G and thesilicon524a,524band the first metal silicide512 are patterned (414 inFIG. 6) via an etch process530 to define patterned NMOS and PMOS gate structures, after which themask528 is removed. Alternatively, the layers can be patterned before annealing, although the illustrated example advantageously avoids gate structure shape changes during annealing by patterning after the anneal. InFIG. 7H, the patterned gate structures are encapsulated (120 InFIG. 3) with anencapsulation structure532, and HDD implants534 are performed (122 inFIG. 3) to provide p-type dopants in prospective PMOS source/drains536 and n-type dopants in prospective NMOS source/drains538.Sidewall spacers540 are formed inFIG. 7I along the lateral sidewalls of the patterned gate structures (124 inFIG. 3), as well as amask520 covering the NMOS region. A p-type source/drain implant542ais performed (126 inFIG. 3) to implant p-type impurities into the PMOS region, further defining the PMOS source/drains536 and providing additional dopants to the PMOSgate stack silicon524b.
• InFIG. 7J, themask520 is removed and a mask527 is formed over the PMOS region. An n-type source/drain implant542bis performed (128 inFIG. 3) to implant arsenic, phosphorus or other n-type impurities into the NMOS region, thus further defining the NMOS source/drains538 and providing additional dopants to the NMOSgate stack silicon524a.InFIGS. 7K and 7L, asecond metal silicide544ais formed (130 inFIG. 3) above the doped first metal silicide512 and thesilicon524, and source/drain silicide contacts544bare formed over the source drains536 and538. InFIG. 7K, a layer ofnickel541 is deposited over thesilicon524 and over the doped source/drains536 and538 of thesubstrate504. Ananneal543 is performed to react thenickel541 with thesilicon524 of the gate stacks, thereby forming asecond metal silicide544aabove the remainingsilicon524 as seen inFIG. 7L, wherein theanneal543 concurrently reacts thenickel541 with the source/drain silicon536 and538 to form nickel silicide source/drain contacts544b.Thereafter, any remaining (e.g., unreacted)nickel541 is removed. Interconnect metalization and other back-end processing (not shown) is thereafter performed to complete the fabrication of the device502 (132 inFIG. 3). As with the above examples, thesecond metal silicide544aand the source/drain silicide contacts544bmay alternatively be formed by separate processes within the scope of the invention.
• InFIGS. 7M-7O, analternative device502ais illustrated, having MOS gate structures comprising first andsecond metal silicides512 and544ain a silicide bilayer with no intervening silicon. InFIG. 7M, afirst metal511 is formed over thegate dielectric516 andsilicon524 is deposited over thefirst metal511. Following gate stack and source/drain fabrication as described above (e.g., including reaction of themetal511 with thesilicon524 to form the first silicide512),FIG. 7N illustrates deposition ofnickel541 over the remainingsilicon524 of the patterned NMOS and PMOS gate structures and over the source/drains536,538. Ananneal543 is performed to react thenickel541 with thesilicon524 of the gate stacks, thereby forming asecond metal silicide544a,wherein the anneal consumes substantially all of thesilicon524 in the gate structures, as shown inFIG. 7O.
• Referring again toFIG. 6, as an alternative to diffusion, thefirst metal511 and/or theoverlying silicon524 may be doped by direct implantation (e.g., “DIRECT IMPLANT” at406 inFIG. 6) following silicon formation within the scope of the invention. At420, n-type dopants are implanted through the silicon and into the underlying first metal in the NMOS region, using any suitable masking and implantation processes. At422, p-type dopants are implanted through the silicon and into the underlying first metal in the PMOS region, after which a post implant anneal is performed at424 to react the silicon and the doped first metal, thus creating doped first metal silicide. The silicon may be partially or entirely consumed in the silicidation anneal at424 within the scope of the invention. Thereafter, the first metal silicide and any remaining silicon are patterned at426, and further fabrication processing is performed as described above.
• Although the invention has been illustrated and described with respect to one or more implementations, alterations, and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.

Claims (8)

1-34. (canceled)

35. A transistor gate structure, comprising:

a gate dielectric formed above a semiconductor body;

a first metal silicide on, and in direct physical contact with, the gate dielectric, the first metal silicide doped with substantially single polarity impurities and having a first metal component; and

a second metal silicide having a metal component different from the first metal component, above the first metal silicide.

36. (canceled)

37. The gate structure ofclaim 35, further comprising a silicon layer between the first and second metal silicides.

38. The gate structure ofclaim 35, wherein the first metal silicide comprises a refractory metal.

39. The gate structure ofclaim 38, wherein the refractory metal is one of molybdenum, tungsten, tantalum, and titanium.

40. The gate structure ofclaim 38, wherein the second metal silicide comprises nickel.

41. The gate structure ofclaim 35, wherein the second metal silicide comprises nickel.

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