US20060234428A1 - Methods of implementing and enhanced silicon-on-insulator (soi) box structures - Google Patents

Abstract

Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.

Description

FIELD OF THE INVENTION
• The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures.
DESCRIPTION OF THE RELATED ART
• Silicon-on-insulator (SOI) transistors provide better performance at low operating voltages than do transistors of similar dimensions fabricated in bulk silicon substrates. Superior performance of SOI transistors at low operating voltage is related to the relatively lower junction capacitances obtained on an SOI device as compared to a bulk silicon device of similar dimensions. A buried oxide layer in an SOI device separates active transistor regions from the bulk silicon substrate, reducing junction capacitance.
• Various SOI transistor arrangements are known. For example, Wei et al., U.S. patent application Publication No. US 2003/0223258 published Dec. 4, 2003, and assigned to the present assignee, discloses a method comprising forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate. In other embodiments, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, performing at least one oxygen implant process after the gate electrode and the protective layer are formed to introduce oxygen atoms into the bulk substrate to thereby form a plurality of oxygen-doped regions in the bulk substrate, and performing at least one anneal process to convert the oxygen-doped regions to dielectric regions comprised of silicon dioxide in the bulk substrate. In one illustrative embodiment, the device comprises a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer, and an active layer, and a plurality of dielectric regions comprised of silicon dioxide formed in the bulk substrate, the dielectric regions being self-aligned with respect to the gate electrode.
• While the above disclosed methods and silicon-on-insulator (SOI) structures provide improvements over prior art arrangements, a need exists for enhanced SOI devices and methods for manufacturing thereof. It is desirable to provide new backgate processing techniques and enhanced SOI BOX structures.
SUMMARY OF THE INVENTION
• Principal aspects of the present invention are to provide enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures. Other important aspects of the present invention are to provide such enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
• In brief, enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures.
• In accordance with one embodiment of the invention, a silicon-on-insulator (SOI) structure is provided including a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. The silicon substrate layer is thinned and an oxygen implant step is performed from the backside into the thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer.
• In accordance with features of one embodiment of the invention, the oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.
• In accordance with features of one embodiment of the invention, a gate oxide and a gate electrode are formed over the active region above the backgate. Doping, formation and activation of each respective source/drain region and the gate electrode are provided for the SOI transistor
• In accordance with features of one embodiment of the invention, an image of the gate electrode is larger than a backgate image, whereby gate alignment problems of the SOI transistor are minimized. A programmable body contact is provided, for example, by applying a first voltage supply potential between the source/drain regions and the backgate and applying a second voltage supply potential between the gate electrode and ground, where the first voltage supply potential is greater than the second voltage supply potential.
• In accordance with features of one embodiment of the invention, a doping implant into the active layer above the backgate forms a doped plate region from the active layer. A contact formation on the backgate and doped plate region provides respective anti-fuse (AF) connections. A voltage supply source is connected between the respective anti-fuse (AF) connections in a fuse programming step forming a conduction path between the backgate and doped plate region.
BRIEF DESCRIPTION OF THE DRAWINGS
• The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
• FIGS. 1-3,4A and4B are diagrams not to scale illustrating exemplary steps for implementing enhanced SOI BOX structures in accordance with one preferred embodiment;
• FIG. 5 is a diagram not to scale illustrating further exemplary steps for implementing silicon-on-insulator (SOI) transistor processing on the enhanced SOI BOX structure ofFIG. 4A in accordance with one preferred embodiment;
• FIG. 6 is a diagram not to scale illustrating further exemplary steps for a backside implant performed to dope an isolated region on the enhanced SOI BOX structure ofFIG. 4A for implementing an enhanced SOI BOX structure in accordance with another preferred embodiment;
• FIG. 7A is a diagram not to scale illustrating further exemplary steps for implementing silicon-on-insulator (SOI) transistor processing on the enhanced SOI BOX structure ofFIG. 6 in accordance with another preferred embodiment;
• FIG. 7B is diagram not to scale illustrating further exemplary steps for implementing metal-oxide semiconductor (MOS) processing on the enhanced SOI BOX structure ofFIG. 7A in accordance with another preferred embodiment;
• FIG. 8 is a diagram not to scale illustrating further exemplary steps for MOS and backside processing on the enhanced SOI BOX structure ofFIG. 7B for implementing an enhanced SOI BOX structure in accordance with another preferred embodiment;
• FIGS. 9A, 9B,10, and11 are diagrams not to scale illustrating exemplary steps for implementing an enhanced SOI BOX structure forming a novel backside anti-fuse (AF) structure in accordance with another preferred embodiment;
• FIGS. 12, 13,14, and15 are diagrams not to scale illustrating exemplary steps for implementing an enhanced SOI BOX structure for another novel backgate fuse structure for providing a programmable body contact in accordance with another preferred embodiment; and
• FIGS. 16, 17,18, and19 are diagrams not to scale illustrating exemplary steps for implementing self-aligned oxygen implants through a top or front side of an SOI structure in accordance with another preferred embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• In accordance with features of preferred embodiments, novel backgate processing methods and backgate structures are provided. The novel backgate processing methods and backgate structures provide preferential Si island strain for both NF and PF device mobility enhancement. Simultaneous thin and thick BOX regions are provided for minimized junction capacitance, and improved backgate coupling. A novel backgate Anti-Fuse structure using a Thin/Thick gate SOI device and another backgate Anti-Fuse (AF) structure of one of preferred embodiment is arranged for providing a programmable body contact.
• Referring now to the drawings,FIGS. 1-3,4A and4B illustrate exemplary steps for implementing enhanced SOI BOX structures in accordance with one preferred embodiment where preferential Si island strain for both NF and PF device mobility enhancement and simultaneous thin and thick BOX regions are provided for minimized junction capacitance, and improved backgate coupling. A non-self-aligned O+ implant is used to form thick box regions under MOS diffusions, or thick regions in the center of an active island. A bulk silicon substrate is first thinned, and an O+ Implant, selectively masked or unmasked, is introduced from the backside. In the region of the O+ implant, the resultant oxide after anneal is thickened. The thick BOX region may consume the entire remaining bulk Si, or a remaining SI layer may be left. The thin Si layer that remains in the vicinity of the thick oxide can be etched if desired.
• Referring initially toFIG. 1, there is shown an exemplary structure generally designated by thereference character100 for implementing enhanced SOI BOX structures of preferred embodiments.Structure100 includes asubstrate102, such as asilicon substrate102, a very thin buried oxide (BOX)layer104, such as an oxynitride layer, of thickness range 2 nm to 10 nm, a gate insulation layer or gate dielectric106 of EOT (electrically Equivalent Oxide Thickness) of 0.9 nm to 2 nm, an active layer orsilicon layer108 of thickness range 5 nm to 750 nm, and shallow trench isolation (STI)region112 formed over thethin BOX layer104. STIregion112 is continuous around the active device region.
• Referring now toFIG. 2, there is shown a nextexemplary structure200 where thesilicon substrate102 is first thinned, providing athin substrate layer202. For example, an initial thickness ofsilicon substrate102 as generally determined for each process technology is reduced either globally or locally to a thickness of 10 nm to 10,000 nm, preferably 500 nm.
• Referring now toFIG. 3, there is shown a nextexemplary structure300 where an oxygen implant step is performed as indicated by arrows O+ implant from the backside to provide a pair ofrespective oxygen implants302 in thethinned bulk substrate202 using anoptional mask304. The regions of oxygen implants are located, for example, under regions ofactive layer108 that are later used for forming source and drain of the SOI transistor. The oxygen implant step through the thinnedsubstrate layer202 is provided at a selected dose and energy level for formingrespective oxygen implants302 slightly below or vertically adjacent to layer108. The oxygen implant step through the backside ofthin substrate layer202 is provided, for example, at an energy level in a range from 20 to 200 KeV using a dose of in the range of 10¹⁶cm⁻²to 5×10¹⁸cm⁻².
• Referring now toFIG. 4A, there is shown a nextexemplary structure400 where all silicon is consumed with a central silicon region selectively removed as indicated byarrow402 and an anneal process convert theoxygen implants302 to a respectivethick BOX region404. Alternatively, the central silicon region indicated byarrow402 can be left in place. The anneal process is performed, for example, at a temperature between 600° C. to 135° C., preferably in a temperature range between 900° C. and 1100° C., for a period of several minutes to 10 hours in a non-reactive ambient.
• Referring now toFIG. 4B, there is shown another nextexemplary structure450 where athick BOX region452 extends across an entire device when theoptional mask304 is not used with the oxygen implant step ofFIG. 3. An anneal process forming thethick BOX region452 is performed, for example, at a temperature between 600° C. to 1350° C., preferably in a temperature range between 900° C. and 1100° C., for a period of several minutes to 10 hours.
• Referring now toFIG. 5, there is shown a next exemplary structure generally designated by thereference character500 for implementing silicon-on-insulator (SOI) transistor processing on the enhanced SOI BOX structure ofFIG. 4A in accordance with one preferred embodiment. Thepad oxide layer106 is stripped and agate oxide layer502 is grown. Agate electrode504 is formed. Thegate electrode504, such as polysilicon or ametal gate electrode504, has, for example, a thickness range 10 nm to 100 nm. Optionally a pair ofspacers506 is formed on the sidewalls of thegate electrode504. Also conventional front-end-of-line (FEOL) processing steps can be used to complete a transistor device. These steps can include but are not limited to source/drain implants, extension implants, silicide formation on the gate, source, and drain, and contact formation (not shown).
• Referring now toFIG. 6, there is shown a next exemplary structure generally designated by thereference character600 where a backside implant indicated by arrows is performed to dope anisolated region602 in the enhancedSOI BOX structure400 ofFIG. 4A for implementing an enhanced SOI BOX structure in accordance with another preferred embodiment.
• Referring now toFIG. 7A, there is shown a next exemplary structure generally designated by thereference character700 where further silicon-on-insulator (SOI) transistor processing steps are performed on the enhancedSOI BOX structure600 ofFIG. 6 in accordance with another preferred embodiment. Thepad oxide layer106 is stripped and agate oxide layer702 and agate electrode704 are formed. Thegate electrode704, such as polysilicon gate electrode has, for example, a thickness range 10 nm to 100 nm. As shown, a pair ofspacers706 optionally is formed on the sidewalls of thegate electrode704.
• Referring now toFIG. 7B, there is shown a next exemplary structure generally designated by thereference character750 where further metal-oxide semiconductor (MOS) processing steps are performed on the enhancedSOI BOX structure700 ofFIG. 7A in accordance with another preferred embodiment. Doping, formation and activation of each respective source/drain region752 and agate electrode754 are provided. Source/drain regions752 are implemented with appropriate strain for mobility improvement for both PFET and NFET devices such as SiGe epitaxy.
• Referring now toFIG. 8, there is shown a next exemplary structure generally designated by thereference character800 where further MOS and backside processing steps are performed on the enhancedSOI BOX structure750 ofFIG. 7B for implementing an enhanced SOI BOX structure in accordance with another preferred embodiment. Asilicide formation802 on the source and drainregions702, asuicide formation804 on thegate752, and asilicide formation806 on the doped isolatedisland region602 are provided for contact formation.
• Referring now toFIGS. 9A, 9B,10, and11, there are shown exemplary steps for implementing an enhanced SOI BOX structure forming a novel backside anti-fuse (AF) structure in accordance with another preferred embodiment.
• Referring now toFIG. 9A, there is shown an exemplary structure generally designated by thereference character900 for forming an enhanced SOI anti-fuse (AF) structure of this preferred embodiment.SOI structure900 results following a backside implant performed to dope theisolated region602 ofFIG. 6 to be used to make a gate or AF structure of this preferred embodiment. In addition, As can be implanted into the backside dielectric602 to weaken the backside dielectric.
• Referring now toFIG. 9B, there is shown a next exemplary structure generally designated by thereference character950 where a front side implant is preformed to provide a heavily dopedplate952 from theactive layer108 for forming an enhanced SOI anti-fuse (AF) structure of this preferred embodiment.
• Referring now toFIG. 10, there is shown a next exemplary structure generally designated by thereference character1000 where a silicide formation forms anindividual AF node1002 on the heavily dopedplate952, and a silicide formation forms a fuse common1004 on the doped isolated island region orbackgate region602 are provided for contact formation.
• Referring now toFIG. 11, there is shown a next exemplary structure generally designated by thereference character1100 where a fuse programming step indicated by line1102 is performed. Avoltage supply source1104 is connected between theindividual AF node1002 on the heavily dopedplate952, and the fuse common1004 on the doped isolatedisland region602 to provide the fuse programming1102 connection between the heavily dopedplate952 and the doped isolatedisland region602.
• Referring now toFIGS. 12, 13,14, and15 are diagrams not to scale illustrating exemplary steps for implementing an enhanced SOI BOX structure for another novel backgate fuse structure for providing a programmable body contact in accordance with another preferred embodiment.
• Referring now toFIG. 12, there is shown an exemplary structure generally designated by thereference character1200 for forming an enhanced SOI backgate structure to provide a programmable body contact of this preferred embodiment.SOI structure1200 results following an anneal step ofFIG. 4B. Abackgate1202 of the enhanced SOI backgate structure of this preferred embodiment is formed that is smaller than a front gate or agate electrode1204 so that alignment problems are avoided. As indicated by an arrow labeled GATE IMAGE, thegate electrode1204 or gate image is larger than thebackgate1202, as indicated by an arrow labeled BACKSIDE IMAGE. This size differential enables aligning the largerfront gate electrode1204 with thebackgate1202 without alignment problems.
• As shown inFIG. 12, agate oxide layer1206 and thegate electrode1204 are grown. Thegate electrode1204, such as polysilicon gate electrode has, for example, a thickness range 10 nm to 100 nm. As shown, a pair ofspacers1208 optionally is formed on the sidewalls of thegate electrode1204.
• Referring now toFIG. 13, there is shown a next exemplary structure generally designated by thereference character1300 where doping, formation and activation of each respective source/drain region1302 and agate electrode1304 are provided. Source/drain regions1302 are implemented with appropriate strain for mobility improvement for both PFET and NFET devices.
• Referring now toFIG. 14, there is shown a next exemplary structure generally designated by thereference character1400 where asilicide formation1402 is provided on each respective source/drain region1302 and asilicide formation1404 is provided on thebackgate1202. Abackside metal1406 is connected to thesilicide formation1402 and thebackgate1202, extending under thethick BOX region404 and is connected to astud contact1408. Thestud contact1408 extends from thebackside metal1406 through the thick and thin BOX layers404 and104, andSTI region112 enabling connection to thestud contact1408 above theSTI region112. Also asilicide formation1410 on thegate electrode1304 is provided.
• Referring now toFIG. 15, there is shown a next exemplary structure generally designated by the reference character1500 where aprogrammable body contact1502 is provided. A first voltage supply source V1,1504 is connected between thebackgate1202 via thestud contact1408 and thebackside metal1406 and the source/drain regions1302 via thesilicide formation1402. A second voltage supply source V2,1506 is connected between thefront gate electrode1304 and ground. Body tie programming indicated byprogrammable body contact1502 creating a resistive path between the active layer orchannel body108 and thebackgate1202 is provided by a voltage bias with the potential of the first voltage supply source V1,1504 greater than the potential of the second voltage supply source V2,1506.
• As shown inFIG. 15, the source anddrain regions1302 are wired as one of the fuse terminals and the backgate or buriedgate1202 is the other terminal. To read the programmable body contact orfuse1502, the buriedgate1202 is raised to a potential such that theback channel108 is in inversion and the leakage current between the buriedgate1202 and source/drain1302 is measured. To blow thefuse1502, the potential of the buriedgate1202 is raised to a higher potential that causes enough oxide damage to change the buried gate leakage current. Sensing the current before and after the fuse blow is used to detect a change in fuse state, optionally using anunblown device1502 for a current reference.
• Qualitative analysis or simulation has been performed for a method for operating thedevice1502, where the body contact of the SOI transistor and the gate are used to set the electric field across the back oxide in order to create oxide damage or breakdown. What this simulation shows is that for moderate well/halo doses and 90 nm type oxides (˜1 nm) and potentials, for example, 1.1 V across the oxide, sufficient field strength was achieved for causing oxide breakdown, such as electric field strength in excess of 10 MV/cm. Also the back oxide could be made intrinsically weaker by design to assist in this process.
• Referring now toFIGS. 16, 17,18, and19, there are shown exemplary steps for implementing self-aligned oxygen implants through a top or front side of an SOI structure in accordance with another preferred embodiment where preferential Si island strain for both NF and PF device mobility enhancement and simultaneous thin and thick BOX regions are provided for minimized junction capacitance, and improved backgate coupling.
• Referring now toFIG. 16, there is shown an exemplary structure generally designated by thereference character1600 for forming enhanced SOI transistors of this embodiment.Structure1600 includes asubstrate1602, such as asilicon substrate1602, a very thin buried oxide (BOX)layer1604, such as an oxynitride layer, of thickness range 2 nm to 10 nm, a gate insulation layer or gate dielectric1606 of EOT (electrically Equivalent Oxide Thickness) of 0.9 nm to 2 nm, an active layer orsilicon layer1608 of thickness range 5 nm to 750 nm, and agate electrode1610, such as polysilicon or ametal gate electrode1610 of thickness range 10 nm to 100 nm. Aprotective cap layer1612, such as a silicon nitride Si₃N₄cap1612 of thickness range 50 nm to 100 nm is formed above thegate electrode1610 of thickness range 13 nm to 30 nm preferably 18 nm, for example, that was etched in-situ. Shallow trench isolation (STI)region1614 is formed over thethin BOX layer1604.STI region1614 is continuous around the active device region. Arespective spacer1616 is formed on the sidewalls of thegate electrode1610 and theprotective cap1612. As shown, the gate stack contains the self aligneddisposable cap1612 anddisposable spacer1616 to protect thegate electrode1610 from damage. It is assumed in this embodiment theactive Si layer1608 is thin so that resultant damage in the silicon area is not a concern. Thegate cap1612 can be used to protect thegate electrode material1610 from dopant introduction, or silicon deposition, during the subsequent formation of source and drain junction regions by ion implanation and selective SiGe epixaxy (not shown).
• Referring now toFIG. 17, there is shown a next exemplary structure generally designated by thereference character1700 where an oxygen implant step is performed as indicated by arrows O+ implant. The O+ implant is self-aligned to thegate electrode structure1612. A plurality of self alignedoxygen implants1702 is used to form thick box regions under MOS diffusions. The oxygen implant step through the seed layer is provided, for example, at an energy level in a range from 20 to 200 KeV using a dose of in the range of 10¹⁶cm⁻²to 5×10¹⁸cm².
• Referring now toFIG. 18, there is shown a next exemplary structure generally designated by thereference character1800 where an anneal process is performed to convert theoxygen implants1702 to respectivethick box region1802 at a temperature between 600° C. to 1350° C., preferably in a temperature range between 900° C. and 1100° C., for a period of several minutes to 10 hours in an inert ambient.
• Referring now toFIG. 19, there is shown a next exemplary structure generally designated by thereference character1900 where in a next process strip nitride step, thenitride cap1612, and the Si₃N₄spacers1616 are removed. Subsequent to these steps selected backgate processing steps are performed as described above with respect to the other embodiments. Also conventional front-end-of-line (FEOL) processing steps can be used to complete a transistor device. These steps can include but are not limited to source/drain implants, extension implants, silicide formation on the gate, source, and drain, and contact formation (not shown).
• While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.

Claims (20)

1. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures comprising the steps of:

providing a thin buried oxide (BOX) layer under a device channel in a silicon substrate layer and a pad oxide layer carried by the active layer;

thinning the silicon substrate layer;

performing an oxygen implant step from the backside into the thinned silicon substrate layer; and

forming thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer.

2. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 1 wherein the oxygen implant step forms an isolated region near the oxygen implants.

3. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 2 includes a backside implant step for selectively doping the isolated region to form a backgate for an SOI device being formed, the SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.

4. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 3 includes forming a gate oxide and a gate electrode over the active region above the backgate.

5. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 4 includes doping each respective source/drain region and the gate electrode for forming the SOI transistor.

6. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 1 includes forming a gate oxide and a gate electrode over the active region above the backgate, said gate electrode having an image larger than a backgate image.

7. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 6 includes doping each respective source/drain region and the gate electrode for forming the SOI transistor.

8. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 7 includes forming a programmable body contact by applying a first voltage supply potential between the source/drain regions and the backgate and applying a second voltage supply potential between the gate electrode and ground, where the first voltage supply potential is greater than the second voltage supply potential.

9. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 3 includes providing a doping implant into the active layer above the backgate to form a doped plate region from the active layer.

10. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 9 includes forming a respective contact on the backgate and doped plate region to form respective anti-fuse (AF) connections.

11. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited inclaim 10 includes applying a voltage potential between the respective anti-fuse (AF) connections in a fuse programming step forming a conduction path between the backgate and doped plate region.

12. A silicon-on-insulator (SOI) buried oxide (BOX) structure comprising:

a thin buried oxide (BOX) layer;

an active channel region over said thin buried oxide (BOX) layer;

a pair of spaced apart thick buried oxide (BOX) regions;

an isolated region between said pair of spaced apart thick buried oxide (BOX) regions; said isolated region being selectively doped for forming a backgate for an SOI device to be formed.

13. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited inclaim 12 wherein the SOI device to be formed includes a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices

14. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited inclaim 12 wherein the SOI device to be formed is a SOI transistor including a gate oxide and a gate electrode over the active region above the backgate.

15. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited inclaim 14 wherein the gate electrode has a gate image larger than a backgate image.

16. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited inclaim 14 includes a respective source/drain region above respective thick buried oxide (BOX) regions forming the SOI transistor.

17. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited inclaim 16 includes a programmable body contact for creating a resistive path between the active layer and the backgate; said programmable body contact being formed by applying a first voltage supply potential between the source/drain regions and the backgate and applying a second voltage supply potential between the gate electrode and ground, where the first voltage supply potential is greater than the second voltage supply potential.

18. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited inclaim 12 wherein the SOI device to be formed is an anti-fuse (AF) device including a doped plate region in the active layer above the backgate.

19. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited inclaim 18 includes a respective contact on the backgate and doped plate region to form respective anti-fuse (AF) connections.

20. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited inclaim 19 includes a programmable fuse conduction path between the backgate and doped plate region; said programmable fuse conduction path formed by applying a voltage potential between the respective anti-fuse (AF) connections.

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