US20060216878A1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor deviceDownload PDFInfo
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- US20060216878A1 US20060216878A1US11/169,707US16970705AUS2006216878A1US 20060216878 A1US20060216878 A1US 20060216878A1US 16970705 AUS16970705 AUS 16970705AUS 2006216878 A1US2006216878 A1US 2006216878A1
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- 229910000577Silicon-germaniumInorganic materials0.000claimsabstractdescription22
- 239000000758substrateSubstances0.000claimsabstractdescription22
- 238000005530etchingMethods0.000claimsabstractdescription14
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- 238000000059patterningMethods0.000claimsabstractdescription3
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- 150000004767nitridesChemical class0.000claimsdescription20
- 238000001039wet etchingMethods0.000claimsdescription11
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- 238000001020plasma etchingMethods0.000claimsdescription2
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- 230000003247decreasing effectEffects0.000description1
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Classifications
- E—FIXED CONSTRUCTIONS
- E01—CONSTRUCTION OF ROADS, RAILWAYS, OR BRIDGES
- E01H—STREET CLEANING; CLEANING OF PERMANENT WAYS; CLEANING BEACHES; DISPERSING OR PREVENTING FOG IN GENERAL CLEANING STREET OR RAILWAY FURNITURE OR TUNNEL WALLS
- E01H5/00—Removing snow or ice from roads or like surfaces; Grading or roughening snow or ice
- E01H5/04—Apparatus propelled by animal or engine power; Apparatus propelled by hand with driven dislodging or conveying levelling elements, conveying pneumatically for the dislodged material
- E01H5/06—Apparatus propelled by animal or engine power; Apparatus propelled by hand with driven dislodging or conveying levelling elements, conveying pneumatically for the dislodged material dislodging essentially by non-driven elements, e.g. scraper blades, snow-plough blades, scoop blades
- E01H5/065—Apparatus propelled by animal or engine power; Apparatus propelled by hand with driven dislodging or conveying levelling elements, conveying pneumatically for the dislodged material dislodging essentially by non-driven elements, e.g. scraper blades, snow-plough blades, scoop blades characterised by the form of the snow-plough blade, e.g. flexible, or by snow-plough blade accessories
- E01H5/066—Snow-plough blade accessories, e.g. deflector plates, skid shoes
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Definitions
- the present inventiongenerally relates to a method for fabricating a semiconductor device, and more specifically to a method for fabricating a semiconductor device wherein a gate is formed on a stepped Si epitaxial layer in order to increase an effective length of a gate channel, and an oxide film is only formed at the interface of the Si epitaxial layer under a bit line contact and the semiconductor substrate, thereby improving a characteristic of a leakage current for a storage node junction.
- FIG. 1is a layout illustrating a conventional method for fabricating a semiconductor device, wherein reference numerals 1000 a, 1 , 2 and 3 denote a cell region, an active region, a first gate region and a second gate region, respectively.
- FIGS. 2 a through 2 fare cross-sectional views illustrating a conventional method for fabricating a semiconductor device, wherein FIGS. 2 a (i) through 2 f (i) are cross-sectional views taken along the line I-I′ in FIG. 1 , and FIGS. 2 a (ii) through 2 f (ii) are cross-sectional views in a core/peripheral circuit region 1000 b.
- a stacked structure of a SiGe epitaxial layer (not shown), a first Si epitaxial layer (not shown), a first oxide film (not shown) and a first nitride film (not shown)is formed on a semiconductor substrate 10 having a cell region 1000 a and a core/peripheral circuit region 1000 b defined therein.
- a first photoresist film(not shown) is deposited on the entire surface of the first nitride film (not shown) in the cell region 1000 a and the core/peripheral circuit region 1000 b.
- the first photoresist film(not shown) is exposed and developed to form a first photoresist film pattern (not shown) exposing the first gate region 2 of FIG. 1 and cover the entire core/peripheral circuit region 1000 b.
- the stacked structureis etched using the first photoresist film pattern as an etching mask to expose the semiconductor substrate 10 of the first gate region 2 and the entire core/peripheral circuit region 1000 b.
- the first photoresist film patternis then removed.
- a first nitride film pattern 19 and a first oxide film pattern 17 in the cell region 1000 aare removed via a wet etching method.
- a second Si expitaxial layer 25is formed on the entire surface of the cell region 1000 a and the core/peripheral circuit region 1000 b.
- a second oxide film 30 and a second nitride film 35are formed on the second Si epitaxial layer 25 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
- a second photoresist film(not shown) is deposited on the entire surface of the second nitride film 35 .
- the second photoresist filmis then exposed and developed to form a second photoresist film pattern (not shown) defining the active region 1 of FIG. 1 in the cell region 1000 a , and also an active region in the core/peripheral circuit region 1000 b.
- the second nitride film 35 , the second oxide film 30 , the second Si epitaxial layer 25 , the first Si epitaxial layer pattern 15 , the SiGe epitaxial layer pattern 13 and a predetermined thickness of the semiconductor substrate 10are etched using the second photoresist film pattern as an etching mask to form a trench 40 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
- the second photoresist film pattern(not shown) is removed.
- the SiGe epitaxial layer pattern 13is then etched through a sidewall of the trench 40 via a wet etching method to form a space 27 under the first Si epitaxial layer pattern 15 .
- a gap-filling insulating film 45is formed on the entire surface to fill up the space 27 and the trench 40 in the cell region 1000 a and to fill up the trench 40 in the core/peripheral circuit region 1000 b.
- the gap-filling insulating film 45is polished until the second nitride film 35 is exposed.
- the gap-filling insulating film 45serves as a device isolation film.
- a predetermined thickness of the gap-filling insulating film 45 in the trench 40is etched.
- the second nitride film 35is then removed via a wet etching method.
- a well implant process and a channel implant processare performed so as to adjust impurity concentrations in the cell region 1000 a and the core/peripheral circuit region 1000 b.
- the second oxide film 30 in the cell region 1000 a and the core/peripheral circuit region 1000 bis removed via a wet etching method to expose the second Si epitaxial layer 25 .
- a gate oxide film 50is then formed on the exposed second Si epitaxial layer 25 .
- gate conductive layers 60 and 70 , and a hard mask insulating film 80are formed on the gate oxide film 50 and the gap-filling insulating film 45 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
- a third photoresist film(not shown) is deposited on the hard mask insulating film 80 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
- the third photoresist film(not shown) is exposed and developed to form a third photoresist film pattern defining the second gate region 3 of FIG. 1 and a gate region (not shown) in the core/peripheral circuit region 1000 b .
- the third photoresist film patternexposes a bit line contact region and storage node contact regions in the cell region 1000 a and covers a region where a gate is to be formed in the core/peripheral circuit region 1000 b.
- the hard mask insulating film 80 and the gate conductive layers 70 and 60are etched using the third photoresist film pattern as an etching mask to respectively form a gate 90 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
- the gate 90 of the active regionis formed on a plane second Si epitaxial layer. As a result, a gate channel length is decreased as a design rule of the semiconductor device is reduced.
- an oxide filmis formed at the interface of the Si epitaxial layer under a storage node contact and the semiconductor substrate. Accordingly, the leakage current for a storage node junction is highly depended upon an interface characteristic between the Si epitaxial layer and an oxide film.
- the SiGe epitaxial layer under the storage node contactis removed for forming a device isolation film.
- Ge in the SiGe epitaxial layeris diffused into the first Si epitaxial layer, the second Si epitaxial layer and the semiconductor substrate due to heat treatment processes prior to the formation of the device isolation film. Accordingly, there is a problem such as increase in the leakage current for the storage node junction.
- FIG. 1is a layout illustrating a conventional method for fabricating a semiconductor device.
- FIGS. 2 a through 2 fare cross-sectional views illustrating a conventional method for fabricating a semiconductor device.
- FIG. 3is a layout illustrating a method for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.
- FIGS. 4 a through 4 f and FIG. 5are cross-sectional views illustrating a method for fabricating a semiconductor device according to a preferred embodiment of the present invention.
- FIG. 3is a layout illustrating a method for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention, wherein reference numerals 2000 a , 101 , 102 and 103 denote a cell region, an active region, a contact region and a gate region, respectively.
- FIGS. 4 a through 4 fillustrate a method for fabricating a semiconductor device according to a preferred embodiment of the present invention, wherein FIGS. 4 a (i) through 4 f (i) are cross-sectional views taken along the line II-II′ of FIG. 3 , and FIGS. 4 a (ii) through 4 f (ii) are cross-sectional views in a core/peripheral circuit region 2000 b.
- a stacked structure of a SiGe epitaxial layer (not shown), a first Si epitaxial layer (not shown) and an insulating film (not shown)is formed on a semiconductor substrate 110 having a cell region 2000 a and a core/peripheral circuit region 2000 b defined therein.
- the insulating filmcomprises an oxide film or a stacked structure of an oxide film and a nitride film.
- a first photoresist film(not shown) is deposited on the entire surface of the insulating film in the cell region 2000 a and the core/peripheral circuit region 2000 b.
- the contact region 102includes a storage node contact region and a portion of the gate region 103 adjacent thereto.
- the portion of the gate region 103has a line width of M ranging from 1 ⁇ 3F to F, where F is a gate line width.
- the stacked structureis etched using the first photoresist film pattern as an etching mask to expose the semiconductor substrate 110 of the contact region 102 and the entire core/peripheral circuit region 2000 b.
- the first photoresist film patternis then removed.
- an insulating film pattern 120 in the cell region 2000 ais removed.
- the removal process for the insulating film pattern 120is performed via a wet etching method.
- a second Si epitaxial layer 125is formed on the entire surface of the cell region 2000 a and the core/peripheral circuit region 2000 b .
- a thickness of the second Si epitaxial layer 125ranges from 10 nm to 100 nm.
- the second epitaxial layer 125 in the cell region 2000 amay have a step difference due to the first Si epitaxial layer pattern 115 and the SiGe epitaxial layer pattern 113 .
- a second oxide film 130 and a second nitride film 135are formed on the second Si epitaxial layer 125 in the cell region 2000 a and the core/peripheral circuit region 2000 b.
- a second photoresist film(not shown) is deposited on the entire surface of the second nitride film 135 .
- the photoresist filmis then exposed and developed to form a second photoresist film pattern (not shown) defining the active region 101 of FIG. 3 in the cell region 2000 a and also an active region in the core/peripheral circuit region 2000 b.
- the second nitride film 135 , the second oxide film 130 , the second Si epitaxial layer 125 , the first Si epitaxial layer pattern 115 , the SiGe epitaxial layer pattern 113 and a predetermined thickness of the semiconductor substrate 110are etched using the second photoresist film pattern as an etching mask to form a trench 140 in the cell region 2000 a and the core/peripheral circuit region 2000 b.
- the second photoresist film pattern(not shown) is removed.
- the SiGe epitaxial layer pattern 113is then etched through a sidewall of the trench 140 to form a space 127 under the first Si epitaxial layer pattern 115 .
- FIG. 5is a cross-sectional view taken along the line III-III′ of FIG. 3 illustrating the structure of FIG. 4 c (i) including the space 127 having a undercut structure.
- the removal process for the SiGe epitaxial layer pattern 113is preformed via a wet etching method utilizing a mixed etchant containing HF, H 2 O 2 and CH 3 CHOOH, a plasma etching method utilizing a mixed gas containing (CF 3 or CH 2 F 2 ), N 2 and O 2 , or combinations thereof.
- a volume ratio of HF, H 2 O 2 and CH 3 COOH in the mixed etchantis preferably 1:2:3.
- a gap-filling insulating film 145is formed on the entire surface to at least fill up the space 127 and the trench 140 in the cell region 2000 a and to fill up the trench 140 in the core/peripheral circuit region 2000 b.
- the formation process of the gap-filling insulating film 145may include forming a thermal oxide film filling up the space 127 and forming an oxide film for a device isolation film filling up the trench 140 .
- a nitride filmmay be further formed at an interface of the thermal oxide film and the oxide film for the device isolation film.
- the formation process of the gap-filling insulating film 145may include forming a thermal oxide film to fill up a portion of the space 127 , forming a nitride film to fill up the remaining portion of the space 127 , and forming an oxide film for the device isolation film to fill up the trench 140 .
- the gap-filling insulating film 145is polished until the second nitride film 135 is exposed.
- the gap-filling insulating film 145 in the trench 140serves as a device isolation film.
- a predetermined thickness of the gap-filling insulating film 145 in the trench 140is etched.
- the second nitride film 135is then removed.
- the etching process for the gap-fill insulating film 145is performed via a wet etching method.
- the removal process for the second nitride film 135is preferably preformed via a wet etching method.
- well implant processes and channel implant processesare performed so as to respectively adjust impurity concentrations in the cell region 2000 a and the core/peripheral circuit region 2000 b.
- the second oxide film 130 in the cell region 2000 a and the core/peripheral circuit region 2000 bis removed to expose the second Si epitaxial layer 125 .
- a gate oxide film 150is then formed on the exposed second Si epitaxial layer 125 .
- the removal process for the second oxide film 130is performed via a wet etching method.
- a stacked structure of a gate conductive layer 175 and a hard mask layer 180is formed on the gate oxide film 150 and the gap-filling insulating film 145 in the cell region 2000 a and the core/peripheral circuit region 2000 b .
- the gate conductive layer 175comprises a lower conductive layer 160 and an upper conductive layer 170 .
- a third photoresist film(not shown) is deposited on the hard mask layer 180 in the cell region 2000 a and the core/peripheral circuit region 2000 b.
- the third photoresist film(not shown) is exposed and developed to form a third photoresist film pattern defining the gate region 103 of FIG. 3 and a gate region (not shown) in the core/peripheral circuit region 2000 b .
- the third photoresist film patternexposes a bit line contact region and storage node contact regions in the cell region 2000 a and covers a region where a gate is to be formed in the core/peripheral circuit region 2000 b.
- the stacked structureis patterned using the third photoresist film pattern as an etching mask to respectively form a gate 190 in the cell region 2000 a and the core/peripheral circuit region 2000 b.
- subsequent processessuch as an ion-implant process for forming source/drain regions in the active regions, a process for forming a spacer on a sidewall of the gate 190 , a process for forming a landing plug, a process for forming a bit line contact and a bit line, a process for forming a capacitor and a process for forming an interconnect may be done.
- the method for fabricating a semiconductor device in accordance with the present inventionprovides exposing the contact region including the storage node contact region and a portion of the gate region adjacent thereto and only forming an oxide film at the interface of the Si epitaxial layer under both a bit line contact and the semiconductor substrate. Accordingly, capacitance for a bit line contact and a short-channel effect of a cell transistor are improved.
- the gate 190 in the cell region 2000 ais formed on a structure having a step difference instead of over a plane structure to increase an effective length of the gate channel, and the storage node contact is formed on the Si epitaxial layer without the oxide film to minimize the leakage current of the storage node junction. Accordingly, a refresh characteristic of a DRAM can be improved.
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Abstract
Description
- 1. Field of the Invention
- The present invention generally relates to a method for fabricating a semiconductor device, and more specifically to a method for fabricating a semiconductor device wherein a gate is formed on a stepped Si epitaxial layer in order to increase an effective length of a gate channel, and an oxide film is only formed at the interface of the Si epitaxial layer under a bit line contact and the semiconductor substrate, thereby improving a characteristic of a leakage current for a storage node junction.
- 2. Description of the Related Art
FIG. 1 is a layout illustrating a conventional method for fabricating a semiconductor device, whereinreference numerals FIGS. 2 athrough2fare cross-sectional views illustrating a conventional method for fabricating a semiconductor device, whereinFIGS. 2 a(i) through2f(i) are cross-sectional views taken along the line I-I′ inFIG. 1 , andFIGS. 2 a(ii) through2f(ii) are cross-sectional views in a core/peripheral circuit region 1000b.- Referring to
FIG. 2 a, a stacked structure of a SiGe epitaxial layer (not shown), a first Si epitaxial layer (not shown), a first oxide film (not shown) and a first nitride film (not shown) is formed on asemiconductor substrate 10 having acell region 1000aand a core/peripheral circuit region 1000bdefined therein. - Next, a first photoresist film (not shown) is deposited on the entire surface of the first nitride film (not shown) in the
cell region 1000aand the core/peripheral circuit region 1000b. - Thereafter, the first photoresist film (not shown) is exposed and developed to form a first photoresist film pattern (not shown) exposing the
first gate region 2 ofFIG. 1 and cover the entire core/peripheral circuit region 1000b. - After that, the stacked structure is etched using the first photoresist film pattern as an etching mask to expose the
semiconductor substrate 10 of thefirst gate region 2 and the entire core/peripheral circuit region 1000b. - The first photoresist film pattern is then removed.
- Referring
FIG. 2 b, a firstnitride film pattern 19 and a first oxide film pattern17 in thecell region 1000aare removed via a wet etching method. - Next, a second Si
expitaxial layer 25 is formed on the entire surface of thecell region 1000aand the core/peripheral circuit region 1000b. - Referring to
FIG. 2 c, asecond oxide film 30 and asecond nitride film 35 are formed on the second Siepitaxial layer 25 in thecell region 1000aand the core/peripheral circuit region 1000b. - Next, a second photoresist film (not shown) is deposited on the entire surface of the
second nitride film 35. The second photoresist film is then exposed and developed to form a second photoresist film pattern (not shown) defining the active region1 ofFIG. 1 in thecell region 1000a, and also an active region in the core/peripheral circuit region 1000b. - Thereafter, the
second nitride film 35, thesecond oxide film 30, the second Siepitaxial layer 25, the first Siepitaxial layer pattern 15, the SiGeepitaxial layer pattern 13 and a predetermined thickness of thesemiconductor substrate 10 are etched using the second photoresist film pattern as an etching mask to form atrench 40 in thecell region 1000aand the core/peripheral circuit region 1000b. - After that, the second photoresist film pattern (not shown) is removed. The SiGe
epitaxial layer pattern 13 is then etched through a sidewall of thetrench 40 via a wet etching method to form a space27 under the first Siepitaxial layer pattern 15. - Referring to
FIG. 2 d, a gap-filling insulatingfilm 45 is formed on the entire surface to fill up the space27 and thetrench 40 in thecell region 1000aand to fill up thetrench 40 in the core/peripheral circuit region 1000b. - Next, the gap-filling insulating
film 45 is polished until thesecond nitride film 35 is exposed. The gap-filling insulatingfilm 45 serves as a device isolation film. - Thereafter, a predetermined thickness of the gap-filling insulating
film 45 in thetrench 40 is etched. Thesecond nitride film 35 is then removed via a wet etching method. - After that, a well implant process and a channel implant process are performed so as to adjust impurity concentrations in the
cell region 1000aand the core/peripheral circuit region 1000b. - Referring to
FIG. 2 e, thesecond oxide film 30 in thecell region 1000aand the core/peripheral circuit region 1000bis removed via a wet etching method to expose the second Siepitaxial layer 25. Agate oxide film 50 is then formed on the exposed second Siepitaxial layer 25. - Next, gate
conductive layers mask insulating film 80 are formed on thegate oxide film 50 and the gap-filling insulatingfilm 45 in thecell region 1000aand the core/peripheral circuit region 1000b. - Referring to
FIG. 2 f, a third photoresist film (not shown) is deposited on the hardmask insulating film 80 in thecell region 1000aand the core/peripheral circuit region 1000b. - Thereafter, the third photoresist film (not shown) is exposed and developed to form a third photoresist film pattern defining the
second gate region 3 ofFIG. 1 and a gate region (not shown) in the core/peripheral circuit region 1000b. Specifically, the third photoresist film pattern exposes a bit line contact region and storage node contact regions in thecell region 1000aand covers a region where a gate is to be formed in the core/peripheral circuit region 1000b. - Next, the hard
mask insulating film 80 and the gateconductive layers gate 90 in thecell region 1000aand the core/peripheral circuit region 1000b. - However, in accordance with the above-described conventional method, the
gate 90 of the active region is formed on a plane second Si epitaxial layer. As a result, a gate channel length is decreased as a design rule of the semiconductor device is reduced. - Moreover, an oxide film is formed at the interface of the Si epitaxial layer under a storage node contact and the semiconductor substrate. Accordingly, the leakage current for a storage node junction is highly depended upon an interface characteristic between the Si epitaxial layer and an oxide film.
- In addition, the SiGe epitaxial layer under the storage node contact is removed for forming a device isolation film. As a result, Ge in the SiGe epitaxial layer is diffused into the first Si epitaxial layer, the second Si epitaxial layer and the semiconductor substrate due to heat treatment processes prior to the formation of the device isolation film. Accordingly, there is a problem such as increase in the leakage current for the storage node junction.
- It is an object of the present invention to provide a method for fabricating a semiconductor device wherein a gate is formed on a stepped Si epitaxial layer to increase an effective length of a gate channel, and an oxide film is only formed at the interface of the Si epitaxial layer under a bit line contact and the semiconductor substrate, thereby improving a characteristic of a leakage current for a storage node junction.
- In order to achieve the object of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps:
- (a) forming a SiGe epitaxial layer, a first Si epitaxial layer and an insulating film on a semiconductor substrate, (b) etching a predetermined region of the insulating film, the first Si epitaxial layer and the SiGe epitaxial layer to expose the semiconductor substrate, wherein the predetermined region includes a storage node contact region and a portion of a gate region adjacent thereto, (c) removing the insulating film, (d) forming a second Si epitaxial layer on the entire surface including the exposed semiconductor substrate, (e) etching the second Si epitaxial layer, the first Si epitaxial layer, the SiGe epitaxial layer and a predetermined thickness of the semiconductor substrate to form a trench defining an active region, (f) removing the SiGe epitaxial layer through a sidewall of the trench to form a space under the first Si epitaxial layer, (g) forming a gap-filling insulating film to at least fill up the space and the trench, (h) forming a gate oxide film on the second Si epitaxial layer, and (i) depositing and patterning a gate conductive layer and a hard mask layer on the entire surface to form a gate in the gate region.
FIG. 1 is a layout illustrating a conventional method for fabricating a semiconductor device.FIGS. 2 athrough2fare cross-sectional views illustrating a conventional method for fabricating a semiconductor device.FIG. 3 is a layout illustrating a method for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.FIGS. 4 athrough4fandFIG. 5 are cross-sectional views illustrating a method for fabricating a semiconductor device according to a preferred embodiment of the present invention.- Reference will now be made in detail to exemplary embodiments of the present invention. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
FIG. 3 is a layout illustrating a method for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention, whereinreference numerals FIGS. 4 athrough4fillustrate a method for fabricating a semiconductor device according to a preferred embodiment of the present invention, whereinFIGS. 4 a(i) through4f(i) are cross-sectional views taken along the line II-II′ ofFIG. 3 , andFIGS. 4 a(ii) through4f(ii) are cross-sectional views in a core/peripheral circuit region 2000b.- Referring to
FIG. 4 a, a stacked structure of a SiGe epitaxial layer (not shown), a first Si epitaxial layer (not shown) and an insulating film (not shown) is formed on asemiconductor substrate 110 having acell region 2000aand a core/peripheral circuit region 2000bdefined therein. Preferably, the insulating film comprises an oxide film or a stacked structure of an oxide film and a nitride film. - Next, a first photoresist film (not shown) is deposited on the entire surface of the insulating film in the
cell region 2000aand the core/peripheral circuit region 2000b. - Thereafter, the first photoresist film (not shown) is exposed and developed to form a first photoresist film pattern (not shown) exposing the
contact region 102 of FIG.3 and cover the entire core/peripheral circuit region 2000b. Thecontact region 102 includes a storage node contact region and a portion of thegate region 103 adjacent thereto. Preferably, the portion of thegate region 103 has a line width of M ranging from ⅓F to F, where F is a gate line width. - After that, the stacked structure is etched using the first photoresist film pattern as an etching mask to expose the
semiconductor substrate 110 of thecontact region 102 and the entire core/peripheral circuit region 2000b. - The first photoresist film pattern is then removed.
- Referring to
FIG. 4 b, aninsulating film pattern 120 in thecell region 2000ais removed. Preferably, the removal process for theinsulating film pattern 120 is performed via a wet etching method. - Next, a second
Si epitaxial layer 125 is formed on the entire surface of thecell region 2000aand the core/peripheral circuit region 2000b. Preferably, a thickness of the secondSi epitaxial layer 125 ranges from 10 nm to 100 nm. - The
second epitaxial layer 125 in thecell region 2000amay have a step difference due to the first Siepitaxial layer pattern 115 and the SiGeepitaxial layer pattern 113. - Referring to
FIG. 4 c, asecond oxide film 130 and asecond nitride film 135 are formed on the secondSi epitaxial layer 125 in thecell region 2000aand the core/peripheral circuit region 2000b. - Next, a second photoresist film (not shown) is deposited on the entire surface of the
second nitride film 135. The photoresist film is then exposed and developed to form a second photoresist film pattern (not shown) defining theactive region 101 ofFIG. 3 in thecell region 2000aand also an active region in the core/peripheral circuit region 2000b. - Thereafter, the
second nitride film 135, thesecond oxide film 130, the secondSi epitaxial layer 125, the first Siepitaxial layer pattern 115, the SiGeepitaxial layer pattern 113 and a predetermined thickness of thesemiconductor substrate 110 are etched using the second photoresist film pattern as an etching mask to form atrench 140 in thecell region 2000aand the core/peripheral circuit region 2000b. - After that, the second photoresist film pattern (not shown) is removed. The SiGe
epitaxial layer pattern 113 is then etched through a sidewall of thetrench 140 to form aspace 127 under the first Siepitaxial layer pattern 115. FIG. 5 is a cross-sectional view taken along the line III-III′ ofFIG. 3 illustrating the structure ofFIG. 4 c(i) including thespace 127 having a undercut structure.- Preferably, the removal process for the SiGe
epitaxial layer pattern 113 is preformed via a wet etching method utilizing a mixed etchant containing HF, H2O2and CH3CHOOH, a plasma etching method utilizing a mixed gas containing (CF3or CH2F2), N2and O2, or combinations thereof. Moreover, a volume ratio of HF, H2O2and CH3COOH in the mixed etchant is preferably 1:2:3. - Referring to
FIG. 4 d, a gap-fillinginsulating film 145 is formed on the entire surface to at least fill up thespace 127 and thetrench 140 in thecell region 2000aand to fill up thetrench 140 in the core/peripheral circuit region 2000b. - Preferably, the formation process of the gap-filling
insulating film 145 may include forming a thermal oxide film filling up thespace 127 and forming an oxide film for a device isolation film filling up thetrench 140. A nitride film may be further formed at an interface of the thermal oxide film and the oxide film for the device isolation film. - Moreover, the formation process of the gap-filling
insulating film 145 may include forming a thermal oxide film to fill up a portion of thespace 127, forming a nitride film to fill up the remaining portion of thespace 127, and forming an oxide film for the device isolation film to fill up thetrench 140. - Next, the gap-filling
insulating film 145 is polished until thesecond nitride film 135 is exposed. The gap-fillinginsulating film 145 in thetrench 140 serves as a device isolation film. - Thereafter, a predetermined thickness of the gap-filling
insulating film 145 in thetrench 140 is etched. Thesecond nitride film 135 is then removed. Preferably, the etching process for the gap-fill insulating film 145 is performed via a wet etching method. The removal process for thesecond nitride film 135 is preferably preformed via a wet etching method. - After that, well implant processes and channel implant processes are performed so as to respectively adjust impurity concentrations in the
cell region 2000aand the core/peripheral circuit region 2000b. - Referring to
FIG. 4 e, thesecond oxide film 130 in thecell region 2000aand the core/peripheral circuit region 2000bis removed to expose the secondSi epitaxial layer 125. Agate oxide film 150 is then formed on the exposed secondSi epitaxial layer 125. Preferably, the removal process for thesecond oxide film 130 is performed via a wet etching method. - Next, a stacked structure of a gate
conductive layer 175 and ahard mask layer 180 is formed on thegate oxide film 150 and the gap-fillinginsulating film 145 in thecell region 2000aand the core/peripheral circuit region 2000b. Preferably, the gateconductive layer 175 comprises a lowerconductive layer 160 and an upperconductive layer 170. - Referring to
FIG. 4 f, a third photoresist film (not shown) is deposited on thehard mask layer 180 in thecell region 2000aand the core/peripheral circuit region 2000b. - Thereafter, the third photoresist film (not shown) is exposed and developed to form a third photoresist film pattern defining the
gate region 103 ofFIG. 3 and a gate region (not shown) in the core/peripheral circuit region 2000b. Specifically, the third photoresist film pattern exposes a bit line contact region and storage node contact regions in thecell region 2000aand covers a region where a gate is to be formed in the core/peripheral circuit region 2000b. - Next, the stacked structure is patterned using the third photoresist film pattern as an etching mask to respectively form a
gate 190 in thecell region 2000aand the core/peripheral circuit region 2000b. - In addition, subsequent processes such as an ion-implant process for forming source/drain regions in the active regions, a process for forming a spacer on a sidewall of the
gate 190, a process for forming a landing plug, a process for forming a bit line contact and a bit line, a process for forming a capacitor and a process for forming an interconnect may be done. - As described above, the method for fabricating a semiconductor device in accordance with the present invention provides exposing the contact region including the storage node contact region and a portion of the gate region adjacent thereto and only forming an oxide film at the interface of the Si epitaxial layer under both a bit line contact and the semiconductor substrate. Accordingly, capacitance for a bit line contact and a short-channel effect of a cell transistor are improved.
- As shown in
FIG. 4 f, thegate 190 in thecell region 2000ais formed on a structure having a step difference instead of over a plane structure to increase an effective length of the gate channel, and the storage node contact is formed on the Si epitaxial layer without the oxide film to minimize the leakage current of the storage node junction. Accordingly, a refresh characteristic of a DRAM can be improved. - The foregoing description of various embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated.
Claims (12)
1. A method for fabricating a semiconductor device, comprising the steps of:
(a) forming a SiGe epitaxial layer, a first Si epitaxial layer and an insulating film on a semiconductor substrate;
(b) etching a predetermined region of the insulating film, the first Si epitaxial layer and the SiGe epitaxial layer to expose the semiconductor substrate, wherein the predetermined region includes a storage node contact region and a portion of a gate region adjacent thereto;
(c) removing the insulating film;
(d) forming a second Si epitaxial layer on the entire surface including the exposed semiconductor substrate;
(e) etching the second Si epitaxial layer, the first Si epitaxial layer, the SiGe epitaxial layer and a predetermined thickness of the semiconductor substrate to form a trench defining an active region;
(f) removing the SiGe epitaxial layer through a sidewall of the trench to form a space under the first Si epitaxial layer;
(g) forming a gap-filling insulating film to at least fill up the space and the trench;
(h) forming a gate oxide film on the second Si epitaxial layer; and
(i) depositing and patterning a gate conductive layer and a hard mask layer on the entire surface to form a gate in the gate region.
2. The method according toclaim 1 , wherein the step (b) comprises:
forming a photoresist film on the entire surface of the semiconductor substrate;
forming a photoresist film pattern exposing the predetermined region by exposing and developing the photoresist film, wherein the portion of the gate region of the predetermined region has a line width of M; and
etching the insulating film, the Si epitaxial layer and the SiGe epitaxial layer using the photoresist film pattern as an etching mask.
3. The method according toclaim 2 , wherein the M ranges from ⅓F to F, wherein F is a gate line width.
4. The method according toclaim 1 , wherein the insulating film comprises an oxide film.
5. The method according toclaim 1 , wherein the insulating film comprises a stacked structure of an oxide film and a nitride film.
6. The method according toclaim 1 , wherein the removal process for the insulating film in the step (e) is performed via a wet etching method.
7. The method according toclaim 1 , wherein a thickness of the second Si epitaxial layer ranges from 10 to 100 nm.
8. The method according toclaim 1 , wherein the removal process for the SiGe epitaxial layer in the step (f) is performed via one method selected from the group consisting of a wet etching method utilizing a mixed etchant containing HF, H2O2and CH3COOH, a plasma etching method utilizing a mixed gas containing (CF4or CH2F2), N2and O2, and combinations thereof.
9. The method according toclaim 8 , wherein a volume ratio of HF, H2O2and CH3COOH in the mixed etchant is 1:2:3.
10. The method according toclaim 1 , wherein the step (g) comprises:
forming a thermal oxide film filling up the space; and
forming an oxide film for a device isolation film to fill up the trench.
11. The method according toclaim 10 , further comprising
forming a nitride film at the interface of the thermal oxide film and the oxide film for the device isolation film.
12. The method according toclaim 1 , wherein the step (g) comprises:
forming a thermal oxide film to fill a portion of the space;
forming a nitride film to fill up a remaining portion of the space; and
forming an oxide film for the device isolation film to fill up the trench.
Priority Applications (2)
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|---|---|---|---|
| US11/822,650US7652331B2 (en) | 2005-03-25 | 2007-07-09 | Semiconductor device and method for fabricating the same |
| US12/693,389US20100197123A1 (en) | 2005-03-25 | 2010-01-25 | Method for fabricating semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050024932AKR100610465B1 (en) | 2005-03-25 | 2005-03-25 | Manufacturing Method of Semiconductor Device |
| KR10-2005-0024932 | 2005-03-25 |
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| US11/822,650Continuation-In-PartUS7652331B2 (en) | 2005-03-25 | 2007-07-09 | Semiconductor device and method for fabricating the same |
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| US20060216878A1true US20060216878A1 (en) | 2006-09-28 |
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| US11/822,650Expired - Fee RelatedUS7652331B2 (en) | 2005-03-25 | 2007-07-09 | Semiconductor device and method for fabricating the same |
| US12/693,389AbandonedUS20100197123A1 (en) | 2005-03-25 | 2010-01-25 | Method for fabricating semiconductor device |
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| US11/822,650Expired - Fee RelatedUS7652331B2 (en) | 2005-03-25 | 2007-07-09 | Semiconductor device and method for fabricating the same |
| US12/693,389AbandonedUS20100197123A1 (en) | 2005-03-25 | 2010-01-25 | Method for fabricating semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US20060216878A1 (en) |
| JP (1) | JP2006279009A (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI267921B (en) | 2006-12-01 |
| US7652331B2 (en) | 2010-01-26 |
| KR100610465B1 (en) | 2006-08-08 |
| US20070284655A1 (en) | 2007-12-13 |
| US20100197123A1 (en) | 2010-08-05 |
| TW200634930A (en) | 2006-10-01 |
| JP2006279009A (en) | 2006-10-12 |
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