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US20060184462A1 - Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems - Google Patents

Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems
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Publication number
US20060184462A1
US20060184462A1US11/010,243US1024304AUS2006184462A1US 20060184462 A1US20060184462 A1US 20060184462A1US 1024304 AUS1024304 AUS 1024304AUS 2006184462 A1US2006184462 A1US 2006184462A1
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processing unit
patterns
sequence
information
pattern
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US11/010,243
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Jeffrey Hawkins
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Numenta Inc
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Numenta Inc
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Priority to US11/010,243priorityCriticalpatent/US20060184462A1/en
Priority to PCT/US2005/044729prioritypatent/WO2006063291A2/en
Priority to CNA2005800422587Aprioritypatent/CN101107618A/en
Priority to CA002589491Aprioritypatent/CA2589491A1/en
Priority to EP05853611Aprioritypatent/EP1836657A2/en
Assigned to NUMENTA, INC.reassignmentNUMENTA, INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: GEORGE, DILEEP, HAWKINS, JEFFREY C.
Publication of US20060184462A1publicationCriticalpatent/US20060184462A1/en
Priority to IL183625Aprioritypatent/IL183625A0/en
Priority to US12/040,849prioritypatent/US8175981B2/en
Priority to US13/438,670prioritypatent/US9530091B2/en
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Abstract

Sophisticated memory systems and intelligent machines may be constructed by creating an active memory system with a hierarchical architecture. Specifically, a system may comprise a plurality of individual cortical processing units arranged into a hierarchical structure. Each individual cortical processing unit receives a sequence of patterns as input. Each cortical processing unit processes the received input sequence of patterns using a memory containing previously encountered sequences with structure and outputs another pattern. As several input sequences are processed by a cortical processing unit, it will therefore generate a sequence of patterns on its output. The sequence of patterns on its output may be passed as an input to one or more cortical processing units in next higher layer of the hierarchy. A lowest layer of cortical processing units may receive sensory input from the outside world. The sensory input also comprises a sequence of patterns.

Description

Claims (43)

27. A method, comprising:
inputting a first sensed pattern to a first processing unit;
inputting a second sensed pattern to a second processing unit;
in response to inputting the first sensed pattern, determining a first distribution having at least one possible cause of the first sensed pattern dependent on at least one sequence of patterns stored in the first processing unit;
in response to inputting the second sensed pattern, determining a second distribution having at least one possible cause of the second sensed pattern dependent on at least one sequence of patterns stored in the second processing unit;
passing the first distribution and the second distribution to a third processing unit; and
determining a cause of the first sensed pattern and the second sensed pattern at least partially dependent on at least one operation performed on the first distribution and the second distribution by the third processing unit.
34. An apparatus, comprising:
a representation of a lower level of processing units, wherein the lower level processing units are arranged to output information regarding possible causes of sequences of sensed input patterns dependent on stored sequences previously learned by the lower level processing units; and
a representation of a higher level of at least one processing unit, wherein the at least one higher level processing unit is arranged to input the output information from the lower level processing units and output information regarding at least one possible cause of the sequences dependent on stored sequences previously learned by the higher level processing unit,
wherein the lower level of processing units and the higher level of at least one processing unit collectively represent at least part of a hierarchical network.
US11/010,2432004-12-102004-12-10Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systemsAbandonedUS20060184462A1 (en)

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US11/010,243US20060184462A1 (en)2004-12-102004-12-10Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems
PCT/US2005/044729WO2006063291A2 (en)2004-12-102005-12-09Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems
CNA2005800422587ACN101107618A (en)2004-12-102005-12-09Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems
CA002589491ACA2589491A1 (en)2004-12-102005-12-09Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems
EP05853611AEP1836657A2 (en)2004-12-102005-12-09Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems
IL183625AIL183625A0 (en)2004-12-102007-06-03Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems
US12/040,849US8175981B2 (en)2004-12-102008-02-29Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems
US13/438,670US9530091B2 (en)2004-12-102012-04-03Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems

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US12/040,849Active2027-04-13US8175981B2 (en)2004-12-102008-02-29Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems
US13/438,670Active2028-02-20US9530091B2 (en)2004-12-102012-04-03Methods, architecture, and apparatus for implementing machine intelligence and hierarchical memory systems

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EP (1)EP1836657A2 (en)
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