CROSS-REFERENCE TO RELATED APPLICATION This application is a divisional of U.S. patent application Ser. No. 10/225,585, filed Aug. 21, 2001, which is incorporated herein by reference in its entirety.
TECHNICAL FIELD The present invention relates to microelectronic workpieces with barrier layers and seed layers that are configured for electrochemical deposition processing, and methods of making and using such microelectronic workpieces.
BACKGROUND Microelectronic devices, such as semiconductor devices, field emission displays, read/write heads, and other products that include integrated circuits, are generally fabricated on and/or in microelectronic workpieces using several different types of machines (“tools”). Many such processing machines have a single processing station that performs one or more procedures on the workpieces. In a typical fabrication process, for example, one or more layers of conductive materials are formed on the workpieces during deposition stages. The workpieces are then typically etched and/or planarized (i.e., chemical-mechanical planarization) to remove an “overburden” portion of the deposited conductive layers and thus form electrically isolated contacts and/or interconnect lines.
Plating tools that plate metals or other materials onto the workpieces are becoming an increasingly useful type of processing tool. Electroplating and electroless plating techniques can be used to deposit copper, solder, permalloy, gold, silver, platinum, polymeric materials and other materials onto workpieces for forming blanket layers or patterned layers. A typical copper plating process involves depositing a barrier layer on the workpiece that conforms to micro-recesses and other features and then depositing a copper seed layer onto the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, or other suitable deposition processes. After forming the seed layer, a blanket layer or patterned layer of copper is plated onto the workpiece by applying an appropriate electrical potential between the seed layer and another electrode in the presence of an electroprocessing solution (i.e., an acidic electrolyte). The workpiece is then cleaned, etched, and/or annealed in subsequent procedures before transferring the workpiece to other processing machines.
FIG. 1 schematically illustrates an embodiment of a single-wafer processing station1 that includes acontainer2 for receiving a flow of electroplating solution from afluid inlet3 at a lower portion of thecontainer2. Theprocessing station1 can include ananode4, a plate-type diffuser6 having a plurality ofapertures7, and aworkpiece holder9 for carrying aworkpiece5. Theworkpiece holder9 can include a plurality of electrical contacts arranged to circumscribe a first diameter. The contacts of the workpiece holder9 contact a perimeter portion of the workpiece for providing electrical current to the seed layer on the surface of theworkpiece5. When the seed layer is biased with a negative potential relative to theanode4, it acts as a cathode. In operation, the electroplating fluid flows around theanode4, through theapertures7 in thediffuser6, and against the plating surface of theworkpiece5. The electroplating solution is typically an acidic electrolyte that conducts electrical current between theanode4 and the cathodic seed layer on the surface of theworkpiece5. Therefore, ions in the electroplating solution plate the surface of theworkpiece5.
The plating machines used in fabricating microelectronic devices must meet many specific performance criteria. For example, many processes must be able to form small contacts in submicron recesses, such as vias that are less than 0.5 micron wide and are desirably on the order of 0.1 micron wide. The plated metal layers should also be of a uniform thickness across the surface of theworkpiece5. One factor that influences the uniformity of the plated layer, and especially the integrity of the plated material in the submicron micro-recesses, is the current density across the surface of the workpiece.
Another objective of electrochemical deposition processes according to the prior art is to maximize the real estate available for forming integrated circuits on the workpiece. Existing contact assemblies typically include a plurality of fingers that project radially inwardly from a ring. Each of the fingers includes a contact point, and the contact points are typically arranged to circumscribe a circle with a slightly small diameter than the workpiece. To maximize the available real estate for forming integrated circuits, the diameter circumscribed by the contact points is typically selected to be as close to the perimeter edge of the workpiece as possible. Therefore, a significant number of tool manufacturers have expended significant resources to develop contact rings that minimize the distance that the contacts extend radially inwardly from the perimeter edge of the workpiece.
Although electrochemical deposition processes are widely used in semiconductor fabrication applications, it is becoming difficult to form uniform layers that completely fill the submicron micro-recesses. One factor contributing to the difficulty of electrochemical deposition processes is that very thin seed layers are necessary to fill 0.1-0.5 micron recesses. The ultrathin seed layers are typically discontinuous layers of copper that do not uniformly cover the topography of the workpieces. As a result, an IR drop occurs across thin seed layers, and the amount of copper that each contact engages varies across the workpiece. The IR drop is exacerbated because oxidation greatly impairs the conductivity of the copper seed layer. Moreover, acidic electroplating baths momentarily etch the copper seed layer before an electrical current is established in the bath causing a further reduction of conductivity. Thus, reduced conductivity of the copper seed layer further increases the IR drop.
The IR drop across the seed layer and the non-uniformities of ultrathin seed layers having a thickness of between 100-1000 Å cause a non-uniform current distribution in which the electrical current at the center of the workpiece is less than the current at the perimeter for an initial portion of the plating cycle. This produces non-uniform surfaces across the workpiece and voids within the submicron micro-recesses. Therefore, the semiconductor industry is currently seeking to reduce such non-uniformities and voids associated with electrochemical deposition processes.
SUMMARY The present invention is directed toward methods for forming microelectronic workpieces used in electrochemical deposition processes, methods of depositing a conductive layer on a microelectronic workpiece, and articles for electrochemical deposition in semiconductor fabrication. One aspect of the invention is directed toward methods for forming microelectronic workpieces that are well-suited for electrochemical deposition processes. An embodiment of such a method comprises depositing a first conductive material on a workpiece to form an electrically conductive first layer that conforms to the workpiece. This embodiment further includes forming a seed region defined by a second layer of a second conductive material on the first layer and forming a contact region defined by an exposed portion of the first layer that is not covered by the second layer. The contact region can extend around at least a portion of the perimeter of the workpiece.
Another embodiment of a method for forming a microelectronic workpiece in accordance with the invention includes depositing a first conductive material on the workpiece, depositing a second conductive material over the first conductive material, and forming a contact region around a perimeter of the workpiece. The first material is a conductive material that forms an electrically conductive contact layer which conforms to submicron recesses in the workpieces. The second material is a different conductive material that is deposited onto the contact layer to form a seed layer. The second conductive material, for example, can be copper. The contact region is an exposed portion of the contact layer that extends radially inwardly from an edge of the workpiece. The contact region, for example, can be an annular band of the first material around the perimeter of the workpiece that is configured to directly engage the contact points of a workpiece holder used in electrochemical deposition chambers. The contact region can be formed by patterning a resist layer in an annular band around the perimeter of the workpiece and then depositing the second conductive material on the contact layer. Alternatively, the contact region can be formed by depositing the second conductive material over the entire surface area of the workpiece and then etching a portion of the second conductive material from the perimeter of the workpiece.
Another aspect of the invention is a method of depositing a conductive layer on a microelectronic workpiece. In one embodiment, such a method includes depositing a first conductive material on the workpiece to form an electrically conductive contact layer that conforms to submicron recesses in the workpiece and then disposing a second conductive layer on the contact layer to form a seed layer. The method also includes forming a contact region around a perimeter portion of the workpiece that is defined by an exposed portion of the contact layer extending radially inwardly from an edge of the workpiece. The method continues by electroplating additional material onto the seed layer in a plating process that includes engaging an electrical contact directly with the contact region and applying a current directly to the contact region in the presence of an electroplating solution.
Another aspect of the invention is an article for electrochemical deposition of a conductive layer on a workpiece in the fabrication of microelectronic circuits. In one embodiment, such an article includes a workpiece having a plurality of submicron micro-components that define integrated circuits, a first layer on the workpiece, and a second layer over the first layer. The first layer is composed of a first electrically conductive material, and the first layer covers an area of the workpiece having a first diameter. The second layer defines a seed layer composed of a second conducive material different than the first material. The second layer covers an area of the workpiece having a second diameter less than the first diameter such that a portion of the first layer along a perimeter edge of the workpiece is exposed. The exposed portion of the first layer defines a contact region for directly engaging contacts of a workpiece holder.
Another embodiment of an article for electrochemical deposition of a conductive layer on a workpiece includes a workpiece having a plurality of submicron micro-components that define integrated circuits, a barrier layer on the workpiece, and a seed layer over the barrier layer. The barrier layer is composed of a first electrically conductive material. The seed layer is composed of a second conductive material different than the first material, and the seed layer covers only a portion of the barrier layer to leave an exposed portion of the barrier layer along a perimeter edge of the workpiece.
BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a schematic cross-sectional view of an electrochemical deposition chamber in accordance with the prior art.
FIGS. 2A-2C are schematic cross-sectional views illustrating a method for forming a workpiece in accordance with an embodiment of the invention.
FIG. 3 is a schematic cross-sectional view of a workpiece in accordance with an embodiment of the invention loaded into a workpiece holder for an electrochemical deposition process in accordance with a method of the invention.
FIG. 4 is a schematic cross-sectional view of an electrochemical deposition chamber for electroplating workpieces in accordance with embodiments of the invention.
FIGS. 5A-5D are schematic cross-sectional views illustrating a method for fabricating a workpiece in accordance with another embodiment of the invention.
FIGS. 6A-6C are schematic cross-sectional views of a method for fabricating a workpiece in accordance with yet another embodiment of the invention.
DETAILED DESCRIPTION The following disclosure describes methods for forming microelectronic workpieces used in electrochemical deposition processes, methods of depositing conductive layers on microelectronic workpieces, and articles for electrochemical deposition of conductive layers on workpieces in the fabrication of microelectronic circuits. As used herein, the terms “micro-device workpiece” and “microelectronic workpiece” include semiconductor wafers, field emission displays, read/write heads, micro-mechanical devices, and other types of devices that have very small components. Several embodiments of the invention are described below with reference toFIGS. 2-6C, but it will be appreciated that the invention can include other embodiments not shown in these figures. For example, aspects of the invention can include embodiments that do not have all of the features disclosed inFIGS. 2-6C, or other embodiments can include features in addition to those disclosed in these figures. Additionally, the embodiments disclosed inFIGS. 2-6C are directed toward forming damascene conductive lines, but it will be appreciated that they can also be used to form dual-damascene conductive lines, interlayer contacts, and other components in micro-device workpieces. It will be appreciated that several aspects of the invention are particularly suitable for fabricating submicron components on the order of 0.1-0.75 micron or even less than 0.1 micron, but many aspects of the invention may also be useful to fabricate components larger than one micron.
FIG. 2A is a schematic cross-sectional view of aworkpiece100 at one stage of a method in accordance with an embodiment of the invention. Theworkpiece100 includes asubstrate102 and adielectric layer104 over thesubstrate102. Thesubstrate102 can be a semiconductor substrate that includes a plurality of cells with transistors, shallow trench isolation structures, and other components. Thesubstrate102 can alternatively be a glass substrate or other material for other types of micro-devices. Thedielectric layer104 is typically a silicon dioxide, a borophosphate silicon glass, a tetraethylorthosilicate, or other suitable dielectric material. In the particular embodiment shown inFIG. 2A, thedielectric layer104 includes a plurality ofmicro-recesses106 that can be contact holes, trenches, or other structures. The micro-recesses106 typically have a sub-micron width on the order of 0.1-0.5 microns and a depth that can be significantly greater than the width. For example, the aspect ratio of the micro-recesses106 can range from 3-8. Theworkpiece100 also includes afirst layer110 of a first conductive material. Thefirst layer110 can be a barrier layer composed of tantalum, tungsten, a titanium-tungsten alloy, or other suitable materials that provide good adhesion to thedielectric layer104 and inhibit migration of bulk fill material to thedielectric layer104 and/or thesubstrate102. The barrier layer is typically deposited to a thickness of 100-5000 Å using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes.
FIG. 2B is a schematic cross-sectional view illustrating a subsequent stage of forming a microelectronic workpiece. Asecond layer120 of a second conductive material is deposited over thefirst layer110 using chemical vapor deposition, physical vapor deposition, atomic layer deposition and/or electroless plating processes. Thesecond layer120 typically defines a seed layer for electroplating additional material onto theworkpiece100 in a manner that fills the micro-recesses106 with the plated material. For example, to fill themicro-recesses106 with copper, thesecond layer120 is typically a copper seed layer. It will be appreciated that other materials can be used for thesecond layer120 to plate other types of metals or polymeric materials onto theworkpiece100. Thesecond layer120 can be deposited to a thickness of approximately 100-1000 Å, and generally more preferably to a thickness of 200-500 Å. When thesecond layer120 is a copper seed layer having a thickness of approximately 100-300 Å, it is generally discontinuous and has several voids (not shown inFIG. 2B). The discontinuity of thin copper seed layers is subject to creating large voids in the plated layer within the micro-recesses. Additionally, copper seed layers are subject to oxidation, which reduces the conductivity of the seed layers. The combination of thin copper seed layers and oxidation causes a drop in the current density from the edge to the center of theworkpiece100 when an electrical contact is engaged directly with thesecond layer120 at the perimeter of theworkpiece100.
FIG. 2C is a schematic cross-sectional view of theworkpiece110 at a subsequent stage of the method. This stage of the method involves forming acontact region130 around a perimeter of the workpiece and aseed region140 within thecontact region130. Thecontact region130 in this embodiment is defined by an exposedportion132 of thefirst layer110 that extends radially inwardly from anedge134 of theworkpiece100 to the perimeter of thesecond layer120. The exposedportion132 of thefirst layer110 is not covered by the second material of thesecond layer120. Thecontact region130 can be an annular band extending around the perimeter edge of theworkpiece100. Thecontact region130 can have a radial width of approximately 1-10 millimeters, and more preferably a radial width of approximately 2-5 millimeters. Theseed region140 is thus defined by thesecond layer120. As a result, thefirst layer110 covers the surface of theworkpiece100 across an area having a first diameter, and thesecond layer120 covers an area of thefirst layer110 having a second diameter less than the first diameter such that a portion of thefirst layer110 is exposed along theperimeter edge134 of theworkpiece100. The embodiment of theworkpiece100 shown inFIG. 2C is suitable for subsequent electrochemical deposition processing in which a plurality of electrical contacts touch the exposedportion132 of thefirst layer110 to apply an electrical current directly to thefirst layer110 without first applying the electrical current to thesecond layer120.
Thecontact region130 shown inFIG. 2C can be formed by depositing a layer of resist over the initial deposition of thesecond layer120 shown inFIG. 2B (resist not shown). The layer of resist is then patterned and removed around the perimeter of the workpiece, and then the perimeter portion of thesecond layer120 is etched away to expose theportion132 of thefirst layer110 shown inFIG. 2C. Suitable photo-patterning and etching processes are well known to those skilled in the art and not described here.
FIG. 3 is a schematic cross-sectional view of theworkpiece100 in aworkpiece holder200 used for electroplating additional material onto thesecond layer120. Theworkpiece holder200 includes ahousing210, amovable backing plate220 in one portion of the housing, and anannular rim230 spaced apart from thebacking plate220. Theworkpiece holder200 also includes a plurality ofcontacts240 arranged in a circle within therim230. Eachcontact240 includes acontact point242 that is configured to engage theworkpiece100. The contact points242 are generally arranged to circumscribe a circle having a diameter that extends radially inwardly relative to theedge134 of theworkpiece100.
Theworkpiece100 is loaded into theworkpiece holder200, and then thebacking plate220 and/or theannular rim230 moves to press the contact points242 directly against the exposedportion132 of thefirst layer110. The lip of therim230 also preferably engages theworkpiece100 to form a seal radially inward from the contact points242. It will be appreciated, however, that certain embodiments can be wet-contact plating processes that do not engage a rim with the workpiece. The contact points242 accordingly directly engage the surface of thefirst layer110 in the contact region to apply an electrical current directly to the first layer. Because thefirst layer110 is conductive, the electrical current initially passes through thefirst layer110 to provide a uniform current distribution across theworkpiece100. The conductivesecond layer120 accordingly conducts the electrical current distributed through thefirst layer110 to provide a uniform current distribution across thesecond layer120.
FIG. 4 is a schematic cross-sectional view showing an electroplating process for bulk plating material onto theworkpiece100 using theworkpiece holder200 shown inFIG. 3. In operation, theworkpiece holder200 positions theworkpiece100 in a bath of an electroplating solution. As shown inFIG. 4, theworkpiece100 is plated in anelectrochemical deposition chamber400 that includes anupper unit410 having ahead412 that carries theworkpiece holder200. TheECD chamber400 also includes alower unit420 that has abowl422 for containing an electrolyte bath and anelectrode424 positioned in thebowl422. More specifically, thehead412 can include arotor414 that rotatably carries theworkpiece holder200. Thehead412 positions theworkpiece100 so that the flow of electrolytic solution engages the face of theworkpiece100. Additionally, an electrical field is established in the electrolytic solution by applying a potential to theelectrode424 in thebowl422 and theelectrodes240 contacting the contact region of theworkpiece100. The ions in the electrolytic bath accordingly attach to the second layer120 (FIG. 2C) of theworkpiece100 to fill the micro-recesses106 (FIG. 2C) with the plated material.
The structure of theworkpiece100 shown in the embodiment ofFIG. 2C is expected to provide a more uniform current distribution in thesecond layer120 to produce more uniform plating in the micro-recesses106. The conductivefirst layer110 can be a continuous layer without voids even when it is very thin. For example, when thefirst layer110 is a thin tantalum layer, it is not subject to including the voids and discontinuities of a thin copper layer. Additionally, thin tantalum layers are not subject to oxidation to the same extent as copper. Therefore, when thecontacts240 apply the current directly to thefirst layer110 instead of thesecond layer120, the electrical current is generally uniform through thetantalum layer110. This accordingly produces a uniform current distribution through thesecond layer120. As a result, by exposing the contact region on thefirst layer110 and engaging thecontact point242 of thecontacts240 directly with the contact region, the embodiments of theworkpiece100 shown inFIG. 2C are expected to produce uniform plating across the face of theworkpiece100.
FIGS. 5A-5D are schematic cross-sectional views of another embodiment of theworkpiece100. Referring toFIG. 5A, theworkpiece100 includes thesubstrate102, the dielectric layer withmicro-recesses106, and thefirst layer110 as described above.FIG. 5B shows theworkpiece100 at a subsequent stage after a layer of resist has been deposited over theworkpiece100 and patterned to form at least onespacer115 at the perimeter of theworkpiece100. Thespacer115 can be a continuous annular ring around the perimeter of theworkpiece100 over thefirst layer110. Alternatively, a plurality of discrete spacers can be formed over areas where the first layer is to be exposed.FIG. 5C illustrates theworkpiece100 at a subsequent stage of the method after having deposited thesecond layer120 over thespacer115 and thefirst layer110. Theworkpiece100 is then subject to a process in which thespacer115 is removed by a suitable wash or etchant to undercut the perimeter portion of thesecond layer120.FIG. 5D illustrates theworkpiece100 after removing thespacer115, which may also remove the undercut portion of thesecond layer120 to expose thesurface132 of thefirst layer110 and thus define thecontact region130.
FIGS. 6A-6C are schematic views illustrating aworkpiece100ain accordance with yet another embodiment of the invention. Referring toFIG. 6A, theworkpiece100ahas asubstrate102, adielectric layer104 withmicro-recesses106, and afirst layer110 as explained above. Theworkpiece100aalso has a layer of resist115awhich has been patterned to form large openings over the micro-recesses106.FIG. 6B illustrates theworkpiece100aafter asecond layer120 has been deposited over thefirst layer110 and the resistlayer115a.FIG. 6C illustrates theworkpiece100aafter removing the top portions of thesecond layer120 and the resistlayer115a. To form the structure shown inFIG. 6C from the structure shown inFIG. 6B, the structure shown inFIG. 6B can be planarized to remove the top portions of thesecond layer120 over the resistlayer115a, and then the resist115acan be removed from the workpiece using a suitable wash or etchant that does not react with thesecond layer120 or thefirst layer110. Theworkpiece100ashown inFIG. 6C can accordingly be loaded into a workpiece holder and electroplated as explained above.
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.