US20060138660A1 - Copper interconnect - Google Patents

Abstract

An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Description

CROSS-REFERENCE TO RELATED APPLICATION
• This application is a continuation of application Ser. No. 10/383,042, filed Mar. 6, 2003, pending, which will issue as U.S. Pat. No. 6,987,324 on Jan. 17, 2006, which is a divisional of application Ser. No. 09/332,665, filed Jun. 14, 1999, now U.S. Pat. No. 6,544,880, issued Apr. 8, 2003.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to improved bonding of conductors with the bond pads of semiconductor devices, such as the bonding of wires to the bond pads of semiconductor devices and lead frames associated therewith or the bonding of the conductor leads in TAB tape bonding to the bond pads of semiconductor devices. More specifically, the present invention relates to improved bonds with copper bond pads of semiconductor devices, such as wire bonding or improved conductor lead bonding of TAB tape to the copper bond pads of semiconductor devices.
• 2. State of the Art
• In semiconductor device manufacture, a single semiconductor die (or chip) is typically mounted within a sealed package. In general, the package protects the semiconductor die from damage and from contaminants in the surrounding environment. In addition, the package provides a substantial lead system for connecting the electrical devices formed on the die to a printed circuit board or any other desired suitable external circuitry.
• Each semiconductor die comprises a substrate having a lower surface (commonly referred to as the back of the die) that is devoid of circuitry and an upper surface (commonly referred to as the active surface or face of the die) having integrated circuitry constructed thereon. The integrated circuitry is electrically accessible via bond pads located on the active surface of the semiconductor die which may be arranged in a wide variety of patterns, such as around the periphery of the semiconductor die, the center of the semiconductor die, or both, etc.
• One of the problems associated with the decreasing size of the semiconductor die and the increasing amount of circuitry included in the semiconductor die is the need to, at least, maintain the speed at which the semiconductor die operates and, if possible, to increase the operating speed of the semiconductor die. Since aluminum is typically used as the material for the connecting circuits of the semiconductor die with smaller circuit line widths of aluminum, it is difficult to maintain or increase the speed of the semiconductor die. Further, it is necessary to connect an ever-increasing number of bond pads on the active surface of the semiconductor die with an ever-increasing number of lead fingers of the lead frame or other type conductors, such as the conductor leads of TAB tape. In each instance, the use of a more conductive material for the connecting circuits of the semiconductor die connecting to the bond pads on the active surface of the semiconductor die is required.
• In an effort to increase the operating speeds of semiconductor dice using small width circuit lines, improved techniques and processes have been developed to substitute the metal copper for aluminum in the circuit lines of the semiconductor die. However, the use of copper for circuit lines and bond pads of the semiconductor die causes problems when wire bonds are used to connect the copper bond pads of the semiconductor die to the leads of a lead frame or the lead conductors of TAB tape. It is difficult to form wire bond connections using standard or conventional wire bonding equipment when forming wire bonds to connect the copper bond pads of a semiconductor die to the leads of a lead frame.
• Typically, the initial component in the packaging process is a lead frame. The lead frame is a metal frame which supports the semiconductor die for packaging and provides the leads for the final semiconductor package. A typical lead frame strip is produced from metal sheet stock (usually a copper, copper alloy, alloy 42, etc.) and is adapted to mount the semiconductor die.
• A conventional lead frame has the semiconductor die adhesively mounted on a die paddle of the lead frame while the lead fingers (leads) extend around the periphery of the semiconductor die (the edges) terminating adjacent thereto. Subsequently, wire bonds are made to connect the bond pads on the active surface of the semiconductor die to the appropriate lead finger of the lead frame. After the wire bonding operation, the lead frame and semiconductor die are encapsulated in a transfer die molding process. After encapsulation, the lead frame is trimmed with the remainder of the individual lead fingers being formed into the desired packaging configuration.
• One of the problems associated with conventional lead frame configurations is that with the decreasing size of the semiconductor die and the increasing amount of circuitry included in the semiconductor die, it is necessary to connect an ever-increasing number of bond pads on the active surface of the semiconductor die with an ever-increasing number of lead fingers of the lead frame. This requires that the bonds pads on the semiconductor die be located on smaller pitch spacings and the width of the lead fingers be smaller. This, in turn, leads to smaller wire bonds on both the bond pads of the semiconductor die and the lead fingers of the lead frame, which causes the wire bonds to be more highly stressed by the forces placed on them. This stress placed on the wire bonds requires that the metal of the bond pad, to which the wire bond is to be made, be highly susceptible to wire bonding and the formation of high strength wire bonds therewith when using well-known wire material, such as gold, etc. and standard or conventional wire bonding equipment.
• In a Leads-Over-Chip (LOC) type lead frame configuration for an integrated circuit semiconductor device, the lead fingers of the lead frame extend over the active surface of the semiconductor die being insulated therefrom by tape which is adhesively bonded to the active surface of the semiconductor die and the bottom of the lead fingers. In this manner, the semiconductor die is supported directly from the lead fingers of the lead frame. Electrical connections are made between the lead fingers of the lead frame and the bond pads on the active surface of the semiconductor die by way of wire bonds extending therebetween. After wire bonding, the lead frame and semiconductor die are encapsulated in suitable plastic material. Subsequently, the lead fingers are trimmed and formed to the desired configuration to complete the packaged semiconductor device assembly.
• One of the shortcomings of the prior art LOC semiconductor die assemblies is that the tape used to bond to the lead fingers of the lead frame does not adequately lock the lead fingers in position for the wire bonding process. At times, the adhesive on the tape is not strong enough to fix or lock the lead fingers in position for wire bonding as the lead fingers pull away from the tape before wire bonding. Alternately, the lead fingers will pull away from the tape after wire bonding of the semiconductor die but before encapsulation of the semiconductor die and lead frame, either causing shorts between adjacent wire bonds or causing the wire bonds to pull loose from either the bond pads of the semiconductor die or lead finger of the lead frame. As before with conventional lead frames, with the decreasing size of the semiconductor die and the increasing amount of circuitry included in the semiconductor die, it is necessary to connect an ever-increasing number of bond pads on the active surface of the semiconductor die with an ever-increasing number of lead fingers of the lead frame. This requires that the bond pads on the semiconductor die be located on smaller pitch spacings and the width of the lead fingers be smaller. This, in turn, leads to smaller wire bonds on both the bond pads and the lead fingers of the lead frame, which cause the wire bonds to be more highly stressed by the forces placed on them.
• Therefore, when using copper as the metal for the formation of circuits and bond pads of a semiconductor die, a need exists for increased-strength wire bonds between the lead fingers of a lead frame and the bond pads of a semiconductor die or between the conductor leads of TAB tape and the bond pads of a semiconductor die, particularly, as the size of the semiconductor die, the size of the bond pads thereon, the size of the lead fingers connected by wire bonds to bond pads, and the pitch thereof, all decrease.
• It is known in the art to form bumps on the bond pads of a semiconductor die using wire bonding apparatus for subsequent wire bond Tape Automated Bonding (TAB) or flip-chip (face-down) assembly of a bare chip die to a substrate. Such is illustrated in U.S. Pat. Nos. 4,750,666 and 5,058,798. It is also known to repair defective or broken wire bonds to bond pads of a semiconductor die by forming a flattened pad over the remaining portion of the wire and, subsequently, bonding the end of another wire thereover. Such is illustrated in U.S. Pat. No. 5,550,083. Other types of wire bonding operations on the bond pads of a semiconductor die are illustrated in U.S. Pat. Nos. 5,235,212, 5,298,793, 5,343,064, 5,371,654, and 5,492,863. However, such patents use aluminum for the circuits and bond pads of the semiconductor die rather than copper, which is difficult to make effective bonds thereto using conventional processes and equipment.
BRIEF SUMMARY OF THE INVENTION
• The present invention relates to improved wire bonds with the bond pads of semiconductor devices and either the lead fingers of lead frames or the conductor leads of TAB tape. More specifically, the present invention relates to improved wire bonds and improved conductor lead bonds of TAB tape to the bond pads of a semiconductor device wherein the bond pads comprise a copper layer and at least one layer of metal covering a portion of the copper layer.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
• In the, drawings, which illustrate what is currently considered to be the best mode for carrying out the invention:
• FIG. 1 is a cross-sectional view of a portion of a semiconductor die having a plurality of copper bond pads thereon having one or more layers of metal thereon;
• FIGS. 2A through 2F are views of a portion of a semiconductor device having a bond pad of the present invention located thereon having a wire bond formed thereon;
• FIGS. 3A through 3C are views of a portion of a semiconductor device illustrating the formation of a bond pad thereon of the present invention having a wire bond formed thereon;
• FIGS. 4A through 4D are views of a portion of a semiconductor device having a bond pad of the present invention located thereon with a conductor lead of a TAB tape bonded thereto; and
• FIGS. 5A through 5J are drawings illustrating processes of forming a bond pad of the present invention on a semiconductor device and a subsequent wire bond and bonding of a conductor lead of a TAB tape therewith.
• The present invention will be better understood when the drawings are taken in conjunction with the following description of the invention.
DETAILED DESCRIPTION OF THE INVENTION
• Referring to drawingFIG. 1, a portion of asemiconductor device10 is illustrated having a plurality ofbond pads12 located on theactive surface14 of asemiconductor device10 having a layer of insulatingmaterial13, and a passivation layer, thereon. Thesemiconductor device10 may be of any desired type having any desired configuration ofbond pads12 connected to the active circuitry therein. As illustrated,bond pads12 include a coppermetal layer base12′ and one or moreadditional metal layers12″ thereon to facilitate the formation of an acceptable wire bond using well-known alloys of metal for the wire to thebond pads12. The wire bond may be formed or secured to thebond pads12 by any desired, well-known wire bonding apparatus used in the industry using any desired type of wire, such as aluminum, copper, copper alloy, aluminum-copper alloy, gold, silver, gold-silver alloy, platinum, etc., although gold wire is preferred to be used as gold does not form an oxide after the deposition thereof on thebond pad12 as would aluminum, silver, etc.
• As necessary, thebond pad12 may be comprised of layers of different metals to enhance bonding characteristics. For instance,layer base12′ is of copper metal such as is used for the circuits of thesemiconductor device10, i.e., copper metal, a copper alloy, etc. Typically, thelayer12″ would be of gold, gold alloy, silver, silver alloy, palladium and alloys thereof, noble metals and alloys thereof, nickel and alloys thereof, nickel and gold alloys, zincated copper, etc. Thelayer12″ may further include an additional intermediate layer of metal or other materials to help prevent intermetallic compounds from forming between thecopper layer base12′ andlayer12″ and/or for adhesion purposes. For instance, thelayer12″ may commonly comprise a layer of TaN, TiN, Ni alloys, etc. If a gold wire is used for wire bonding, themetal layer12″ may typically be a gold or gold alloy metal layer. In this manner, by forming thebond pad12 of multiple layers of metal, a strong bond between the wire used for wire bonding and the coppermetal layer base12′ of thebond pad12 may be formed, particularly since gold does not form an oxide coating after the deposition thereof to affect any subsequent bond of material thereto. If desired, one layer of themetal layer12″ ormultiple metal layers12″ may be a layer of metal forming a barrier to prevent any copper from thelayer base12′ from migrating therethrough or any metal of themetal layer12″ from migrating to thecopper layer12′. Additionally, one layer of themetal layer12″ may be a layer of metal for adhesion promoting purposes to either thecopper layer base12′ or themetal layer12″.
• Referring to drawingFIGS. 2A through 2C, a process for formingmulti-layer bond pads12 on theactive surface14 ofsubstrate11 is illustrated. A portion of asemiconductor device10 is shown in drawingFIG. 2A having acopper layer base12′ forming a portion of thebond pad12. Illustrated in drawingFIG. 2B, is a layer ofmetal12″ overlying thecopper layer base12′ of thebond pad12. The layer ofmetal12″ may be selectively plated by well-known techniques over thecopper layer12′, the layer ofmetal12″ having good properties for the wire bonding of awire20 to thebond pad12. Illustrated in drawingFIG. 2C, awire20 is bonded by well-known wire bonding apparatus to the layer ofmetal12″ of thebond pad12 using awire bond ball22.
• Still referring to drawingFIGS. 2A through 2C, a portion of asemiconductor device10 is shown having abond pad12 thereon with thecopper layer base12′ located thereon having the upper surface thereof located at approximately the same level as theactive surface14 ofsubstrate11 of thesemiconductor device10, theactive surface14 having a layer of insulating material13 (typically a passivation layer of an insulating oxide or insulating nitride) thereon. As illustrated in drawingFIG. 2B, thecopper layer base12′ ofbond pad12 has asuitable metal layer12″ selectively plated thereon using well-known plating processes, the function of themetal layer12″ being to provide a good metal to which an effective wire bond may be formed using well-known wire bonding apparatus.
• Illustrated in drawingFIG. 2C, awire20 is wire bonded tometal layer12″ using aball22 formed on the end of thewire20 using any well-known suitable wire bonding apparatus. In the wire bonding process, the portion of themetal layer12″ on thebond pad12 located underball22 of thewire20 of the wire bond thereto may be consumed during the wire bonding process, thereby allowing theball22 of thewire20 of the wire bond to make direct contact with thecopper layer base12′ of thebond pad12. For example, when themetal layer12″ is gold and theball22 ofwire20 is gold wire, themetal layer12″ located under theball22 will become part of theball22 during the wire bonding process with theball22 being bonded to thecopper layer base12′ of thebond pad12.
• Referring to drawingFIG. 2D, awire20 is wire bonded tocopper layer base12′ with theball22 on the end ofwire20 consuming or adding part of themetal layer12″ during the bonding process forming theball22 on the end ofwire20 connecting thewire20 to thecopper layer12′.
• Referring to drawingFIG.2E, a portion of asemiconductor device10 is shown having abond pad12 thereon with thecopper layer base12′ located thereon having the upper surface thereof located at approximately the same level as theactive surface14 ofsubstrate11 of thesemiconductor device10, theactive surface14 having a layer of insulating material13 (typically a passivation layer of an insulating oxide or insulating nitride) thereon. As illustrated in drawingFIG. 2E, thecopper layer base12′ ofbond pad12 has abarrier layer12′″ formed of a suitable material having asuitable metal layer12″ selectively plated thereon using well-known plating processes. The function of thebarrier layer12′″ is to help prevent interaction between thecopper layer base12′ and thesuitable metal layer12 ″ of thebond pad12 and/or to help prevent or decrease the growth of intermetallics between thecopper layer base12′ and themetal layer12″. For instance, barrier materials, such as titanium, tungsten, tantalum, nickel, tantalum-nickel alloys, titanium-nickel alloys, titanium-tungsten alloys, etc. are frequently used in conjunction with aluminum alloy interconnects. In other instances, a barrier layer of nickel between copper and tin will decrease the growth of tin-copper intermetallics. The layers of metal forming thebond pads12 also occasionally are silicided, or have a refractory interconnect material, such as molybdenum, tungsten, or tungsten silicide, as part thereof. The function of themetal layer12″ is to provide a good metal to which an effective wire bond may be formed using well-known wire bonding apparatus, such as ametal layer12″ of gold whengold wire20 is being used for wire bonding.
• Referring to drawingFIG. 2F, awire20 is wired bonded tobarrier layer12′″ with theball22 on the end ofwire20 consuming part of themetal layer12″ during the bonding process forming theball22 on the end ofwire20 connecting thewire20 to thebarrier layer12′″.
• Referring to drawingFIGS. 3A through 3C, a portion of asemiconductor device10 is shown wherein acopper layer base12′ is deposited on thesubstrate11 using any desired well-known process having a thin layer ofmetal12″, as described hereinbefore, deposited thereon. The thin layer ofmetal12″ may be deposited on thecopper layer base12′ by any well-known process, such as sputter deposition, electrodeposition, electroless deposition, etc.
• Referring to drawingFIG. 3B, the portion of thesemiconductor device10 is shown after thecopper layer base12′ and layer ofmetal12″ deposited thereon have been patterned using well-known techniques to apply a photoresist in a desired pattern with the subsequent etching of thecopper layer base12′ and layer ofmetal12″ to form abond pad12 on thesubstrate11 of thesemiconductor device10. Thecopper layer base12′ and layer ofmetal12″ deposited thereon may be any desired shape, size, and number for the desired number ofbond pads12 on thesubstrate11. Further, thecopper layer base12′ may include at least two or more layers of metal with the upper layer being a copper layer, thereby forming a stack of layers of differing metal with the upper layer being a copper layer.
• Referring to drawingFIG. 3C, a portion of thesemiconductor device10 is shown having awire20 bonded to the layer ofmetal12″ of thebond pad12 using aball22 type bond thereto for wire bonding using any desired well-known wire bonding apparatus. Thesemiconductor substrate11 includes a layer of insulatingmaterial13, as described hereinbefore, onactive surface14 thereof surrounding thebond pad12.
• Referring to drawingFIGS. 4A through 4D, in drawingFIG. 4A, a portion of asemiconductor device10 is shown having abond pad12 thereon with thecopper layer base12′ located thereon having the upper surface thereof located at approximately the same level as theactive surface14 ofsubstrate11 of thesemiconductor device10, theactive surface14 having a layer of insulating material13 (typically a passivation layer of an insulating oxide or insulating nitride) thereon. Also illustrated in drawingFIG. 4A, thecopper layer base12′ ofbond pad12 has asuitable metal layer12″ selectively plated thereon using well-known plating processes. The function of themetal layer12″ is to provide a good metal to which an effective wire bond may be formed using well-known wire bonding apparatus.
• Illustrated in drawingFIG. 4B, thecopper layer base12′ ofbond pad12 has asuitable barrier layer12′″ located between thecopper layer base12′ and thesuitable metal layer12″, such as described hereinbefore.
• Referring to drawingFIG. 4C, a portion of asemiconductor device10 is shown having abond pad12 thereon having acopper layer base12′ located thereon having a portion bonded thereto of aconductive lead23 located on a portion of asubstrate24 of a portion of aTAB tape21. Theactive surface14 ofsubstrate11 of thesemiconductor device10 has a layer of insulating material13 (typically a passivation layer of an insulating oxide or insulating nitride) thereon. Also illustrated in drawingFIG. 4C, the function of themetal layer12″ is to provide a good metal to which an effective bond may be formed using well-known bonding apparatus to bond theconductive lead23 of theTAB tape21. Theconductive lead23 of theTAB tape21 may be of any suitable metal, such as copper, copper alloys, etc. Themetal layer12″ may be of any suitable metal, such as described herein.
• Referring to drawingFIG. 4D, a portion of asemiconductor device10 is shown having abond pad12 thereon having acopper layer base12′ located thereon having abarrier layer12′″ located thereon having, in turn, ametal layer12″ located thereon. Themetal layer12″ of thebond pad12, is bonded to a portion of aconductive lead23 located on a portion of asubstrate24 of a portion of aTAB tape21. Theconductive lead23 of the portion of theTAB tape21 includes alayer26 of suitable metal located thereon for the bonding of theconductive lead23 to themetal layer12″ of thebond pad12 of thesemiconductor device10. Theactive surface14 ofsubstrate11 of thesemiconductor device10 has a layer of insulating material13 (typically a passivation layer of an insulating oxide or insulating nitride) thereon. Also illustrated in drawingFIG. 4D, the function of themetal layer12″ is to provide a good metal to which an effective bond may be formed using well-known bonding apparatus to themetal layer26 of theconductive lead23 of theTAB tape21. Thesubstrate24 andmetal layer26 may be of any suitable metal for bonding purposes, such as gold, alloys of gold, etc. Theconductive lead23 of theTAB tape21 may be of any suitable metal, such as copper, copper alloys, etc. Themetal layer12″ may be of any suitable metal, such as described herein. Thebarrier layer12′″ may be of any suitable metal or material, such as described herein.
• Referring to drawingFIGS. 5A through 5J, various differing processes for the formation of thebond pad12 including acopper layer base12′ and a layer ofmetal12″ and, if desired, abarrier layer12′″ are illustrated.
• Referring to drawingFIG. 5A, aprocess100 for the formation of abond pad12 including acopper layer base12′ and a layer ofmetal12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep102, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep104, a layer ofmetal12″ is deposited on thecopper layer base12′ using any well-known deposition process. Then, instep106, thecopper layer base12′ and layer ofmetal12″ is patterned and etched to form the desired shape, number, and pattern for thebond pads12 on theactive surface14 of thesubstrate11 of thesemiconductor device10. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of thesemiconductor device10 havingbond pads12 including acopper layer base12′ and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to a lead frame (not shown) for wire bonding awire20 to thebond pad12 of thesemiconductor device10 using any suitablewire bonding process108 and apparatus.
• Referring to drawingFIG. 5B, aprocess200 for the formation of abond pad12 including acopper layer base12′ and a layer ofmetal12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep202, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep204, thecopper layer base12′ is patterned and etched to form the desired shape, number, and pattern for thebond pads12 on theactive surface14 of thesubstrate11 of thesemiconductor device10. Then, instep206, the layer ofmetal12″ is deposited on thecopper layer base12′ using any desired deposition process, as described hereinbefore, such as electrodeposition, electroless deposition, etc. to form thebond pad12 having acopper layer base12′ and layer ofmetal12″ thereon for good wire bonding properties. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of thesemiconductor device10 havingbond pads12 including acopper layer base12′ and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to a lead frame (not shown) for wire bonding awire20 to thebond pad12 of thesemiconductor device10 using any suitablewire bonding process208 and apparatus.
• Referring to drawingFIG. 5C, aprocess300 for the formation of abond pad12 including acopper layer12′, abarrier layer12′″, and a layer ofmetal12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep302, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep304, abarrier layer12′″ of suitable material is deposited on thecopper layer base12′ using any well-known deposition process. Then, instep306, thecopper layer base12′ andbarrier layer12′″ are patterned and etched to form the desired shape, number, and pattern for thebond pads12 on theactive surface14 of thesubstrate11 of thesemiconductor device10. Then ametal layer12″ is deposited instep308 over thebarrier layer12′″ and subsequently patterned instep310. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of thesemiconductor device10 havingbond pads12 including acopper layer12′,barrier layer12′″, and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to a lead frame (not shown) for wire bonding awire20 to thebond pad12 of thesemiconductor device10 using any suitablewire bonding process312 and apparatus.
• Referring to drawingFIG. 5D, aprocess400 for the formation of abond pad12 including acopper layer12′, abarrier layer12′″, and a layer ofmetal12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep402, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep404, abarrier layer12′″ of suitable material is deposited on thecopper layer base12′ using any well-known deposition process. Then, instep406, ametal layer12″ is deposited on thebarrier layer12′″. Instep408, thecopper layer12′ ,barrier layer12′″. andmetal layer12″ are patterned and etched to form the desired shape, number, and pattern for thebond pads12 on theactive surface14 of thesubstrate11 of thesemiconductor device10. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of thesemiconductor device10 havingbond pads12 including acopper layer12′,barrier layer12′″, and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to a lead frame (not shown) for wire bonding awire20 to thebond pad12 of thesemiconductor device10 using any suitablewire bonding process410 and apparatus.
• Referring to drawingFIG. 5E, aprocess500 for the formation of abond pad12 including acopper layer base12′ and a layer ofmetal12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep502, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep504, at least twobarrier layers12′″ are deposited on thecopper layer12′. Instep506, ametal layer12″ is deposited on thebarrier layer12′″ using any desired deposition process, as described hereinbefore, such as electrodeposition, electroless deposition, etc. Instep508, thecopper layer12′,barrier layer12′″ , andmetal layer12″ are patterned to form thebond pad12 having acopper layer12′,barrier layer12′″, and layer ofmetal12″ thereon for good wire bonding properties. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of thesemiconductor device10 havingbond pads12 including acopper layer12′, at least twobarrier layers12′″, and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to a lead frame (not shown) for wire bonding awire20 to thebond pad12 of thesemiconductor device10 using any suitablewire bonding process510 and apparatus.
• Referring to drawingFIGS. 5F through 5J, the processes set forth therein are similar to those described regarding those illustrated in drawingFIGS. 5A through SE, except that aconductive lead23 of aTAB tape21 is bonded to thebond pad12 of thesemiconductor device10, rather than a wire bond being made to thebond pad12 of asemiconductor device10.
• Referring to drawingFIG. 5F, aprocess600 for the formation of abond pad12 including acopper layer base12′ and a layer ofmetal12″ thereon forconductive lead23 ofTAB tape21 bonding purposes as described hereinbefore is illustrated. As illustrated instep602, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep604, a layer ofmetal12″ is deposited on thecopper layer base12′ using any well-known deposition process. Then, instep606, thecopper layer base12′ and layer ofmetal12″ are patterned and etched to form the desired shape, number, and pattern for thebond pads12 on theactive surface14 of thesubstrate11 of thesemiconductor device10. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of thesemiconductor device10 havingbond pads12 including acopper layer base12′ and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to aconductive lead23 of aTAB tape21 for bonding aconductive lead23 to thebond pad12 of thesemiconductor device10 using anysuitable bonding process608 and apparatus.
• Referring to drawingFIG. 5G, aprocess700 for the formation of abond pad12 including acopper layer base12′ and a layer ofmetal12″ thereon forconductive lead23 ofTAB tape21 bonding purposes as described hereinbefore is illustrated. As illustrated instep702, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep704, thecopper layer base12′ is patterned and etched to form the desired shape, number, and pattern for thebond pads12 on theactive surface14 of thesubstrate11 of thesemiconductor device10. Then, instep706, the layer ofmetal12″ is deposited on thecopper layer base12′ using any desired deposition process, as described hereinbefore, such as electrodeposition, electroless deposition, etc. to form thebond pad12 having acopper layer base12′ and layer ofmetal12″ thereon for good wire bonding properties. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of thesemiconductor device10 havingbond pads12 including acopper layer base12′ and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to aconductive lead23 of aTAB tape21 for wire bonding aconductive lead23 to thebond pad12 of thesemiconductor device10 using anysuitable bonding process708 and apparatus.
• Referring to drawingFIG. 5H, aprocess800 for the formation of abond pad12 including acopper layer12′, abarrier layer12′″, and a layer ofmetal12″ thereon forconductive lead23 ofTAB tape21 bonding purposes as described hereinbefore is illustrated. As illustrated instep802, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep804, abarrier layer12′″ of suitable material is deposited on thecopper layer base12′ using any well-known deposition process. Then, instep806, thecopper layer base12′ andbarrier layer12′″ are patterned and etched to form the desired shape, number, and pattern for thebond pads12 on theactive surface14 of thesubstrate11 of thesemiconductor device10. Then ametal layer12″ is deposited instep808 over thebarrier layer12′″ and subsequently patterned instep810. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of the semiconductor device.10 havingbond pads12 including acopper layer12′,barrier layer12′″ , and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to aconductive lead23 of aTAB tape21 for bonding aconductive lead23 to thebond pad12 of thesemiconductor device10 using anysuitable bonding process812 and apparatus.
• Referring to drawingFIG. 5I, aprocess900 for the formation of abond pad12 including acopper layer12′, abarrier layer12′″ , and a layer ofmetal12″ thereon forconductive lead23 ofTAB tape21 bonding purposes as described hereinbefore is illustrated. As illustrated instep902, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep904, abarrier layer12′″ of suitable material is deposited on thecopper layer base12′ using any well-known deposition process. Then, instep906, ametal layer12″ is deposited on thebarrier layer12′″. Instep908, thecopper layer12′,barrier layer12′″ , andmetal layer12″ are patterned and etched to form the desired shape, number, and pattern for thebond pads12 on theactive surface14 of thesubstrate11 of thesemiconductor device10. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of thesemiconductor device10 havingbond pads12 including acopper layer12′,barrier layer12′″ , and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to aconductive lead23 of aTAB tape21 for bonding aconductive lead23 to thebond pad12 of thesemiconductor device10 using anysuitable bonding process910 and apparatus.
• Referring to drawingFIG. 5J, aprocess1000 for the formation of abond pad12 including acopper layer base12′ and a layer ofmetal12″ thereon forconductive lead23 ofTAB tape21 bonding purposes as described hereinbefore is illustrated. As illustrated instep1002, asubstrate11 as described hereinbefore for asemiconductor device10 has a layer of copper or copper alloy deposited thereon using any desired deposition process. Subsequently, instep1004, at least twobarrier layers12′″ are deposited on thecopper layer12′. Instep1006, ametal layer12″ is deposited on thebarrier layer12′″ using any desired deposition process, as described hereinbefore, such as electrodeposition, electroless deposition, etc. Instep1008, thecopper layer12′, barrier layers12′″, andmetal layer12″ are patterned to form thebond pad12 having acopper layer12′, barrier layers12′″, and layer ofmetal12″ thereon for good wire bonding properties. A layer of insulatingmaterial13 is typically applied to theactive surface14 of thesubstrate11 to protect the circuitry formed thereon of thesemiconductor device10. After the completion of thesemiconductor device10 havingbond pads12 including acopper layer12′,barrier layer12′″, and layer ofmetal12″ thereon, thesemiconductor device10 may be assembled to aconductive lead23 of aTAB tape21 for wire bonding aconductive lead23 to thebond pad12 of thesemiconductor device10 using anysuitable bonding process1010 and apparatus.
• It will be understood that changes, additions, deletions, and modifications may be made to the present invention which are intended to be within the scope of the claimed invention, such as the use of more than a single layer of metal over the copper layer to form a bond pad, the copper layer being multiple layers of differing materials, the barrier layer being multiple layers of differing materials, the metal layer being multiple layers of differing materials, etc.

Claims (6)

1. An assembly comprising:

a semiconductor device having at least one bond pad including:

a copper layer base; and

at least two layers of metal, one layer comprising at least one layer of metal covering a portion of the copper layer base and at least one other layer of metal covering a portion of the at least one layer of metal, the at least one layer of metal comprising a noble metal alloy and the at least one other layer of metal comprising a nickel metal alloy; and

one end of a wire connected to the at least one layer of metal covering a portion of the copper layer base.

2. An assembly comprising:

a semiconductor device having at least one bond pad located thereon including:

a copper layer base;

a barrier layer over at least a portion of the copper layer base; and

at least two layers of metal, one layer comprising at least one layer of metal covering a portion of the copper layer base and the barrier layer of the at least one bond pad and at least one other layer of metal covering a portion of the at least one layer of metal, the at least one layer of metal comprising a noble metal alloy and the at least one other layer of metal comprising a nickel metal alloy; and

one end of a wire connected to one layer of the at least two layers of metal covering a portion of the copper layer base.

3. A semiconductor device assembly comprising:

a semiconductor device having an active surface with at least one bond pad located thereon, the

at least one bond pad including:

a copper layer base; and

at least two layers of metal, one layer comprising at least one layer of metal covering a portion of the copper layer base of the at least one bond pad and at least one other layer of metal covering a portion of the at least one layer of metal, the at least one layer of metal comprising a silver metal alloy and the at least one other layer of metal comprising a nickel metal alloy.

4. A semiconductor device assembly comprising:

a semiconductor device having an active surface with at least one bond pad located thereon, the

at least one bond pad including:

a copper layer base; and

at least two layers of metal, one layer comprising at least one layer of metal covering a portion of the copper layer base of the at least one bond pad and at least one other layer of metal covering a portion of the at least one layer of metal, the at least one layer of metal comprising silver metal and the at least one other layer of metal comprising nickel metal.

5. A semiconductor device assembly comprising:

a semiconductor device having an active surface with at least one bond pad located thereon, the

at least one bond pad including:

a copper layer base;

a barrier layer over at least a portion of the copper layer base; and

at least two layers of metal, one layer comprising at least one layer of metal covering a portion of the copper layer base and the barrier layer of the at least one bond pad and at least one other layer of metal covering a portion of the at least one layer of metal, the at least one layer of metal comprising a silver metal alloy and the at least one other layer of metal comprising a nickel metal alloy.

6. A semiconductor device assembly comprising:

a semiconductor device having an active surface with at least one bond pad located thereon, the

at least one bond pad including:

a copper layer base;

a barrier layer over at least a portion of the copper layer base; and

at least two layers of metal, one layer comprising at least one layer of metal covering a portion of the copper layer base and the barrier layer of the at least one bond pad and at least one other layer of metal covering a portion of the at least one layer of metal, the at least one layer of metal comprising silver metal and the at least one other layer of metal comprising nickel metal.

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