US20060131262A1 - Fabrication of a reflective spatial light modulator - Google Patents

Abstract

Fabrication of a reflective spatial light modulator including a micro-mirror array. In one embodiment, the micro-mirror array is fabricated from a substrate that is a single crystal material by only two main etching steps. A first etch forms cavities in a first side of the material. A second etch forms support post, a vertical hinge, and a mirror plate. Between the first and second etches, the substrate can be bonded to addressing and control circuitry.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
• The present patent application is a continuation of U.S. patent application Ser. No. 10/756,923, filed Jan. 13, 2004, which is a continuation of U.S. patent application Ser. No. 10/378,041, filed Feb. 27, 2003, which claims priority from provisional U.S. Patent Application Serial No. 60/390,389, filed Jun. 19, 2002, the disclosures of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• This invention relates to spatial light modulators (SLMs), and more particularly to a micro-mirror array with electronically addressable control circuitry for display applications.
• 2. Background of the Invention
• Spatial light modulators (SLMs) have numerous applications in the areas of optical information processing, projection displays, video and graphics monitors, televisions, and electrophotographic printing. Reflective SLMs are devices that modulate incident light in a spatial pattern to reflect an image corresponding to an electrical or optical input. The incident light may be modulated in phase, intensity, polarization, or deflection direction. A reflective SLM is typically comprised of an area or two-dimensional array of addressable picture elements (pixels) capable of reflecting incident lights. Source pixel data is first processed by an associated control circuit, then loaded into the pixel array, one frame at a time.
• Prior art SLMs have various drawbacks. These drawbacks include: a lower than optimal optically active area (measured as what fraction of the device's surface area that is reflective, also called the “fill ratio”) that reduces optical efficiency, rough reflective surfaces that reduce the reflectivity of the mirrors, diffraction that lowers the contrast ratio of the display, use of materials that have long-term reliability problems, and complex manufacturing processes that increase the expense of the product.
• Many prior art devices include substantial non-reflective areas on their surfaces. This provides low fill ratios, and provides lower than optimum reflective efficiency. For example, U.S. Pat. No. 4,229,732 discloses MOSFET devices that are formed on the surface of a device in addition to mirrors. These MOSFET devices take up surface area, reducing the fraction of the device area that is optically active and reducing reflective efficiency. The MOSFET devices on the surface of the device also diffract incident light, which lowers the contrast ratio of the display. Further, intense light striking exposed MOSFET devices interfere with the proper operation of the devices, both by charging the MOSFET devices and overheating the circuitry.
• Some SLM designs have rough surfaces, which also reduce reflective efficiency. For example, in some SLM designs the reflective surface is an aluminum film deposited on an LPCVD silicon nitride layer. It is difficult to control the smoothness of these reflective mirror surfaces as they are deposited thin films. Thus, the final product has rough surfaces, which reduce the reflective efficiency.
• Another problem that reduces reflective efficiency with some SLM designs, particularly in some top hanging mirror designs, is large exposed hinge surface areas. These large exposed hinge surface areas have to be blocked by a slab, typically made of tungsten, on top of the hinge to prevent the scattering of incident light. These slabs significantly reduce the optically active area and lower the reflective efficiency.
• Many conventional SLMs, such as the SLM disclosed in U.S. Pat. No. 4,566,935, have hinges made of aluminum alloy. Aluminum, as well as other metals, is susceptible to fatigue and plastic deformation, which can lead to long-term reliability problems. Also, aluminum is susceptible to cell “memory”, where the rest position begins to tilt towards its most frequently occupied position. Further, the mirrors disclosed in the U.S. Pat. No. 4,566,935 patent are released by undercutting the mirror surface. This technique often results in breakage of the delicate micro-mirror structures during release. It also requires large gaps between mirrors, which reduce the fraction of the device area that is optically active.
• What is desired is an SLM with improved reflective efficiency, SLM device long-term reliability, and simplified manufacturing processes.
SUMMARY OF THE INVENTION
• The present invention is a spatial light modulator (SLM). In one embodiment, the SLM has a reflective selectively deflectable micro mirror array fabricated from a first substrate bonded to a second substrate having individually addressable electrodes. The second substrate may also have addressing and control circuitry for the micro mirror array. Alternatively, portions of the addressing and control circuitry are on a separate substrate and connected to the circuitry and electrodes on the second substrate.
• The micro array includes a controllably deflectable mirror plate with a reflective surface to reflect incident light. The mirror plate is connected to a vertical hinge by a connector, and the hinge is in turn connected to spacer walls by support posts. Each of the mirror plate, the connector, the vertical hinge, the support posts, and the spacer walls is fabricated from a first substrate. This first substrate is a wafer of a single material, single crystal silicon in one embodiment. The spacer walls provide separation between the mirror plate and an electrode associated with that mirror plate that controls the deflection of the mirror plate, and is located on the second substrate bonded to the micro mirror array. The close spacing of the mirror plates and the vertical orientation of the hinge allow the reflective surfaces to have a very high fill ratio for the micro mirror array. Very little light gets past the micro mirror array to strike the circuitry on the second substrate.
• The spatial light modulator is fabricated with few steps, which keeps the fabrication cost and complexity low. Cavities are formed in a first side of the first substrate. This is done in a single anisotropic etch in one embodiment. In parallel, the electrodes and addressing and control circuitry are fabricated on a first side of the second substrate. The first side of the first substrate is bonded to the first side of the second substrate. The sides are aligned so the electrodes on the second substrate are in proper relation with the mirror plates which the electrodes will control. The second side of the first substrate is thinned to the desired thickness. Optionally, a layer of reflective material may be deposited on a second side of the first substrate. A second anisotropic etch defines the support posts, the vertical hinges, and the connectors, and releases the mirror plates from the second side of the first substrate. Thus, the spatial light modulator may be fabricated by only two main etch steps.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a diagram that illustrates the general architecture of a spatial light modulator according to one embodiment of the invention.
• FIGS. 2aand2bare perspective views of a single micro mirror.
• FIGS. 3aand3bare perspective views showing the top and sides of a micro mirror array.
• FIGS. 4aand4bare perspective views showing the bottom and sides of the micro mirror array.
• FIGS. 5aand5bare top views of the micro mirror array.
• FIGS. 6aand6bare bottom views of the micro mirror array.
• FIGS. 7a-7dare perspective views showing the top, bottom, and sides of a single mirror of an alternate embodiment of the micro mirror array.
• FIGS. 8a-8dare perspective views showing the top and bottom of the alternate micro mirror array.
• FIG. 9ais a flowchart illustrating a preferred embodiment of how the spatial light modulator is fabricated.
• FIGS. 9bthrough9jare block diagrams illustrating the fabrication of the spatial light modulator in more detail.
• FIG. 10 illustrates the generation of the mask and the etching that forms the cavities in the first substrate in more detail.
• FIG. 11 is a perspective view of one embodiment of the electrodes formed on the second substrate.
• FIG. 12 is a perspective view showing the micro mirror array on the first substrate positioned over the electrodes and other circuitry on the second substrate.
• FIG. 13 illustrates a simplified embodiment of a mask that is used in etching the upper surface of the first substrate.
• FIG. 14 is a cross-section of a portion of the two substrates bonded together.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• The reflective spatial light modulator (“SLM”)100 has anarray103 of deflectable mirrors202. Individual mirrors202 can be selectively deflected by applying a voltage bias between that mirror and acorresponding electrode126. The deflection of eachmirror202 controls light reflected from a light source to a video display. Thus, controlling the deflection of amirror202 allows light striking that mirror202 to be reflected in a selected direction, and thereby allows control of the appearance of a pixel in the video display.
• Spatial Light Modulator Overview:
• FIG. 1 is a diagram that illustrates the general architecture of anSLM100 according to one embodiment of the invention. The illustrated embodiment has three layers. The first layer is amirror array103 that has a plurality of deflectable micro mirrors202. In one preferred embodiment; themicro-mirror array103 is fabricated from afirst substrate105 that is a single material, such as single crystal silicon.
• The second layer is anelectrode array104 with a plurality ofelectrodes126 for controlling the micro-mirrors202. Eachelectrode126 is associated with a micro-mirror202 and controls the deflection of that micro-mirror202. Addressing circuitry allows selection of asingle electrode126 for control of theparticular micro-mirror202 associated with thatelectrode126.
• The third layer is a layer ofcontrol circuitry106. Thiscontrol circuitry106 has addressing circuitry, which allows thecontrol circuitry106 to control a voltage applied to selectedelectrodes126. This allows thecontrol circuitry106 to control the deflections of themirrors202 in themirror array103 via theelectrodes126. Typically, thecontrol circuitry106 also includes adisplay control108, line memory buffers110, a pulsewidth modulation array112, and inputs forvideo signals120 and graphics signals122. Amicrocontroller114, optics controlcircuitry116, and aflash memory118 may be external components connected to thecontrol circuitry106, or may be included in thecontrol circuitry106 in some embodiments. In various embodiments, some of the above listed parts of thecontrol circuitry106 may be absent, may be on a separate substrate and connected to thecontrol circuitry106, or other additional components may be present as part of thecontrol circuitry106 or connected to thecontrol circuitry106.
• In one embodiment, both thesecond layer104 and thethird layer106 are fabricated using semiconductor fabrication technology on a singlesecond substrate107. That is, thesecond layer104 is not necessarily separate and above thethird layer106. Rather, the term “layer” is an aid for conceptualizing different parts of the spatiallight modulator100. For example, in one embodiment, both thesecond layer104 of electrodes is fabricated on top of the third layer ofcontrol circuitry106, both fabricated on a singlesecond substrate107. That is, theelectrodes126, as well as thedisplay control108, line memory buffers110, and the pulsewidth modulation array112 are all fabricated on a single substrate in one embodiment. Integration of several functional components of thecontrol circuitry106 on the same substrate provides an advantage of improved data transfer rate over conventional spatial light modulators, which have thedisplay control108, line memory buffers110, and the pulsewidth modulation array112 fabricated on a separate substrate. Further, fabricating the second layer of theelectrode array104 and the third layer of thecontrol circuitry106 on asingle substrate107 provides the advantage of simple and cheap fabrication, and a compact final product.
• After thelayers103,104, and106 are fabricated, they are bonded together to form theSLM100. The first layer with themirror array103 covers the second andthird layers104,106. The area under themirrors202 in themirror array103 determines how much room there is beneath thefirst layer103 for theelectrodes126, and addressing andcontrol circuitry106. There is limited room beneath the micro mirrors202 in themirror array103 to fit theelectrodes126 and the electronic components that form thedisplay control108, line memory buffers110, and the pulsewidth modulation array112. The present invention uses fabrication techniques (described more fully below) that allow the creation of small feature sizes, such as processes that allow fabrication of features of 0.18 microns, and processes that allow the fabrication of features of 0.13 microns or smaller. Conventional spatial light modulators are made through fabrication processes that do not allow such small features. Typically, conventional spatial light modulators are made through fabrication processes that limit feature size to approximately 1 micron or larger. Thus, the present invention allows the fabrication of many more circuit devices, such as transistors, in the limited area beneath the micro mirrors of themirror array103. This allows integration of items such as thedisplay control108, line memory buffers110, and the pulsewidth modulation array112 on the same substrate as theelectrodes126. Includingsuch control circuitry106 on thesame substrate107 as theelectrodes126 improves the performance of theSLM100.
• In other embodiments, various combinations of theelectrodes126 and components of the control circuitry may be fabricated on different substrates and electrically connected.
• The Mirror:
• FIG. 2ais a perspective view of a singlemicro mirror202. In one preferred embodiment, themicro mirror202 is fabricated from a wafer of a single material, such as single crystal silicon. Thus, thefirst substrate105 in such an embodiment is a wafer of single crystal silicon. Fabricating themicro mirror202 out of a single material wafer greatly simplifies the fabrication of themirror202. Further, single crystal silicon can be polished to create smooth mirror surfaces that have an order of magnitude smoother surface roughness than those of deposited films.Mirrors202 fabricated from single crystal silicon are mechanically rigid, which prevents undesired bending or warping of the mirror surface, and hinges fabricated from single crystal silicon are durable, flexible, and reliable. In other embodiments, other materials may be used instead of single crystal silicon. One possibility is the use of another type of silicon (e.g., polysilicon or amorphous silicon) for themicro mirror202, or even making themirror202 completely out of a metal (e.g., an aluminum alloy or tungsten alloy).
• Themicro mirror202 has atop mirror plate204. Thismirror plate204 is the portion of themicro mirror202 that is selectively deflected by applying a voltage bias between themirror202 and acorresponding electrode126. In one embodiment thisreflective mirror plate204 is substantially square in shape, and approximately fifteen microns by fifteen microns, for an approximate area of 225 square microns, although other shapes and sizes are also possible. In one preferred embodiment, a large proportion of the surface area of themicro mirror array103 is made up of the areas of themirror plates204 of the micro mirrors202.
• Themirror plate204 has a reflective surface that reflects light from a light source at an angle determined by the deflection of themirror plate204. This reflective surface may be the same material from which themicro mirror202 is fabricated, in which case the surface of themirror plate204 is polished to a smoothness that provides the desired level of reflectivity. Alternatively, after fabrication of themicro-mirrors202, a layer of reflective material, such as aluminum, maybe added to the surface of themirror plate204. Since in a preferred embodiment a large proportion of the surface area of themicro mirror array103 is made up of the areas of themirror plates204 of the micro mirrors, and themirror plates204 have reflective surfaces, a large proportion of the surface area of themicro mirror array103 is reflective and capable of reflecting light at a selected angle. Thus, theSLM100 has a large fill ratio, and efficiently reflects incident light.
• Themirror plate204 is connected to atorsion spring hinge206 by aconnector216. Thetorsion spring hinge206 is connected to aspacer support frame210, which holds thetorsion spring206 in place. Note that other springs and connection schemes between themirror plate204, thehinge206, andspacer support frame210 could also be used. Thetorsion spring hinge206 allows themirror plate204 to rotate relative to thespacer support frame210 about an axis between the walls of thespacer support frame210 when a force such as an electrostatic force is applied to themirror plate204 by applying a voltage between themirror202 and thecorresponding electrode126. This rotation produces the angular deflection for reflecting light in a selected direction. In one embodiment, this rotation occurs about an axis that is substantially collinear with the long axis of the hinge. In one preferred embodiment, thetorsion spring hinge206 has a “vertical” alignment. That is, thehinge206 has awidth222 that is smaller than the depth of the hinge (perpendicular to themirror plate204 surface). The width of the hinge is typically between 0.1 microns to 0.5 microns, and is approximately 0.2 microns in one embodiment. This “vertical” alignment of the hinge functions to help minimize non-reflective surfaces on the surface of themirror array103, and keep the fill ratio high.
• Thespacer support frame210 separates themirror plate204 from the electrodes and addressing circuitry so that themirror plate204 may deflect downward without contacting the electrodes and other circuitry below. Thespacer support frame210 includes spacer walls in one embodiment, which are typically not separate components from the rest of thespacer support frame210. These walls help define the height of thespacer support frame210. The height of thespacers210 is chosen based on the desired separation between themirror plates204 and theelectrodes126, and the topographic design of the electrodes. A larger height allows more deflection of themirror plate204, and a higher maximum deflection angle. A larger deflection angle provides a better contrast ratio. In one embodiment, the maximum deflection angle of themirror plate204 is 20 degrees. Thespacer support frame210 also provides support for thehinge206 and spaces themirror plate204 fromother mirror plates204 in themirror array103. Thespacer support frame210 has aspacer wall width212, which, when added to a gap between themirror plate204 and thesupport frame210, is substantially equal to the distance betweenadjacent mirror plates204 of adjacent micro mirrors202. In one embodiment, thespacer wall width212 is 1 micron or less. In one preferred embodiment, thespacer wall width212 is 0.5 microns or less. This places themirror plates204 closely together to increase the fill ratio of themirror array103.
• In some embodiments, themicro mirror202 includes elements that stop the deflection of themirror plate204 when theplate204 has deflected downward to a predetermined angle. Typically, these elements include a motion stop and a landing tip. When themirror surface204 deflects, the motion stop on themirror plate204 contacts the landing tip. When this occurs, themirror plate204 can deflect no further. There are several possible configurations for the motion stop and landing tip. In one embodiment, a landing tip is fabricated on the spacer frames210 opposite to the hinge side. The maximum tilt angle ofmirror plate204 will be limited by the landing tip on the spacer frames210 which stops the downward mechanical motion of themirror plate204. Having a fixed maximum tilt angle simplifies controlling the spatiallight modulator100 to reflect incident light in a known direction.
• In another embodiment, landing tips are fabricated along with theelectrodes126 on thesecond substrate107. The landing tips of this embodiment may be fabricated from an insulator, such as silicon dioxide, to prevent a short circuit between themirror plate204 and theelectrode126. The maximum tilt angle of themirror plate204 is limited in this embodiment by the angle at which themirror plate204 contacts the landing tip on thesecond substrate107. The height of thespacers210 affects this angle;higher spacers210 allow larger angles than lower ones. The landing tip on thesecond substrate107 can be a protruding bump, which reduces the total surface area actually in contact. The bumps can be held at the same electrical potential as themirror plate204 to avoid welding on contact.
• In yet another embodiment, the gap between themirror plate204 and thehinge206 is accurately fabricated so when themirror plate204 tilts to a predetermined angle, the comers of theplate204 near thehinge206 will contact the ends of thehinge206, which act as mechanical stops. This occurs because the section of thehinge206 connected to themirror plate204 deflects along with themirror plate204, but the sections of thehinge206 near thesupport wall210 remain relatively undeflected. For example, with a height of thetorsion hinge206 being 1 micron, a gap of 0.13 microns between the support wall and thehinge206 will result in a maximum tilting angle of themirror plate204 of 15 degrees.
• In one preferred embodiment, the motion stop and landing tip are both made out of the same material as the rest of themirror202, and are both fabricated out of thefirst substrate105. In embodiments where the material is single crystal silicon, the motion stop and landing tip are therefore made out of a hard material that has a long functional lifetime, which allows themirror array103 to last a long time. Further, because single crystal silicon is a hard material, the motion stop and landing tip can be fabricated with a small area where the motion stop contacts the landing tip, which greatly reduces sticking forces and allows themirror plate204 to deflect freely. Also, this means that the motion stop and landing tip remain at the same electrical potential, which prevents sticking that would occur via welding and charge injection processes were the motion stop and landing tip at different electrical potentials.
• FIG. 2bis a perspective view illustrating the underside of a singlemicro mirror202, including thesupport walls210, themirror plate204, thehinge206, and theconnector216.
• FIG. 3ais a perspective view showing the top and sides of amicro mirror array103 having nine micro mirrors202-1 through202-9. WhileFIG. 3ashows themicro mirror array103 with three rows and three columns, for a total of ninemicro mirrors202,micro mirror arrays103 of other sizes are also possible. Typically, eachmicro mirror202 corresponds to a pixel on a video display. Thus,larger arrays103 with moremicro mirrors202 provide a video display with more pixels. Since thehinges206 in themirror array103 all face in parallel along one direction, light sources are directed at themirrors202 in thearray103 along a single direction to be reflected to form a projected image on the video display.
• As shown inFIG. 3a, the surface of themicro mirror array103 has a large fill ratio. That is, most of the surface of themicro mirror array103 is made up of the reflective surfaces of themirror plates204 of the micro mirrors202. Very little of the surface of themicro mirror array103 is nonreflective. As illustrated inFIG. 3a, the nonreflective portions of themicro mirror array103 surface are the areas between the reflective surfaces of the micro mirrors202. For example, the width of the area between mirror202-1 and202-2 is determined by thespacer wall width212 and the sum of the width of the gaps between themirror plates204 of mirrors202-1 and202-2 and thesupport wall210. The gaps and thespacer wall width212 can be made as small as the feature size supported by the fabrication technique. Thus, in one embodiment, the gaps are 0.2 micron, and in another embodiment the gaps are 0.13 micron. As semiconductor fabrication techniques allow smaller features, the size of thespacer wall210 and the gaps can decrease to allow higher fill ratios.FIG. 3bis a perspective view detailing onemirror202 of themirror array103 ofFIG. 3a. Embodiments of the present invention allow fill ratios of 85%, 90%, or even higher.
• FIG. 4ais a perspective view showing the bottom and sides of themicro mirror array103 shown inFIG. 3. As shown inFIG. 4a, the spacer support frames210 of the micro mirrors202 define cavities beneath themirror plates204. These cavities provide room for themirror plates204 to deflect downwards, and also allow large areas beneath themirror plates204 for placement of thesecond layer104 with theelectrodes126, and/or the third layer with thecontrol circuitry106.FIG. 4bis a perspective view detailing onemirror202 of themirror array103 ofFIG. 4a.
• FIG. 5ais a top view of themicro mirror array103 having nine micro mirrors202-1 through202-9 shown inFIGS. 3aand4a. For example, for micro mirror202-1,FIG. 5aillustrates themirror plate204, thespacer support frame210, thetorsion spring206, and theconnector216 connecting themirror plate204 to thetorsion spring206.FIG. 5aalso clearly illustrates, as described above with respect toFIG. 3a, that themicro mirror array103 has a large fill ratio. Most of the surface of themicro mirror array103 is made up of the reflective surfaces of the micro mirrors202-1 through202-9.FIG. 5aclearly illustrates how fill ratio is determined by the areas of thereflective mirror plates204 and the areas between the reflective surfaces of themirror plates204. The size of the areas between the reflective surfaces of themirror plates204 in one embodiment is limited by the feature size limit of the fabrication process. This determines how small the gaps between themirror plate204 and thespacer wall210 can be made, and how thick thespacer wall210 is. Note that, while thesingle mirror202 as shown inFIG. 2 has been described as having its ownspacer support frame210, there are not typically two separate abuttingspacer walls210 between mirrors such as mirrors202-1 and202-2. Rather, there is typically one physical spacer wall of thesupport frame210 between mirrors202-1 and202-2.FIG. 5bis a perspective view detailing onemirror202 of themirror array103 ofFIG. 5a.
• FIG. 6ais a bottom view of themicro mirror array103 having nine micro mirrors202-1 through202-9, as shown inFIGS. 3 through 5.FIG. 6ashows the bottom of themirror plates204, as well as the bottoms of the spacer support frames210, the torsion springs206, and theconnectors216. The area beneath themirror plates204 is large enough in many embodiments to allow the optimum design and placement ofelectrodes126 andcontrol circuitry106, and space for accommodating a possible mirror landing tip.FIG. 6bis a perspective view detailing onemirror202 of themirror array103 ofFIG. 6a.
• As seen inFIGS. 5aand6a, very little light that is normal to themirror plate204 can pass beyond themicro mirror array103 to reach any theelectrodes126 orcontrol circuitry106 beneath themicro mirror array103. This is because thespacer support frame210, thetorsion spring206, theconnector216, and themirror plate204 provide near complete coverage for the circuitry beneath themicro mirror array103. Also, since thespacer support frame210 separates themirror plate204 from the circuitry beneath themicro mirror array103, light traveling at a non perpendicular angle to themirror plate204 and passing beyond themirror plate204 is likely to strike a wall of thespacer support frame210 and not reach the circuitry beneath themicro mirror array103. Since little intense light incident on themirror array103 reaches the circuitry, theSLM100 avoids problems associated with intense light striking the circuitry. These problems include the incident light heating up the circuitry, and the incident light photons charging circuitry elements, both of which can cause the circuitry to malfunction.
• InFIGS. 3-6 eachmicro mirror202 in themicro mirror array103 has itstorsion spring206 on the same side. In one alternate embodiment, differentmicro mirrors202 in themicro mirror array103 have torsion springs206 on different sides. For example, returning toFIG. 3a, mirrors202-1 and202-3 would havesprings206 on the same side as illustrated. Mirror202-2, in contrast, would have aspring206 on a different side so that thespring206 of mirror202-2 is perpendicular to thesprings206 of mirrors202-1 and202-3. This allows themirror plates204 of the different micro mirrors202-1 and202-2 to deflect in different directions, which gives themirror array103 as a whole more than one controllable degree of freedom. In this alternate embodiment, two different light sources (for example, light sources with differently colored light) can be directed toward themicro mirror array103 and separately selectively redirected by the micro mirrors202 in themicro mirror array103 form an image on a video display. In such an embodiment, multiplemicro mirrors202 can be used to reflect light from the multiple light sources to the same pixel in the video display. For example, two different color light sources can be directed toward themirror array103 along different directions, and reflected by thearray103 to form a multicolor image on a video display. The micro mirrors202-1 and202-3 with torsion springs206 on a first side control the reflection of a first light source to the video display. The micro mirrors such as micro mirror202-2 with torsion springs206 on a different second side control the reflection of a second light source to the video display.
• FIG. 7ais a perspective view of amicro mirror702 according to an alternate embodiment of the invention. Thetorsion hinge206 in this embodiment is diagonally oriented with respect to thespacer support wall210, and divides themirror plate204 into two parts, or sides: afirst side704 and asecond side706. Twoelectrodes126 are associated with themirror702, oneelectrode126 for afirst side704 and oneelectrode126 for asecond side706. This allows eitherside704,706 to be attracted to one of theelectrodes126 beneath and pivot downward, and provides more total range of angular motion for thesame support wall210 height as compared to the mirror illustrated inFIGS. 2-6.FIG. 7bis a more detailed view of themirror702 and illustrates themirror plate204, hinge206, andsupport wall210.FIGS. 7cand7dillustrate the underside of asingle mirror702 and a more detailed view of the interior corner of themirror702. In other embodiments, thehinge206 may be substantially parallel to one of the sides of themirror plate204, rather than diagonal, and still be positioned to divide themirror plate204 into twoparts704,706.
• FIGS. 8athrough8dare various perspective views of mirror arrays composed of multiplemicro mirrors702 as described inFIGS. 7athrough7d.FIGS. 8aand8billustrate the top of amirror702 array and a more detailed view of onemirror702 in the array.FIGS. 8cand8dillustrate the underside of amirror702 array and a more detailed view of onemirror702 in the array.
• Fabrication of the Spatial Light Modulator:
• FIG. 9ais a flowchart illustrating one preferred embodiment of how the spatiallight modulator100 is fabricated.FIGS. 9bthrough9gare block diagrams illustrating the fabrication of the spatiallight modulator100 in more detail. In summary, the micro mirrors202 are partially fabricated on thefirst substrate105. Separately, some or all of the electrodes, addressing circuitry, and control circuitry are fabricated on thesecond substrate107. The first andsecond substrates105 and107 are then bonded together. Thefirst substrate105 is thinned, then lithography and etch steps follow. Then the fabrication of the micro mirrors202 is completed. Final steps, including packaging, complete the spatiallight modulator100. In one embodiment, themirror array103 is fabricated from a wafer of single crystal silicon using only anisotropic dry etch methods, only two etches are done to fabricate themirror array103, and the circuitry is fabricated using standard CMOS techniques. This provides an easy and inexpensive way to fabricate theSLM100.
• Conventional spatial light modulators are fabricated with surface micro machining techniques that include etching, deposition of structural layers, deposition and removal of sacrificial layers. These conventional MEMS fabrication techniques result in poor yield, poor uniformity, and result feature sizes of approximately 1 micron or larger. In contrast, one embodiment of the present invention uses semiconductor fabrication techniques, which do not include sacrificial layers, have much higher yields, and allow creation of features of 0.13 microns or smaller.
• Referring toFIG. 9a, a first mask is generated902 to initially partially fabricate the micro mirrors202. This mask defines what will be etched from one side of thefirst substrate105 to form the cavities on the underside of themicro mirror array103 that define the spacer support frames210 and support posts208. Standard techniques, such as photolithography, can be used to generate the mask on the first substrate. As mentioned previously, in one preferred embodiment the micro mirrors202 are formed from a single material, such as single crystal silicon. Thus, in one preferred embodiment, thefirst substrate105 is a wafer of single crystal silicon. Note that typically multiplemicro mirror arrays103, to be used inmultiple SLMs100, are fabricated on a single wafer, to be separated later. The structures fabricated to create themicro mirror array103 are typically larger than the features used in CMOS circuitry, so it is relatively easy to form themicro mirror array103 structures using known techniques for fabricating CMOS circuitry.FIG. 9bis a side view that illustrates thefirst substrate105 prior to fabrication. Thesubstrate105 initially includes adevice layer938, which is the material from which themirror array103 will be fabricated, an insulatingoxide layer936, and ahandling substrate934.FIG. 9cis a side view that illustrates thefirst substrate105 with the mask upon it.
• After the mask is generated902, in a preferred embodiment, thefirst substrate105 is anisotropically ion etched904 to form the cavities beneath themirror plates204. Put in another way, a “well” is formed in the first substrate for everymicro mirror202. Other methods besides an anisotropic ion etch may also be used to form the cavities or “wells,” such as a wet etch or a plasma etch.FIG. 9dis a block diagram that shows thefirst substrate105 with the cavities etched.
• Separately from the fabrication of the cavities beneath themirror plates204, theelectrodes126 andcontrol circuitry106 are fabricated906 on thesecond substrate107. Thesecond substrate107 may be a transparent material, such as quartz, or another material. If the second substrate is quartz, transistors may be made from polysilicon, as compared to crystalline silicon. The circuitry can be fabricated906 using standard CMOS fabrication technology. For example, in one embodiment, thecontrol circuitry106 fabricated906 on thesecond substrate107 includes an array of memory cells, row address circuitry, and column data loading circuitry. There are many different methods to make electrical circuitry that performs the addressing function. The DRAM, SRAM, and latch devices commonly known may all perform the addressing function. Since themirror plate204 area may be relatively large on semiconductor scales (for example, themirror plate204 may have an area of 225 square microns), complex circuitry can be manufactured beneathmicro mirror202. Possible circuitry includes, but is not limited to, storage buffers to store time sequential pixel information, circuitry to compensate for possible non-uniformity ofmirror plate204 toelectrode126 separation distances by driving theelectrodes126 at varying voltage levels, and circuitry to perform pulse width modulation conversions.
• Thiscontrol circuitry106 is covered with a passivation layer such as silicon oxide or silicon nitride. Next, a metallization layer is deposited. This metallization layer is patterned and etched to defineelectrodes126, as well as a bias/reset bus in one embodiment. Theelectrodes126 are placed during fabrication so that one or more of theelectrodes126 corresponds to eachmicro mirror202. As with thefirst substrate105, typically multiple sets of circuitry to be used inmultiple SLMs100 are fabricated906 on thesecond substrate107 to be separated later.
• Next, the first and second substrates are bonded910 together. The side of thefirst substrate105 that has the cavities is bonded to the side of thesecond substrate107 that has the electrodes. Thesubstrates105 and107 are aligned so that the electrodes on thesecond substrate107 are in the proper position to control the deflection of the micro mirrors202 in themicro mirror array103. In one embodiment, the twosubstrates105 and107 are optically aligned using double focusing microscopes by aligning a pattern on thefirst substrate105 with a pattern on thesecond substrate107, and the twosubstrates105 and107 are bonded together by low temperature bonding methods such as anodic or eutectic bonding. There are many possible alternate embodiments to thefabrication906. For example, thermoplastics or dielectric spin glass bonding materials can be used, so that thesubstrates105 and107 are bonded thermal-mechanically.FIG. 9eis a side view that shows the first andsecond substrates105,107 bonded together.
• After bonding the first andsecond substrates105 and107 together, the surface of thefirst substrate105 that has not been etched is thinned912 to a desired thickness. First, the handlingsubstrate934 is removed, as shown inFIG. 9f, typically by grinding or etching. Then theoxide936 is removed. Then, thedevice layer938 is thinned or polished, if necessary. This thinning is done in one embodiment by mechanical grinding thesubstrate105 to a thickness between the bottom of the fabricated “well” and the opposing surface of thefirst substrate105 that is near the desired thickness of themicro mirror202. In one embodiment, this thickness achieved by mechanical grinding is approximately 5 microns. Thesubstrate105 is then polished by mechanical fine polishing or chemical mechanical polishing to thickness desired between the bottom of the “well” and the opposing surface of thefirst substrate105. This thickness defines the thickness of themirror plates204. In one embodiment, this desired thickness is less than approximately 1 micron or less.FIG. 9gis a side view showing the bonded first andsecond substrates105,107 after thefirst substrate105 has been thinned.
• Next, the reflective surface of themicro mirror202 is created. This can be done through polishing913 thefirst substrate105 so that the surface of thefirst substrate105 is reflective. It is also possible to deposit914 a layer of a reflective material on thefirst substrate105 to create a reflective surface. Other methods to create a reflective surface may also be used.
• In one embodiment, a reflective layer of aluminum is deposited914. The thinned surface of thefirst substrate105 is coated with approximately 10 nm of titanium seed thin film. Then an approximately 30 nm thick layer of aluminum is deposited to form a reflective layer with a reflectivity above 95% over much of the visible optical spectrum.FIG. 9his a side view that shows a depositedreflective layer932.
• The reflective surface of thefirst substrate105 is then masked and, in a preferred embodiment, high-aspect-ratio anisotropically ion etched916 to finish forming themicro mirror array103 and release themirror plates204. This second etch defines themirror plate204, thetorsion spring hinge206, and theconnector216. Thus, it only takes two etchings of thefirst substrate105 to fabricate the micro mirrors202. This significantly decreases the cost of fabricating the micro mirrors202.FIG. 9iis a block diagram showing the surface of thefirst substrate105 covered with themask933, andFIG. 9jis a block diagram showing the spatiallight modulator100 after the second etching, including themirror plate204, thehinge206, thespacer support frame210, and theelectrode126.
• In some embodiments, thehinges206 are partially etched to be recessed from the surface of themirror plates204. Also, in some embodiments a reflective surface is deposited914 after the second etch that defines themirror plate204, thetorsion spring hinge206, and theconnector216. Such a reflective layer may be deposited by, for example, evaporating aluminum downwardly at an angle such that the horizontal vector of the angle is frommirror plate204 to hinges206. With this angle, and if thehinges206 were etched so that they are recessed from the surface of themirror plates204, it is possible to deposit substantially no reflective coating on the surfaces of recessed hinges206 to minimize the optical scattering of incident light by the surfaces of the torsion hinges206. The evaporation may occur, for example, in the reaction chamber of an e-gun thermal evaporator at a deposition rate of one nanometer per second.
• In some embodiments, themicro-mirror array103 is protected by a piece of glass or other transparent material. In one embodiment, during fabrication of themicro mirror array103, a rim is left around the perimeter of eachmicro mirror array103 fabricated on thefirst substrate105. To protect the micro mirrors202 in themicro mirror array103, a piece of glass or other transparent material is bonded918 to the rim. This transparent material protects the micro mirrors202 from physical harm. In one alternative embodiment, lithography is used to produce an array of rims in a layer of photosensitive resin on a glass plate. Then epoxy is applied to the upper edge of the rims, and the glass plate is aligned and attached to the completedreflective SLM100.
• As discussed above, multiple spatiallight modulators100 may be fabricated from the twosubstrates105 and107; multiplemicro mirror arrays103 may be fabricated in thefirst substrate105 and multiple sets of circuitry may be fabricated in thesecond substrate107. Fabricatingmultiple SLMs100 increases the efficiency of the spatiallight modulator100 fabrication process. However, ifmultiple SLMs100 are fabricated at once, they must be separated into theindividual SLMs100. There are many ways to separate each spatiallight modulator100 and ready it for use. In a first method, each spatiallight modulator100 is simply die separated920 from the rest of theSLMs100 on the combinedsubstrates105 and107. Each separated spatiallight modulator100 is then packaged922 using standard packaging techniques.
• In a second method, a wafer-level-chip-scale packaging is carried out to encapsulate eachSLM100 into separate cavities and form electrical leads before theSLMs100 are separated. This further protects the reflective deflectable elements and reduces the packaging cost. In one embodiment of this method, the backside of thesecond substrate107 is bonded924 with solder bumps. The backside of thesecond substrate107 is then etched926 to expose metal connectors that were formed during fabrication of the circuitry on thesecond substrate107. Next, conductive lines are deposited928 between the metal connectors and the solder bumps to electrically connect the two. Finally, the multiple SLMs are die separated930.
• FIG. 10 illustrates thegeneration902 of the mask1000 and theetching904 that forms the cavities in the first substrate in more detail. In a preferred embodiment, the first substrate is a wafer of single crystal silicon. Oxide is deposited and patterned on the first substrate. This results in the pattern shown inFIG. 10, wherearea1004 is oxide that will prevent the substrate beneath from being etched, andareas1002 are areas of exposed substrate. The areas of exposedsubstrate1002 will be etched to form the cavities. Theareas1004 that are not etched remain, and form the spacer support posts208 and thespacer support frame210.
• In one embodiment, the substrate is etched in a reactive ion etch chamber flowing with SF₆, HBr, and oxygen gases at flow rates of 100 sccm, 50 sccm, and 10 sccm respectively. The operating pressure is in the range of 10 to 50 mTorr, the bias power is 60 W, and the source power is 300 W. In another embodiment, the substrate is etched in a reactive ion etch chamber flowing with Cl₂, HBr, and oxygen gases at flow rates of 100 sccm, 50 sccm, and 10 sccm respectively. In these embodiments, the etch processes stop when the cavities are about 3-4 microns deep. This depth is measured using in-situ etch depth monitoring, such as in-situ optical interferometer techniques, or by timing the etch rate.
• In another embodiment, the cavities are formed in the wafer by an anisotropic reactive ion etch process. The wafer is placed in a reaction chamber. SF₆, HBr, and oxygen gases are introduced into the reaction chamber at a total flow rate of 100 sccm, 50 sccm, and 20 sccm respectively. A bias power setting of 50 W and a source power of 150 W are used at a pressure of 50 mTorr for approximately 5 minutes. The wafers are then cooled with a backside helium gas flow of 20 sccm at a pressure of 1 mTorr. In one preferred embodiment, the etch processes stop when the cavities are about 3-4 microns deep. This depth is measured using in-situ etch depth monitoring, such as in-situ optical interferometer techniques, or by timing the etch rate.
• FIG. 11 is a perspective view of one embodiment of theelectrodes126 formed on thesecond substrate107. In this embodiment, eachmicro mirror202 has acorresponding electrode126. Theelectrodes126 in this illustrated embodiment are fabricated to be higher than the rest of the circuitry on thesecond substrate107. As shown inFIG. 11, material on the sides of theelectrodes126 slopes down from the electrodes' top surface in a somewhat pyramid shape. In other embodiments, theelectrodes126 are located on the same level as the rest of the circuitry on thesecond substrate107, rather than extending above the circuitry. In one embodiment of the invention, theelectrodes126 are individual aluminum pads of approximately 10×10 microns in size. Theseelectrodes126 are fabricated on the surface of thesecond substrate107. The large surface area of theelectrodes126 in this embodiment results in relatively low addressing voltages required to pull themirror plate204 down onto the mechanical stops, to cause the full predetermined angular deflection of themirror plates204.
• FIG. 12 is a perspective view showing themicro mirror array103 on thefirst substrate105 positioned over theelectrodes126 and other circuitry on thesecond substrate107. This illustrates the relative positions of the micro mirrors202 in themicro mirror array103 and the electrodes prior tobonding910 the first andsecond substrates105 and107 together. Note that, for illustrative purposes, the micro mirrors202 in themicro mirror array103 are shown as completed micro mirrors202. However, in a preferred embodiment, as described with respect toFIG. 9a, only the cavities beneath themirror plates204 in thefirst substrate105 would have been etched prior to bonding thefirst substrate105 to thesecond substrate107. Themirror plate204, hinges206, andconnectors216 would not be fabricated yet. In embodiments where theelectrodes126 are located above the level of the rest of the circuitry and material on the side of theelectrodes126 slopes down, the sloping material helps correctly position thefirst substrate105 on thesecond substrate107.
• FIG. 13 illustrates a simplified embodiment of a mask that is used inetching916 the upper surface of thefirst substrate105. In theetching916 step,areas1302 are left exposed and are etched to release themirror plates204 and form the torsion springs206, theconnectors216, and the support posts208.Other areas1304 are covered with photoresist material and are not etched. These areas include themirror plates204 themselves and the material that will form the hinges206. As shown inFIG. 13, most of the surface of themirror array103 is reflective. The fabrication process only creates small nonreflective gaps that separate themirror plates204 from thesupport walls210 and hinges206.
• The upper surface of thefirst substrate105 is etched to release themirror plates204 and form thehinges206 after the upper surface of thefirst substrate105 is masked. In one embodiment, it is etched in a reactive ion etch chamber flowing with SF₆, HBr, and oxygen gases at a flow rate of 100 sccm, 50 sccm, and 10 sccm respectively. The operating pressure is in the range of 10 to 50 mTorr, and the bias power of 60 W and a source power 300 W. Since the etch depth is typically less than 1 micron, there are several other fabrication processes can achieve the same goal. Another embodiment uses Cl₂and oxygen gases at an operating pressure of 10 mTorr to 50 mTorr with bias and source power settings of the etching reaction chamber of 50 W and 300 W, respectively, to achieve tight dimension control. The etch process is stopped at the desired depth (in one embodiment, about 5 microns deep) using in-situ etch depth monitoring or by timing the etch rate.
• Operation:
• In operation, individual reflective elements are selectively deflected and serve to spatially modulate light that is incident to and reflected by the mirrors.
• FIG. 14 is a cross-section that shows themicro mirror202 above anelectrode126. In operation, a voltage is applied to anelectrode126 to control the deflection of thecorresponding mirror plate204 above theelectrode126. As shown inFIG. 14, when a voltage is applied to theelectrode126, themirror plate204 is attracted to the electrode. This causes themirror plate204 to rotate about thetorsion spring206. When the voltage is removed from theelectrode126, thehinge206 causes themirror plate204 to spring back upward. Thus, light striking themirror plate204 is reflected in a direction that can be controlled by the application of voltage to the electrode.
• One embodiment is operated as follows. Initially the mirror plate is undeflected. In this unbiased state, an incoming light beam, from a light source, obliquely incident toSLM100 is reflected by theflat mirror plates204. The outgoing, reflected light beam may be received by, for example, an optical dump. The light reflected from theundeflected mirror plate204 is not reflected to a video display.
• When a voltage bias applied between themirror plate204 and thebottom electrode126, themirror plate204 is deflected due to electrostatic attraction. Because of the design of thehinge206, the free end of themirror plate204 is deflected towards thesecond substrate107. Note that in one preferred embodiment substantially all the bending occurs in thehinge206 rather than themirror plate204. This may be accomplished in one embodiment by making thehinge width222 thin, and connecting thehinge206 to the support posts208 only on both ends. The deflection of themirror plate204 is limited by motion stops, as described above. The full deflection of themirror plate204 deflects the outgoing reflected light beam into the imaging optics and to the video display.
• When themirror plate204 deflects past the “snapping” or “pulling” voltage (approximately 12 volts in one embodiment), the restoring mechanical force or torque of thehinge206 can no longer balance the electrostatic force or torque and themirror plate204 “snaps” down toward theelectrode126 to achieve full deflection, limited only by the motion stops. To release themirror plate204 from its fully deflected position, the voltage must be lowered substantially below the snapping voltage to a releasing voltage (e.g., approximately 3.3 volts, in the embodiment where the snapping voltage is 5.0 volts). Thus, themicro mirror202 is an electromechanically bistable device. Given a specific voltage between the releasing voltage and the snapping voltage, there are two possible deflection angles at which themirror plate204 may be, depending on the history ofmirror plate204 deflection. Therefore, themirror plate204 deflection acts as a latch. These bistability and latching properties exist since the mechanical force required for deflection of themirror plate204 is roughly linear with respect to deflection angle, whereas the opposing electrostatic force is inversely proportional to the distance between themirror plate204 and theelectrode126.
• Since the electrostatic force between themirror plate204 and theelectrode126 depends on the total voltage between themirror plate204 and theelectrode126, a negative voltage applied to amirror plate204 reduces the positive voltage needed to be applied to theelectrode126 to achieve a given deflection amount. Thus, applying a voltage to amirror array103 can reduce the voltage magnitude requirement of theelectrodes126. This can be useful, for example, because in some applications it is desirable to keep the maximum voltage that must be applied to theelectrodes126 below 12V because a 5V switching capability is more common in the semiconductor industry. In addition, the amount of charge needed to bias eachelectrode126 where a voltage is applied to amirror array103 is smaller than the charge needed in an embodiment in which themirror array103 is held at a ground potential. Thus the time required to correctly apply the proper voltage to theelectrode126 and deflect themirror plate204 is relatively fast.
• Since the maximum deflection of themirror plate204 is fixed, theSLM100 can be operated in a digital manner if it is operated at voltages past the snapping voltage. The operation is essentially digital because themirror plate204 is either fully deflected downward by application of a voltage to the associatedelectrode126 or is allowed to spring upward, with no voltage applied to the associatedelectrode126. A voltage that causes themirror plate204 to fully deflect downward until stopped by the physical elements that stop the deflection of themirror plate204 is known as a “snapping” or “pulling” voltage. Thus, to deflect themirror plate204 fully downward, a voltage equal or greater to the snapping voltage is applied to thecorresponding electrode126. In video display applications, when themirror plate204 is fully deflected downward, the incident light on thatmirror plate204 is reflected to a corresponding pixel on a video display. When themirror plate204 is allowed to spring upward, the light is reflected in such a direction so that it does not strike the video display.
• During such digital operation, it is not necessary to keep the full snapping voltage on anelectrode126 after an associatedmirror plate204 has been fully deflected. During an “addressing stage,” voltages for selectedelectrodes126 that correspond to themirror plates204 which should be fully deflected are set to levels required to deflect themirror plates204. After themirror plates204 in question have deflected due to the voltages onelectrodes126, the voltage required to hold themirror plates204 in the deflected position is less than that required for the actual deflection. This is because the gap between the deflectedmirror plate204 and the addressingelectrode126 is smaller than when themirror plate204 is in the process of being deflected. Therefore, in the “hold stage” after the addressing stage the voltage applied to the selectedelectrodes126 can be reduced from its original required level without substantially affecting the state of deflection of themirror plates204. One advantage of having a lower hold stage voltage is that nearbyundeflected mirror plates204 are subject to a smaller electrostatic attractive force, and they therefore remain closer to a zero-deflected position. This improves the optical contrast ratio between the deflectedmirror plates204 and theundeflected mirror plates204.
• With the appropriate choice of dimensions (in one embodiment,spacer210 separation between themirror plate204 and theelectrode126 of 1 to 5 microns and hinge206 thickness of 0.05 to 0.45 microns) and materials (such as single crystal silicon (100)), areflective SLM100 can be made to have an operating voltage of only a few volts. The torsion modulus of thehinge206 made of single crystal silicon may be, for example, 5×10¹⁰Newton per meter-squared per radium. The voltage at which theelectrode126 operates to fully deflect the associatedmirror plate204 can be made even lower by maintaining themirror plate204 at an appropriate voltage (a “negative bias”), rather than ground. This results in a larger deflection angle for a given voltage applied to anelectrode126. The maximum negative bias voltage is the releasing voltage, so when the addressing voltage reduced to zero themirror plate204 can snap back to the undeflected position.
• It is also possible to control themirror plate204 deflections in a more “analog” manner. Voltages less than the “snapping voltage” are applied to deflect themirror plate204 and control the direction in which the incident light is reflected.
• Alternate Applications:
• Aside from video displays, the spatiallight modulator100 is also useful in other applications. One such application is in maskless photolithography, where the spatiallight modulator100 directs light to develop deposited photoresist. This removes the need for a mask to correctly develop the photoresist in the desired pattern.
• Although the invention has been particularly shown and described with reference to multiple embodiments, it will be understood by persons skilled in the relevant art that various changes in form and details can be made therein without departing from the spirit and scope of the invention. For example, themirror plates204 may be deflected through methods other than electrostatic attraction as well. Themirror plates204 may be deflected using magnetic, thermal, or piezo-electric actuation instead.

Claims (24)

1. A method of fabricating a spatial light modulator, the method comprising:

forming cavities in a first side of a first substrate;

fabricating electrodes and addressing and control circuitry on a first side of a second substrate;

then bonding the first side of the first substrate to the first side of the second substrate; and

then forming hinges, connectors, and mirror plates on a second side of the first substrate.

2. The method ofclaim 1 wherein the first substrate comprises a single continuous piece of a material.

3. The method ofclaim 2 wherein the first substrate comprises single crystal silicon.

4. The method ofclaim 1 wherein the cavities define a spacer support frame extending to a predetermined depth into the first substrate.

5. The method ofclaim 4 wherein the spacer support frame comprises a plurality of spacer walls.

6. The method ofclaim 5 wherein the plurality of spacer walls form a grid-based three-dimensional structure surrounding the cavities on four sides.

7. The method ofclaim 4 wherein the hinges are connected to the spacer support frame.

8. A method of fabricating a plurality of mirror plates of a spatial light modulator for display applications, the method comprising:

forming a plurality of wells in a first side of a first substrate;

fabricating addressing and control circuitry and electrodes on a second substrate;

bonding the first side of the first substrate to the second substrate; and

then processing the second side of the first substrate to release the plurality of mirror plates from the first substrate.

9. The method ofclaim 8 wherein the mirror plates are connected to the first substrate by hinges.

10. The method ofclaim 8 wherein the plurality of wells are bordered in a plane parallel to the first side of the first substrate by a plurality of spacer walls.

11. The method ofclaim 10 wherein the plurality of spacer walls form a two-dimensional grid pattern in the plane parallel of the first substrate.

12. The method ofclaim 10 wherein the spacer walls define a separation between the mirror plates of the first substrate and the electrodes on the second substrate.

13. The method ofclaim 8 further comprising thinning the second side of the first substrate prior to processing the second side of the first substrate.

14. The method ofclaim 13 further comprising depositing a reflective surface on the second side of the first substrate.

15. The method ofclaim 8 wherein fabricating addressing and control circuitry comprises fabricating a memory buffer, a display controller and a pulse width modulation array.

16. The method ofclaim 8 further comprising, prior to bonding the first side of the first substrate to the second substrate, aligning the first substrate with the second substrate so that the electrodes on the second substrate are positioned to control the deflection of mirror plates in the first substrate when the first and second substrates are bonded together.

17. The method ofclaim 16 wherein aligning the first substrate with the second substrate comprises aligning a pattern on the first substrate with a pattern on the second substrate.

18. The method ofclaim 8 wherein bonding the first side of the first substrate to the second substrate comprises using a low temperature bonding method performed at less than approximately 500 degrees Celsius.

19. A method of fabricating an array of micro-mirrors for a reflective spatial light modulator, the method comprising:

forming an array of cavities in a first side of a first substrate;

fabricating addressing and control circuitry and an array of electrodes on a first side of a second substrate;

then bonding the first side of the first substrate to the first side of the second substrate; and

then forming the array of micro-mirrors on a second side of the first substrate, wherein the micro-mirrors in the array of micro-mirrors comprise a mirror plate and a hinge.

20. The method ofclaim 19 further comprising aligning the first substrate with the second substrate so that the array of electrodes are positioned to control the deflection of an associated mirror plate in the array of micro-mirrors when the first and second substrates are bonded together.

21. The method ofclaim 20 wherein the array of cavities provide room for the associated mirror plate in the array of micro-mirrors to deflect.

22. The method ofclaim 19 wherein the first substrate comprises single crystal silicon.

23. The method ofclaim 19 wherein boundary regions of the array of cavities form a spacer support frame extending to a predetermined depth into the first substrate.

24. The method ofclaim 23 wherein the boundary regions comprise a plurality of spacer walls.

Images