US20060108651A1 - Lowered Source/Drain Transistors - Google Patents

Abstract

A novel transistor structure and method for fabrication the same. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. The method for fabricating the transistor structure starts out with a planar semiconductor layer and a gate stack on top of the semiconductor layer. Then, top regions of the semiconductor layer on opposing sides of the gate stack are removed. Then, regions beneath the removed regions are doped to form lowered S/D regions of the transistor structure

Description

BACKGROUND OF THE INVENTION
• 1. Technical Field
• The present invention relates to semiconductor transistors, and more particularly, to lowered source/drain semiconductor transistors.
• 2. Related Art
• A typical semiconductor transistor comprises a channel region and first and second source/drain (S/D) regions formed in a semiconductor layer, wherein the channel region is disposed between the first and second S/D regions. The typical semiconductor transistor further comprises a gate stack (that includes a gate dielectric region directly on top the channel region and a gate region on top of the gate dielectric region) directly above the channel region. In addition, first and second gate spacers are formed on sidewalls of the gate stack so as to define the first and second S/D regions, respectively. The capacitance between the gate region and the first S/D region has several components one of which is defined by a path from the gate region to the first S/D region through the first gate spacer. This capacitance component is usually referred to as the out-fringing capacitance. For example, the out-fringing capacitance between the gate region and the second S/D region is defined by a path from the gate region to the second S/D region through the second gate spacer.
• It is desirable to minimize the out-fringing capacitances between the gate region and the first and second S/D regions in order to increase transistor performance or to reduce transistor switching time. Therefore, there is a need for a novel transistor structure in which the out-fringing capacitances between the gate region and the first and second S/D regions are relatively less than those of the prior art. There is also a need for a method for fabricating the novel transistor structure.
SUMMARY OF THE INVENTION
• The present invention provides a semiconductor structure, comprising (a) a semiconductor layer including a channel region and first and second source/drain regions, wherein the channel region is disposed between the first and second source/drain regions, and wherein top surfaces of the first and second source/drain regions are below a top surface of the channel region; (b) a gate dielectric region on the channel region; and (c) a gate region on the gate dielectric region, wherein the gate region is electrically isolated from the channel region by the gate dielectric region.
• The present invention also provides a method for fabricating a semiconductor structure, the method comprising the steps of (a) providing a semiconductor layer and a gate stack on the semiconductor layer, wherein the semiconductor layer comprises (i) a channel region directly beneath the gate stack and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions; (b) removing the first and second semiconductor regions; and (c) doping regions directly beneath the removed first and second semiconductor regions so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.
• The present invention also provides a method for fabricating a semiconductor structure, the method comprising the steps of (a) providing (i) an underlying dielectric layer, (ii) a semiconductor layer on the underlying dielectric layer, and (iii) a gate stack on the semiconductor layer; (b) implanting first dopants in a top layer of the underlying dielectric layer except in a separating dielectric region of the top layer directly beneath the gate stack; (c) removing the top layer of the underlying dielectric layer except the separating dielectric region; (d) epitaxially growing semiconductor regions to fill the removed top layer of the underlying dielectric layer; and (e) implanting second dopants in semiconductor regions of the semiconductor layer and the epitaxially grown semiconductor regions on opposing sides of the gate stack so as to form first and second source/drain regions such that the separating dielectric region is disposed between the first and second source/drain regions.
• The present invention provides a novel transistor structure in which the out-fringing capacitances between the gate region and the first and second S/D regions are relatively less than those of the prior art. The present invention also provides a method for fabricating the novel transistor structure.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIGS. 1A-1K show cross-section views of a semiconductor structure used to illustrate a method of fabricating semiconductor structures, in accordance with embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
• FIGS. 1A-1K show cross-section views of asemiconductor structure100 used to illustrate a method of fabricating semiconductor structures, in accordance with embodiments of the present invention. More specifically, with reference toFIG. 1A, in one embodiment, the method starts out with an SOI (silicon on insulator)substrate110 comprising, illustratively, asilicon layer110a, an underlyingdielectric layer110b(usually referred to as BOX, i.e., buried oxide layer) on top of thesilicon layer110a, and anothersilicon layer110con top of the underlyingdielectric layer110b. Starting fromFIG. 1B, thesilicon layer110ais omitted for simplicity.
• Next, in one embodiment, the method comprises the step of forming a gatedielectric layer120 on top of thesilicon layer110c. In one embodiment, the gatedielectric layer120 can comprise silicon dioxide and can be formed by thermally oxidizing atop surface112 of thesilicon layer110c.
• Next, in one embodiment, agate layer130 is formed on top of the gatedielectric layer120. In one embodiment, thegate layer130 can comprise poly-silicon. Next, in one embodiment, a hard maskdielectric layer140 is formed on top of the poly-silicon layer130. In one embodiment, hard maskdielectric layer140 can comprise silicon dioxide and can be formed by, illustratively, chemical vapor deposition (i.e., CVD). Then, in one embodiment, aphotoresist layer150 is formed on top of the hard maskdielectric layer140.
• Next, in one embodiment, thephotoresist layer150 is patterned to become the patternedphotoresist layer150′ by, illustratively, photolithography (i.e., the regions of thephotoresist layer150 represented by the dashed lines are removed).
• Next, in one embodiment, the patternedphotoresist layer150′ can be used as a mask to etch the hard maskdielectric layer140 and then thegate layer130 so as to form the hard maskdielectric region140′ and thegate region130′, respectively. In other words, the regions of the hard maskdielectric layer140 and thegate layer130 represented by the dashed lines are removed.
• Next, with reference toFIG. 1B, in one embodiment, the method proceeds with an implantation step of using theregions130′,140′, and150′ as a mask to implant nitrogen in atop layer114 of the underlyingdielectric layer110b. As a result,regions114aand114bof thetop layer114 are doped with nitrogen except for a separatingdielectric region114cdirectly beneath theregions130′,140′, and150′. In general, any dopants can be used here instead of nitrogen provided that thedoped regions114aand114bdoped with the dopants can be later etched away (i.e., removed) essentially without affecting the other regions of the underlyingdielectric layer110b.
• Next, with reference toFIG. 1C, in one embodiment, the patternedphotoresist layer150′ (FIG. 1B) can be removed, and anitride layer150 can be blanket-deposited on top of thestructure100.
• Next, with reference toFIG. 1D, in one embodiment, the method can proceed with an anisotropic etching step that removes most of thenitride layer150 and leavesnitride spacers150aand150bon sidewalls of thegate stack130′,140′ (that comprises thegate region130′ and the hard maskdielectric region140′). In one embodiment, the anisotropic etching step can be RIE (Reactive Ion Etching). Next, in one embodiment, an oxide (e.g., SiO₂)layer160 can be blanket-deposited on thestructure100 by, illustratively, CVD.
• Next, in one embodiment, thegate stack130′,140′ can be used as a mask to implant germanium in atop layer116 of thesilicon layer110c. As a result, dopedregions116aand116bof thetop layer116 are doped with germanium except for aregion116cdirectly beneath thegate stack130′,140′. In general, any dopants can be used here instead of germanium provided that the resultingsilicon regions116aand116bdoped with the dopants can be later etched away essentially without affecting the other regions of thesilicon layer110c.
• Next, with reference toFIG. 1E, in one embodiment,nitride spacers170aand170bcan be formed on sidewalls of thegate stack130′,140′ (that now includes a portion of theoxide layer160 that covers thegate stack130′,140′). In one embodiment, thenitride spacers170aand170bcan be formed by blanket-depositing a nitride layer (not shown) on top of thestructure100 and then etching back.
• Next, in one embodiment, the method proceeds with an implantation step (represented byarrow117a′) of implanting germanium in thesilicon layer110cat an angle such that the resultingdoped region117ais deeper than thedoped region116aand extends under thenitride spacer170a. Then, in one embodiment, the method proceeds with an implantation step (represented by arrow117b′) of implanting germanium in thesilicon layer110cat an angle such that the resulting doped region117bis deeper than thedoped region116band extends under thenitride spacer170b. Thearrows117a′ and117b′ also indicate the respective directions of germanium bombardments.
• Next, in one embodiment, the method proceeds with an implantation step (represented by arrow118) of implanting germanium vertically in thesilicon layer110csuch that the resultingdoped regions118aand118bare deeper than thedoped regions117aand117b, respectively. Thearrow118 also indicates the direction of germanium bombardment. Starting fromFIG. 1F, thedoped regions116a,117a, and118aare collectively referred to as thedoped region119a. Similarly, the dopedregions116b,117b, and118bare collectively referred to as the dopedregion119b.
• Next, with reference toFIG. 1F, in one embodiment,oxide spacers180aand180bare formed on sidewalls of thenitride spacers170aand170b, respectively. In one embodiment, theoxide spacers180aand180bcan be formed by blanket-depositing an oxide layer (not shown) on top of thestructure100 and then etching back. As a result, a top region of theoxide layer160 is etched away, and thenitride spacers160aand160bare exposed to the atmosphere. Also as a result, the dopedregions119aand119bare exposed to the atmosphere. Theoxide layer160 is reduced to theoxide regions160aand160b. Thegate dielectric layer120 is reduced togate dielectric region120′.
• Next, with reference toFIG. 1G, in one embodiment, the method proceeds with an etching step of anisotropically etching away (illustratively, using RIE) silicon regions exposed to the atmosphere while leaving essentially intact other regions comprising other materials such as oxide and nitride. As a result,regions119aand119bof thesilicon layer110care removed.
• Next, in one embodiment, the nitrogen-dopedregions114aand114bcan be removed by a wet-etching process which essentially affects only nitrogen-doped oxide material and essentially does not affect other materials such as nitride, silicon, and undoped oxide.
• Next, with reference toFIG. 1H, in one embodiment, silicon is epitaxially grown from thesilicon layer110c(including the dopedregions119aand119b) totop surfaces192aand192b.
• Next, in one embodiment, the resultingsilicon layer110cis anisotropically etched back (illustratively, using RIE) totop surfaces194aand194b, respectively. In one embodiment, thetop surfaces194aand194bof the resultingsilicon layer110cafter etching back are below the bottom surfaces195aand195b(FIG. 1G) of the germanium-dopedregions119aand119b, respectively.
• Next, in one embodiment, an anneal process can be performed to diffuse germanium in the germanium-dopedregions119aand119binto thesilicon layer110c.
• Next, with reference toFIG. 1I, in one embodiment, the germanium-dopedregions119aand119b(FIG. 1H) of thesilicon layer110ccan be removed (illustratively, by wet etching) while leaving essentially intact other regions of thesilicon layer110cthat are not doped with germanium.
• Next, in one embodiment, an S/D implantation step can be performed to form S/D regions210aand210bin thesilicon layer110c. In one embodiment, an S/D anneal step can be performed after the S/D implantation step.
• Next, with reference toFIG. 1J, in one embodiment, the method proceeds with a step of anisotropically etching (illustratively, using RIE) the exposednitride regions150a,150b,170a, and170b(FIG. 1I). As a result, thenitride spacers170aand170bare removed. Thenitride regions150aand150bare thin and protected by surroundingoxide regions160a,160b, and140′ (FIG. 1I). As a result, the etch rate for thenitride regions150aand150bis much slower than that for thenitride spacers170aand170b. Therefore, when thenitride spacers170aand170bare completely removed, thenitride regions150aand150bcan be almost intact.
• Next, in one embodiment, the method proceeds with a step of anisotropically etching (illustratively, using RIE) the exposedoxide regions160a,160b, and140′ (FIG. 1I). As a result, the hard maskdielectric region140′ is removed, while theoxide regions160aand160bare reduced to theoxide spacers160a′ and160b′, respectively.
• Next, in one embodiment, a halo implantation step (represented by anarrow220a′) can be performed to form ahalo region220a. Next, in one embodiment, another halo implantation step (represented by anarrow220b′) can be performed to form ahalo region220b. Thearrows220a′ and220b′ also indicate the respective directions of halo ion bombardments.
• Next, in one embodiment, an extension implantation step (represented by arrows230) can be performed to formextension regions230aand230b. Thearrow230 also indicates the direction of extension ion bombardments.
• Next, in one embodiment, a halo and extension anneal step can be performed to anneal the resultinghalo regions220aand220band the resultingextension regions230aand230b.
• Next, with reference toFIG. 1K, in one embodiment,oxide spacers240aand240bare formed on sidewalls of theoxide spacers160a′ and160b′, respectively. In one embodiment, theoxide spacers240aand240bcan be formed by blanket-depositing an oxide layer (not shown) on top of thestructure100 and then etching back. Now, thegate region130′ and thegate dielectric region120′ can be collectively referred to as thegate stack120′,130′ of thestructure100.
• In summary, the method for forming lowered S/D transistor100 starts out with aplanar silicon layer110c(FIG. 1A). Then, thesilicon regions119aand119b(FIG. 1H) are doped with germanium so that they can be removed later (FIG. 1I) without affecting other silicon regions of thesilicon layer110c. As a result, the transistor100 (FIG. 1K) has lowered S/D regions210aand210b(i.e.,top surfaces212aand212bof the S/D regions210aand210b, respectively, are lower than atop surface242 of the channel region240). Considering a path from thegate region130′ to the S/D region210athrough thenitride spacer150a, theoxide spacers160a′ and240a, because of the lowered S/D region210a, the path is extended when it goes through theoxide spacer240a. As a result, the out-fringing capacitance between thegate region130′ to the S/D region210ais reduced. For a similar reason, the out-fringing capacitance between thegate region130′ and the S/D region210bis also reduced.
• To form the separatingdielectric region114c(FIG. 1C), theoxide regions114aand114bof theunderlying dielectric layer110bare doped with nitrogen so that theoxide regions114aand114bcan be later removed (FIG. 1G) and replaced by epi-silicon (epi=epitaxially grown) as shown inFIG. 1H. As a result, the separatingdielectric region114cis disposed between the S/D regions210aand210b(FIG. 1K). Because of the separatingdielectric region114c, the channel region240 (immediately beneath thegate dielectric region120′) is thinner. As a result, short channel effects are improved.
• While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.

Claims (20)

1. A semiconductor structure, comprising:

(a) a semiconductor layer including a channel region and first and second source/drain regions, wherein the channel region is disposed between the first and second source/drain regions, and wherein top surfaces of the first and second source/drain regions are below a top surface of the channel region;

(b) a gate dielectric region on the channel region; and

(c) a gate region on the gate dielectric region, wherein the gate region is electrically isolated from the channel region by the gate dielectric region.

2. The structure ofclaim 1, further comprising an underlying dielectric layer beneath and in direct physical contact with the semiconductor layer, wherein the underlying dielectric layer is directly beneath the channel region and the first and second source/drain regions.

3. The structure ofclaim 2, wherein the underlying dielectric layer comprises a separating dielectric region disposed between the first and second source/drain regions.

4. The structure ofclaim 3, wherein the separating dielectric region is directly beneath the channel region.

5. A method for fabricating a semiconductor structure, the method comprising the steps of:

(a) providing a semiconductor layer and a gate stack on the semiconductor layer,

wherein the semiconductor layer comprises (i) a channel region directly beneath the gate stack and (ii) first and second semiconductor regions essentially not covered by the gate stack, and

wherein the channel region is disposed between the first and second semiconductor regions;

(b) removing the first and second semiconductor regions; and

(c) doping regions directly beneath the removed first and second semiconductor regions so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.

6. The method ofclaim 5, wherein the gate stack comprises (i) a gate dielectric region on the semiconductor layer and (ii) a gate region on the gate dielectric region, wherein the gate region is electrically isolated from the channel region by the gate dielectric region.

7. The method ofclaim 5, wherein the step of removing the first and second semiconductor regions comprises the steps of:

doping the first and second semiconductor regions of the semiconductor layer with first dopants; and

etching away the first and second semiconductor regions but leaving essentially intact the gate stack and regions of the semiconductor layer which are not doped with the first dopants.

8. The method ofclaim 7, wherein the step of doping the first and second semiconductor regions with the first dopants is performed such that each region of the first and second semiconductor regions of the semiconductor layer has a thickness in a first direction perpendicular to a top surface of the channel region that increases when moving in a second direction away from the gate stack, and wherein the second direction is parallel to the top surface of the channel region.

9. The method ofclaim 8, wherein the step of doping the first and second semiconductor regions with the first dopants further comprises the step of forming spacers on sidewalls of the gate stack.

10. The method ofclaim 5, wherein the semiconductor layer comprises silicon, and wherein the first dopants in the first and second semiconductor regions comprise germanium.

11. The method ofclaim 5, further comprising the steps of:

(α) providing an underlying dielectric layer wherein the semiconductor layer is on the underlying dielectric layer;

(β) implanting second dopants in a top layer of the underlying dielectric layer except in a separating dielectric region of the top layer directly beneath the gate stack;

(γ) etching away the top layer of the underlying dielectric layer except the separating dielectric region; and

(δ) epitaxially growing a semiconductor material to fill the removed top layer of the underlying dielectric layer before the step (b) is performed.

12. The method ofclaim 11,

wherein step (β) comprises the step of using the gate stack as a mask to implant the second dopants in the top layer of the underlying dielectric layer except in the separating dielectric region, and

wherein step (γ) is performed such that regions of the underlying dielectric layer which are not doped with the second dopants are essentially intact.

13. The method ofclaim 12, wherein the second dopants comprise nitrogen, and wherein the underlying dielectric layer comprises silicon dioxide.

14. The method ofclaim 11, wherein the step (δ) is performed until a top surface of epitaxially grown semiconductor regions is at a level lower than a bottom surface of the first and second semiconductor regions.

15. A method for fabricating a semiconductor structure, the method comprising the steps of:

(a) providing (i) an underlying dielectric layer, (ii) a semiconductor layer on the underlying dielectric layer, and (iii) a gate stack on the semiconductor layer;

(b) implanting first dopants in a top layer of the underlying dielectric layer except in a separating dielectric region of the top layer directly beneath the gate stack;

(c) removing the top layer of the underlying dielectric layer except the separating dielectric region;

(d) epitaxially growing semiconductor regions to fill the removed top layer of the underlying dielectric layer; and

(e) implanting second dopants in semiconductor regions of the semiconductor layer and the epitaxially grown semiconductor regions on opposing sides of the gate stack so as to form first and second source/drain regions such that the separating dielectric region is disposed between the first and second source/drain regions.

16. The method ofclaim 15, wherein step (b) comprises the step of using the gate stack as a mask to implant the first dopants in the top layer of the underlying dielectric layer except in the separating dielectric region.

17. The method ofclaim 15, wherein step (c) comprises a wet-etching process that etches away regions of the underlying dielectric layer doped with the first dopants but leaves essentially intact regions of the underlying dielectric layer not doped with the first dopants.

18. The method ofclaim 17, wherein step (c) further comprises the step of, before the wet-etching process is performed, removing regions of the semiconductor layer so as to expose regions of the underlying dielectric layer that are doped with the first dopants.

19. The method ofclaim 18, wherein the step of removing the regions of the semiconductor layer so as to expose the regions of the underlying dielectric layer that are doped with the first dopants comprises the steps of:

forming gate spacers on side walls of the gate stack; and

using the gate stack and the gate spacers as a mask to RIE (reactive ion etching) away the regions of the semiconductor layer so as to expose the regions of the underlying dielectric layer that are doped with the first dopants.

20. The method ofclaim 15, wherein the first dopants comprise nitrogen, and wherein the underlying dielectric layer comprises silicon dioxide.

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