US20060097345A1

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Publication number: US20060097345A1
Application number: US11/292,653
Authority: US
Inventors: Kenneth Marr
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2000-08-31
Filing date: 2005-12-02
Publication date: 2006-05-11
Also published as: US20040065941A1; US6630724B1; US7030458B2

Abstract

A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode. The common bus line may be coupled to a reference voltage through a common bus line driver circuit in the active mode to pass current to or from the read circuit. The common bus line driver circuit has a control transistor and a high-voltage transistor with a diode coupled to its gate to bear the elevated voltage on the common bus line during the programming mode. The read circuit may have a latch circuit to latch a state of the antifuse in a sleep mode. A floating well driver logic circuit raises the voltage potential of wells and gate terminals of p-channel transistors in the read circuit during the programming mode to reduce current flow from the common bus line.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 10/680,481 filed on Oct. 6, 2003, which is a divisional of U.S. application Ser. No. 09/652,429 filed on Aug. 31, 2000, now U.S. Pat. No. 6,630,724, which applications are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits, and more particularly, to antifuse circuits and methods for operating them.

BACKGROUND

Integrated circuits are interconnected networks of electrical components fabricated on a common foundation called a substrate. The electrical components are typically fabricated on a wafer of semiconductor material that serves as a substrate. Various fabrication techniques, such as layering, doping, masking, and etching, are used to build millions of resistors, transistors, and other electrical components on the wafer. The components are then wired together, or interconnected, to define a specific electrical circuit, such as a processor or a memory device.

Fusible elements are employed in integrated circuits to permit changes in the configuration of the integrated circuits after fabrication. For example, fusible elements may be used to replace defective circuits with redundant circuits. Memory devices are typically fabricated with redundant memory cells. The redundant memory cells may be enabled with fusible elements after fabrication to replace defective memory cells found during a test of fabricated memory devices. Fusible elements are also used to customize the configuration of a generic integrated circuit after it is fabricated, or to identify an integrated circuit.

One type of fusible element is a polysilicon fuse. The polysilicon fuse comprises a polysilicon conductor fabricated to conduct electrical current on an integrated circuit. A portion of the polysilicon fuse may be evaporated or opened by a laser beam to create an open circuit between terminals of the polysilicon fuse. The laser beam may be used to open selected polysilicon fuses in an integrated circuit to change its configuration. The use of polysilicon fuses is attended by several disadvantages. Polysilicon fuses must be spaced apart from each other in an integrated circuit such that when one of them is being opened by a laser beam the other polysilicon fuses are not damaged. A bank of polysilicon fuses therefore occupies a substantial area of an integrated circuit. In addition, polysilicon fuses cannot be opened once an integrated circuit is placed in an integrated circuit package, or is encapsulated in any manner.

Another type of fusible element is an antifuse. An antifuse comprises two conductive terminals separated by an insulator or a dielectric, and is fabricated as an open circuit. The antifuse is programmed by applying a high voltage across its terminals to rupture the insulator and form an electrical path between the terminals.

Antifuses have several advantages that are not available with fuses. A bank of antifuses takes up much less area of an integrated circuit because they are programmed by a voltage difference that can be supplied on wires connected to the terminals of each of the antifuses. The antifuses may be placed close together in the bank, and adjacent antifuses are not at risk when one is being programmed. Antifuses may also be programmed after an integrated circuit is placed in an integrated circuit package, or encapsulated, by applying appropriate signals to pins of the package. This is a significant advantage for several reasons. First, an integrated circuit may be tested after it is in a package, and may then be repaired by replacing defective circuits with redundant circuits by programming selected antifuses. A generic integrated circuit may be tested and placed in a package before it is configured to meet the specifications of a customer. This reduces the delay between a customer order and shipment. The use of antifuses to customize generic integrated circuits also improves the production yield for integrated circuits because the same generic integrated circuit may be produced to meet the needs of a wide variety of customers.

Despite their advantages, the use of antifuses in integrated circuits is limited by a lack of adequate circuitry to support the programming and reading of the antifuses. There exists a need for improved circuits and methods for programming and reading antifuses in integrated circuits.

SUMMARY OF THE INVENTION

The above mentioned and other deficiencies are addressed in the following detailed description. According to embodiments of the present invention several support circuits have elements to program and read antifuses. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode. The common bus line may be coupled to a reference voltage through a common bus line driver circuit in the active mode to pass current to or from the read circuit. The common bus line driver circuit has a control transistor and a high-voltage transistor with a diode coupled to its gate to bear the elevated voltage on the common bus line during the programming mode. The read circuit may have a latch circuit to latch a state of the antifuse in a sleep mode. A floating well driver logic circuit raises the voltage potential of wells and gate terminals of p-channel transistors in the read circuit during the programming mode to reduce current flow from the common bus line.

The embodiments of the present invention support the programming and reading of antifuses in an integrated circuit, and facilitate all the advantages associated with the use of antifuses in integrated circuits. Other advantages of the present invention will be apparent to one skilled in the art upon an examination of the detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an antifuse according to an embodiment of the present invention.

FIG. 1A is a cross-sectional view of an antifuse according to an embodiment of the present invention.

FIG. 1B is a cross-sectional view of an antifuse according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of an antifuse according to an embodiment of the present invention.

FIG. 2A is a cross-sectional view of an antifuse according to an embodiment of the present invention.

FIG. 3 is an electrical schematic diagram of a portion of an integrated circuit according to an embodiment of the present invention.

FIG. 4 is an electrical schematic diagram of an antifuse bank according to an embodiment of the present invention.

FIG. 5 is a block diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.

FIG. 8A is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention.

FIG. 10 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view of an n-channel transistor according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view of a diode according to an embodiment of the present invention.

FIG. 13 is a cross-sectional view of a diode according to an embodiment of the present invention.

FIG. 14 is a cross-sectional view of a diode according to an embodiment of the present invention.

FIG. 15 is a cross-sectional view of a diode according to an embodiment of the present invention.

FIG. 16 is a cross-sectional view of a diode according to an embodiment of the present invention.

FIG. 17 is a cross-sectional view of a p-channel transistor according to an embodiment of the present invention.

FIG. 18 is an electrical schematic diagram of an integrated circuit with a common bus line driver circuit according to an embodiment of the present invention.

FIG. 19 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 20 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 21 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 22 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 23 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 24 is an electrical schematic diagram of an integrated circuit with a common bus line driver circuit according to an embodiment of the present invention.

FIG. 25 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 26 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 27 is an electrical schematic diagram of support circuits for antifuses according to an embodiment of the present invention.

FIG. 28 is a block diagram of a static random access memory device according to an embodiment of the present invention.

FIG. 29 is an electrical schematic diagram of an integrated circuit package according to an embodiment of the present invention.

FIG. 30 is a block diagram of an information-handling system according to an embodiment of the present invention.

DETAILED DESCRIPTION

In the following detailed description of exemplary embodiments of the present invention, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific exemplary embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical, electrical and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.

The terms wafer and substrate may be used in the following description and include any structure having an exposed surface with which to form an integrated circuit (IC) according to embodiments of the present invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during fabrication, and may include other layers that have been fabricated thereupon. The term substrate includes doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor, or semiconductor layers supported by an insulator, as well as other semiconductor structures well known to one skilled in the art. The term insulator is defined to include any material that is less electrically conductive than materials generally referred to as conductors by those skilled in the art.

The term “horizontal” as used in this application is defined as a plane substantially parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction substantially perpendicular to the horizonal as defined above. Prepositions, such as “on,” “upper,” “side” (as in “sidewall”), “higher,” “lower,” “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.

Antifuses and transistors described herein according to embodiments of the present invention may have wells that may be formed in other wells or tanks rather than substrates. Such wells or tanks may be situated with other wells or tanks, or within other wells or tanks, in a larger substrate. The wells or tanks may also be situated in a silicon-on-insulator (SOI) device.

The term “source/drain” refers generally to the terminals or diffusion regions of a field effect transistor. A terminal or a diffusion region may be more specifically described as a “source” or a “drain” on the basis of a voltage applied to it when the field effect transistor is in operation.

P-type conductivity is conductivity associated with holes in a semiconductor material, and n-type conductivity is conductivity associated with electrons in a semiconductor material. Throughout this specification the designation “n+” refers to semiconductor material that is heavily doped n-type semiconductor material, e.g., monocrystalline silicon or polycrystalline silicon. Similarly, the designation “p+” refers to semiconductor material that is heavily doped p-type semiconductor material. The designations “n−” and “p−” refer to lightly doped n and p-type semiconductor materials, respectively.

In this description a transistor is described as being activated or switched on when it is rendered conductive by a control gate voltage that is separated from its source voltage by at least its threshold voltage. The transistor is described as being in an inactive state or switched off when the control gate voltage is separated from its source voltage by less than the threshold voltage and the transistor is rendered non-conductive. A digital signal of 1 may be called a high signal and a digital signal of 0 may be called a low signal. Embodiments of the present invention described herein may be coupled to receive a power supply voltage Vcc which is within approximately 1 to 5 volts. By way of example in this description, and not by way of limitation, Vcc is approximately 3 volts. Two supply voltages, VccX and VccR, may be used in an integrated circuit to improve the noise margin of the embodiments of the invention described herein. VccX is an external supply voltage coupled to the integrated circuit. VccR is a regulated supply voltage generated inside the integrated circuit, and is often less than VccX. By way of example in this description, and not by way of limitation, VccX is approximately 3 volts, and VccR is between 2 volts and 3 volts. Embodiments of the present invention described herein may also be coupled to receive a ground voltage reference Vss, and a bulk node voltage Vbb. The voltage Vbb may be approximately equal to Vss, or may be slightly less than Vss such as approximately minus 1 tominus 2 volts. Vbb is often coupled to p-type wells and p-type substrates in integrated circuits described herein. Vcc, VccX, VccR, Vss, and Vbb are received directly or are generated by circuits that are not shown for purposes of brevity, but are known to those skilled in the art.

A cross-sectional view of anantifuse100 according to an embodiment of the present invention is shown inFIG. 1. An n-type well110 is formed in a p-type substrate112, and an n+-typesource diffusion region114 and an n+-typedrain diffusion region116 are formed in thewell110. Each of the n+-

type diffusion regions

114,116 provide an ohmic contact for thewell110. A p-type gate electrode120 is formed over a layer of gate dielectric122 which is formed over the well110 between thesource diffusion region114 and thedrain diffusion region116. One ormore spacers123 are formed on the sides of thegate dielectric122 and thegate electrode120. Thegate electrode120 is connected to afirst terminal124 of theantifuse100, and asecond terminal126 is connected to each of the n+-

type diffusion regions

114,116. In alternate embodiments of the present invention thegate electrode120 comprises polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate dielectric122 may be oxide, oxynitride, or nitrided oxide. A p+-type diffusion region130 is formed in thesubstrate112 to provide an ohmic contact coupling thesubstrate112 to Vbb.

Two separate circuits in an integrated circuit may be connected respectively to the first and

second terminals

124,126 of theantifuse100. Theantifuse100 is an open circuit between the terminals until it is programmed in the following manner. The p-type substrate112 is coupled to Vbb and thefirst terminal124 attached to the p-type gate electrode120 is coupled to a low voltage. Thesecond terminal126 is coupled to bring the well110 to a positive elevated voltage, such as approximately 15 volts. A voltage drop between the well110 and the p-type gate electrode120 is enough to rupture thegate dielectric122. When programmed theantifuse100 has a conductive connection between the first and

second terminals

124,126 which may be biased appropriately such that the p-n junction between the p-type gate electrode120 and the well110 allows current to flow. The programmed antifuse100 is an impedance element similar to a diode between the circuits.

A cross-sectional view of anantifuse140 according to an embodiment of the present invention is shown inFIG. 1A. Theantifuse140 is similar to theantifuse100 shown inFIG. 1, and similar elements have been given the same reference numerals and will not be further described for purposes of brevity. Theantifuse140 is one-sided because it has only a single n+-type diffusion region142. The n+-type diffusion region142 takes the place of the n+-

type diffusion regions

114,116 in theantifuse100, and is connected to thesecond terminal126. Theantifuse140 is programmed and functions in a manner similar to theantifuse100.

A cross-sectional view of anantifuse150 according to an embodiment of the present invention is shown inFIG. 1B. Theantifuse150 is similar to theantifuse100 shown inFIG. 1, and similar elements have been given the same reference numerals and will not be further described for purposes of brevity. Theantifuse150 is offset because it has an n+-type diffusion region152 that is offset from thegate electrode120 and thespacers123. The n+-type diffusion region152 takes the place of the n+-

type diffusion regions

114,116 in theantifuse100, and is connected to thesecond terminal126. Theantifuse150 is programmed and functions in a manner similar to theantifuse100.

A cross-sectional view of anantifuse200 according to another embodiment of the present invention is shown inFIG. 2. An n-type well210 is formed in a p-type substrate212, and an n+-typesource diffusion region214 and an n+-typedrain diffusion region216 are formed in thewell210. Each of the n+-

type diffusion regions

214,216 provide an ohmic contact for thewell210. An n-type gate electrode220 is formed over a layer of gate dielectric222 which is formed over the well210 between thesource diffusion region214 and thedrain diffusion region216. One ormore spacers223 are formed on the sides of thegate dielectric222 and thegate electrode220. Thegate electrode220 is connected to afirst terminal224 of theantifuse200, and asecond terminal226 is connected to each of the n+-

type diffusion regions

214,216. In alternate embodiments of the present invention thegate electrode220 comprises polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate dielectric222 may be oxide, oxynitride, or nitrided oxide. A p+-type diffusion region230 is formed in thesubstrate212 to provide an ohmic contact coupling thesubstrate212 to Vbb.

Theantifuse200 is an open circuit between the first and

second terminals

224,226 until it is programmed in a manner similar to the programming of theantifuse100 described above. When programmed theantifuse200 is an impedance element similar to a resistor between the first and

second terminals

224,226.

A cross-sectional view of anantifuse250 according to an embodiment of the present invention is shown inFIG. 2A. Theantifuse250 is similar to theantifuse200 shown inFIG. 2, and similar elements have been given the same reference numerals and will not be further described for purposes of brevity. Theantifuse250 has ametal gate electrode260 instead of thegate electrode220 shown inFIG. 2. Theantifuse250 is programmed and functions in a manner similar to theantifuse200. Once theantifuse250 is programmed themetal gate electrode260 forms a schottky barrier with the n-type well210. A conductive connection between the first and

second terminals

224,226 in the programmed antifuse250 may be biased appropriately to allow current to flow through the schottky barrier.

In alternate embodiments of the present invention the

antifuses

100,200 may have only one of the n+-

type diffusion regions

114,116,214,216 similar to theantifuse140. The n+-

type diffusion regions

114,116,214,216 may be self-aligned with the

respective spacers

123,223, or may be offset from and not self aligned with the

spacers

123,223 similar to the n+-type diffusion region152 in theantifuse150.

The

gate dielectrics

122 and222 may be fabricated to be thinner than gate dielectrics in conventional field effect transistors to reduce the voltage drop necessary to rupture them.

Antifuses

100,140,150,200, and250 with

thinner gate dielectrics

122 and222, respectively, would be programmable with a lower elevated voltage, and thus reduce the effects of the elevated voltage on neighboring circuits which will be described below.

The

antifuses

100,140,150,200, and250 may also be formed in a semiconductor layer formed over an insulator according to alternate embodiments of the present invention.

The

antifuses

100,140,150,200, and250 described above with reference toFIGS. 1, 1A,1B,2, and2A may be used for a variety of purposes in an integrated circuit. For example, the

antifuses

100,140,150,200, and250 may be programmed to provide a coupling to redundant circuits, to change a configuration of the integrated circuit, to tie a line to a voltage or to Vss, or to provide identification for the integrated circuit. An electrical schematic diagram of a portion of anintegrated circuit300 is shown inFIG. 3 according to an embodiment of the present invention. Theintegrated circuit300 may be a memory device, a processor, or any other type of integrated circuit device by way of example and not by way of limitation. Theintegrated circuit300 includes a number of

circuits

310,312,314,316,318, and320 coupled together by a number of

direct connections

330,332, and334 and a number of

antifuses

340,342,344, and346. The antifuses340-346 are represented by triangles inscribed with the letter A. One or more of the antifuses340-346 has the structure and the operational method of one of the antifuses shown inFIGS. 1, 1A,1B,2, and2A described above. One or more of the antifuses340-346 is programmed according to the methods discussed above to provide electrically conductive couplings between two or more of the circuits310-320 to change the configuration of theintegrated circuit300. The circuits310-320 may be separate components or devices as well as circuits, and theintegrated circuit300 could include more or less circuits, devices, components, and antifuses according to alternate embodiments of the present invention.

The

antifuses

100,140,150,200, and250 described above with reference toFIGS. 1, 1A,1B,2, and2A may be arranged in banks of antifuses in an integrated circuit, and anantifuse bank400 is shown inFIG. 4 according to an embodiment of the present invention. Thebank400 includes four

antifuses

410,412,414, and416, one or more having the structure and the operational method of one of the

antifuses

100,140,150,200, or250 described above with respect toFIGS. 1, 1A,1B,2, and2A. Thebank400 may have more or less than four antifuses according to alternate embodiments of the present invention. The antifuses410-416 are coupled in parallel to aprogramming logic circuit420, and each of the antifuses410-416 may be programmed in a similar manner. For example, theantifuse410 has a first terminal coupled to theprogramming logic circuit420 and a second terminal coupled to anexternal pin430 and abias circuit440 through acommon bus line442. The first and second terminals correspond to the terminals of one of the

antifuses

100,140,150,200, and250. Theexternal pin430 is external to an integrated circuit including thebank400, and will be more fully described hereinbelow. Thebias circuit440 may be a transistor, a group of transistors coupled together, or a high breakdown voltage resistor. The second terminal is also coupled to an electro-static discharge (ESD)

device

450,452 through thecommon bus line442.

Thebank400 is operated on one of three modes: a programming mode, an active mode, and a sleep mode. The antifuses410-416 are programmed in the programming mode, and the active and sleep modes will be described hereinbelow. In the programming mode, an elevated voltage is applied to theexternal pin430 and thecommon bus line442 that exceeds Vcc of the integrated circuit by a substantial amount. The elevated voltage provides the potential necessary to rupture the gate dielectrics of the antifuses410-416 selected to be programmed. The elevated voltage is removed from theexternal pin430 during the active and sleep modes and the integrated circuit operates from Vcc. In the active and sleep modes theexternal pin430 may be allowed to float, or it may be coupled to a reference voltage such as Vss. The use of theexternal pin430 to couple the elevated voltage to the antifuses410-416 in the programming mode substantially protects other portions of the integrated circuit from damage that may be caused by the elevated voltage.

One of the antifuses410-416 may be similar to theantifuse100 shown inFIG. 1, and a programming of theantifuse100 in thebank400 will now be described. In the programming mode the p-type substrate112 is coupled to Vbb and an elevated voltage, such as approximately 15 volts, is coupled to the well110 from theexternal pin430 through thecommon bus line442, thesecond terminal126, and the

diffusion regions

114,116. Theantifuse100 is selected to be programmed by theprogramming logic circuit420 which couples a sufficiently low potential to the p-type gate electrode120 to rupture thegate dielectric122 in theantifuse100. Theprogramming logic circuit420 may prevent others of the antifuses410-416 from being programmed by raising a potential of the p-type gate electrodes120 to prevent thegate dielectrics122 from being ruptured. The operation of theprogramming logic circuit420 will be more fully described hereinbelow according to embodiments of the present invention.

One of the antifuses410-416 may be similar to one of the

antifuses

140,150,200, or250 shown inFIGS. 1A, 1B,2, and2A and a programming of one of the

antifuses

140,150, or200 in thebank400 will be similar to the programming of theantifuse100 described above. Those skilled in the art having the benefit of this description will recognize that the voltage levels recited herein may be changed depending on characteristics of the antifuses410-416 in thebank400.

Additional support circuits

500 in theprogramming logic circuit420 are shown in a block diagram inFIG. 5 according to an embodiment of the present invention. Thecircuits500 are for programming and reading the antifuses410-416 in thebank400, and are shown for programming and reading asingle antifuse510 for purposes of brevity. Additional, similar circuits may be used to program and read a larger number of antifuses. Theantifuse510 has the structure and operational method of one of the

antifuses

100,140,150,200, or250 described above with reference toFIGS. 1, 1A,1B,2, and2A. Theantifuse510 has a first terminal coupled to anexternal pin520 through acommon bus line530, and a second terminal coupled to aprogram driver circuit542. Theexternal pin520 corresponds to theexternal pin430 shown inFIG. 4. Theprogram driver circuit542 is used to select theantifuse510 to be programmed. Aread circuit544 is coupled to theantifuse510 through theprogram driver circuit542 to read a state of theantifuse510 during the active and sleep modes, and a floating welldriver logic circuit550 is coupled to theread circuit544. Theantifuse510 is one of several antifuses in a bank (not shown), and the floating welldriver logic circuit550 is also coupled to a read circuit for each of the other antifuses in the bank. In the programming mode an elevated voltage is applied to thecommon bus line530 through theexternal pin520 to program theantifuse510. A common busline driver circuit560 is coupled to thecommon bus line530 to drive thecommon bus line530 to a reference voltage such as Vss when theantifuse510 is being read by theread circuit544. In other embodiments of the present invention the floating welldriver logic circuit550 or the common busline driver circuit560 may not be needed or included in thecircuits500.

The common busline driver circuit560 and theprogram driver circuit542 each include a high-voltage transistor (HVT). One example of such a HVT is an n-well drain transistor600, a cross-sectional view of which is shown inFIG. 6 according to an embodiment of the present invention. An n-type well610 is formed in a p-type substrate612, and an n+-typedrain diffusion region616 is formed in thewell610. An n+-typesource diffusion region618 is formed in thesubstrate612. Agate electrode620 is formed over a layer of gate dielectric622 which is formed over thesubstrate612 between the source and drain

diffusion regions

618 and616. Thegate electrode620 is connected to a gate terminal624. Likewise, adrain terminal626 is connected to the n+-typedrain diffusion region616 and asource terminal628 is connected to the n+-typesource diffusion region618. In alternate embodiments of the present invention thegate electrode620 comprises metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate dielectric622 may be oxide, oxynitride, or nitrided oxide. A p+-type diffusion region640 is formed in thesubstrate612 to provide an ohmic contact coupling thesubstrate612 to Vbb.

The n-well drain transistor600 has a high drain breakdown voltage. In operation thesubstrate612 is coupled to Vbb and thedrain terminal626 is coupled to a line with a high positive voltage, such as thecommon bus line530 shown inFIG. 5 during the programming mode. The n-well drain transistor600 will break down and allow current to flow between thedrain terminal626 and thesubstrate612 when a critical electric field intensity (E) is reached across a boundary between the n-type well610 and the p-type substrate612. E may be approximated as the voltage drop across the boundary divided by a width of a depletion region at the boundary of the n-type well610 and the p-type substrate612. Dopant concentrations in the n-type well610 and the p-type substrate612 are relatively low such that the width of the depletion region between the two is relatively large. The boundary will not break down even under a very large voltage drop across the boundary because the E is less than the critical E. As a result, the n-well drain transistor600 will not break down even if the voltage on thedrain terminal626 is relatively high. In contrast, an ordinary n-channel transistor does not have the n-type well610, and there is a boundary between a p-type substrate and an n+-type drain diffusion region with a very high dopant concentration. A depletion region at this boundary is not very wide, and as a consequence it will break down under a smaller voltage.

Other examples of a HVT will now be described. A cross-sectional view of an n-well drain transistor700 is shown inFIG. 7 according to another embodiment of the present invention. An n-type well710 is formed in a drain side of a p-type substrate712, and a p-type halo implant714 is formed in a source side of thesubstrate712. An n-type lightly doped drain (LDD)716 is implanted inside thehalo implant714. Agate720 is formed over a layer of gate dielectric722 which is formed over thesubstrate712 between the n-type well710 and thehalo implant714. Anelectrode724 is formed over thegate720. In alternate embodiments of the present invention gate may comprise polysilicon and theelectrode724 may comprise a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate dielectric722 may be oxide, oxynitride, or nitrided oxide. Thegate720 and theelectrode724 may also comprise metal. One ormore spacers726 are then formed on the sides of thegate dielectric722, thegate720, and theelectrode724. An n+-typesource diffusion region730 is implanted inside theLDD716 and thehalo implant714. Also, an n+-typedrain diffusion region732 is implanted in the n-type well710. Thedrain diffusion region732 is not surrounded by LDD or halo implants which are blocked from the drain side of thesubstrate712. Asource terminal740 is connected to thesource diffusion region730, agate terminal742 is connected to theelectrode724, and adrain terminal744 is connected to thedrain diffusion region732. A p+-type diffusion region760 is formed in thesubstrate712 to provide an ohmic contact coupling thesubstrate712 to Vbb. The n-well drain transistor700 has a high drain breakdown voltage for reasons analogous to those recited in the description of the n-well drain transistor600 shown inFIG. 6.

A cross-sectional view of an n-channel transistor800 is shown inFIG. 8 which is a HVT according to an embodiment of the present invention. A p-type halo implant810 is formed in a source side of a p-type substrate812. An n-type lightly doped drain (LDD)816 is implanted inside thehalo implant810. Agate820 is formed over a layer of gate dielectric822 which is formed over thesubstrate812. Anelectrode824 is formed over thegate820. In alternate embodiments of the present invention thegate820 comprises polysilicon and theelectrode824 may comprise a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate820 and theelectrode824 may comprise metal. Thegate dielectric822 may be oxide, oxynitride, or nitrided oxide. One ormore spacers826 are then formed on the sides of thegate dielectric822, thegate820, and theelectrode824. An n+-typesource diffusion region830 is implanted inside theLDD816 and thehalo implant810. Also, an n+-typedrain diffusion region832 is implanted in thesubstrate812. Thedrain diffusion region832 is not surrounded by LDD or halo implants which are blocked from a drain side of thesubstrate812. Asource terminal840 is connected to thesource diffusion region830, agate terminal842 is connected to theelectrode824, and adrain terminal844 is connected to thedrain diffusion region832. Thedrain diffusion region832 and thesource diffusion region830 are self-aligned with thespacers826. A p+-type diffusion region860 is formed in thesubstrate812 to provide an ohmic contact coupling thesubstrate812 to Vbb. The n-channel transistor800 has a high drain breakdown voltage and may be used in embodiments of the present invention described above in place of the n-well drain transistor600 shown inFIG. 6.

A cross-sectional view of an n-channel transistor860 is shown inFIG. 8A which is a HVT according to an embodiment of the present invention. Thetransistor860 is similar to thetransistor800 shown inFIG. 8, and similar elements have been given the same reference numerals and will not be further described for purposes of brevity. In addition to the elements of thetransistor800, the LDD implant is not blocked, and an n-type LDD862 is implanted in a drain side of the p-type substrate812. An n+-typedrain diffusion region864 is implanted inside theLDD862 in place of thedrain diffusion region832 of thetransistor800. Thetransistor860 functions in a manner similar to thetransistor800.

The

transistors

600,700,800, and860 shown inFIGS. 6, 7,8, and8A may be fabricated according to process steps used to fabricate field-effect transistors in an integrated circuit, and do not require extra process steps. In another embodiment of the present invention, an added mask and implant could be applied to thedrain diffusion region832 to customize the high drain breakdown voltage of thetransistor800.

A cross-sectional view of an n-well drain transistor900 is shown inFIG. 9 which is a HVT according to another embodiment of the present invention. An n-type well910 is formed in a drain side of a p-type substrate912, and a p-type halo implant914 is formed in a source side of thesubstrate912 and blocked from the drain side. Two n-type lightly doped drains (LDD)916 and917 are implanted inside thehalo implant914 and the n-type well910. Agate920 is formed over a layer of gate dielectric922 which is formed over thesubstrate912 between the n-type well910 and thehalo implant914. Anelectrode924 is formed over thegate920. In alternate embodiments of the present invention thegate920 comprises polysilicon and theelectrode924 may comprise a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate dielectric922 may be oxide, oxynitride, or nitrided oxide. Thegate920 and theelectrode924 may comprise metal. One ormore spacers926 are then formed on the sides of thegate dielectric922, thegate920, and theelectrode924. An n+-typesource diffusion region930 is implanted inside theLDD916 and thehalo implant914. Also, an n+-typedrain diffusion region932 is implanted in theLDD917 and the n-type well910. Thedrain diffusion region932 in theLDD917 is not surrounded by a halo implant which was blocked. Asource terminal940 is connected to thesource diffusion region930, agate terminal942 is connected to theelectrode924, and adrain terminal944 is connected to thedrain diffusion region932. Thedrain diffusion region932 and thesource diffusion region930 are self-aligned with thespacers926. A p+-type diffusion region960 is formed in thesubstrate912 to provide an ohmic contact coupling thesubstrate912 to Vbb. The n-well drain transistor900 has a high drain breakdown voltage for reasons analogous to those recited in the description of the n-well drain transistor600 shown inFIG. 6.

Several of thecircuits500 shown inFIG. 5 are shown in greater detail inFIG. 10. An electrical schematic diagram ofseveral support circuits1000 for programming and reading antifuses is shown inFIG. 10 according to an embodiment of the present invention. Thecircuits1000 are located in theprogramming logic circuit420 shown inFIG. 4, and include aprogram driver circuit1010, aread circuit1011, and a floating welldriver logic circuit1012. Theprogram driver circuit1010 is coupled to agate electrode1014 of anantifuse1016, and a well1018 of theantifuse1016 is coupled through acommon bus line1020 to anexternal pin1022. Theantifuse1016 is similar in structure and operation to theantifuse100 shown inFIG. 1.

Theprogram driver circuit1010 includes aHVT1024 having adrain terminal1026, asource terminal1028, and agate terminal1030. TheHVT1024 is similar in structure and operating characteristics to the n-well drain transistor600 shown inFIG. 6. Thedrain terminal1026 is coupled to thegate electrode1014 of theantifuse1016. Thegate terminal1030 is coupled to acathode1033 of adiode1034, and ananode1038 of thediode1034 is coupled to Vcc. Thediode1034 is forward biased as long as Vcc exceeds a voltage at thegate terminal1030. Thegate terminal1030 is coupled to acathode1040 of adiode1042. Ananode1044 of thediode1042 is coupled to Vbb. The

diodes

1034 and1042 maintain thegate terminal1030 at a voltage slightly less than Vcc, or higher. Current will flow through theHVT1024 as long as the other elements of thecircuits1000 allow current to flow, as will be described hereinbelow.

Theprogram driver circuit1010 also includes a first n-channel transistor1045 and a second n-channel transistor1046 coupled in cascode between thesource terminal1028 and Vss. A gate terminal of thetransistor1045 is coupled to Vcc, and thetransistor1045 is switched on as long as Vcc exceeds a voltage at its source terminal by a threshold voltage V_Tof thetransistor1045. A gate terminal of thetransistor1046 is coupled to alogic circuit1048 which controls theprogram driver circuit1010 during the programming, active, and sleep modes. A body terminal of thetransistor1046 is coupled to Vbb.

Thetransistor1046 is switched off by thelogic circuit1048 in each of the programming, active, and sleep modes, and is switched on for a short period to program theantifuse1016 in the programming mode. In the active mode, current may flow from theread circuit1011 through theHVT1024 and theantifuse1016 to thecommon bus line1020. A more detailed description of the active mode is recited below. No substantial current passes through the

transistors

1045 and1046 in the active mode or in the sleep mode which will also be described below.

Thecommon bus line1020 is coupled to receive an elevated voltage in the programming mode, for example 15 volts, through theexternal pin1022. Before it is programmed the elevated voltage on thecommon bus line1020 is distributed across theantifuse1016, the

transistors

1024,1045, and1046, and the

diodes

1034 and1042 which are non-linear elements. The distribution of the elevated voltage is non-linear and may vary over time. Once theantifuse1016 is programmed it is an impedance element and the distribution of the elevated voltage changes. Thetransistor1046 is switched off and no current path exists through theread circuit1011 in the programming mode so no substantial current passes through theHVT1024. Voltages along theprogram driver circuit1010 rise as a result, and the elevated voltage is distributed across the

transistors

1024,1045, and1046 and the

diodes

1034 and1042 in a manner described hereinbelow.

Theantifuse1016 may be selected to be programmed by thelogic circuit1048 by switching on thetransistor1046 and conduct current from thecommon bus line1020 through to Vss. Thetransistor1046 is switched on for a short period of time to allow the elevated voltage on thecommon bus line1020 to rupture a gate dielectric in theantifuse1016, and is then switched off.

The two

transistors

1045 and1046 are coupled in cascode to substantially prevent the occurrence of a snap-back condition when thetransistor1046 is switched off. Snap-back occurs when there is current flowing between a source terminal and a drain terminal of a transistor that cannot be shut off by a voltage at a gate terminal of the transistor. Snap-back may start if the transistor is switched on by a high voltage at the gate terminal, a voltage at the drain terminal is very high, and a substantial current is passing through the transistor. If the voltage at the gate terminal is reduced to a low voltage the transistor may not switch off if the voltage at the drain terminal is too high and there is too much current conducting through the transistor. Snap-back may occur in thetransistor1046 as theantifuse1016 is programmed and thelogic circuit1048 attempts to switch off thetransistor1046 with a low voltage on its gate terminal. The elevated voltage on thecommon bus line1020 and the current passing through theantifuse1016 may be high enough to cause snap-back in thetransistor1046.

One way of reducing snap back is to lower the voltage on thecommon bus line1020 after an antifuse is programmed. This method substantially slows the programming of a sequence of antifuses because the voltage must be lowered after each antifuse is programmed. In theprogram driver circuit1010, snap-back is substantially prevented in thetransistor1046 by thetransistor1045 which is placed to reduce the voltage on the drain terminal of thetransistor1046. Thetransistor1045 reduces the voltage on the drain terminal of thetransistor1046 to approximately Vcc less a threshold voltage of thetransistor1045, which is enough to substantially prevent snap-back. The

transistors

1045 and1046 comprise a cascode configuration.

Thetransistor1045 is also employed to reduce current leakage through theantifuse1016. If theantifuse1016 is unprogrammed, any current leakage through it will degrade its gate dielectric. It is therefore advantageous to reduce sources of current leakage in theprogram driver circuit1010 as much as possible.

One source of current leakage in theprogram driver circuit1010 is thetransistor1046. Current may leak through thetransistor1046 due to drain induced barrier lowering (DIBL). Thetransistor1046 is an n-channel transistor and is switched on to conduct current between its drain and source terminals when the voltage at its gate terminal exceeds the voltage at its source terminal by a threshold voltage V_Tof thetransistor1046. The difference between the voltage at the gate terminal and the voltage at the source terminal is called V_GS. DIBL leakage current flows between the drain terminal and the source terminal at a subthreshold V_GS, when V_GSis less than V_Tof thetransistor1046. DIBL leakage current therefore occurs when thetransistor1046 is switched off, and this current can damage theantifuse1016 when it is unprogrammed. The subthreshold V_GSis lowered as the voltage at the drain terminal of thetransistor1046 increases, and the DIBL leakage current will therefore occur at lower and lower values of V_GS. If the voltage at the drain terminal is high enough, DIBL leakage current will occur when V_GSis zero. Thetransistor1045 reduces DIBL leakage current by reducing the voltage at the drain terminal of thetransistor1046, and therefore reduces leakage current through theantifuse1016.

Current may also leak through thetransistor1046 due to gate induced drain leakage (GIDL). Thetransistor1046 is similar to a conventional n-channel transistor and has n+-type source and drain regions separated by a channel region in a p-type substrate that is coupled to Vbb. A thin layer of oxide separates the channel region from a gate electrode. The source and drain regions and the gate electrode are connected to the corresponding terminals described above, the n+-type drain region being coupled to thetransistor1045. The n+-type drain region and the p-type substrate comprise a parasitic diode which is reverse biased with a positive voltage on the drain terminal of thetransistor1046. GIDL current leaks across the reverse biased parasitic diode, and increases with an increase of an electric field intensity (E) near the drain region which is increased due to the proximity of the gate electrode. GIDL current increases with a rising voltage on the drain terminal of thetransistor1046 which raises E near the drain region. Thetransistor1045 reduces GIDL current by reducing the voltage at the drain terminal of thetransistor1046, and therefore reduces leakage current through theantifuse1016.

Snap-back and the DIBL and GIDL leakage current described above may be substantially prevented without the use of thetransistor1045 according to alternate embodiments of the present invention. In an alternate embodiment of the present invention, the cascode configuration of the

transistors

1045 and1046 is replaced by thesingle transistor1046.

For example, DIBL leakage current may flow in thetransistor1046 even if the voltage at its drain terminal is not elevated due to process conditions in which thetransistor1046 is fabricated. A method that may be used to reduce DIBL leakage current is to adjust an implant for thetransistor1046, or to add a masked implant step to raise the threshold voltage of thetransistor1046. Another method is to lower Vbb, the voltage coupled to the body terminal of thetransistor1046, to raise its threshold voltage. These methods may be used if thetransistor1046 is employed alone or as part of the cascode configuration with thetransistor1045.

Theread circuit1011 includes elements used to read a state of theantifuse1016, and these elements will now be described. Theread circuit1011 includes a first p-channel transistor1050 and a second p-channel transistor1052. Thetransistor1052 is switched on by a bias voltage BIAS applied to its gate terminal, and its source terminal is coupled to Vcc. The voltage BIAS is generated by a current mirror (not shown) and is approximately equal to Vcc less an amount selected to control current through thetransistor1052. A drain terminal of thetransistor1052 is coupled to a source terminal of thetransistor1050, and the drain terminal of thetransistor1050 is coupled to thesource terminal1028 of theHVT1024. The gate terminal of thetransistor1050 is coupled to a signal TZZ1 which is low when theprogramming logic circuit420 is in the active mode to read theantifuse1016 as will be described hereinbelow. Thetransistor1050 is therefore switched on to read theantifuse1016. Aninverter1054 is coupled to thesource terminal1028 and generates an output signal OUTPUT at an output indicating the state of theantifuse1016.

When theantifuse1016 is read thecommon bus line1020 is coupled to Vss and the impedance of theantifuse1016 is compared with the impedance of thetransistor1052 that is switched on by the voltage BIAS. Thetransistor1052 may be replaced by a resistor or other load device in alternate embodiments of the present invention. Thetransistor1050 is switched on to create a current path from Vcc through the

transistors

1052,1050,1024, and theantifuse1016 to thecommon bus line1020. If the antifuse is programmed and has a low impedance a very low voltage will occur at thesource terminal1028 that is inverted by theinverter1054 into a high OUTPUT signal indicating theantifuse1016 is programmed. If theantifuse1016 is unprogrammed it will have a very high impedance and the voltage at thesource terminal1028 will be close to Vcc. Theinverter1054 will invert this high voltage into a low OUTPUT signal indicating that theantifuse1016 is unprogrammed.

With reference to thebank400 shown inFIG. 4, once one of the antifuses410416 in thebank400 is programmed, it is an impedance element similar to a diode or a resistor, and provides a possible current path for current on thecommon bus line442. It is desirable to limit current on thecommon bus line442, and therefore additional sources of current on thecommon bus line442 are to be substantially eliminated as far as is possible. For this reason, thecircuits1000 include several features to substantially eliminate current flow from thecommon bus line1020 through theantifuse1016, and these features will now be described.

TheHVT1024 is a possible source of current flow from thecommon bus line1020 during the programming mode when thecommon bus line1020 is at the elevated voltage and theantifuse1016 is programmed. The elevated voltage may induce breakdown current in theHVT1024, and this does not occur through its substrate because of the high drain breakdown voltage of theHVT1024. The elevated voltage is distributed across the

transistors

1024,1045, and1046 and the

diodes

1034 and1042 as described below.

The structure including theHVT1024 and the

diodes

1034 and1042 described above give theprogram driver circuit1010 the following operating characteristics. Current will flow through theHVT1024 as long as theantifuse1016 is programmed and either the

transistors

1045 and1046 or theread circuit1011 allow current to flow. If current ceases in theHVT1024 in the active or sleep modes, then the voltage at thesource terminal1028 rises to approximately a voltage at thegate terminal1030 less a threshold voltage V_Tof theHVT1024. If the elevated voltage is on thecommon bus line1020 then a first portion of it is held across thegate dielectric622, and a second portion of it is held across a depletion region in thediode1042. This voltage distribution is non-linear, and is determined by the reverse bias characteristics of thediode1042 and the characteristics of thegate dielectric622. The voltage distribution may vary over time. The reverse bias characteristics of thediode1042 may be modified during the operation of thecircuits1000, particularly in the programming mode, by modulating Vbb. For example, Vbb may be tied to Vss, or raised or lowered by 1 or 2 volts from Vss to change the voltage distribution across thegate dielectric622 and thediode1042.

The

diodes

1034 and1042 may be fabricated as a single n-channel transistor1100 shown inFIG. 11 according to an embodiment of the present invention. Thetransistor1100 is formed in a p-type well1110 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. An n+-typedrain diffusion region1112 and an n+-typesource diffusion region1114 are formed in thewell1110. A p+-type welltie diffusion region1116 is also formed in the well1110 to provide an ohmic contact to bias thewell1110. Agate electrode1120 is formed over a layer of gate dielectric1122 which is formed over the well1110 between thedrain diffusion region1112 and thesource diffusion region1114. In alternate embodiments of the present invention thegate electrode1120 may be formed by metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate dielectric1122 may be oxide, oxynitride, or nitrided oxide. Thegate electrode1120 and thedrain diffusion region1112 comprise theanode1038 and are connected to Vcc. Thesource diffusion region1114 comprises the

cathodes

1033 and1040 and is connected to thegate terminal1030. Thewell1110 and thediffusion region1116 comprise theanode1044 and are coupled to Vbb.

Thediode1034 may be fabricated as a p+-type diode1200 shown inFIG. 12 according to an embodiment of the present invention. Thediode1200 is formed in an n-type well1210 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. An n+-type diffusion region1212 and a p+-type diffusion region1214 are formed in thewell1210. The n+-type diffusion region1212 comprises thecathode1033 and is connected to thegate terminal1030, and the p+-type diffusion region1214 comprises theanode1038 and is connected to Vcc.

Thediode1034 may be fabricated as a p-type well diode1300 shown inFIG. 13 according to an embodiment of the present invention. An n-type triple well1306 is formed in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. An n-type isolation region1308 is also formed in the substrate above the triple well1306. Thediode1300 is formed in a p-type well1310 formed between the triple well1306 and theisolation region1308. An n+-type diffusion region1312 and a p+-type diffusion region1314 are formed in thewell1310. The n+-type diffusion region1312 comprises thecathode1033 and is connected to thegate terminal1030, and the p+-type diffusion region1314 comprises theanode1038 and is connected to Vcc.

Thediode1042 may be fabricated as the p+-type diode1200 shown inFIG. 12 according to an embodiment of the present invention. The n+-type diffusion region1212 comprises thecathode1040 and is connected to thegate terminal1030, and the p+-type diffusion region1214 comprises theanode1044 and is connected to Vbb instead of Vcc as shown inFIG. 12.

Thediode1042 may be fabricated as an n+diode1400 shown inFIG. 14 according to an embodiment of the present invention. Thediode1400 is formed in a p-type well1410 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. An n+-type diffusion region1412 is formed in the well1410 between regions of shallowtrench isolation oxide1414. A p+-type diffusion region1416 is formed in the well1410 to provide an ohmic contact coupled to Vbb. The n+-type diffusion region1412 comprises thecathode1040 and is connected to thegate terminal1030, and the p+-type diffusion region1416 and the well1410 comprise theanode1044 coupled to Vbb.

Thediode1042 may be fabricated as an n+-typegated diode1500 shown inFIG. 15 according to an embodiment of the present invention. Thediode1500 is formed in a p-type well1510 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. Agate electrode1512 is formed over a layer of gate dielectric1514 which is formed over thewell1510. Thegate electrode1512 is connected to Vss. In alternate embodiments of the present invention thegate electrode1512 may comprise metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate dielectric1514 may be oxide, oxynitride, or nitrided oxide. An n+-type diffusion region1516 is formed in the well1510 to comprise thecathode1040 of thediode1042, and is connected to thegate terminal1030. A p+-type diffusion region1518 is formed in the well1510 to provide an ohmic contact comprising theanode1044 of thediode1042 coupled to Vbb. Thegate dielectric1514 is formed near theregion1516 and thegate electrode1512 modulates the performance of thediode1042 with a strong electric field.

Thediode1042 may be fabricated as a p+-typegated diode1600 shown inFIG. 16 according to an embodiment of the present invention. Thediode1600 is formed in an n-type well1610 in a substrate, a surrounding well, or tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. Agate electrode1612 is formed over a layer of gate dielectric1614 which is formed over thewell1610. In alternate embodiments of the present invention thegate electrode1612 comprises metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate dielectric1614 may be oxide, oxynitride, or nitrided oxide. An n+-type diffusion region1616 is formed in the well1610 to comprise thecathode1040 of thediode1042, and is connected to thegate electrode1612 and to thegate terminal1030. A p+-type diffusion region1618 is formed in the well1610 to comprise theanode1044 of thediode1042 coupled to Vbb. Thegate dielectric1614 is formed near theregion1618 and thegate electrode1612 modulates the performance of thediode1042 with a strong electric field.

The

diodes

1034 and1042 described above with reference toFIGS. 12-16 may be modified by adding or subtracting implants and mask steps to change their reverse bias characteristics.

Theread circuit1011 also includes elements that are possible sources of current flow from thecommon bus line1020. Theread circuit1011 has several p-channel transistors which are favored over n-channel transistors because p-channel transistors provide a better noise margin by not sustaining a threshold voltage drop from Vcc when theantifuse1016 is read as described above. However, when theprogramming logic circuit420 is in the programming mode and there is an elevated voltage on thecommon bus line1020, the p-channel transistors provide a path for current from thecommon bus line1020. This will be described with reference to a cross-sectional view of a p-channel transistor1700 shown inFIG. 17 according to an embodiment of the present invention. The

transistors

1050 and1052 are similar to the p-channel transistor1700.

The p-channel transistor1700 is formed in an n-type well1710 in a substrate, a surrounding well, or a tank (not shown). The substrate may be a silicon substrate or a semiconductor layer formed over an insulator. A p+-typesource diffusion region1712 and a p+-typedrain diffusion region1714 are formed in thewell1710. An n+-type welltie diffusion region1716 is also formed in the well1710 to provide an ohmic contact to bias the well1710 with a reference voltage. Agate electrode1720 is formed over a layer of gate dielectric1722 which is formed over the well1710 between thesource diffusion region1712 and thedrain diffusion region1714. In alternate embodiments of the present invention thegate electrode1720 may comprise metal or polysilicon or layers of polysilicon and a silicide such as tungsten silicide (WSi_x), titanium silicide (TiSi₂), or cobalt silicide (CoSi₂). Thegate dielectric1722 may be oxide, oxynitride, or nitrided oxide. Thegate electrode1720 is connected to agate terminal1730. Asource terminal1732 is connected to thesource diffusion region1712, and adrain terminal1734 is connected to thedrain diffusion region1714. Finally, areference terminal1736 is connected to the welltie diffusion region1716.

As an example for illustrative purposes only, if the p-channel transistor1700 is connected in theread circuit1011 in a manner similar to thetransistor1050, and if both thegate terminal1730 and thereference terminal1736 are coupled to Vcc during the programming mode, then unwanted current may flow in thetransistor1700 for the following reasons. According to the example, thedrain terminal1734 is coupled to thesource terminal1028 of theHVT1024. If theantifuse1016 is programmed and the elevated voltage is on thecommon bus line1020 in the programming mode, a voltage at thesource terminal1028 will rise. With thegate terminal1730 and thereference terminal1736 are both coupled to Vcc, the p-channel transistor1700 may be switched on because the voltage of thedrain terminal1734 rises substantially above Vcc at thegate terminal1730. As a result, device current will pass between thesource terminal1732 and thedrain terminal1734 to Vcc. In addition, current may be induced through a parasitic diode comprising thedrain diffusion region1714 and the well1710 coupled to Vcc through the welltie diffusion region1716. This current is substantially eliminated by thelogic circuit1012.

Thelogic circuit1012 switches off p-channel transistors in theread circuit1011 when theprogramming logic circuit420 is in the programming mode and an elevated voltage is on thecommon bus line1020. Thelogic circuit1012 switches off the p-channel transistors by raising the voltage potential of thewells1710 by coupling them to an n-well voltage (NWV). The NWV rises as the voltage at thesource terminal1028 rises. As a result, the p-channel transistors are not switched on and no current flows through the parasitic diode in each p-channel transistor. This reduces current flow from thecommon bus line1020 through theHVT1024 and theread circuit1011 to Vcc in the programming mode. The structure and operation of thelogic circuit1012 will now be described.

Thelogic circuit1012 is coupled to receive three signals labeled PROGRAM, ZZ1, and ZZ2, which select one of the programming mode, the active mode, and the sleep mode. The signals PROGRAM, ZZ1, and ZZ2 are defined in Table 1:

TABLE 1


MODE	PROGRAM	ZZ1	ZZ2

PROGRAMMING	HIGH	LOW	LOW
ACTIVE	LOW	HIGH	LOW
SLEEP	LOW	LOW	HIGH

The signals PROGRAM, ZZ1, and ZZ2 can be generated by any appropriate circuit known to those skilled in the art to indicate the mode of operation of theprogramming logic circuit420.

When theprogramming logic circuit420 is in the active mode thecommon bus line1020 is coupled to Vss, and the state of theantifuse1016 is read as the

transistors

1050 and1052 are switched on and the OUTPUT signal is generated by theinverter1054. A substantial amount of current is dissipated through thecommon bus line1020 during the active mode if theantifuse1016 is programmed.

Thetransistor1052 is switched on by the voltage BIAS, and thetransistor1050 is switched on in the following manner. The PROGRAM signal is low, the signal ZZ1 is high and the signal ZZ2 is low in the active mode. The low PROGRAM signal is provided from acircuit1056 to force NWV to Vcc as it is coupled to an input of afirst inverter1058 and a source of an n-channel transistor1060. An output of theinverter1058 generates a high signal that is coupled to a gate terminal of a p-channel transistor1062 to switch it off. A gate terminal of thetransistor1060 is coupled to Vcc such that thetransistor1060 is rendered conductive, and the low PROGRAM signal is coupled through thetransistor1060 to switch on a p-channel transistor1064 at its gate terminal and couple Vcc to anNWV line1066 that is coupled to the welltie diffusion region1716 in each p-channel transistor in theread circuit1011. In the active mode, the NWV is approximately Vcc. TheNWV line1066 thereby couples the NWV to thewells1710 of p-channel transistors in theread circuit1011.

Thelogic circuit1012 includes a second inverter comprising a p-channel transistor1068, an n-channel transistor1070, and a terminal between the two to generate a signal TZZ1. A gate terminal of each of the

transistors

1068 and1070 is coupled to receive the signal ZZ1 which is high. Thetransistor1068 is switched off and thetransistor1070 is switched on to generate a low signal TZZ1 which is coupled to the gate terminal of thetransistor1050 to switch it on.

Thelogic circuit1012 also includes a third inverter comprising a p-channel transistor1072, an n-channel transistor1074, and a terminal between the two to generate a signal TZZ2. A gate terminal of each of the

transistors

1072 and1074 is coupled to receive the signal ZZ2 which is low. Thetransistor1072 is switched on and thetransistor1074 is switched off to generate the signal TZZ2 to be high, or approximately Vcc. The high signal TZZ2 is coupled to theread circuit1011 as will now be described.

In addition to the elements described above, theread circuit1011 includes a third p-channel transistor1076, a fourth p-channel transistor1078, and a fifth p-channel transistor1080. Each of the

transistors

1076,1078, and1080 is similar to the p-channel transistor1700 shown inFIG. 17. The gate terminal of thetransistor1076 is coupled to Vcc, and its reference terminal is coupled to its drain terminal and theNWV line1066. The

transistors

1078 and1080 are coupled in series between Vcc and theinverter1054. The high signal TZZ2 is coupled to a gate terminal of thetransistor1078 to switch it off so that the

transistors

1078 and1080 to not add to the current used to read theantifuse1016. Additional features of theread circuit1011 will be described hereinbelow.

When theprogramming logic circuit420 is in the programming mode thecommon bus line1020 is coupled to an elevated voltage. If theantifuse1016 is programmed, it is an impedance element between the elevated voltage and the rest of the elements in theprogram driver circuit1010 and theread circuit1011. Thelogic circuit1012 substantially eliminates current flow in the p-channel transistors in theread circuit1011 in the following manner.

In the programming mode the PROGRAM signal is high and is coupled to a drain of thetransistor1060 to switch it off.Inverter1058 generates a low signal to switch on thetransistor1062. The NWV on theNWV line1066 will rise, for reasons described below, and the high NWV is coupled to the gate terminal of thetransistor1064 to switch it off. With the

transistors

1060 and1064 both switched off, theNWV line1066 is isolated from both the PROGRAM signal and Vcc. Thesource terminal1028 may rise above Vcc in the programming mode when the elevated voltage is on thecommon bus line1020 and theantifuse1016 is programmed. When this happens thetransistor1076 will be switched on because its gate terminal is held at Vcc, and the rising voltage at thesource terminal1028 is coupled to theNWV line1066 to raise the NWV. TheNWV line1066 is coupled to the wells of each of the

transistors

1050,1052,1076,1078, and1080 which comprise a capacitive load that absorbs charge as the NWV rises.

In the programming mode, both of the signals ZZ1 and ZZ2 are low such that the p-

channel transistors

1068 and1072 are switched on and the n-

channel transistors

1070 and1074 are switched off and both of the signals TZZ1 and TZZ2 rise with the NWV. The signal TZZ1 is coupled to a gate terminal of thetransistor1050, and the signal TZZ2 is coupled to a gate terminal of thetransistor1078. The rise in NWV reduces current being passed through the parasitic diodes in the

transistors

1050,1052,1076,1078, and1080 because thewells1010 of those transistors have nearly the same voltage potential as thesource terminal1028, and there is not enough voltage potential to forward bias the parasitic diodes. In addition, the gate terminals of the

transistors

1050 and1078 are also coupled to the NWV to prevent them from being switched on by the voltage at thesource terminal1028. Substantial device current is thereby reduced in the

transistors

1050,1052,1078, and1080. In this manner the floating welldriver logic circuit1012 prevents substantial current in the p-

channel transistors

1050,1052,1076,1078, and1080 in the programming mode when the elevated voltage is on thecommon bus line1020 and an antifuse is to be programmed.

Theinverter1054 and the

transistors

1078 and1080 in theread circuit1011 are part of a latch circuit used to latch a state of theantifuse1016 when theprogramming logic circuit420 is in the sleep mode. Theprogramming logic circuit420 is receiving power and operating in both the active and sleep modes. However, in the sleep mode theprogramming logic circuit420 shuts down some operations to reduce power dissipation. As mentioned above, a substantial amount of current is dissipated through thecommon bus line1020 in the active mode if theantifuse1016 is programmed. This current is substantially eliminated in the sleep mode.

The latch circuit is used in the sleep mode to latch the state of theantifuse1016 to indicate correctly the state of theantifuse1016 in the sleep mode. The latch circuit also includes a first n-channel transistor1082 and a second n-channel transistor1084. The

transistors

The latch circuit is disabled in the active mode described above when the signal ZZ1 is high and the signal ZZ2 is low. The resulting signal TZZ1 is low to switch thetransistor1050 on while switching off thetransistor1082. The signal TZZ2 is high to switch off thetransistor1078. Thus no substantial current passes through the

transistors

1078 and1082 while theantifuse1016 is being read in the active mode.

In the sleep mode the PROGRAM signal is low so that theNWV line1066 is coupled to Vcc. The signal ZZ1 is low so the signal TZZ1 is high to switch off thetransistor1050 and block current from thetransistor1052. The high signal TZZ1 also enables thetransistor1082 to be switched on depending on a voltage between the

transistors

1082 and1084. The signal ZZ2 is high so the signal TZZ2 is low to enable thetransistor1078 to be switched on depending on a voltage between the

transistors

1078 and1080. Thesource terminal1028 will retain its voltage potential, near either Vcc or Vss, after being read in the active mode. If thesource terminal1028 is high, or is close to or above Vcc, the output of theinverter1054 will be low to switch off thetransistor1084 and enable thetransistor1080 to be switched on. The high voltage on thesource terminal1028 causes the

transistors

1078 and1080 to be switched on to couple thesource terminal1028 to Vcc and latch the output of theinverter1054 low. If thesource terminal1028 is low the output of theinverter1054 will be high to switch off thetransistor1080 and enable thetransistor1084 to be switched on. The low voltage at thesource terminal1028 causes the

transistors

1082 and1084 to be switched on to couple thesource terminal1028 to Vss and latch the output of theinverter1054 high.

The latch including the

transistors

1078,1080,1082, and1084, and theinverter1054, is used to latch a state of theantifuse1016 only in the sleep mode because the state of the latch is unknown when theprogramming logic circuit420 first receives power after being in a power-down mode. The latch will indicate the correct state of theantifuse1016 only after it has been read in the active mode. One advantage of the sleep mode is that thetransistor1050 is switched off to reduce the dissipation of current from Vcc through the

transistors

1052,1050,1024, and theantifuse1016 to thecommon bus line1020.

Theantifuse1016 may be read only intermittently during the operation of an integrated circuit and then its state may be latched the rest of the time according to an alternate embodiment of the present invention. In this embodiment of the invention, the state of the antifuse is read as it is in the active mode described above in response to a signal such as a power-up signal or a wake-up signal for the integrated circuit that initiates the read. The power-up or wake-up signal sets TZZ1 low and TZZ2 high for a period of time to read theantifuse1016 and allow theinverter1054 to generate a settled OUTPUT signal. As the period of time ends TZZ1 is set high and TZZ2 is set low to latch the state of theantifuse1016 as described above.

The capacitance of theNWV line1066 and the wells of the transistors it is coupled to absorbs charge as the NWV rises. TheNWV line1066 is coupled not only to the transistors shown inFIG. 10, but transistors associated with other antifuses in thebank400. If all of the antifuses in thebank400 are unprogrammed, then the capacitive load of theNWV line1066 will be charged from current passed through one or more of them and which will damage the antifuses. One way of preventing this damage is to short at least one antifuse in each bank, such as theantifuse410 in thebank400, with metal such that a current path exists to charge the capacitive load of theNWV line1066 and its transistors. The shorted antifuse may also be used in a test mode.

The

transistors

1070,1074, and1084 shown inFIG. 10 may each be replaced by an upper transistor and a lower transistor of similar types coupled in cascode to manage high voltages. The upper transistor has a gate terminal coupled to Vcc and the lower transistor has a gate terminal connected in a manner similar to the corresponding

original transistor

1070,1074, and1084.

An electrical schematic diagram of anintegrated circuit1800 with a common busline driver circuit1802 is shown inFIG. 18 according to an embodiment of the present invention. Theintegrated circuit1800 includes threebanks1810,1812, and1814 of antifuses coupled to acommon bus line1820. Thebanks1810,1812, and1814 may be similar to thebank400 shown inFIG. 4. Integrated circuits according to other embodiments of the present invention may include more or fewer banks of antifuses. Thecommon bus line1820 is coupled to an

ESD device

1822,1824, and anexternal pin1826 of theintegrated circuit1800. Theexternal pin1826 is similar to theexternal pin430 shown inFIG. 4.

The common busline driver circuit1802 is coupled to provide a path to Vss for thecommon bus line1820. The common busline driver circuit1802 includes aHVT1830 having adrain terminal1832, asource terminal1834, and agate terminal1836. TheHVT1830 is similar in structure and operating characteristics to the n-well drain transistor600 shown inFIG. 6. Thegate terminal1836 is coupled to acathode1841 of adiode1842, and ananode1846 of thediode1842 is coupled to Vcc. Thediode1842 is forward biased as long as Vcc exceeds a voltage at thegate terminal1836. Thegate terminal1836 is also coupled to acathode1850 of adiode1852. Ananode1854 of thediode1852 is coupled to Vbb. The

diodes

1842 and1852 maintain thegate terminal1836 at a voltage slightly less than Vcc, or higher.

A first n-channel transistor1860 and a second n-channel transistor1870 are coupled in cascode between thesource terminal1834 and Vss. A gate terminal of thetransistor1860 is coupled to Vcc, and a gate terminal of thetransistor1870 is coupled to alogic circuit1872 which controls current in the common busline driver circuit1802. A body terminal of thetransistor1870 is coupled to Vbb.

In the active mode thelogic circuit1872 switches on thetransistor1870 such that current on thecommon bus line1820 is given a path to Vss. The current flows from the antifuses in thebanks1810,1812, and1814 through theHVT1830 and the

transistors

1860,1870 to Vss as they are read in the active mode according to the description ofFIG. 10 recited above. The

transistors

1830,1860, and1870 are sized to accommodate current from all of these antifuses while maintaining thecommon bus line1820 near Vss.

In the programming mode thelogic circuit1872 switches off thetransistor1870 to prevent substantial current flow. This is done to maintain an elevated voltage on thecommon bus line1820, and to minimize current flow from thecommon bus line1820. Voltages along the common busline driver circuit1802 rise when thetransistor1870 is switched off to substantially end current flow, and the voltage rises on thecommon bus line1820. Thetransistor1830 and the

diodes

1842 and1852 function in a manner similar to thetransistor1024 and the

diodes

1034 and1042 described with reference toFIG. 10.

Theprogram driver circuit1010 shown inFIG. 10 and the common busline driver circuit1802 may be different in alternate embodiments of the present invention. For example, the two

circuits

1010 and1802 may have different HVTs, or one may have a cascode coupling of transistors and the other may have only a single corresponding transistor. The two

circuits

1010 and1802 may also have different combinations of diodes such as those described with reference toFIGS. 11-16.

Thelogic circuit1872 may also switch off thetransistor1870 during a test mode to permit an analog characterization of the impedance of each programmed antifuse in thebanks1810,1812, and1814. The current/voltage characteristics of each programmed antifuse are tested with a test apparatus such as a curve tracer coupled to theexternal pin1826. Current passes through the programmed antifuse, and other current sources coupled to thecommon bus line1820 must be substantially blocked during the test mode. Another test mode permits a modulation of the voltage BIAS to modulate the impedance of thetransistor1052. A noise margin for thecircuits1000 may be quantified by determining an impedance of thetransistor1052 at which theinverter1054 changes the OUTPUT signal. A wider noise margin will allow for more variability in the impedance of the antifuse over the operating lifetime of thecircuits1000 without impairing performance.

In alternate embodiments of the present invention the common busline driver circuit1802 is not included in theintegrated circuit1800 because a programming of its antifuses takes place during its manufacture, and theexternal pin1826 is coupled to Vss during its operation. This is called supply stealing. Thecommon bus line1820 is then always coupled to Vss during operation, and the common busline driver circuit1802 is not needed.

Theread circuit1011 shown inFIG. 10 may be modified to read theantifuse1016 as it is read in the active mode all of the time. A set ofsupport circuits1900 including a modifiedread circuit1910 are shown inFIG. 19 according to an embodiment of the present invention. All of the other elements of thesupport circuits1900 are similar to thesupport circuits1000 shown inFIG. 10, have been given the same reference numerals, and will not be further described for purposes of brevity. The state of theantifuse1016 is never latched by theread circuit1900.

Theread circuit1910 retains only two of the transistors,1052 and1076, from theread circuit1011, the remaining transistors not being necessary or included in theread circuit1910. Thetransistor1052 may be replaced by a resistor or other load device in alternate embodiments of the present invention. The operation of thetransistor1076 is the same as described above for theread circuit1011. Theantifuse1016 is read by comparing the impedance of thetransistor1052 with the impedance of theantifuse1016 with current flow from Vcc through the

transistors

1052 and1024 and theantifuse1016. The resulting OUTPUT signal is the same as described above for theread circuit1011.

Theantifuse510 may be similar to theantifuse200 shown inFIG. 2, in which case the programmed antifuse510 will be similar to a resistor and include aruptured gate dielectric222 between the n-type well210 and the n-type gate electrode220. Theantifuse510 may then be read with Vcc on thecommon bus line530 using a read circuit similar to theread circuit1011 shown inFIG. 10. A set ofsupport circuits2000 including an example of such a read circuit are shown inFIG. 20 according to an embodiment of the present invention. Thecircuits2000 include a programmed antifuse2008 similar to theantifuse200 having a first terminal coupled to acommon bus line2010. Thecommon bus line2010 is coupled to Vcc, and this may be called supply stealing for Vcc if it is supplied from a source external to thecircuits2000. A second terminal of theantifuse2008 is coupled to aprogram driver circuit2012 having the same elements as theprogram driver circuit1010 shown inFIG. 10. Also shown is the floating welldriver logic circuit1012. The same elements have retained the same reference numerals and will not be further described herein for purposes of brevity.

Aread circuit2020 is coupled to theprogram driver circuit2012 at thesource terminal1028 of theHVT1024 and includes elements similar to the elements of theread circuit1011 shown inFIG. 10. The similar elements have been given the same reference numerals and will not be further described for purposes of brevity. Theread circuit2020 does not include the

transistors

1050 and1052 shown inFIG. 10. Instead, a first n-channel transistor2030 and a second n-channel transistor2032 are coupled in series between thesource terminal1028 and Vss. Thetransistor2032 is switched on by a bias voltage BIAS applied to its gate terminal, and the voltage BIAS is generated by a current mirror (not shown) to control current through thetransistor2032 to Vss at its source terminal. A drain terminal of thetransistor2032 is coupled to a source terminal of thetransistor2030, and the drain terminal of thetransistor2030 is coupled to thesource terminal1028. The gate terminal of thetransistor2030 is coupled to the signal TZZ2 which is high to switch on thetransistor2030 when theprogramming logic circuit420 is in the active mode to read theantifuse2008.

When theantifuse2008 is read current flows from thecommon bus line1020 at Vcc through theantifuse2008 and the

transistors

1024,2030, and2032 to Vss. The impedance of theantifuse2008 is compared with the impedance of thetransistor2032 when it is switched on. If theantifuse2008 is programmed and has a low impedance then a voltage at thesource terminal1028 will be close to Vcc less the threshold voltages of thediode1034 and theHVT1024. The inverter will invert this high voltage into a low OUTPUT signal indicating that theantifuse2008 is programmed. If theantifuse2008 is unprogrammed it will have a very high impedance and the voltage at thesource terminal1028 will be slightly above Vss. Theinverter1054 will invert this low voltage into a high OUTPUT signal indicating theantifuse1016 is unprogrammed. Thetransistor2032 is a long-L n-channel transistor or a long-L p-channel transistor, or it may be replaced by a resistor. Thetransistor2032 may also be replaced by an upper transistor and a lower transistor of a similar type coupled in cascode to manage high voltages. The upper transistor has a gate terminal coupled to Vcc and the lower transistor has a gate terminal connected in a manner similar to the correspondingoriginal transistor2032.

Thelogic circuit1012 shown inFIG. 10 may not be necessary to reduce current flow in theread circuit1011 for many reasons. For example, process parameters may result in an integrated circuit that minimizes this current, or theHVT1024 may have characteristics which minimize this current. A pass-gate device may also reduce the need for thelogic circuit1012. A set ofsupport circuits2100 including a pass-gate device are shown inFIG. 21 according to an embodiment of the present invention. Thecircuits2100 include elements similar to the elements of thesupport circuits1000 shown inFIG. 10, and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity.

Theprogram driver circuit1010 is coupled to aread circuit2120 through an n-channel pass-gate transistor2130 according to an embodiment of the present invention. A drain of thepass-gate transistor2130 is coupled to the source of theHVT1024, and a source of thepass-gate transistor2130 is coupled to thetransistor1050. Vcc is coupled to a gate of thepass-gate transistor2130. Both of the signals ZZ1 and ZZ2 are low during the programming mode such that Vcc is coupled to the source of thepass-gate transistor2130 to ensure that it is not conductive and substantially prevents current flow from thecommon bus line1020. The voltage at the source of thepass-gate transistor2130 will vary during the active and sleep modes.

The use of thepass-gate transistor2130 to reduce current flow in theread circuit2120 may also permit the use of n-channel transistors instead of the p-channel transistors in theread circuit2120. A set ofsupport circuits2200 are shown inFIG. 22 according to an embodiment of the present invention. Thecircuits2200 include elements similar to the elements of thesupport circuits2100 shown inFIG. 21, and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Theprogram driver circuit1010 is coupled to aread circuit2220 through an n-channel pass-gate transistor2130 having Vcc coupled to its gate. Thepass-gate transistor2130 substantially prevents current flow from thecommon bus line1020. Theread circuit2220 includes elements similar to the elements of theread circuit2120 shown inFIG. 21, and further includes n-

channel transistors

2230,2232,2240, and2242 in place of the p-

channel transistors

1050,1052,1078, and1080 shown inFIG. 21. The signal ZZ1 is coupled to a gate of thetransistor2230 while the signal ZZ2 is coupled to gates of the

transistors

1082 and2240. An inverted signal OUTPUT is coupled to a gate of thetransistor2242, being inverted by aninverter2254. Theread circuit2220 operates in a manner substantially similar to theread circuit2120.

Thepass-gate transistor2130 shown inFIGS. 21 and 22 eliminates the need for thelogic circuit1012, but it also reduces the noise margin of the

read circuits

2120 and2220 during a read of theantifuse1016. The noise margin is improved by using the external supply voltage VccX and the regulated supply voltage VccR described above to supply power to the

read circuits

2120 and2220. For example, a set ofsupport circuits2300 are shown inFIG. 23 according to an embodiment of the present invention. Most of the elements of thecircuits2300 are similar to the elements of thesupport circuits2100 shown inFIG. 21, and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Theread circuit2120 is coupled to receive VccR on the sources of the

transistors

1052 and1080 while the gate of thepass-gate transistor2130 is coupled to VccX. Either VccX or VccR is coupled to the anode of thediode1034. During a read of theantifuse1016 VccR is regulated to be less than VccX to improve the noise margin of theread circuit2120. However, when antifuses such as theantifuse1016 are being programmed, VccR is raised to be approximately equal to VccX. A similar use of VccR and VccX would also improve the noise margin of thecircuits2200 shown inFIG. 22.

Thecommon bus line2010 in thecircuits2000 shown inFIG. 20 is coupled to Vcc. This may be replaced by a driver circuit driven by both of the supply voltages VccX and VccR. An electrical schematic diagram of anintegrated circuit2400 with a common busline driver circuit2402 is shown inFIG. 24 according to an embodiment of the present invention. Theintegrated circuit2400 includes three

banks

2410,2412, and2414 of antifuses coupled to acommon bus line2420. The

banks

2410,2412, and2414 may be similar to thebank400 shown inFIG. 4. Integrated circuits according to other embodiments of the present invention may include more or fewer banks of antifuses. Thecommon bus line2420 is coupled to an

ESD device

2422,2424, and anexternal pin2426 of theintegrated circuit2400. Theexternal pin2426 is similar to theexternal pin430 shown inFIG. 4.

The common busline driver circuit2402 couples thecommon bus line2420 to VccR when necessary. The common busline driver circuit2402 includes aHVT2430 having adrain terminal2432, asource terminal2434, and agate terminal2436. TheHVT2430 is similar in structure and operating characteristics to the n-well drain transistor600 shown inFIG. 6. Thegate terminal2436 is coupled to acathode2441 of adiode2442, and ananode2446 of thediode2442 is coupled to VccX. Thediode2442 is forward biased as long as VccX exceeds a voltage at thegate terminal2436. Thegate terminal2436 is also coupled to a cathode2450 of adiode2452. Ananode2454 of thediode2452 is coupled to Vss. The

diodes

2442 and2452 maintain thegate terminal2436 at a voltage slightly less than VccX, or higher.

A first n-channel transistor2460 and a second n-channel transistor2470 are coupled in cascode between thesource terminal2434 and VccR. A body terminal of thetransistor2470 is coupled to Vbb. A gate terminal of thetransistor2460 is coupled to VccX, and a gate terminal of thetransistor2470 is coupled to alogic circuit2472 which controls current in the common busline driver circuit2402. Thelogic circuit2472 is coupled to receive VccX as its supply voltage.

In the active mode thelogic circuit2472 switches on thetransistor2470 such that thecommon bus line2420 is coupled to VccR. The current flows from VccR to the antifuses in the

banks

2410,2412, and2414 as they are read in the active mode according to the description ofFIG. 10 recited above. The

transistors

2430,2460, and2470 are sized to accommodate current drawn by all of these antifuses while maintaining thecommon bus line2420 near VccR.

In the programming mode thelogic circuit2472 switches off thetransistor2470 to prevent substantial current flow. This is done to maintain an elevated voltage on thecommon bus line2420, and to minimize current flow from thecommon bus line2420. Voltages along the common busline driver circuit2402 rise when thetransistor2470 is switched off to substantially end current flow, and the voltage rises on thecommon bus line2420. Thetransistor2430 and the

diodes

2442 and2452 function in a manner similar to thetransistor1024 and the

diodes

1034 and1042 described with reference toFIG. 10.

Theprogram driver circuit1010 shown inFIG. 10 and the common bus

line driver circuits

1802 and2402 may be different in alternate embodiments of the present invention. For example, the

circuits

1010,1802, and2402 may have different HVTs, or one may have a cascode coupling of transistors and the other may have only a single corresponding transistor. The

circuits

1010,1802, and2402 may also have different combinations of diodes such as those described with reference toFIGS. 11-16.

With reference to thecircuits1000 shown inFIG. 10, another possible source of unwanted current in theantifuse1016 exists through the

transistors

1082 and1084. If the voltage at thesource1028 of theHVT1024 is low, then the OUTPUT signal is high and thetransistor1084 is switched on. If this condition occurs during the programming mode the

transistors

1082,1084 may draw current through theantifuse1016 causing damage if it is unprogrammed. A set ofsupport circuits2500 are shown inFIG. 25 according to an embodiment of the present invention. Most of the elements of thecircuits2500 are similar to the elements of thesupport circuits1000 shown inFIG. 10, and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Thecircuits2500 include aread circuit2520 that has, in addition to the elements shown inFIG. 10, elements that substantially prevent current through the

transistors

1082,1084 in the programming mode. Theinverter1054 comprises a p-channel transistor2530 and an n-channel transistor2532 connected in series, with drains of the

transistors

2530 and2532 connected together to form the output of theinverter1054. Gates of the

transistors

2530 and2532 are connected together to thesource1028 of theHVT1024. A source of thetransistor2532 is coupled to Vss, and a p-channel transistor2534 is coupled between a source of thetransistor2530 and Vcc. In addition, an n-channel transistor2536 is coupled between the output of theinverter1054 and Vss. The output of theinverter1054 remains connected to the gate of thetransistor1084. Gates of the

transistors

2534 and2536 are coupled to receive a signal SW, which is shown in the following Table 2:

	TABLE 2


	MODE	SW

	PROGRAMMING	HIGH
	ACTIVE	LOW
	SLEEP	LOW

In the programming mode the signal SW is high to switch off thetransistor2534 and substantially block current to theinverter1054. The high SW signal also switches on thetransistor2536 to couple the output of theinverter1054 to Vss and thus ensure that thetransistor1084 is switched off to substantially prevent unwanted current in theantifuse1016. In the active and sleep modes the signal SW is low to decouple the output of theinverter1054 from Vss and switch on thetransistor2534. Theinverter1054 is thereby coupled to Vcc and theread circuit2520 operates similarly to theread circuit1011 shown inFIG. 10 to read a state of theantifuse1016.

The

antifuses

100,140,150,200, and250 shown inFIGS. 1, 1A,1B,2, and2A, the

transistors

600,700,800,860,900,1100, and1700 shown inFIGS. 6, 7,8,8A,9,11, and17, and the

diodes

1200,1300,1400,1500, and1600 shown inFIGS. 12, 13,14,15, and16 according to embodiments of the present invention may be formed in wells within other wells or tanks rather than the substrates shown. Such wells or tanks may be situated with other wells or tanks, or within other wells or tanks, in a larger substrate. The wells or tanks may also be situated in a silicon-on-insulator (SOI) device.

An integrated circuit fabricated with one or more of the antifuses and circuits described above may be tested in a test mode. For example, an integrated circuit having a bank of antifuses is prestressed by applying a prestress voltage that is less than the elevated voltage used to program the antifuses. The antifuses are exposed to the prestress voltage and weaker antifuses are programmed as a result. The antifuses are then read to indicate the antifuses that have been programmed. The antifuses may be read by determining their analog resistances, by detecting a digital output of an addressed antifuse, or by detecting digital output from an addressed antifuse compared with several different load elements.

Thelogic circuit1012 shown inFIG. 10 may not be necessary to reduce current flow in theread circuit1011 for many reasons. For example, process parameters may result in an integrated circuit that minimizes this current, or theHVT1024 may have characteristics which minimize this current. A set ofsupport circuits2600 are shown inFIG. 26 according to an embodiment of the present invention. Thecircuits2600 include elements similar to the elements of thecircuits1000 shown inFIG. 10, and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Thelogic circuit1012, thetransistor1076, and the connections to theNWV line1066 shown inFIG. 10 are not included in thecircuits2600. Thecircuits2600 operate in a manner similar to thecircuits1000 without the above-listed elements.

Thepass-gate transistor2130 shown inFIG. 22 may not be necessary to reduce current flow in theread circuit2220 for the reasons mentioned above. A set ofsupport circuits2700 are shown inFIG. 27 according to an embodiment of the present invention. Thecircuits2700 include elements similar to the elements of thecircuits2200 shown inFIG. 22, and the same elements have retained the same reference numerals and will not be further described herein for purposes of brevity. Thepass-gate transistor2130 shown inFIG. 22 is not included in thecircuits2700. Thecircuits2700 operate in a manner similar to thecircuits2200 without thepass-gate transistor2130.

A block diagram of a static random access memory device (SRAM)2800 is shown inFIG. 28 according to an embodiment of the present invention. TheSRAM2800 may include one or more of the circuits and devices described above with respect toFIGS. 1-25 according to embodiments of the present invention. TheSRAM2800 has anarray2810 of memory cells that are accessed according to address signals provided to theSRAM2800 at a number of address inputs A0-A16. Anaddress decoder2820 decodes the address signals and accesses memory cells in thearray2810 according to the address signals. Data is written to the memory cells in thearray2810 when a write enable signal WE* and a chip enable signal CE* coupled to theSRAM2800 are both low. The data is received by theSRAM2800 over eight data input/output (I/O) paths DQ1-DQ8. The data is coupled to the memory cells in thearray2810 from the I/O paths DQ1-DQ8 through an I/O control circuit2830. Data is read from the memory cells in thearray2810 when the write enable signal WE* is high and an output enable signal OE* coupled to theSRAM2800 and the chip enable signal CE* are both low. A power downcircuit2840 controls theSRAM2800 during a power-down mode. The circuits and devices described above with respect toFIGS. 1-25 according to embodiments of the present invention may be included in other types of memory devices such as DRAMs, programmable logic devices, PROMs, EPROMs, and EEPROMs.

Anintegrated circuit package2900 of a 32 k×36 SRAM memory device is shown inFIG. 29 according to an embodiment of the present invention. The SRAM may include one or more of the circuits and devices described above with respect toFIGS. 1-25 according to embodiments of the present invention. One of the

external pins

430,520,1022,1826, or2426 described above is one of

several pins

16,38,39,42,43, or66 in thepackage2900. The

pins

16,38,39,42,43, or66 are non-reserved pins, one of which is used as one of the

external pins

430,520,1022,1826, or2426. The pin selected as one of the

external pins

430,520,1022,1826, or2426 will receive an elevated voltage if an antifuse in the SRAM is to be programmed. The selected pin may be left floating, or may be coupled to Vss during a normal operation of the SRAM. In an alternate embodiment of the present invention, one of the

external pins

430,520,1022, or1826 described above is one of

several pins

17,40,67, or90 coupled to Vss during the operation of the SRAM. Similarly, theexternal pin2426 is one of

several pins

14,15,41,65, or91 coupled to Vcc during the operation of the SRAM. This is called supply stealing, and is described above with reference to theexternal pin1826 shown inFIG. 18.

A block diagram of an information-handling system3000 is shown inFIG. 30 according to an embodiment of the present invention. The information-handling system3000 includes amemory system3008, aprocessor3010, adisplay unit3020, and an input/output (I/O)subsystem3030. Theprocessor3010 may be, for example, a microprocessor. One or more of thememory system3008, theprocessor3010, thedisplay unit3020, and the I/O subsystem3030 may include one or more of the circuits and devices described above with respect toFIGS. 1-25 according to embodiments of the present invention. Theprocessor3010, thedisplay unit3020, the I/O subsystem3030, and thememory system3008 are coupled together by a suitable communication line orbus3040. Theprocessor3010 and thememory system3008 may be integrated circuits formed on a single substrate.

In various embodiments of the present invention, the information-handling system3000 is a computer system (such as, for example, a video game, a hand-held calculator, a television set-top box, a fixed-screen telephone, a smart mobile phone, a personal digital assistant (PDA), a network computer (NC), a hand-held computer, a personal computer, or a multi-processor supercomputer), an information appliance (such as, for example, a cellular telephone or any wireless device, a pager, or a daily planner or organizer), an information component (such as, for example, a magnetic disk drive or telecommunications modem), or other appliance (such as, for example, a hearing aid, washing machine or microwave oven having an electronic controller).

Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art having the benefit of this description that any equivalent arrangement may be substituted for the specific embodiments shown. For example, specific memory devices have been described and shown in the Figures. One skilled in the art having the benefit of this description will recognize that the invention may be employed in other types of memory devices and in other types of integrated circuit devices. The voltage Vbb described above may be approximately equal to Vss, or may be negative. In addition, in alternate embodiments of the present invention, the common bus line is sized to provide a programming current for more than one antifuse at the same time. The present invention is therefore limited only by the claims and equivalents thereof.

Claims

1. A transistor comprising:

a p-type halo in a source side of a p-type substrate;

an n-type lightly doped drain in the halo;

an n+-type source diffusion region in the lightly doped drain; and

an n+-type drain diffusion region in a drain side of the substrate.

2. The transistor ofclaim 1, further including:

a drain terminal connected to the drain diffusion region;

a source terminal connected to the source diffusion region;

a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;

a polysilicon gate over the layer of gate dielectric;

an electrode over the polysilicon gate;

a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and

a gate terminal connected to the electrode.

3. A method of forming a transistor comprising:

forming a p-type halo in a source side of a p-type substrate;

forming an n-type lightly doped drain in the halo;

forming an n+-type source diffusion region in the lightly doped drain; and

forming an n+-type drain diffusion region in a drain side of the substrate.

4. The method ofclaim 3, further including:

connecting a drain terminal to the drain diffusion region;

connecting a source terminal to the source diffusion region;

forming a layer of gate dielectric over the substrate between the drain diffusion region and the source diffusion region;

forming a polysilicon gate over the layer of gate dielectric;

forming an electrode over the polysilicon gate;

forming a spacer on sides of the gate dielectric, the polysilicon gate, and the electrode; and

connecting a gate terminal to the electrode.

5. A transistor comprising:

an n-type well in a drain side of a p-type substrate;

an n+-type drain diffusion region in the well;

a p-type halo in a source side of the substrate;

an n-type lightly doped drain in the halo; and

an n+-type source diffusion region in the lightly doped drain.

6. The transistor ofclaim 5, further including:

a drain terminal connected to the drain diffusion region;

a source terminal connected to the source diffusion region;

a polysilicon gate over the layer of gate dielectric;

an electrode over the polysilicon gate;

a gate terminal connected to the electrode.

7. A method of forming a transistor comprising:

forming an n-type well in a drain side of a p-type substrate;

forming an n+-type drain diffusion region in the well;

forming a p-type halo in a source side of the substrate;

forming an n-type lightly doped drain in the halo; and

forming an n+-type source diffusion region in the lightly doped drain.

8. The method ofclaim 7, further including:

connecting a drain terminal to the drain diffusion region;

connecting a source terminal to the source diffusion region;

forming a polysilicon gate over the layer of gate dielectric;

forming an electrode over the polysilicon gate;

connecting a gate terminal to the electrode.

9. An integrated circuit comprising:

an external pin;

a common bus line coupled to the external pin;

an antifuse bank coupled to the common bus line, the antifuse bank including a plurality of antifuses; and

a common bus line driver circuit including:

a high-voltage transistor having a first terminal coupled to the common bus line, a control terminal, and a second terminal;

a diode coupled between the control terminal and a reference voltage; and

a control transistor coupled between the second terminal and a voltage reference.

10. The integrated circuit ofclaim 9, wherein:

the high-voltage transistor includes an n-well drain transistor having a drain terminal coupled to the common bus line, a control terminal coupled to the diode, and a source terminal coupled to the control transistor;

the diode includes:

a first diode including an anode coupled to a voltage supply and a cathode coupled to the control terminal of the n-well drain transistor; and

a second diode including a cathode coupled to the control terminal of the n-well drain transistor and an anode coupled to a voltage reference to withstand a high voltage on the control terminal of the n-well drain transistor;

the control transistor is coupled between the second terminal and a reference voltage and further includes a control circuit to switch on the control transistor to couple the common bus line to the ground voltage reference and to switch off the control transistor to permit an elevated voltage on the common bus line.

11. A method of operating an integrated circuit comprising:

coupling an elevated voltage through an external pin to a common bus line in the integrated circuit to program an antifuse coupled to the common bus line;

switching off a control transistor in a common bus line driver circuit coupled between the common bus line and a voltage reference to substantially prevent current flow from the common bus line;

bearing a portion of the elevated voltage across a high-voltage transistor having a first terminal coupled to the common bus line, a control terminal, and a second terminal coupled to the control transistor;

bearing a portion of the elevated voltage between a diode and the control terminal of the high-voltage transistor; and

switching on the control transistor to couple the common bus line to the voltage reference to read the antifuse.

12. The method ofclaim 11, wherein:

switching off a control transistor includes switching off a control transistor with a control circuit in a common bus line driver circuit coupled between the common bus line and a voltage reference to substantially prevent current flow from the common bus line;

bearing a portion of the elevated voltage across a high-voltage transistor includes bearing a portion of the elevated voltage across an n-well drain transistor having a drain terminal coupled to the common bus line, a control terminal coupled to a diode, and a source terminal coupled to the control transistor;

bearing a portion of the elevated voltage between a diode and the control terminal includes bearing a portion of the elevated voltage between the control terminal of the n-well drain transistor, a first diode including an anode coupled to a voltage supply and a cathode coupled to the control terminal of the n-well drain transistor, and a second diode including a cathode coupled to the control terminal of the n-well drain transistor and an anode coupled to a reference voltage; and

switching on the control transistor includes switching on the control transistor with the control circuit to couple the common bus line to the voltage reference to read the antifuse.

13. A circuit comprising:

a high-voltage transistor including:

a well of a first conductivity type in a substrate of a second conductivity type;

a drain diffusion region of the first conductivity type in the well, the drain diffusion region being coupled to an elevated voltage source;

a source diffusion region of the first conductivity type in the substrate;

a layer of gate dielectric over the substrate; and

a gate electrode over the gate dielectric;

a diode coupled between the gate electrode and a reference voltage to hold a voltage on the gate electrode caused by a charge transfer across the gate dielectric due to the elevated voltage source;

a support circuit coupled to the source diffusion region.

14. The circuit ofclaim 13, wherein:

the substrate includes a p-type substrate;

the well includes an n-type well in the p-type substrate;

the drain diffusion region includes an n+-type drain diffusion region in the n-type well;

the source diffusion region includes an n+-type source diffusion region in the p-type substrate;

the gate dielectric includes a layer of oxide;

the gate electrode includes a gate electrode over the layer of oxide;

the diode includes:

a first diode including an anode coupled to a voltage supply and a cathode coupled to the gate electrode of the high-voltage transistor to switch on the high-voltage transistor; and

a second diode including a cathode coupled to the gate electrode of the high-voltage transistor and an anode coupled to a reference voltage to withstand a high voltage on the gate electrode; and

the support circuit includes a control transistor is coupled between the source diffusion region and a ground voltage reference and further includes a control circuit to switch on the control transistor to couple the elevated voltage source to the ground voltage reference and to switch off the control transistor to permit the circuit to bear the elevated voltage.

15. A method comprising:

coupling an elevated voltage to a drain of a high-voltage transistor;

allowing charge to transfer from the drain across a layer of gate dielectric to a gate electrode of the high-voltage transistor; and

allowing the charge to accumulate in the gate electrode to raise a voltage of the gate electrode to a balanced voltage to reduce further charge transfer across the layer of gate dielectric.

16. The method ofclaim 15, wherein:

coupling an elevated voltage to a drain includes coupling an elevated voltage to an n+-type drain diffusion region in an n-type well in a p-type substrate of a high-voltage transistor;

allowing charge to transfer from the drain includes allowing charge to transfer from the n+-type drain diffusion region across a layer of gate oxide to a gate electrode of the high-voltage transistor; and

allowing the charge to accumulate includes holding the charge in the gate electrode with a first diode including an anode coupled to a voltage supply and a cathode coupled to the gate electrode and a second diode including an cathode coupled to the gate electrode and an anode coupled to a reference voltage to raise a voltage of the gate electrode to a balanced voltage to reduce further charge transfer across the layer of oxide.

17. An antifuse circuit comprising:

an antifuse having a first terminal coupled to a programming voltage supply and a second terminal;

a high-voltage transistor including:

a drain diffusion region of the first conductivity type in the well, the drain diffusion region being coupled to the second terminal of the antifuse;

a source diffusion region of the first conductivity type in the substrate;

a layer of gate dielectric over the substrate; and

a gate electrode over the gate dielectric;

a diode coupled between the gate electrode and a first reference voltage to hold a voltage on the gate electrode caused by a charge transfer across the gate dielectric due to the programming voltage;

an impedance transistor having a first terminal coupled to the source diffusion region of the antifuse and a second terminal; and

a control transistor having a first terminal coupled to the second terminal of the impedance transistor, a second terminal coupled to a second reference voltage, and a control terminal coupled to a control circuit to switch the control transistor on to couple the second terminal of the anti fuse to the second reference voltage to program the antifuse, and to switch the control transistor off when the antifuse is not being programmed.

18. The antifuse circuit ofclaim 17, wherein:

the substrate includes a p-type substrate;

the well includes an n-type well in the p-type substrate;

the gate dielectric includes a layer of oxide;

the gate electrode includes a gate electrode over the layer of oxide;

the diode includes:

a second diode including a cathode coupled to the gate electrode of the high-voltage transistor and an anode coupled to a reference voltage to withstand a high voltage on the gate electrode;

the control transistor includes an n-channel transistor; and

the impedance transistor includes an n-channel transistor including a gate terminal coupled to the voltage supply.

19. A method of operating an antifuse circuit comprising:

coupling an elevated voltage to a first terminal of an antifuse from a common bus line;

coupling a second terminal of the antifuse to a reference voltage through a control transistor to program the antifuse with current from the common bus line;

switching off the control transistor to uncouple the second terminal of the antifuse from the reference voltage after the antifuse is programmed; and

reducing a voltage on a terminal of the control transistor with an impedance transistor coupled between the second terminal of the antifuse and the terminal of the control transistor to reduce a probability of snap-back in the control transistor.

20. The method ofclaim 19, wherein:

coupling an elevated voltage includes coupling an elevated voltage from an external pin to a first terminal of an antifuse through a common bus line;

coupling a second terminal of the antifuse includes coupling a second terminal of the antifuse to a ground reference voltage through an n-channel control transistor to program the antifuse with current from the common bus line;

switching off the control transistor includes switching off the n-channel control transistor with a control circuit to uncouple the second terminal of the antifuse from the ground reference voltage after the antifuse is programmed; and

reducing a voltage includes reducing a voltage on a drain terminal of the n-channel control transistor with an n-channel impedance transistor that is switched on and coupled between the second terminal of the antifuse and the drain terminal of the control transistor to reduce a probability of snap-back in the control transistor.

21. A method of operating an antifuse circuit including:

coupling an elevated voltage to a first terminal of an unprogrammed antifuse from a common bus line;

separating a second terminal of the antifuse from a reference voltage with a control transistor that is switched off; and

reducing a voltage on a terminal of the control transistor with an impedance transistor coupled between the second terminal of the antifuse and the terminal of the control transistor to reduce leakage current in the control transistor.

22. The method ofclaim 21, wherein:

separating a second terminal of the antifuse includes separating a second terminal of the antifuse from a ground reference voltage with an n-channel control transistor that is switched off; and

reducing a voltage includes reducing a voltage on a drain terminal of the n-channel control transistor with an n-channel impedance transistor that is switched on and coupled between the second terminal of the antifuse and the drain terminal of the control transistor to reduce leakage current in the control transistor.

23. An antifuse circuit comprising:

an antifuse having a first terminal coupled to an elevated voltage in a programming mode and a reference voltage in an active mode;

a read circuit including a p-channel transistor coupled between a read voltage source and a second terminal of the antifuse to couple the read voltage source to the antifuse to read the antifuse in the active mode; and

a floating well driver logic circuit coupled to a gate terminal and a well of the p-channel transistor to raise a voltage of the gate terminal and the well in the programming mode to substantially prevent current in the p-channel transistor.

24. The antifuse circuit ofclaim 23, wherein:

the antifuse includes an antifuse having a first terminal coupled to a common bus line, the common bus line being coupled to the elevated voltage in the programming mode and to a ground reference voltage in the active mode;

the read circuit further includes a plurality of p-channel transistors, one of the p-channel transistors being coupled between the second terminal of the antifuse and the floating well driver logic circuit to couple a rising voltage on the second terminal of the antifuse to the floating well driver logic circuit; and

the floating well driver logic circuit further includes a voltage source coupled to a gate terminal and a well of selected ones of the p-channel transistors in the read circuit to raise a voltage of the gate terminals and the wells in the programming mode to substantially prevent current in the selected p-channel transistors.

25. A method of operating an antifuse circuit, comprising:

coupling an elevated voltage to a first terminal of an antifuse in a programming mode and coupling a reference voltage to the first terminal in an active mode;

reading the antifuse in the active mode with a p-channel transistor coupled between a read voltage source and a second terminal of the antifuse; and

raising a voltage of a gate terminal and a well of the p-channel transistor in the programming mode to substantially prevent current in the p-channel transistor.

26. The method ofclaim 25, wherein:

coupling a reference voltage includes coupling a ground reference voltage to the first terminal in the active mode;

reading the antifuse further includes:

coupling the read voltage source to the second terminal of the antifuse; and

detecting a voltage on the second terminal of the antifuse with an inverter in a read circuit; and

raising a voltage includes:

coupling a rising voltage on the second terminal of the antifuse to a gate terminal and a well of each of a plurality of p-channel transistors in the read circuit.

27. An integrated memory device comprising:

an array of memory cells;

an address decoder;

a plurality of input/output paths;

an input/output control circuit; and

an antifuse circuit including:

an external pin coupled to a common bus line to couple an elevated voltage to an antifuse having a first terminal coupled to the common bus line to program the antifuse in a programming mode;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed in the programming mode;

a common bus line driver circuit to couple the common bus line to a reference voltage during an active mode;

a read circuit coupled to the second terminal of the antifuse to read the antifuse during the active mode;

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode; and

a floating well driver logic circuit coupled to the read circuit and the latch circuit to switch off transistors in the read circuit and the latch circuit during the programming mode.

28. An integrated circuit comprising:

means for reading the antifuse during the active mode;

means for switching off transistors in the latch circuit and in the means for reading the antifuse during the programming mode.