US20060049449A1 - Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory - Google Patents

Abstract

A non-volatile semiconductor memory includes memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.

Description

CROSS REFERENCE TO RELATED APPLICATIONS AND INCORPORATION BY REFERRENCE
• This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2004-258523, filed on Sep. 6, 2004; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• This present invention relates to a non-volatile semiconductor memory, more particularly, a non-volatile semiconductor memory and a method for fabricating the same using Silicon On Insulator (SOI) technique.
• 2. Description of the Related Art
• An electrically erasable programmable read-only memory (EEPROM) is known as a non-volatile semiconductor memory. In the EEPROM, a cell array is comprised in such a way that a memory cell transistor is arranged at an intersection where a word line in the row direction and a bit line in the column direction cross over each other. Among EEPROMS, the NAND flash EEPROM in which a plurality of memory cell transistors are connected in series, and which can erase all the written data simultaneously, has been in wide use.
• A memory cell transistor of the NAND flash EEPROM includes n⁺-source and drain regions which are opposite to each other; and a p channel region between the source and drain regions. A stacked gate structure is formed on the channel region in which a control gate electrode and a floating gate electrode are stacked. Memory cell transistors adjacent to one another in the row direction are isolated from one another by an element isolation region. The NAND flash EEPROM experiences of fluctuations in gate threshold voltage due to influence of parasitic capacitance in the element isolation region between memory cell transistors and parasitic capacitance between an interconnect and a substrate, and the like.
• In order to reduce the fluctuation in the gate threshold voltage due to the influence of the parasitic capacitance in the element isolation region and the parasitic capacitance between the interconnect and the substrate, a NAND flash EEPROM has been considered which employs SOI technology in which a semiconductor layer (SOI layer), arranged on the an embedded insulating layer (SOI insulator), serves as an active layer. According to the NAND flash EEPROM employing the SOI technology, the memory cell transistors adjacent to one another in the row direction are isolated from one another by the element isolation insulating film which is embedded as far as the SOI insulator, thereby enabling the parasitic capacitance in the element isolation region be reduced. In addition, since the SOI layer is formed on the SOI insulator, the parasitic capacitance between the interconnect and the substrate can be reduced, and hence the fluctuation in the gate threshold voltage can be reduced. As the memory cell transistor has been minaturized, an interval between the source and the drain of the memory cell transistor has become so narrower that influence of the short channel effect has increased in the NAND flash EEPROM employing the SOI technology.
SUMMARY OF THE INVENTION
• An aspect of the present invention inheres in a non-volatile semiconductor memory comprising memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.
• Another aspect of the present invention inheres in a non-volatile semiconductor memory having a plurality of memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor including: source and drain regions having a first conductivity type disposed on an insulating layer; a channel region having the first conductivity type disposed between the source and drain regions, and having a lower impurity concentration than the source and drain regions; a floating gate electrode disposed above the channel region and insulated from the channel region; and a control gate electrode disposed above the floating gate electrode and insulated from the floating electrode.
• Further aspect of the present invention inheres in a method for fabricating a non-volatile semiconductor memory comprising, forming a depletion mode memory cell transistor, comprising: depositing a gate insulating film on a semiconductor layer having a first conductivity type disposed on an insulating layer; depositing a floating gate electrode on the gate insulating film; depositing an inter-electrode insulating film on the floating gate electrode; depositing a control gate electrode on the inter-electrode insulating film; forming a groove penetrating the control gate electrode, the inter-electrode insulating film and the floating gate electrode; and forming source and drain regions having the first conductivity type in the semiconductor layer under the groove.
BRIEF DESCRIPTION OF DRAWINGS
• FIG. 1 is a cross-sectional view in the column direction (I-I direction ofFIG. 2) showing an example of a cell array of a non-volatile semiconductor memory according to an embodiment of the present invention.
• FIG. 2 is a plan view showing an example of the cell array of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 3 is a cross-sectional view in the row direction (II-II direction ofFIG. 2) showing an example of the cell array of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 4 is an equivalent circuit diagram showing an example of the cell array of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 5 is a graph showing an example of I-V characteristic of a memory cell transistor of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 6 is a chart showing an example of operation voltage supplying to a wiring of the cell array of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 7 is an equivalent circuit diagram for explaining writing operation of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 8 is an equivalent circuit diagram for explaining erasing operation of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 9 is an equivalent circuit diagram for explaining reading operation of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 10 is a cross-sectional view for explaining a floating gate electrode, which does not store electron of the memory cell transistor of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 11 is a cross-sectional view for explaining the floating gate electrode stores electron of the memory cell transistor of the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 12A is a cross-sectional view in the column direction (III-III direction ofFIG. 2) showing an example of a method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 12B is a cross-sectional view in the column direction (II-II direction ofFIG. 2) showing an example of the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 13A is a cross-sectional view in the column direction after the process ofFIG. 12A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 13B is a cross-sectional view in the row direction after the process ofFIG. 12B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 14A is a cross-sectional view in the column direction after the process ofFIG. 13A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 14B is a cross-sectional view in the row direction after the process ofFIG. 13B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 15A is a cross-sectional view in the column direction after the process ofFIG. 14A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 15B is a cross-sectional view in the row direction after the process ofFIG. 14B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 16A is a cross-sectional view in the column direction after the process ofFIG. 15A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 16B is a cross-sectional view in the row direction after the process ofFIG. 15B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 17A is a cross-sectional view in the column direction after the process ofFIG. 16A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 17B is a cross-sectional view in the row direction after the process ofFIG. 16B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 18A is a cross-sectional view in the column direction after the process ofFIG. 17A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 18B is a cross-sectional view in the row direction after the process ofFIG. 17B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 19A is a cross-sectional view in the column direction after the process ofFIG. 18A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 19B is a cross-sectional view in the row direction after the process ofFIG. 18B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 20A is a cross-sectional view in the column direction after the process ofFIG. 19A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 20B is a cross-sectional view in the row direction after the process ofFIG. 19B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 21A is a cross-sectional view in the column direction after the process ofFIG. 20A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 21B is a cross-sectional view in the row direction after the process ofFIG. 20B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 22A is a cross-sectional view in the column direction after the process ofFIG. 21A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 22B is a cross-sectional view in the row direction after the process ofFIG. 21B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 23A is a cross-sectional view in the column direction after the process ofFIG. 22A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 23B is a cross-sectional view in the row direction after the process ofFIG. 22B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
• FIG. 24 is a cross-sectional view showing an example of a memory cell transistor of a non-volatile semiconductor memory according to a first modification of the present invention.
• FIG. 25 is a cross-sectional view for explaining operation of the memory cell transistor of the non-volatile semiconductor memory according to the first modification of the present invention.
• FIG. 26 is a cross-sectional view in the column direction (III-III direction ofFIG. 2) showing an example of a method for fabricating the non-volatile semiconductor memory according to a second modification of the present invention.
• FIG. 27 is a cross-sectional view in the column direction after the process ofFIG. 26 showing the method for fabricating the non-volatile semiconductor memory according to the second modification of the present invention.
• FIG. 28 is a cross-sectional view in the column direction showing an example of a cell array of a non-volatile semiconductor memory according to a third modification of the present invention.
• FIG. 29 is a cross-sectional view showing an example of a peripheral circuit in the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 30A is a cross-sectional view showing an example of method for fabricating a cell array of a non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 30B is a cross-sectional view showing a method for fabricating a peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 31A is a cross-sectional view after the process ofFIG. 30A showing the method for fabricating the cell array of the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 31B is a cross-sectional view after the process ofFIG. 30B showing the method for fabricating the peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 32A is a cross-sectional view after viewFIG. 31A showing the method for fabricating the cell array of the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 32B is a cross-sectional view after the process ofFIG. 31B showing the method for fabricating the peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 33A is a cross-sectional view after viewFIG. 32A showing the method for fabricating the cell array of the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 33B is a cross-sectional view after the process ofFIG. 32B showing the method for fabricating the peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 34A is a cross-sectional view after viewFIG. 33A showing the method for fabricating the cell array of the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 34B is a cross-sectional view after the process ofFIG. 33B showing the method for fabricating the peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 35 is a cross-sectional view showing another example of a peripheral circuit in a non-volatile semiconductor memory according to the third modification of the present invention.
• FIG. 36 is a circuit diagram showing an example of a two-transistor type cell array in a non-volatile semiconductor memory according to the fourth modification of the present invention.
• FIG. 37 is a block diagram showing an example of a flash memory system using a non-volatile semiconductor memory according to the fifth modification of the present invention.
• FIG. 38 is a cross-sectional view in the column direction showing an example of a non-volatile semiconductor memory according to the sixth modification of the present invention.
• FIG. 39 is a cross-sectional view in the row direction showing an example of a non-volatile semiconductor memory according to the sixth modification of the present invention.
• FIG. 40 is a cross-sectional view showing another example of a non-volatile semiconductor memory according to the sixth modification of the present invention.
• FIG. 41 is a cross-sectional view in the row direction showing a cell array of a non-volatile semiconductor memory according to a comparative example.
• FIG. 42 is a cross-sectional view in the row direction showing the call array of a non-volatile semiconductor memory according to the comparative example.
DETAILED DESCRIPTION OF THE INVENTION
• Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.
• Generally and as it is conventional in the representation of semiconductor devices, it will be appreciated that the various drawings are not drawn to scale from one figure to another nor inside a given figure, and in particular that the layer thicknesses are arbitrarily drawn for facilitating the reading of the drawings.
• In the following descriptions, numerous specific details are set forth such as specific signal values, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits have been shown in block diagram form in order not to obscure the present invention in unnecessary detail.
• A non-volatile semiconductor memory according to an embodiment of the present invention is an insulating film (SOI insulator) and an NAND flash EEPROM in which a plurality of memory cell transistors are arranged in a matrix on the SOI insulator.FIG. 1 is a cross-sectional view of the non-volatile semiconductor memory taken along the I-I line in the column direction as shown inFIG. 2. As shown inFIG. 1, the memory cell transistors MT₁₁to MT_1nare depletion mode MIS transistors including source and drainregions421 to42 (n+1) having a first conductivity (n⁺) type. The memory cell transistors MT₁₁to MT_1nare arranged on theSOI insulator1, and are opposite to each other.Channel regions411 to41nhaving a first conductivity (n⁻) type are interposed between each adjacent pair of the source and drainregions421 to42 (n+1). The impurity concentrations of thechannel regions411 to41nare lower than that of the source and drainregions421 to42(n+1). Floatinggate electrodes13 are insulated, and each is arranged above each of thechannel regions411 to41n.Control gate electrodes15 are insulated, and each is arranged above each of the floatinggate electrodes13.
• The memory cell transistors MT₁₁to MT_1ninclude thechannel regions411 to41nhaving a conductivity which is the same as that of the source and drainregions421 to42(n+1), thereby constituting the depletion mode MIS transistors. The “MIS transistor” is an insulated gate transistor, such as a field effect transistor (FET) and a static induction transistor (SIT), which controls channel current by gate voltage through an insulating film (gate insulating film) interposed between a gate electrode and a channel region. A MISFET in which a silicon oxide film (SiO₂film) is used as a gate insulating film is referred to as a metal oxide semiconductor field effect transistor (MOSFET). In addition SiO₂, silicon nitride (Si₃N₄) tantalum oxide (Ta₂O₅), titanium oxide (TiO₂), alumina (Al₂O₃), zirconium oxide (ZrO₂) and the like can be used as a material for the gate insulating film of the MIS transistor.
• InFIG. 1, for example, n (n is an integer) memory cell transistors MT₁₁to MT_1nare arranged in the column direction so that they are adjacent to one another. Each of the memory cell transistors MT₁₁to MT_1nis a depletion mode MIS transistor including: the source and drainregions421 to42(n+1), each of which is common to each adjacent pair of the memory cell transistors MT₁₁to MT_1n; floatinggate electrodes13, each of which is arranged above one of thechannel regions411 to41ninterposed between each adjacent pair of the source and drainregions421 to42(n+1) with a gate insulating film (tunnel oxide film)12 interposed between the floating gate electrode and the channel region; andcontrol gate electrodes15, each of which is arranged above each of the floatinggate electrodes13 with an inter-electrodeinsulating film14 interposed between the control gate electrode and the floating gate electrode. Each of the memory cell transistors Mt₁₁to MT₁₁is a depletion mode MIS transistor implemented by a stacked gate structure in which the floatinggate electrodes13 and thecontrol gate electrodes15 are stacked. Si₃N₄, Ta₂O₅, TiO₂, Al₂O₃, ZrO₂, oxide/nitride/oxide (ONO), phosphor silicate glass (PSG), boron phosphor silicate glass (BPSG), silicon oxide nitride (SiON), barium titanate (BaTiO₃), silicon oxide fluoride (SiO_xF_x), and organic resins such as polyimide can be used as materials for the inter-electrode insulatingfilm14.
• SiO₂, sapphire (Al₂O₃) and the like can be used as materials of theSOI insulator1 with which an SOI structure is provided. Single crystal silicon, silicon germanium (SiGe) and the like can be used as a material for an semiconductor layer (SOI layer)2 provided on the top of theSOI insulating film1. The n⁻ channel regions411 to41nand the n⁺-source and drainregions421 to42(n+1) are arranged in theSOI insulating layer2. Each of thesource regions421 to42n,each of thechannel regions411 to41nand each of thedrain regions422 to42(n+1) are arranged alternately in one column direction so that, out of the plurality of memory cell transistors MT₁₁to MT_1narranged in the column direction in the matrix, thedrain region422 of one memory cell transistor MT₁₁serves as thesource region422 of another memory cell transistor MT₁₂, adjacent to the memory cell transistor MT₁₁. The memory cell transistors MT₁₁to MT_mnare arranged in a plurality of parallel columns so that thesource regions421 to42n,thechannel regions411 to41nand thedrain regions422 to42(n+1) are isolated from the corresponding source regions, channel regions and drain regions in other columns.
• Each of two select gate transistors STS1 and STD1 is arranged in, and adjacent to, each end of the column direction of the memory cell transistors MT₁₁to MT_1n. The select gate transistor STS1 is an enhancement MIS transistor including: an n⁺ drain region421 which is common asource region421 of the memory cell transistor MT11 positioned in one end of the arrangement in the column direction; achannel region42 having a second conductivity (p) type arranged so as to be adjacent to thedrain region421; an n⁺ source region43 arranged so as to be adjacent to thechannel region42;select gate electrodes13aand15aarranged above thechannel region42 with thegate insulating film12 interposed between thechannel region42 and the set ofselect gate electrodes13aand15a.Thedrain region421, thechannel region42 and thesource region43 are arranged in theSOI layer2. Asource line contact18 is arranged on thesource region43 so that thesource line contact18 is adjacent to the select gate transistor STS1.
• Alternatively, the select gate transistor STD1 is an enhancement MIS transistor including: an n⁺ source region42(n+1) which is common a drain region42(n+1) of the memory cell transistor MT in positioned in another end of the arrangement in the column direction; achannel region44 having a second conductivity type (p) arranged so as to be adjacent to the source region42(n+1); an n⁺ drain region45 arranged so as to be adjacent to thechannel region44;select gate electrodes13band15barranged above thechannel region44 with thegate insulating film12 interposed between thechannel region44 and the set ofselect gate electrodes13band15b.The source region42(n⁺), thechannel region44 and thedrain region45 are arranged in theSOI layer2. Abit line contact17 is arranged on thedrain region45 so that thebit line contact17 is adjacent to the select gate transistor STDl.
• As shown inFIG. 2, the following are arranged in the column direction of a cell array in the non-volatile semiconductor memory according to the present embodiment: a source line SL connected to thesource line contact18; a select gate line SGS to which theselect gate electrodes13aand15aof a select gate transistor STS1 are connected; word lines WL1 to WLn to which thecontrol gate electrodes15 of the respective memory cell transistors MT₁₁to MT_1nare connected; and a select gate line SGD to which theselect gate electrodes13band15bof the select gate transistor STD1 are connected. Bit lines BL1 and BL2 connected to thebit line contact17 are arranged in the row direction.
• FIG. 3 is a cross-sectional view of the non-volatile semiconductor memory taken along the II-II line in the row direction shown inFIG. 2. As shown inFIG. 3, an elementisolation insulating film6 is embedded between the floatinggate electrode13 and thechannel region411 of each of the memory cell transistors MT₁₁and MT₂₁which are adjacent to one another in the row direction. Elements of the respective memory cell transistors MT₁₁and MT₂₁, which are adjacent to one another in the row direction, are completely isolated from one another. A peripheral circuit of a cell array arranged on a semiconductor substrate is further provided in the outside of the cell array comprised of a plurality of memory cell transistors.
• An equivalent circuit of the non-volatile semiconductor memory according to the embodiment shown in FIGS.1 to3 is shown inFIG. 4. As shown inFIG. 4, acell array100 comprises m×n (m and n are integers) memory cell transistors MT₁₁to MT_1n, MT₂₁to MT_2n, . . . , MT_mnto MT_mnwhich are depletion mode MIS transistors. In thecell array100, a plurality of memory cell transistors MT₁₁to MT₁₁are arranged as a group in a column; a plurality of memory cell transistors MT₂₁to MT_2nare arranged as a group in another column; . . . ; and a plurality of memory cell transistors MT_m1to MT_mnare arranged as a group in the other column. In addition, the group of memory cell transistors MT₁₁to MT_1n, the group of memory cell transistors MT₂₁to MT_2n, and the group of memory cell transistors MT_m1to MT_mnare arranged in the row direction. In this way, the plurality of memory cell transistors MT₁₁to MT_1n, MT₂₁to MT_2n, . . . , MT_m1to MT_mnare arranged in a matrix.
• In acell array100, the memory cell transistors MT11 to MT1n, the select gate transistors STS1 and STD1 are connected in series, thereby comprising a cell unit. The drain region of the enhancement mode select gate transistor STS1 which selects one out of the memory cell transistors MT₁₁to MT_1nis connected to the source region of the memory cell transistor MT₁₁positioned at one end of the arrangement in which the group of memory cell transistors MT₁₁to MT_1nare connected in series. The source region of the enhancement selective gate transistor STD1 which selects one out of the memory cell transistors MT₁₁to MT_1nis connected to the drain region of the memory cell transistor MT_1npositioned at the other end of the arrangement in which the group of memory cell transistors MT₁₁to MT_1nare connected in series. The select gate transistor STS2, the memory cell transistors MT₂₁to MT_2nand the select gate transistor STD2 are also connected in series, thereby comprising a cell unit; . . . ; the select gate transistor STSm, the memory cell transistors MT_m1to MT_mnand the select gate transistor STDm are also connected in series, thereby comprising a cell unit.
• The source regions of the respective select gate transistors STS1 to STSm are connected with a source line SL common the source regions. Asource line driver103 which supplies voltage to the source line SL is connected to the source line SL. The following are connected to a row decoder101: a select gate line SGS common the select gate transistors STS1 to STSm; a select gate line SGD common the select gate transistors STD1 to STDm; a word line WL1 common the memory cell transistors MT₁₁, MT₂₁, . . . , MT_m1; a word line WL2 common the memory cell transistors MT₁₂, MT₂₂, . . . , MT_m2; . . . ; and a word line WLn common the memory cell transistors MT_1n, MT_2n, . . . , MTmn. Therow decoder101 obtains a row address decoded signal by decoding a row address signal, and supplies operation voltage to the word lines WL1 to WLm and the select gate lines SGS and SGD in a selective manner. Each of bit lines BL1 to BLm is connected to the drain region of each of the select gate transistors STD1 to STDm. Asense amplifier102 and acolumn decoder104 are connected to the bit lines BL1 to BLm. Thecolumn decoder104 obtains a column address decoded signal by decoding a column address signal, and selects one out of the bit lines BL1 to BLm based on the column address decoded signal. Thesense amplifier102 amplifies data which has been read from a memory cell transistor selected by therow decoder101 and thecolumn decoder104.
• Next, a description will be provided for operations of writing, erasing and reading performed by the non-volatile semiconductor memory according to the embodiment of the present invention. In an initial state (data is 1) where the memory cell transistor MT₁₁shown inFIG. 1 has not accumulated electrons in its floatinggate electrode13, a threshold voltage of the memory cell transistor MT₁₁is a negative threshold voltage Ve as shown inFIG. 5, since the memory cell transistor MT₁₁is a depletion mode memory cell transistor. To begin with, a description will be provided for an example of a writing operation with reference toFIGS. 6 and 7. Hereinafter, it is assumed that the memory cell transistor MT₁₁is selected during its writing and reading operations. The memory cell transistor MT₁₁which has been selected is referred to as a “selected memory cell transistor,” and the memory cell transistors MT₁₂to MT_1n, MT₂₁to MT_2n, . . . , and MT_m1to MT_mnwhich have not been selected are referred to as “non-selected memory cell transistors.” The bit line BL1 and the word line WL1 connected to the selected memory cell transistor MT₁₁are referred to as a “selected bit line” and a “selected word line” respectively. The bit lines BL2 to BLm and the word lines WL2 to WLn connected only to the non-selected memory cell transistors MT21 to MT2n,. . . , MTm1 and MTmn are referred to as “non-selected bit lines” and “non-selected word lines.”
• A voltage of 0 V and a power supply voltage Vcc (for example, 3V) are applied to the selected bit line BL1 and the source line SL respectively. A voltage of 0 V is applied to the select gate line SGS, thus causing the select gate transistor STS1 to be in the “off” state, thus causing the source line SL to be in the “cut-off” state. The power supply voltage Vcc (for example, 3 V) is applied to the select gate line SGD, and the select gate transistor STD1 is caused to be in the “on” state, accordingly causing 0 V in the selected bit line BL1 to be transmitted to the selected memory cell transistor MT_1n.
• A write voltage V_pgm(for example, 20 V) is applied to the selected word line WL1. An intermediate potential V_pass1(for example, 10 V) is applied to each of the non-selected word lines WL2 to WLm. The selected memory cell transistor MT₁₁and the non-selected memory cell transistors MT₁₂to MT₁₁are all caused to be in the “on” state, thus causing 0 V in the selected bit line BL1 to be transmitted.
• In the selected memory cell transistor MT₁₁, the write voltage V_pgm(for example, 20 V) is applied to thecontrol gate electrode15 shown inFIG. 1, and a high electric field is applied between thechannel region411 underneath the floatinggate electrode13 to which 0 V is transmitted from the selected bit line BL1 and the floatinggate electrode13, thus injecting electrons into the floatinggate electrode13 through thegate insulating film12. Once electrons have been accumulated in floatinggate electrode13, a threshold voltage of the selected memory cell transistor MT₁₁increases by ΔV from the negative threshold voltage Ve to a positive threshold voltage Vp, and accordingly the selected memory cell transistor MT₁₁is in the “write” state (data is 0).
• For example, the power supply voltage Vcc (for instance, 3 V) is applied to each of the non-selected bit lines BL2 to BLm. A voltage of 0 V is applied to the select gate line SGS, and thus each of the select gate transistors STS2 to STSm is in the “off” state, accordingly causing the source line SL to be in the “cut-off” state. The power supply voltage Vcc (for example, 3 V) is applied to the select gate line SGD, thus causing each of the selected gate transistors STD2 to STDm to be in the “on” state. Accordingly, voltages (for example, 3 V-Vth V), which are obtained by subtracting the threshold voltage Vth in the select gate transistors STD2 to STDm from the power supply voltages Vcc in the non-selected bit lines BL2 to BLm respectively, to be transmitted to the non-selected memory cell transistors MT₂₁to MT_2n, . . . , MT_m1to MT_mn. Since the select gate line SGS is in the “cut-off” state, electric potential differences between each of the select gate transistors STD2 to STDm and each of the source regions of the respective non-selected memory cell transistors, to which the aforementioned voltages are transmitted, are caused to be (Vcc)−(Vcc−Vth)=Vth V. Consequently, the select gate transistors SGD2 to SGDm are also in the “cut-off” state.
• When the select gate transistors SGD2 to SGDm and the select gate transistors SGS2 to SGSm are cut off, the channel regions underneath the respective non-selected memory cell transistors MT₂₁to MT_2n, . . . , MT_m1to MT_mnare in the “on” state, and the channel regions from the source line SL and the bit lines BL2 to BLm are in the “floating” state. Potentials of channel regions which have been in the “floating” state are increased (larger than, or equal to, Vcc and smaller than, equal to, Vpass, for example 7 to 8 V) by the coupling of the potentials Vpgm and Vpass.
• Since channel potentials of the non-selected memory cell transistors MT₂₁to MT_2n, . . . , MT_m1to MT_mnare increased, even if the write voltage Vpgm (for example, 20V) is applied to the non-selected memory cell transistors MT₂₁to MT_2n, . . . , MT_m1to MT_mn, differences in potential between each of the non-selected memory cell transistors MT21 to MTm1 and each of the corresponding floatinggate electrodes13 are small. Accordingly, electrons are not injected into the floatinggate electrodes13.
• Next, a description will be provided for an example of the erasing operation with reference toFIGS. 6 and 8. In the NAND flash EEPROM, data can be erased simultaneously from all the memory cell transistors in a selected block. Here, a description will be provided for an example of a simultaneous erasure of all the written data from the memory cell transistors MT₁₁to MT_1n, MT₂₁to MT_2n, . . . , MT_m1to MT_mnin thecell array100.
• An erase voltage Vera (for example, 20 V) is applied to all the bit lines BL1 to BLm and the source line SL, respectively. An initial voltage Vsgd (for example, 4 V) is applied to the select gate line SGD, so that the select gate transistor STD1 is in the “on” state. Accordingly, the erase voltage Vera (for example, 20 V) in the bit line BL1 to BLm is transmitted to the memory cell transistors MT_1n, MT_2n, . . . , MT_mn. An initial voltage Vsgs (for example, 4 V) is applied to the select gate line SGS, so that the select gate transistor STS1 is in an “on” state. Accordingly, the erase voltage Vera (for example, 20 V) in the source line SL is transmitted to the memory cell transistors MT₁₁, MT₂₁, . . . , MT_m1.
• A voltage of 0 V is applied to all the word lines WL1 to WLn. Since the memory cell transistors MT₁₁to MT_1n, MT₂₁to MT_2n, . . . , MT_m1to MT_mnare depletion mode memory cell transistors, the memory cell transistors MT₁₁to MT_1n, MT₂₁to MT_2n, . . . , MT_m1to MT_mnare in the “on” state if 0 V is applied to thecontrol gate electrodes15. When the erase voltage Vera (for example, 20 V) is applied to theSOI layer2, electrons are emitted from the floatinggate electrodes13 to the channel regions through thegate insulating film12. Once the electrons are emitted from the floatinggate electrodes13, the threshold voltage of the selected memory cell transistor MT₁₁is decreased by ΔV from a positive threshold voltage Vp to a negative threshold voltage Ve as shown inFIG. 5. Thus, the selected memory cell transistor MT₁₁will in the “erase” state (date is 1). Consequently, data are erased simultaneously from the memory cell transistors MT₁₁to MT_1n, MT₂₁to MT_2n, . . . , MT_m1to MT_mn.
• Next, a description will be provided for an example of a reading operation with reference toFIGS. 6 and 9. A pre-charged voltage V_b1(for example, 1 V) is applied to each of the bit lines BL1 to BLm, and 0 V is applied to the source line SL. The power supply voltage Vcc (for example, 3 V) is applied to the select gate line SGS, so that the select gate transistor STS1 is in the “on” state Accordingly, 0 V in the source line SL is transmitted to the memory cell transistors MT_1n, MT₂₁, . . . , MT_m1. The power supply voltage Vcc (for example, 3 V) is applied to the select gate line SGD, so that the select gate transistor STD1 is in the “on” state. Accordingly, the pre-charged voltage V_b1(for example, 1 V) in the bit lines BL1 to BLm is transmitted to the memory cell transistors MT_1n, MT_2n, . . . , MT_mn.
• A voltage V_read(for example, 4.5 V), which is higher than the power supply voltage Vcc, is applied to the non-selected word lines WL2 to WLm, so that the non-selected memory cell transistors MT₁₂to MT_1n, MT₂₁to MT_2n, and MT_m1to MT_mnare in the “on” state. Accordingly, the non-selected memory cell transistors MT₁₂to MT_1n, MT₂₁to MT_2n, and MT_m1to MT_mnserve as transfer transistors. A voltage of 0 V is applied to the selected word line WL1. In the memory cell transistor MT₁₁, 0 V is applied to thecontrol gate electrode15 as shown inFIGS. 10 and 11. In a case where electrons have not been accumulated in the floatinggate electrode13 as shown inFIG. 10, the threshold voltage Ve of the selected memory cell transistor MT₁₁is less than 0 V as shown inFIG. 5. For this reason, even if the voltage applied to thecontrol gate electrode15 is 0 V, the selected memory cell transistor MT₁₁is in the “on” state, and accordingly channel current flows. On the other hand, when electrons have accumulated in the floatinggate electrode13 as shown inFIG. 11, the threshold voltage Vp of the selected memory cell transistor MT₁₁is higher than 0 V as shown inFIG. 5. A depletion layer A of thechannel region411 underneath the floatinggate electrode13 spreads as shown inFIG. 11. Accordingly, the memory cell transistor MT₁₁is in the “off” state. Thus, the channel current does not flow. If the channel current flows into the selected memory cell transistor MT₁₁, it is judged on determined that the selected memory cell transistor MT₁₁is in the “erase” state (data is “1”). If the channel current does not flow into the selected memory cell transistor MT₁₁, it is judged on determined that the selected memory cell transistor MT₁₁is in the “write” state (data is “0”).
• FIG. 41 shows a comparative example of enhancement memory cell transistors MT₁₁₁to MT_11n. Each of the memory cell transistors MT₁₁₁to MT11nincludes an n⁺-source and drainregion104 which are provided on a p-semiconductor substrate111, and a floatinggate electrode113 and acontrol gate electrode115 which are provided above a channel region between the source and drainregions104. As each of the memory cell transistors MT111 to MT11nas the enhancement transistor has been minaturized, the width W of the channel region between the source and drainregions104 has become so narrow that the influence of the short channel effect has increased. On the contrary, the channel region is depleted in a state whrere electrons have been accumulated in the floatinggate electrode13, thereby enabling the short channel effect to be reduced. This is because the memory cell transistors MT₁₁to MT_1nare depletion mode transistors having the source and drainregions421 to42(n+1) and thechannel regions411 to41n.
• In addition, in a case where electrons have accumulated in the floatinggate electrode13 of the selected memory cell transistor MT₁₁as shown inFIG. 11, when 0 V is applied to thecontrol gate electrode15 during a reading operation, thechannel region411 is depleted, thus enabling the selected memory cell transistor MT₁₁to be fully in the “off” state. The thinner theSOI layer2 is, the easier for the memory cell transistors MT11 to MT1nto be in the “off” state. For this reason, it is preferable that theSOI layer2 may have a thickness of approximately 30 nm to 40 nm, and it is more preferable that theSOI layer2 may have a thickness of approximately 30 nm to 35 nm.
• Furthermore, in the NAND flash EEPROM to which the SOI technology is adapted, a voltage of the same polarity is applied during operations of writing, erasing and reading as shown inFIG. 6, thereby the operations can be performed in common with the NAND flash EEPROM to which the SOI technology is not adapted. Consequently, the timing adjustment is easier, and the area of the peripheral circuit portion can be reduced, in comparison with a case where operation voltages of the two polarities, positive and negative, are applied.
• Moreover, it is easier to cut off the source line SL and the bit line BL1, since the selectgate transistors STS1 and STD1, shown inFIG. 1, connected in series in the column direction with the memory cell transistors MT₁₁to MT_1nare enhancement transistors.
• Additionally, in the comparative example, influence of a capacitance C_ch-subbetween thechannel region104 and thesemiconductor substrate111 is large as shown inFIG. 42. On the other hand, the capacitance of theSOI layer2 can be reduced because of the SOI structure in which theSOI layer2 is formed on theSOI insulator1 as shown inFIG. 1. In addition, the memory cell transistors MT111 and MT121 of the comparative case are isolated from one another in the row direction by element isolation regions (STI)106, respectively, as shown inFIG. 42, and a parasitic capacitance C_stiis generated between the element isolation regions (STI)106. On the other hand, the memory cell transistors MT₁₁and MT₂₁in the row direction are completely isolated from each other by the elementisolation insulating film6 as shown inFIG. 3. Consequently, parasitic capacitance C_stiinfluence between the element isolation regions (STI)106 shown inFIG. 42 can be reduced. Accordingly, punch-through immunity, field inversion breakdown voltage and the like do not have to be considered. For this reason, the widths Ws of the respective elementisolation insulating films6 in the row direction shown inFIG. 3 can be set at a minimum width for allowing lithographic and etching techniques.
• The peripheral circuit (MOS transistor), which is not illustrated, for driving the memory cell transistors MT₁₁to MT_1n, MT₂₁to MT_2n, . . . , MTm1 to MTmn can also be formed on theSOI layer2 provided in theSOI insulator1. With regard to an n-channel MOS transistor used for a CMOS circuit, a p-type impurity diffusion layer and an n-type impurity diffusion layer may be used, in common with the select gate transistor. With regard to a p-channel MOS transistor used for the CMOS circuit, an n-type impurity diffusion layer and a p-type impurity diffusion layer may be used.
• Next, a description will be provided for an example of a method for fabricating the non-volatile semiconductor memory according to the present embodiment. Here,FIGS. 12A, 13A, and23A show a fabrication cross-sectional process flow of thecell array100 shown inFIG. 2 in the column direction taken along the III-III line. In addition,FIGS. 12B, 13B, . . . , and23B show a fabrication cross-sectional process flow of thecell array100 in the row direction taken along the II-II line.
• As shown inFIGS. 12A and 12B, theSOI layer2 having a first conductivity type provided on theSOI insulator1 is prepared. As a technique for providing theSOI layer2 on theSOI insulator1, the SIMOX technique, the wafer bonding technique and the like can be used. According to the SIMOX technique, oxygen ions (O⁺) are implanted into a silicon (Si) substrate, which is not illustrated, and then the silicon substrate is thermally treated. Thereby, theSOI insulator1 is formed in the Si substrate, and theSOI layer2 is formed on theSOI insulator1. According to the wafer bonding technique, theSOI insulator1 is formed on one of the two wafers. Then, the two wafers are bonded, and are thermally treated. Subsequently, one of the two wafers is made into a thin film through planarization, thereby forming theSOI layer2.
• A resist film is coated on theSOI layer2, and the resist film is patterned by the lithographic technique. As shown inFIGS. 13A and 13B, ions having p-type impurity such as boron (¹¹B⁺) are implanted with the patterned resistfilm21 used as a mask. Residual resistfilm21 is removed by use of resist remover or the like. A resist film is coated on theSOI layer2, and then the resist film is patterned with the lithographic technique. Subsequently, as shown inFIGS. 14A and 14B, ions having n-type impurity, such as phosphorus (³¹P⁺) and arsenic (⁷⁵As⁺), are implanted with the patterned resistfilm22 used as a mask. When deemed necessary, a resist film is also coated on the region surrounding thecell array100, where the peripheral circuit is to be formed, and the coated resist film is patterned. Then, if necessary, ions are implanted.
• As shown inFIGS. 15A and 15B, a gate insulating film (tunnel oxidation film)12 such as a SiO₂film is formed by use of the thermal oxidation method so that the thickness of the gate insulating film is approximately 1 nm to 15 nm. A p-doped first polysilicon layer (floating gate electrode)13x,which is going to be a floating gate electrode, is deposited on thegate insulating film12 by reduced pressurized CVD so that the thickness of the first polysilicon layer may be 10 nm to 200 nm. Subsequently, amask material5 such as a Si₃N₄film is deposited on thefirst polysilicon layer13xby CVD so that the thickness of the mask material may be approximately 50 nm to 200 nm.
• A resist film is spin-coated on themask material5, and an etching mask of the resist film is formed by the lithographic technique. Parts of themask material5 are removed in a selective manner by the reactive ion etching (RIE) in which an etching mask is used. After etching, the resist film is removed. With themask material5 used as a mask, parts of thefirst polysilicon layer13x,thegate insulating film12 and theSOI layer2 are removed in the column direction in a selective manner until theSOI insulating layer1 underneath the parts is exposed. As a result,groove portions7 are formed which penetrate through thefirst polysilicon layer13x,thegate insulating film12 and theSOI layer2, as shown inFIGS. 16A and 16B. AlthoughFIG. 16B shows that parts of theSOI insulating layer1 are removed, theSOI insulating layer1 may remain planar.
• As shown inFIGS. 17A and 17B, an elementisolation insulating film6 is embedded in thegroove portions7 shown inFIG. 16B by CVD or the like so that the thickness of the elementisolation insulating film6 is approximately 200 nm to 1,500 nm. As shown inFIGS. 18A and 18B, the elementisolation insulating film6 is etched back by use of chemical-mechanical polishing (CMP) so that the elementisolation insulating film6 may be planarized. The upper surfaces of the elementisolation insulating films6 are situated in positions higher than the upper surfaces of thegate insulating films12. As a result, the elements of the memory cell transistors MT₁₁to MT₂₁in the row direction are completely isolated from one another.
• As shown inFIGS. 19A and 19B, an inter-electrodeinsulating film14 is deposited on the tops of the first polysilicn layers13xand the tops of the elementisolation insulating films6 by CVD or the like. A resistfilm23 is coated on the inter-electrode insulatingfilm14, and the resistfilm23 is patterned by the lithographic technique. As shown inFIGS. 20A and 20B, openingportions8 are formed in a part of the inter-electrode insulatingfilm14 with the patterned resistfilm23 used as a mask by RIE or the like. As shown inFIGS. 21A and 21B, a p-doped second polysilicon layer (control gate electrode)15x,which will be a control gate electrode, is deposited on the inter-electrode insulatingfilm14 by CVD so that the thickness of thesecond polysilicon layer15xis approximately 10 nm to 200 nm.
• A resistfilm24 is coated on thesecond polysilicon layer15x,and the resistfilm24 is patterned by the lithographic technique. As shown inFIGS. 22A and 22B, parts of thesecond polysilicon layer15x,the inter-electrode insulatinglayer14, and thefirst polysilicon layer13xare removed in the row direction with the patterned resistfilm24 used as a mask by RIE in a selective manner until thegate insulating film12 underneath the parts is exposed. As a result, grooves are formed which penetrate through thesecond polysislicon layer15x,the inter-electrode insulatingfilm14 and thefirst polysilicon layer13x.The resistfilm24 is removed by a resist remover and the like.
• Ions of³¹P⁺ or⁷⁵As⁺ are implanted through thegate insulating films12 in a self-aligned manner with thesecond polysilicon layer15xused as a mask. Subsequently, n-type impurity ions of the first polysilicon layers13xand the second polysilison layers15xare activated by thermal treatment. Thereby, the floatinggate electrodes13 and thecontrol gate electrodes15 are formed. As shown inFIGS. 23A and 23B, p-type impurity ions and n-type impurity ions in theSOI layer2 are activated. Accordingly, n⁺-type impurity diffusion layers (source and drain regions)421 and422 are formed in theSOI layer2 positioned at the bottom of grooves as shown inFIG. 1, and an n⁻-type impurity diffusion layer (channel region)411 is formed in theSOI layer2 underneath thefirst polysilicon layer13x.Consequently, the depletion mode memory cell transistor MT₁₁is formed. Similarly, n⁺-type impurity diffusion layers (source and drain regions)423 to42(n+1) are formed in theSOI layer2 positioned at the bottom of the grooves as shown inFIG. 1, and n⁻-type impurity diffusion layers (channel regions)412 to41nare formed in theSOI layer2 underneath thefirst polysilicon layer13x.Consequently, the memory cell transistors, illustration omitted, are crossed in the column direction and in the row direction and the memory cell transistors are formed in a matrix.
• Simultaneously, theselect gate electrodes13aand15aare formed as shown inFIGS. 23A and 23B. A p-type impurity diffusion layer (channel region)42 is formed in theSOI layer2, and an n⁺-type impurity diffusion layer (source region)43 is formed. Thereby, an enhancement mode select gate transistor STS1 is formed. Theselect gate electrodes13band15bshown inFIG. 1 are formed, and the p-impurity diffusion layer (channel region)44 and the n⁺-type impurity diffusion layer (drain region)45 are formed. Thereby, the enhancement mode select gate transistor STD1 is also formed. Subsequently, predetermined interconnects and insulating films are formed or deposited, thereby completing the non-volatile semiconductor memory shown inFIG. 1.
• In accordance with the method for fabricating the semiconductor storage device according to the embodiment shown inFIGS. 12A to23B, the non-volatile semiconductor memory shown inFIG. 1 can be provided. Since the element isolation region (STI)6 as shown inFIG. 1 does not have to be embedded, a minaturized process can be performed with ease. Note that the method for fabricating the non-volatile semiconductor memory shown inFIG. 12A toFIG. 23B is an example. It is possible to provide the non-volatile semiconductor memory by other various methods.
• (First Modification)
• In a first modification of the present invention, with regard to the memory cell transistor MT₁₁shown inFIG. 1, n⁺-source and drainregions421 and422 may be extended to parts of anSOI layer2 underneath a floatinggate electrode13 as shown inFIG. 24.
• In a case where theSOI layer2 underneath the floatinggate electrode13 is comprised of only ann channel region411 as shown inFIG. 1, if the voltage in acontrol gate electrode15 is 0 V for an erasing operation in a state whrere electrons have accumulated in the floatinggate electrode13, the erasing operation is retarded due to formation of a depletion layer in the n⁻ channel region411.
• By contrast, according to the first modification, the n⁺-source and drainregions421 and422 are provided in theSOI layer2 underneath the floatinggate electrode13 as shown inFIG. 24, thereby the n⁺-source and drainregions421 and422 are not easily depleted. Accordingly, electrons are easily extracted between the floatinggate electrode13 and each of the n⁺-source and drainregions421 and422. For this reason, it is possible to speed up the erasing operation. Ann channel region411 is provided in the middle of theSOI layer2 underneath the floatinggate electrode13. Because of this, during the reading operation, the n⁻ channel region411 underneath the floatinggate electrode13 is depleted as shown inFIG. 25, accordingly forming a depletion layer A′. Thus, channel current can be fully off.
• In according with the method for fabricating the non-volatile semiconductor memory according to the first modification, during the source and drain diffusion, the source and drainregions421 and422 may be formed by forming then channel region411 in the middle of theSOI layer2 underneath the floatinggate electrode13 and by diffusing an n-type impurity as far as parts of theSOI layer2 underneath the floatinggate electrode13.
• (Second Modification)
• In a method for fabricating a non-volatile semiconductor memory according to a second modification, only p-type impurity ions are implanted in the entire surface of anSOI layer2, instead of implanting p-type impurity ions and n-type impurity ions into theSOI layer2 in a selective manner as shown inFIGS. 13A to14B. Subsequently, a series of steps shown inFIGS. 15A to22B are performed in substantially the same manner.
• Then, as shown inFIG. 26, n-type impurity ions are implanted in a self-aligned manner with asecond polysilicon layer15xused as a mask, and a thermal treatment is performed. As a result, n-type impurity ions in theSOI layer2 are activated, and hence n⁺-source and drainregions421 and422 as well as asource region43 are formed as shown inFIG. 27. In addition, the n-type impurity ions diffuse, and ann channel region411 is formed in theSOI layer2 underneath a floatinggate electrode13. In the same way, n⁺-source and drainregions423 to42(n+1) as well as n-channel regions412 to41nshown inFIG. 1 are formed. The n-type impurity ions diffuse, and hence each of the source and drainregion421 and thesource region43 is expanded by a length Ln into theSOI layer2 underneathselect gate electrodes13aand15a.On this point, a length Lw1 of acontrol gate electrode15 in a memory cell transistor MT₁₁may be shorter than a length 2Ln aggregating the length Ln of the expansion of the source and drainregion421 and the length Ln of the expanded thesource region43. A length Lsg of each of theselect gate electrodes13aand15amay be set longer than the length 2Ln aggregating the length Ln of the expanded the source and drainregion421 and the length Ln of the expanded thesource region43.
• As shown inFIG. 13A, it is difficult to implant p-type impurity ions into parts of theSOI layer2, on which a select gate transistor STS1 is formed, the length of which is denoted by Lp. By contrast, according to the second modification, ions are implanted in a self-aligned manner with thesecond polysilicon layer15xas a mask, and a thermal treatment is performed, as shown inFIG. 27. Hence, a measurement margin equal to the length 2Ln can be achieved while a channel length Lp of a p channel region is formed, anda p channel region42 underneath theselect gate electrodes13aand15acan be easily formed.
• Note that it is possible to formp channel region44 underneath theselect gate electrode13b,15bof the select gate transistors SGD1 shown inFIG. 1 easily in the same way. Since other steps are substantially the same as the steps shown inFIGS. 12A to23B, repeated explanation is omitted.
• (Third Modification)
• A non-volatile semiconductor memory according to a third modification is different from the non-volatile semiconductor memory shown inFIG. 1 in that asemiconductor substrate30 is arranged under anSOI insulator1xas shown inFIG. 28. A convexcell array portion30xis provided in thesemiconductor substrate30, and is connected with asource region43 through afirst opening portion32 provided in theSOI insulator1x.Asource line contact18 is arranged over the convexcell array portion30xwith thesource region43 interposed between thesource line contact18 and the convexcell array portion30x.
• As shown inFIG. 29, a peripheral circuit (MIS transistor) Tp is arranged in the outer periphery of the cell array. The peripheral circuit Tp is formed by using as an active layer a peripheralconvex portion30yof thesemiconductor substrate30 in contact with the peripheral circuit, through asecond opening portion33 provided in theSOI insulator1x.Impurity diffusion layers31aand31bare provided in the peripheralconvex portion30yof thesemiconductor substrate30.Gate electrodes13cand15care arranged over a channel region between the impurity diffusion layers31aand31bwith agate insulating film12 interposed between thegate electrode13cand the channel region. The peripheral circuit Tp is isolated from an adjacent element, illustration is omitted, by theSOI insulator1x.According to the third modification, the peripheral circuit Tp can be arranged, as it is, on thepresent semiconductor substrate30, instead of being formed on theSOI insulator1 employing the SOI technology.
• Next, a description will be provided for a method for fabricating a non-volatile semiconductor memory according to the third modification shown inFIGS. 28 and 29, along with the cell array portion shown inFIGS. 30A, 31A, . . . ,34A and the peripheral circuit portion shown inFIGS. 30B, 31B, . . . ,34B.
• As shown inFIGS. 30A and 30B, thesemiconductor substrate30 is prepared. A resist film is coated on thesemiconductor substrate30, and the resist film is patterned by the lithographic technique. With the patterned resist film used as a mask, parts of thesemiconductor substrate30 are removed in a selective manner by RIE or the like. As a result, the convexcell array portion30xand the peripheralconvex portion30y,which are at substantially the same horizontal level, are formed as shown inFIG. 28.
• By CVD or the like, theSOI insulator1xis deposited on thesemiconductor substrate30, as shown inFIG. 32A andFIG. 32B. As shown in33A and33B, theSOI insulator1xis etched back and planarized by CMP and the like, until the convexcell array portion30xand the peripheralconvex portion30yare exposed.
• As shown inFIGS. 34A and 34B, theSOI layer2 is deposited on theSOI insulator1xby CVD and the like. As shown inFIG. 28, thesource line contact18 is formed over the convexcell array portion30xof thesemiconductor substrate30 with theSOI layer2 interposed between thesource line contact18 and the convexcell array portion30x.Moreover, as shown inFIG. 29, the peripheral circuit Tp is formed in the peripheralconvex portion30yof thesemiconductor substrate30. The other steps are substantially the same as the series of steps shown inFIGS. 13A toFIG. 23B. For this reason, a description will be omitted for the common steps.
• When the CMP shown inFIGS. 33A and 33B is performed, if there is a planar surface which is larger than a certain area, it is difficult to control the flatness during the CMP. According to the third modification, it is easy to control the flatness by CMP, since the convexcell array portion30xis exposed in parts of theplanar SOI insulator1xas shown inFIG. 33A in the cell array section.
• The peripheral circuit Tpx may be arranged in theSOI layer2 on thesemiconductor substrate30, as shown inFIG. 35. An element of the peripheral circuit Tpx is isolated by an element isolation region (STI)31 from an element, illustration omitted, and which is adjacent the element of the peripheral circuit Tpx. The peripheral circuit Tpx can be provided by selectively removing parts of theSOI layer2 and by embedding the element isolation region (STI)31.
• (Fourth Modification)
• As shown inFIG. 36, a non-volatile semiconductor memory according to a fourth modification of the present invention may have a two-transistor cell structure which is an expansion of a planar pattern structure of a one-transistor cell structure shown inFIG. 2. The non-volatile semiconductor memory shown inFIG. 36 comprises acell array100x,acolumn decoder104, asense amplifier102, afirst row decoder101x,asecond row decoder101yand asource line driver103.
• Thecell array100xcomprises a plurality ((m+1)×(n+1); m and n are integers) of memory cells MC₀₀to MC_mn. Each of the memory cells MC includes a memory cell transistor MT and a select transistor ST. In each of the cell transistor and the select transistor a current pathway is connected in series. The memory cell transistor MT comprises a stacked gate structure including: a floating gate electrode formed above a semiconductor substrate with a gate insulating film interposed between the floating gate electrode and the semiconductor substrate; and a control gate electrode formed above the floating gate electrode with an inter-electrode insulating film interposed between the control gate electrode and the floating gate electrode. A source region of the memory cell transistor MT is connected to a drain region of the select transistor ST. Each of two memory cells MC adjacent to each other in the column direction share the source region of the select transistor ST or the drain region of the memory cell transistor MT.
• The control gate electrodes of the respective memory cell transistors MT of the respective memory cells MC in the same row are commonly connected to one of word lines WL0 to WLm. The gates of the respective select transistors ST of the respective memory cells in the same row are connected to any one of select gate lines SG0 to SGm. The drain regions of the respective memory cell transistors MT of the respective memory cells MC in the same row are commonly connected to one of bit lines BL0 to BLn. The sources of the respective select transistors ST of the respective memory cells MC are commonly connected to a source line SL, and the source line SL is connected to asource line driver103.
• Thecolumn decoder104 decodes a column address signal, thereby obtaining a column address decoded signal. One of the bit lines BL0 to BLn is selected on a basis of the column address decoded signal. The first andsecond row decoders101xand101ydecode a row address signal, thereby obtaining a row address decoded signal. Thefirst row decoder101xselects one of the word lines WL0 to WLn when writing is initiated. Thesecond row decoder101yselects one of the select gate lines SG0 to SGm when reading is initiated. Thesense amplifier102 amplifies data which have been read out from a memory cell selected by thesecond row decoder101yand thecolumn decoder104. Thesource line driver103 supplies voltage to the source line SL during reading.
• According to the fourth modification, the non-volatile semiconductor memory is designed to comprise the two-transistor cell structure, so that the memory cell MC is positively cut off, and thus enabling a readers operation to be performed. In addition, a three-transistor cell structure in which a select transistor ST is connected to both a source region and a drain region for each of the memory cell transistors MT can be easily expanded from the planar pattern shown inFIG. 2.
• (Fifth Modification)
• As a fifth modification of the present invention, a description will be provided for aflash memory system142, which is an applied example of the non-volatile semiconductor memory shown inFIG. 1, with reference toFIG. 37. Theflash memory system142 comprises ahost platform144 and a universal serial bus (USB)flash device146. Thehost platform144 is connected to theUSB flash device146 through a USB cable148. Thehost platform144 is connected to the USB cable148 through aUSB host connector150, and theUSB flash device146 is connected to the USB cable148 through a USBflash device connector152. Thehost platform144 comprises aUSB host controller154 for controlling packet transfer on the USB.
• TheUSB flash device146 includes: a USBflash device controller156 for controlling other elements in theUSB flash device146, and for controlling an interface to the USB bus of theUSB flash device146; a USBflash device connector152; and at least oneflash memory module158 including a non-volatile semiconductor memory according to an embodiment of the present invention.
• Once theUSB flash device146 is connected to thehost platform144, a standard USB listing process is started. At this point, thehot platform114 recognizes theUSB flash device146, and selects a mode of communications with theUSB flash device146. Then, thehost platform114 transmits data to, and receives data from, theUSB flash device146 through an FIFO buffer, termed as an endpoint, for storing transmitted data. Thehost platform144 recognizes changes in physical, electrical conditions such as disconnection and connection of theUSB flash device146 and the like through the endpoint. In addition, if there is a packet to be received, thehost platform144 receives it.
• Thehost platform144 requests a service from theUSB flash device146 by transmitting a request packet to theUSB host controller154. TheUSB host controller154 transmits a packet on the USB cable148. If theUSB flash device146 has an endpoint which receives this request packet, the requests are received by the USBflash device controller156.
• The USBflash device controller156 performs various operations such as reading data from theflash memory module158, writing data to theflash memory module158, erasing data and the like. In addition, the USBflash device controller156 supports basic USB functions such as the acquisition of a USB address and the like. The USBflash device controller156 controls theflash memory module158 through acontrol line160 for controlling output from theflash memory module158, or, for example, through a read/write signal and various other signals such as a chip enable signal and the like. Theflash memory module158 is also connected to the USBflash device controller156 through anaddress data bus162. Theaddress data bus12 transfers a read command, a write command and an erase command as well as an address and data in theflash memory module158.
• In order to inform thehost platform144 of a result and the state of various operations requested by thehost platform144, theUSB flash device146 transmits a state packet by use of a state endpoint (endpoint0). At this point, thehost platform144 checks whether or not there is a state packet, and theSB flash device146 returns an empty packet or the state packet if there is no new packet of a state message.
• According to the fifth modification, various functions of theUSB flash device146 can be achieved. By eliminating the USB cable148, the connectors may be connected directly.
• (Sixth Modification)
• As show inFIG. 38 andFIG. 39, a non-volatile semiconductor memory according to a sixth modification of the present invention is -three-dimensionally integrated by stacking SOI structures. Theinter-layer dielectric3 is disposed on elements such as the memory cell transistors MT₁₁to MT_1n, the select gate transistors STD1 and STS1, and the like. Theinter-layer dielectric3 is used for insulation material of an upper layer of the SOI structure. Memory cell transistors MT₁₁₁to MT_11nare depletion mode MIS transistors including: n⁺ source and drainregions521 to52 (n+1) which are arranged on the inter-layer dielectric (SOI insulator)3, and which are opposite to each other;n channel regions511 to51n,each of which is interposed between each adjacent pair of the source and drainregions521 to52(n+1), and whose impurity concentrations are lower than those of the source and drainregions521 to52(n+1) ; floatinggate electrodes63 which are insulated, and each of which is arranged above each of thechannel regions511 to51n;andcontrol gate electrodes65 which are insulated, each of which is arranged above each of the floatinggate electrodes63.
• Each of two select gate transistors STS11 and STD11 is arranged in, and adjacent to, each end of the column direction of the memory cell transistors MT₁₁₁to MT_11n. The select gate transistor STS11 is an enhancement MIS transistor including: an n⁺ drain region521 which is a region common asource region521 of the memory cell transistor MT₁₁₁positioned at one end of the arrangement in the column direction;p channel region52 arranged so as to be adjacent to thedrain region521; ann source region53 arranged so as to be adjacent to thechannel region52;select gate electrodes63aand65aarranged above thechannel region52 with thegate insulating film62 interposed between thechannel region52 and the set ofselect gate electrodes63aand65a.
• Alternatively, the select gate transistor STD11 is an enhancement MIS transistor including: an n⁺ source region52(n+1) which is common a drain region52(n+1) of the memory cell transistor MT_11npositioned at another end of the arrangement in the column direction;a p channel region54 arranged so as to be adjacent to the source region52(n+1) ; an n⁺ drain region55 arranged so as to be adjacent to thechannel region54;select gate electrodes63band65barranged above thechannel region54 with thegate insulating film62 interposed between thechannel region54 and the set ofselect gate electrodes63band65b.
• Abit line contact171 is arranged on thedrain region55 so that thebit line contact171 is adjacent to the select gate transistor STD11. Asource line contact181 is arranged on thesource region53 so that thesource line contact181 is adjacent to the select gate transistor STS11. Thebit line contact171 and thesource line contact181 are insulated at the periphery by theinter-layer dielectric3, the insulatingfilm7 on theinter-layer dielectric3, and theinter-layer dielectric4 on the insulatingfilm7.
• As shown inFIG. 39, theword line contacts91 and92, which are different from each other, are disposed in upper and lower layers, respectively. Theelement isolation region8 isolates the memory cell transistors MT₁₁₁and MT₁₂₁. Anelement insulation region4 is disposed on elements such as the memory cell transistors MT₁₁₁to MT_11nand the select gate transistors STS11 and STD11, and the like.
• According to the sixth embodiment of the present invention, it is possible to integrate three-dimensionally by stacking SOI structures. Note that as shown inFIG. 40, thebit line contact17 and thesource line contact18 may be commonly disposed from the lower layer to the upper layer. In this case, as shown inFIG. 39, theword line contacts91 and92 are disposed in the upper layer and lower layer, respectively. Furthermore, the memory cell transistors MT₁₁₁to MT_11nare described as depletion transistors, however the memory cell transistors MT₁₁₁to MT_11nmay be enhancement transistors. The structure is described in which two layers of SOI structures are stacked, SOI structure having a plurality of layers, which may be more than three layers, may be provided.
• In the method for fabricating the non-volatile semiconductor memory according to the sixth embodiment of the present invention, after forming the memory cell transistors MT₁₁to MT_1nand the select gate transistors STD1 and STS1, theinter-layer dielectric3 is formed by CVD or the like in order to cover the memory cell transistors MT₁₁to MT_1nand the select gate transistors STD1 and STS1. Thereafter, the same procedure as other modifications may be used for forming the memory cell transistors MT₁₁to MT_1nand the select gate transistors STD1 and STS1, the memory cell transistors MT₁₁₁to MT_11nand the select gate transistors STD11 and STS11 on theinter-layer dielectric3.
Other Embodiments
• In the embodiment, m×n memory cell transistors MT₁₁to MT_1n, MT₂₁to MT_2n, . . . , MT_m1to MT_mnare explained. However, actually a cell array may be comprised by more plurality of memory cell transistors, memory cells and blocks.
• Furthermore, in the embodiment, a biary NAND EEPROM is described. However, it is possible to adapt a multi-level storage, for example, three-level or more storage in the NAND EEPROM. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

Claims (20)

1. A non-volatile semiconductor memory comprising memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.

2. The non-volatile semiconductor memory ofclaim 1, further comprising an enhancement mode select gate transistor connected to a source region of one of the memory cell transistors at one end of an array of the memory cell transistors arranded in a column direction of the matrix.

3. The non-volatile semiconductor memory ofclaim 1, further comprising an enhancement mode select gate transistor connected to a drain region of one of the memory cell transistors at one end of an array of the memory cell transistors arranded in a column direction of the matrix.

4. A non-volatile semiconductor memory having a plurality of memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor comprising:

source and drain regions having a first conductivity type disposed on an insulating layer;

a channel region having the first conductivity type disposed between the source and drain regions, and having a lower impurity concentration than the source and drain regions;

a floating gate electrode disposed above the channel region and insulated from the channel region; and

a control gate electrode disposed above the floating gate electrode and insulated from the floating electrode.

5. The non-volatile semiconductor memory ofclaim 4, wherein a plurality of the source regions, the channel regions and the drain regions are extended in a column direction on the matrix so as to implement an array of memory cell transistors, sharing each of the drain regions with one of the source regions in a pair of the memory cell transistors adjacent to each other in the array, and the source regions, the channel regions and the drain regions arranged in a subject column are isolated respectively from the source regions, the channel regions and the drain regions of the memory cell transistors arranged in a column adjacent to the subject column.

6. The non-volatile semiconductor memory ofclaim 4, further comprising a semiconductor substrate disposed under the insulating layer.

7. The non-volatile semiconductor memory ofclaim 4, further comprising a select gate transistor comprising:

a second drain region having the first conductivity type common to a source region of one of the memory cell transistors at one end of the memory cell transistors arranged in a column direction of the matrix so as to implement an array;

a channel region having a second conductivity type adjacent to the second drain region;

a second source region having the first conductivity type adjacent to the second channel region; and

a select gate electrode disposed above the second conductivity type channel region and insulated from the second channel region.

8. The non-volatile semiconductor memory ofclaim 7, further comprising a source line contact being contacted with the second source region.

9. The non-volatile semiconductor memory ofclaim 4, further comprising a select gate transistor comprising:

a second source region having the first conductivity type common to a drain region of one of the memory cell transistors at one end of the memory cell transistors arranged in column direction of the matrix so as to implement an array;

a second channel region having a second conductivity type adjacent to the second drain region;

a second drain region having the first conductivity type adjacent to the second channel region; and

a select gate electrode disposed above the second channel region and insulated from the second channel region.

10. The non-volatile semiconductor memory ofclaim 9, further comprising a bit line contact being contacted with the second drain region.

11. The non-volatile semiconductor memory ofclaim 5, further comprising an element isolation insulating film isolating a plurality of the source regions, the channel regions and the drain regions from each other in respective column direction.

12. The non-volatile semiconductor memory ofclaim 6, further comprising a peripheral circuit disposed on the semiconductor substrate outside of a cell array comprising the memory cell transistors.

13. The non-volatile semiconductor memory ofclaim 6, wherein the semiconductor substrate comprises a peripheral convex portion contacting the peripheral circuit through an opening disposed in the insulating layer.

14. The non-volatile semiconductor memory ofclaim 8, wherein the semiconductor substrate comprises a convex cell array portion contacting with the second source region through an opening disposed in the insulating layer.

15. A method for fabricating a non-volatile semiconductor memory comprising, forming a depletion mode memory cell transistor, comprising:

depositing a gate insulating film on a semiconductor layer having a first conductivity type disposed on an insulating layer;

depositing a floating gate electrode on the gate insulating film;

depositing an inter-electrode insulating film on the floating gate electrode;

depositing a control gate electrode on the inter-electrode insulating film;

forming a groove penetrating the control gate electrode, the inter-electrode insulating film and the floating gate electrode; and

forming source and drain regions having the first conductivity type in the semiconductor layer under the groove.

16. The method ofclaim 15, further comprising forming enhancement mode select gate transistor, comprising:

forming an impurity diffusion having a second conductivity type layer in the semiconductor layer;

forming a select gate electrode on the impurity diffusion layer through the gate insulating film; and

forming second source and drain regions having the first type conductivity type in the impurity diffusion layer using the select gate electrode as a mask in a self-aligned manner.

17. The method ofclaim 15, further comprising:

forming a peripheral convex portion from a part of the semiconductor substrate by removing a part of the semiconductor substrate selectively, before forming the semiconductor layer; and

removing a part of the insulating layer so as to expose the peripheral convex portion.

18. The method ofclaim 17, wherein forming the semiconductor layer comprises depositing the semiconductor layer on the insulating layer and the peripheral convex portion.

19. The method ofclaim 18, further comprising:

removing a part of the semiconductor layer so as to expose the peripheral convex portion; and

forming a peripheral circuit on the peripheral convex portion.

20. The method ofclaim 18, further comprising:

forming a convex cell array portion from a part of the semiconductor substrate by removing a part of the semiconductor substrate selectively, before forming the semiconductor layer;

removing a part of the insulating layer so as to expose the convex cell array portion; and

forming a source line contact on the semiconductor layer directly above the convex cell array portion.

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