US20060003255A1 - Methods for optimizing physical characteristics of selectively consolidatable materials - Google Patents

Abstract

Methods for optimizing physical properties of selectively consolidatable materials, such as photoimageable materials, include mixing filler materials with the selectively consolidatable materials. The resulting compound has the desired physical property, as well as selective consolidatability. Examples of physical properties that may optimized in a selectively consolidatable compound by mixing a filler material with a selectively consolidatable material include, without limitation, coefficient of thermal expansion, rigidity, fracture toughness, thermal stability, and strength.

Description

CROSS-REFERENCE TO RELATED APPLICATION
• This application is a divisional of application Ser. No. 10/666,742, filed Sep. 19, 2003, pending.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to structures for supporting semiconductor substrates during and following thinning thereof. More specifically, the present invention relates to support structures that are configured to entirely cover at least the outer peripheral portions of the active surfaces of semiconductor substrates to impart the semiconductor substrates with some rigidity following thinning thereof.
• 2. Background of Related Art
• Since its inception, the trend in electronics has been to develop devices of ever-decreasing dimensions and ever-increasing capabilities. In order to drive these trends, semiconductor device manufacturers continually develop new technologies to put more processing power, more memory, and more ancillary finctionality into the same or smaller amounts of space.
• One of the approaches that has been taken for reducing the size of semiconductor device packages or for facilitating the incorporation of more semiconductor dice into packages of a standard size has been to reduce sizes of the various package features, including the wire bond heights, the thicknesses of adhesive layers, the thickness of packaging material which covers the package components, and the thicknesses of the semiconductor dice themselves.
• The thicknesses of semiconductor dice may be reduced prior to singulation thereof from a semiconductor substrate, typically in the form of a silicon wafer, by reducing the thickness of the entire semiconductor substrate. This is typically done by so-called “backgrinding” processes, which include mechanical or chemical removal of material from the back side of the semiconductor substrate and, thus, from the devices, or dice, that have been fabricated on the opposite, active surface thereof.
• State-of-the-art backgrinding processes are useful for reducing the thicknesses of 200 mm diameter silicon wafers, which are typically about 728 μm thick, and 300 mm diameter wafers, which are typically about 800 μm thick, to as thin as about 50 μm. When the thickness of a semiconductor substrate is reduced, however, the semiconductor substrate becomes less robust. For example, when the thickness of a 200 mm diameter silicon wafer is reduced to about 230 μm or less, it becomes pliable and is prone to sagging when positioned on an edge or when an edge thereof is handled. As a consequence of the reduced robustness of thinned semiconductor substrates, the semiconductor devices that have been fabricated thereon are more likely to be damaged when thinned semiconductor substrates are handled or packaged.
• Moreover, when semiconductor substrates are thinned, they are typically secured, in active surface-down orientation, to a carrier, such as a vacuum chuck. While the semiconductor substrate may be adequately secured to the carrier, the active surface of the semiconductor substrate may not be completely sealed from chemical backgrinding/polishing agents or particles of removed material. Thus, material may be removed from the active surface of the semiconductor substrate or the active surface may become undesirably contaminated.
• Accordingly, there are needs for structures and methods for supporting semiconductor substrates and for sealing the active surfaces thereof during and following thinning thereof.
SUMMARY OF THE INVENTION
• The present invention includes a support structure, or carrier, for semiconductor substrates. The support structure is configured to be disposed upon an active surface of a semiconductor substrate and to structurally support and impart rigidity to at least an outer peripheral portion of the semiconductor substrate.
• In one embodiment, the support structure comprises a ring which covers only the outer peripheral portion of the active surface of the semiconductor substrate. An outer peripheral edge of the ring extends substantially to or beyond an outer peripheral edge of the semiconductor substrate. An inner peripheral edge of the ring laterally surrounds an interior portion of the active surface of the semiconductor substrate, on which semiconductor devices have been fabricated. Thus, the semiconductor devices are laterally within the inner peripheral edge of the ring.
• Another embodiment of the support structure includes an outer peripheral section which covers the outer peripheral portion of the active surface of the semiconductor substrate, as well as an interior section which comprises a plurality of protective structures for each of the semiconductor devices that have been fabricated on the active surface of the semiconductor substrate. The outer peripheral and interior sections of the support structure may be integral with one another. The thicknesses of these sections may be substantially the same as or different from one another.
• In another aspect, the present invention includes semiconductor substrates with support structures that incorporate teachings of the present invention on at least portions of active surfaces thereof.
• The present invention, in another aspect thereof, also includes methods for forming support structures on and securing support structures to the active surfaces of semiconductor substrates. In one embodiment of such a method, a support structure may be formed on an active surface of a semiconductor substrate by selectively consolidating regions of a layer of an unconsolidated material that has been applied to or otherwise formed over the active surface. In another embodiment, a support structure of the present invention may be molded onto an active surface of a semiconductor substrate. In yet another embodiment, a preformed film may be applied and laminated to an active surface of a semiconductor substrate, and then so-called “subtractive” processes may be used to form a support structure therefrom.
• Additionally, the present invention includes methods for thinning and processing semiconductor substrates while support structures that incorporate teachings of the present invention are secured to active surfaces thereof. The present invention also includes methods for removing support structures of the present invention from semiconductor substrates.
• Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
• In the drawings, which depict exemplary features of various aspects of the present invention:
• FIG. 1 is a top view of an exemplary semiconductor substrate, depicted as a wafer, which is shown as including a plurality of semiconductor devices on an active surface thereof;
• FIGS. 2 and 2A are top views of the semiconductor substrate shown inFIG. 1, with exemplary embodiments of support structures according to the present invention on the active surfaces thereof.
• FIG. 3 is a cross-section taken along line3-3 ofFIG. 2, depicting a first example of the manner in which the outer periphery of the support structure may be associated with an outer peripheral edge of the semiconductor substrate;
• FIGS. 4A through 4D are cross-sections that are also taken along line3-3 ofFIG. 2, illustrating second and third examples of the manner in which the outer periphery of the support structure may be associated with an outer peripheral edge of the semiconductor substrate;
• FIG. 5 is a partial top view of the semiconductor substrate shown inFIG. 1, depicting a variation of the support structure which includes a series of concentrically positioned upwardly protruding members, each of which extends along the full extent (e.g., length, circumference, etc.) of the support structure;
• FIG. 6 is a cross-section taken along line6-6 ofFIG. 5;
• FIG. 7 is a top view of the substrate shown inFIG. 1, illustrating another exemplary embodiment of support structure that incorporates teachings of the present invention;
• FIG. 8 is an enlarged, partial cross-section taken along line8-8 ofFIG. 7, showing a first example of the manner in which the outer periphery of the support structure may be associated with an outer peripheral edge of the semiconductor substrate;
• FIG. 9 is also an enlarged, partial cross-section taken along line8-8 ofFIG. 7, showing a second example of the manner in which the outer periphery of the support structure may be associated with an outer peripheral edge of the semiconductor substrate;
• FIG. 10 is a schematic representation of an example of a layered manufacturing (e.g., stereolithography) apparatus that may be used to fabricate a support structure of the present invention upon an active surface of a semiconductor substrate;
• FIGS. 11A through 11E schematically depict use of the apparatus ofFIG. 10 to fabricate the support structure shown inFIG. 4 upon the active surface of a semiconductor substrate;
• FIGS. 12A and 12B schematically depict use of molding processes to form a support structure (e.g., that shown inFIG. 3) on the active surface of a semiconductor substrate;
• FIGS. 13A and 13B schematically depict lamination of a preformed material film to the active surface of a semiconductor substrate and use of subtractive processes to remove material of the preformed film and to thereby form a support structure therefrom;
• FIGS. 14A and 14B are schematic representations depicting thinning of a semiconductor substrate that has a support structure of the present invention secured to an active surface thereof;
• FIG. 15 is a schematic representation of a method for transporting a thinned semiconductor substrate in accordance with teachings of the present invention;
• FIG. 16 schematically depicts processing of a semiconductor substrate following thinning thereof; and
• FIGS. 17A through 17C are schematic representations of a method for removing a support structure of the present invention from a thinned semiconductor substrate.
DETAILED DESCRIPTION OF THE INVENTION
• An example of asemiconductor substrate10 is shown inFIG. 1. As illustrated,semiconductor substrate10 may comprise a wafer of a semiconductor material, such as silicon, gallium arsenide, or indium phosphide.
• Semiconductor substrate10 includes two opposite major surfaces, one of which is commonly referred to in the art as an “active surface”12 and the other of which is typically referred to in the art as a “back side”16 (seeFIGS. 3, 4A,4B,6,8, and9). Bothactive surface12 and backside16 are bounded by an outerperipheral edge18 ofsemiconductor substrate10. Whensemiconductor substrate10 comprises a full wafer, as in the depicted example, outerperipheral edge18 forms the circumference of the wafer.
• An edgebead removal area20 may be located onactive surface12, adjacent to outerperipheral edge18. Edgebead removal area20 is a relatively narrow feature (e.g., three millimeters across) which may extend around the entire outer periphery ofsemiconductor substrate10. Notably, processing ofsemiconductor substrates10 which lack edgebead removal areas20 is also within the scope of the present invention, although not specifically depicted in the drawings.
• Within the interior of edgebead removal area20 or, if asemiconductor substrate10 lacks an edgebead removal area20, of outerperipheral edge18, at aninterior section22 ofactive surface12,semiconductor substrate10 may include a plurality ofsemiconductor devices24.Adjacent semiconductor devices24 are separated from one another bystreets30, which extend acrossinterior section22 ofactive surface12, such as in the illustrated grid-like configuration. At least some of thesemiconductor devices24 that are located adjacent to outerperipheral edge18 ofsemiconductor substrate10 comprise onlyblanks24p, whilesemiconductor devices24fare located somewhat internally from outerperipheral edge18.
• Alternatively, although not shown in the drawings,semiconductor substrate10 may lacksemiconductor devices24 oninterior section22 ofactive surface12 thereof. This is because it may be desirable to thin asemiconductor substrate10 prior to fabricating structures, such as semiconductor devices, thereon or therefrom. For example, the loss of semiconductor devices and the expenses incurred in fabricating the same may be avoided if a thinnedsemiconductor substrate10″ (FIG. 14B) without any semiconductor devices thereon breaks or is otherwise damaged during the thinning process. Alternatively, one entity maythin semiconductor substrates10, then provide the thinnedsemiconductor substrates10″ to one or more other entities for further processing (e.g., device fabrication).
• In the illustrated examples, eachsemiconductor device24 includes one or more bond pads27 (FIGS. 8 and 9), which facilitate electrical communication with integrated circuitry of thatsemiconductor device24.
• Turning now toFIGS. 2 through 4B, an example of a support structure according to the present invention, in this case asupport ring40,40′,40a′,40b′,40c′ (shown inFIGS. 3, 4A,4B,4C, and4D, respectively) is depicted. As shown,support ring40,40′,40a′,40b′,40c′ is positioned onactive surface12 ofsemiconductor substrate10, over edgebead removal area20 thereof.Support ring40,40′,40a′,40b′,40c′ extends completely around anouter periphery13 ofactive surface12.
• An outerperipheral edge42,42′ ofsupport ring40,40′,40a′,40b′,40c′ is in substantial alignment with (FIG. 3) or is located outside (FIGS. 4A and 4B) of outerperipheral edge18. Aninterior edge44 ofsupport ring40,40′,40a′,40b′,40c′ defines surfaces of anaperture45 throughsupport ring40,40′,40a′,40b′,40c′.Interior section22 ofactive surface12 and, thus, all of thesemiconductor devices24fthereon are completely surrounded byinterior edge44 ofsupport ring40,40′,40a′,40b′,40c′ and exposed throughaperture45 thereof.
• Support ring40,40′,40a′,40b′,40c′ is formed from a material that is compatible with the material or materials ofsemiconductor substrate10. The material ofsupport ring40,40′,40a′,40b′,40c′ will, along with the thickness ofsupport ring40,40′,40a′,40b′,40c′, impart a thinnedsemiconductor substrate10″ (FIG. 14B) with the desired amount of rigidity. For example, it may be desirable to impart a thinnedsemiconductor substrate10″ with approximately the same amount of rigidity as that of thesemiconductor substrate10 prior to thinning thereof. As another example, it may be desirable to impart a thinnedsemiconductor substrate10″ with sufficient rigidity to prevent bending, sagging, or other nonplanarity thereof during processing or transportation thereof following the thinning process.
• In addition, the material from which supportring40,40′,40a′,40b′,40c′ is formed may be substantially impervious to chemicals (e.g., wet and dry etchants) that may be used in backgrinding processes, as well as compatible with conditions of any post-thinning processes.
• The material from which supportring40,40′,40a′,40b′,40c′ is formed may also facilitate or enhance sealing ofsupport ring40,40′,40a′,40b′,40c′ to a support structure, such as a vacuum chuck, assemiconductor substrate10 is being thinned or otherwise processed.
• It is also desirable to formsupport ring40,40′,40a′,40b′,40c′ from a material that has a coefficient of thermal expansion (CTE) that is as close as possible to that of the material or materials from whichsemiconductor substrate10 is formed (e.g., silicon has a CTE of about 2.9×10⁻⁶/° C.), thereby preventing warpage ofsemiconductor substrate10 and delamination ofsupport ring40,40′,40a′,40b′,40c′ therefrom during processing of semiconductor substrate10 (e.g., thinning or any processing that occurs thereafter).
• Exemplary materials that may be used to formsupport ring40,40′,40a′,40b′,40c′ include consolidatable materials that are useful in layered manufacturing processes (e.g., photoimageable polymers that are useful in stereolithography processes), photoresists, thermoset polymers (e.g., moldable silicones), and the like. While many of these materials may be less rigid than desired or have CTEs which differ significantly from the material or materials ofsemiconductor substrate10, fillers may be added thereto to impart the materials and, thus,support ring40,40′,40a′,40b′,40c′ with the desired properties. Examples of fillers that may be used with any of the foregoing materials include, but are not limited to, silica (i.e., glass, silicon) particles, alumina (i.e., ceramic) particles, nitride (e.g., silicon nitride, boron nitride) particles, and polymeric particles or fibers (e.g., poly(p-phenyleneterephtalamide) fibers, which are marketed under the tradename KEVLAR® by E.I. du Pont de Nemours & Company of Wilmington, De.). Photoimageable polymers that are useful in stereolithography processes may have CTEs of about 55×10⁻⁶/° C. When a silica filler material is included therein, with the mixture including about 50%, by weight, photoimageable polymer and about 50%, by weight, silica particles, the CTE of the mixture is lowered significantly, to about 32×10⁻⁶/° C. Fillers may also increase or enhance the fracture toughness (e.g., KEVLAR®), strength, rigidity, thermal properties (e.g., boron nitride), or structural integrity of the material (e.g., photoimageable polymer, photoresist, thermoset polymer, etc.) within which they are mixed.
• Along with the materials from which supportring40,40′,40a′,40b′,40c′ is formed, the dimensions or configuration thereof may provide the desired properties. For example, as illustrated inFIGS. 3 through 4D, asupport ring40,40′,40a′,40b′,40c′ according to the present invention may have a width W which is at leastas great as the width of edge bead removal area20 (i.e., typically about 3 mm or more).
• In another example, with continued reference toFIGS. 3 through 4D, the height H ofsupport ring40,40′,40a′,40b′,40c′ may impartsupport ring40,40′,40a′,40b′,40c′ and, thus, a thinnedsemiconductor substrate10″ (FIG. 14B) with whichsupport ring40,40′,40a′,40b′,40c′ is to be used with a desired amount of rigidity. For example, depending, of course, upon the rigidity and CTE of the material from which supportring40,40′,40a′,40b′,40c′ is formed, support ring may have a height of as small as about 25 μm (one mil) to about 200 μm (eight mils) or greater.
• When a thinnedsemiconductor substrate10″ and asupport ring40,40′,40a′,40b′,40c′ thereon will be handled or processed with equipment which is configured to handle and process semiconductor substrates of standard diameters and thicknesses, the combined height H ofsupport ring40,40′,40a′,40b′,40c′ and thickness of a thinnedsemiconductor substrate10″ (FIG. 14B) should not exceed the maximum substrate thickness (e.g., about 800 μm) that such equipment is configured to accommodate. Likewise, the outer diameter (OD) ofsupport ring40,40′,40a′,40b′,40c′ should not exceed the maximum substrate diameter (e.g., 200 mm, 300 mm, etc.) that equipment for handling or processing a thinnedsemiconductor substrate10″ may be configured to accommodate.
• As shown inFIG. 3, an outerperipheral edge44 ofsupport ring40 may be substantially coextensive and, thus, in substantial alignment with an outerperipheral edge18 ofsemiconductor substrate10.
• Alternatively, as depicted inFIG.4A, asupport ring40′ may extend beyond outerperipheral edge18 ofsemiconductor substrate10, with an outerperipheral edge42′ ofsupport ring40′ being positioned outside of outerperipheral edge18 ofsemiconductor substrate10. Accordingly,support ring40′ includes anoverhang region46′, which is located beyond outerperipheral edge18 ofsemiconductor substrate10.
• In addition,support ring40′ may include acircumferential support element48′ beneathoverhang region46′, substantially coplanar withsemiconductor substrate10, and in substantial contact with outerperipheral edge18.Circumferential support element48′ may have a height which is about the same as or less than the desired thickness ofsemiconductor substrate10 following thinning thereof (i.e., the thickness of thinnedsemiconductor substrate10″ (FIG. 14B)).
• Overhang region46′ ofsupport ring40′ or a variation thereof may include one or more ancillary features, such as one or more markings, locating features, or fixturing features. By way of example only, one or more dowel holes55,slots56, orfiducial marks57 may be formed on, in, or throughoverhang region46′, as shown inFIG. 2A.
• Thesupport ring40a′ shown inFIG.4B includes all of the features ofsupport ring40′, except forcircumferential support element48? (FIG. 4A).
• Shown inFIG. 4C is another variation ofsupport ring40b′, which includes all of the features ofsupport ring40′ (FIG. 4A).Support ring40b′ differs fromsupport ring40′ in thatcircumferential support element48b′ ofsupport ring40b′ extends fromoverhang region46′ substantially to, as shown, or beyond a plane in which backside16 ofsemiconductor substrate10 is located.
• Once asemiconductor substrate10 with asupport ring40b′ thereon has been thinned (e.g., by chemical thinning or polishing processes),circumferential support element48b′ will protrude beyond backside16, forming a lip (not shown) that extends completely around outerperipheral edge18 at backside16. Such a lip may be useful for enhancing the rigidity of the thinnedsemiconductor substrate10″ (seeFIG. 14B), as well as for sealing backside16 against a carrier while processing is being effected overactive surface12 of thinnedsemiconductor substrate10″.
• FIG. 4D illustrates still another variation ofsupport ring40c′, which includes anoverhang region46′ and acircumferential support element48c′.Circumferential support element48c′ differs fromcircumferential support element48′ (FIG. 4A) in thatcircumferential support element48c′ extends fromoverhang region46′ to a location beyond a plane in which backside16 ofsemiconductor substrate10 is located. In addition,circumferential support element48c′ is spaced apart from outerperipheral edge18 ofsemiconductor substrate10, providing a gap G that accommodates expansion or contraction ofsupport ring40c′ orsemiconductor substrate10 due to CTE mismatch therebetween. Due to the presence of gap G,support ring40c′ also includes aretention ledge49′ that extends inwardly from a lower edge ofcircumferential support element48c′, along a plane which is parallel to a plane in which backside16 ofsemiconductor substrate10 is located, and over at least aperipheral portion17 of backside16, thereby trapping outerperipheral edge18.
• As shown inFIGS. 5 and 6, another variation ofsupport ring40″ may comprise one ormore sealing elements50″ which protrude from anupper surface49″ ofsupport ring40″.FIGS. 5 and 6 depictsupport ring40″ as including three concentrically arranged sealingelements50″, although support rings40″ with other numbers (i.e., as few as one or more than three) of sealingelements50′ are also within the scope of the present invention.Sealing elements50″ are somewhat compliant features that are configured to facilitate the creation of a seal betweenupper surface49″ ofsupport ring40″ and a surface or feature (not shown) against which supportring40″ is to be positioned, such as a surface of a sealing ring of a vacuum chuck.
• Features of other embodiments of support structures according to the present invention, which are referred to herein as “support members”140,140′, are pictured inFIGS. 7 through 9. In addition to including an outerperipheral portion150,150′ that covers an edgebead removal area20 ofactive surface12 ofsemiconductor substrate10,support member140,140′ also includes aninterior portion160,160′ that formsprotective structures28,28′ oversemiconductor devices24fthat are carried byinterior section22 ofactive surface12.
• AsFIGS. 8 and 9 illustrate, outerperipheral portion150,150′ ofsupport member140,140′ may be configured substantially the same as support rings40,40′ depicted inFIGS. 3 and 4A, respectively. In addition, although not illustrated, outerperipheral portion150,150′ ofsupport member140,140′ may include one or more sealing elements, such as the sealingelements50″ that are shown inFIGS. 5 and 6.
• With continued reference toFIGS. 8 and 9, eachprotective structure28,28′ ofinterior portion160,160′ ofsupport member140,140′ includes at least oneaperture162 through which acorresponding bond pad27 of the corresponding, underlyingsemiconductor device24fis exposed.
• FIG. 9 shows asemiconductor substrate10′ which includestrenches32 at the locations ofstreets30, material ofstreets30 having been removed by known processes, such as partial cutting with a wafer saw, photolithography (e.g., mask) and etch processes, or the like, to formtrenches32. Thus,protective structure28′ covers anactive surface26 of eachcorresponding semiconductor device24f, as well as at least a portion ofperipheral edges25 thereof.
• No material has been removed fromstreets30 of thesemiconductor substrate10 shown inFIG. 8. Accordingly, an alternative configuration of theprotective structure28′ that is shown inFIG. 8 covers only theactive surface26 of asemiconductor device24f, not any portions of theperipheral edges25 thereof.
• Like support rings40,40′,40a′,40b′,40c′,40″,support members140,140′ may be formed from a material which provides the desired degrees of rigidity and sealability. The thickness and other dimensions ofsupport members140,140′ may also factor into the rigidities thereof.
• In addition, sincesupport members140,140′ includeprotective structures28,28′, the material from which supportmembers140,140′ also provides other desirable properties, such as a particular level of electrical insulation, an ability to withstand subsequent processing conditions (e.g., dicing, further packaging, etc.), an ability to withstand operating conditions (e.g., temperature) to which eachsemiconductor device24fis subjected when in use, a particular degree of impermeability to moisture, or the like.
• Turning now toFIGS. 10 through 13B, various exemplary methods for forming support structures, including support rings40,40′,40″ andsupport members140,140′, are depicted. Although the description of these processes herein is limited to forming of asupport ring40′ (FIGS. 11A through 12C) or a support ring40 (FIGS. 13A and 13B), they are also useful for forming other embodiments of support structures that incorporate teachings of the present invention.
• FIGS. 10 and 11A through11E show a layered manufacturing process that may be used to form asupport ring40′.
• InFIG. 10, an example of astereolithography system1000, which effects a type of layered manufacturing process that employs selective irradiation of radiation-curable (e.g., by ultraviolet light, etc.) curable resin, is schematically represented.
• Stereolithography system1000 includes afabrication tank1100 and amaterial consolidation system1200, amachine vision system1300, acleaning component1400, and amaterial reclamation system1500 that are associated withfabrication tank1100. The depictedstereolithography system1000 also includes asubstrate handling system1600, such as a rotary feed system or linear feed system available from Genmark Automation Inc. of Sunnyvale, Calif., for moving fabrication substrates (e.g., semiconductor substrates10) from one system ofstereolithography system1000 to another. Features of one or more of the foregoing systems may be associated with one ormore controllers1700, such as computer processors or smaller groups of logic circuits, in such a way as to effect their operation in a desired manner.
• Controller1700 may comprise a computer or a computer processor, such as a so-called “microprocessor,” which may be programmed to effect a number of different functions. Alternatively,controller1700 may be programmed to effect a specific set of related fimctions or even a single function. Eachcontroller1700 ofstereolithography system1000 may be associated with a single system thereof or a plurality of systems so as to orchestrate the operation of such systems relative to one another.
• Fabrication tank1100 includes achamber1110 which is configured to contain asupport system1130. In turn,support system1130 is configured to carry one ormore semiconductor substrates10.
• Fabrication tank1100 may also have areservoir1120 associated therewith.Reservoir1120 may be continuous withchamber1110. Alternatively,reservoir1120 may be separate from but communicate withchamber1110 in such a way as to provideunconsolidated material1126 thereto.Reservoir1120 is configured to at least partially contain avolume1124 ofunconsolidated material1126, such as a photoimageable polymer, or “photopolymer,” particles of thermoplastic polymer, resin-coated particles, or the like.
• Photopolymers believed to be suitable for use with astereolithography system1000 and for fabricating support structures, such as support rings40′, in accordance with teachings of the present invention, include, without limitation, Cibatool SL 5170, SL 5210, SL 5530, and SL 7510 resins. All of these photopolymers are available from Ciba Specialty Chemicals Inc. of Basel, Switzerland.
• Reservoir1120 or another component associated with one or both offabrication tank1100 andreservoir1120 thereof may be configured to maintain asurface1128 of a portion ofvolume1124 located withinchamber1110 at a substantially constant elevation relative tochamber1110.
• Amaterial consolidation system1200 is associated withfabrication tank1100 in such a way as to direct consolidatingenergy1220 intochamber1110 thereof, toward at least areas ofsurface1128 ofvolume1124 ofunconsolidated material1126 withinreservoir1120 that are located oversemiconductor substrate10. Consolidatingenergy1220 may comprise, for example, electromagnetic radiation of a selected wavelength or a range of wavelengths, an electron beam, or other suitable energy for consolidatingunconsolidated material1126.Material consolidation system1200 includes asource1210 of consolidatingenergy1220. If consolidatingenergy1220 is focused,source1210 or alocation control element1212 associated therewith (e.g., a set of galvanometers, including one for x-axis movement and another for y-axis movement) may be configured to direct, or position, consolidatingenergy1220 toward a plurality of desired areas ofsurface1128. Alternatively, if consolidatingenergy1220 remains relatively unfocused, it may be directed generally towardsurface1128 from a single, fixed location or from a plurality of different locations. In any event, operation ofsource1210, as well as movement thereof, if any, may be effected under the direction ofcontroller1700.
• Whenmaterial consolidation system1200 directs focused consolidatingenergy1220 towardsurface1128 ofvolume1124 ofunconsolidated material1126,stereolithography system1000 may also include amachine vision system1300.Machine vision system1300 facilitates the direction of focused consolidatingenergy1220 toward desired locations of features onsemiconductor substrate10. As withmaterial consolidation system1200, operation ofmachine vision system1300 may be proscribed bycontroller1700. If any portion ofmachine vision system1300, such as acamera1310 thereof, moves relative tochamber1110 offabrication tank1100, that portion ofmachine vision system1300 may be positioned so as provide a clear path to all of the locations ofsurface1128 that are located over eachsemiconductor substrate10 withinchamber1110.
• Optionally, one or both of material consolidation system1200 (which may include a plurality of mirrors1214) andmachine vision system1300 may be oriented and configured to operate in association with a plurality offabrication tanks1100. Of course, one ormore controllers1700 would be useful for orchestrating the operation ofmaterial consolidation system1200,machine vision system1300, andsubstrate handling system1600 relative to a plurality offabrication tanks1100.
• Cleaning component1400 ofstereolithography system1000 may also operate under the direction ofcontroller1700.Cleaning component1400 ofstereolithography system1000 may be continuous withchamber1110 offabrication tank1100 or positioned adjacent tofabrication tank1100. Ifcleaning component1400 is continuous withchamber1110, anyunconsolidated material1126 that remains on asemiconductor substrate10 may be removed therefrom prior to introduction of anothersemiconductor substrate10 intochamber1110.
• Ifcleaning component1400 is positioned adjacent tofabrication tank1100, residualunconsolidated material1126 may be removed from asemiconductor substrate10 assemiconductor substrate10 is removed fromchamber1110. Alternatively, anyunconsolidated material1126 remaining onsemiconductor substrate10 may be removed therefrom aftersemiconductor substrate10 has been removed fromchamber1110, in which case the cleaning process may occur as anothersemiconductor substrate10 is positioned withinchamber1110.
• Material reclamation system1500 collects excessunconsolidated material1126 that has been removed from asemiconductor substrate10 by cleaningcomponent1400, then returns the excessunconsolidated material1126 toreservoir1120 associated withfabrication tank1100.
• In use,controller1700, under control of computer-aided drafting (CAD) or stereolithography (.stl) programming, may orchestrate operation of various components ofstereolithography system1000 to fabricate support structures, such as support rings40′, as well as other features.
• FIGS. 11A through 11E depict an example of the manner in which a support structure, such assupport ring40′, may be fabricated.
• With reference toFIG. 11A,semiconductor substrate10 is positioned on asupport platen1112 withinchamber1110 of fabrication tank1100 (FIG. 10). As depicted,semiconductor substrate10 is submerged withinvolume1124 ofunconsolidated material1126 so thatunconsolidated material1126 covers and fills all of the features that are located atactive surface12 ofsemiconductor substrate10.
• Next, as shown inFIG. 11B,support platen1112 is raised such that the upper surface ofsemiconductor substrate10 is brought to about the same level as (i.e., coplanar with)surface1128, as shown, or abovesurface1128 ofvolume1124.Areas1129 ofunconsolidated material1126 that are located adjacent to outerperipheral edge18 ofsemiconductor substrate10 are then at least partially selectively consolidated (e.g., with a laser or other focused consolidating energy1220) to initiate the formation ofcircumferential support element48′ (FIGS. 4A and 11C) ofsupport ring40′ (FIG. 4A). This process may be effected once ifcircumferential support element48′ comprises a single material layer, or repeated multiple times, loweringsemiconductor substrate10 in multiple increments untilactive surface12 thereof is substantially planar withsurface1128 ofvolume1124, ifcircumferential support element48′ includes a plurality of superimposed, contiguous, mutually adhered layers of material.
• Oncecircumferential support element48′ has been formed, portions ofsupport ring40′ which are located above the plane in whichactive surface12 ofsemiconductor substrate10 is located, includingoverhang region46′ thereof, may be fabricated, as shown inFIG. 11C.Support platen1112 is lowered such thatactive surface12 is submerged beneathsurface1128 of volume1124 a distance that, considering any change in the density ofunconsolidated material1126 upon consolidation thereof, will result in a layer or sublayer of consolidated material that protrudes above active surface12 a desired height (e.g., about one mil, about four mils, about eight mils, etc.).Unconsolidated material1126 at locations where the fabrication of a support structure, such assupport ring40′, is desired may then be selectively consolidated with focused consolidating energy1220 (e.g., a laser beam) to form at least another layer ofsupport ring40′.
• As illustrated inFIG. 11D, these processes may be repeated a number of times until a support structure, such assupport ring40′, and features thereof (e.g., the sealingelements50″ shown inFIGS. 5 and 6, which may be formed as one or more separate layers from the remainder ofsupport ring40′) have been completely formed.
• Following the fabrication of a support structure, such assupport ring40′, onsemiconductor substrate10,support platen1112 may be raised such that atleast semiconductor substrate10 and the support structure (e.g.,support ring40′) carried thereby are removed fromvolume1124 ofunconsolidated material1126, as shown inFIG. 11E. Thereafter,semiconductor substrate10 and the support structure thereon may be cleaned, as known in the art.
• Alternatively, a support structure according to the present invention may be formed by applying a photoresist (e.g., by spin-on processes or otherwise, as known in the art) ontoactive surface12 of semiconductor substrate10 (FIG. 1), then exposing desired regions of the photoresist to one or more suitable wavelengths of radiation (e.g., through a reticle), as in known photolithography processes, and developing the exposed regions with a chemical or chemicals that are suitable for consolidating the photoresist that has been exposed.
• Referring now toFIGS. 12A and 12B, an exemplary process for molding a support structure, such as asupport ring40′ (FIGS. 4A and 12B) in place upon asemiconductor substrate10 is depicted.
• As shown inFIG. 12A,semiconductor substrate10 is positioned within asupport cavity212 of or otherwise supported by afirst half210 of amold200, withactive surface12 ofsemiconductor substrate10 remaining exposed. Thereafter, asecond half220 ofmold200 is then positioned overactive surface12. Regions ofactive surface12, including edgebead removal area20 thereof, upon which the support structure (e.g.,support ring40′) is to be positioned, communicate with one ormore cavities222 ofsecond half220. Of course, first andsecond halves210,220 ofmold200 may include other features (e.g., runners, vents, etc.) that are positioned appropriately for the type of molding process in whichmold200 is to be used.
• Oncesemiconductor substrate10 has been properly positioned withinmold200, known mold processes (e.g., transfer molding, pot molding, injection molding, etc.) may be used to introduce liquid mold material from which the support structure (e.g.,support ring40′) is to be formed into eachcavity222 and onto regions ofactive surface12 that communicate with eachcavity222.
• As shown inFIG. 12B, once the mold material has sufficiently hardened (e.g., cured, cooled, etc.),semiconductor substrate10 and the support structure (e.g.,support ring40′) that has been molded in place thereon may be removed frommold200, as known in the art.
• Another exemplary process for forming a support structure, such assupport ring40′ on at least anactive surface12 of asemiconductor substrate10 is pictured inFIGS. 13A and 13B.
• InFIG. 13A, apreformed sheet300 of a material from which a support structure, such as support ring40 (FIG. 2), is to be formed is positioned over and secured toactive surface12 ofsemiconductor substrate10.Preformed sheet300 may be secured toactive surface12 by any technique which is compatible with the material ofpreformed sheet300 and withsemiconductor substrate10 and semiconductor devices24 (FIGS. 1 and 2) that have been fabricated onactive surface12 thereof. By way of nonlimiting example, preformedsheet300 may be secured toactive surface12 with a pressure-sensitive or curable adhesive, by heating preformedsheet300 oractive surface12, by applying solvent to at least alower surface302 ofpreformed sheet300 or toactive surface12, or by any other suitable process known in the art.
• Once preformedsheet300 has been laminated toactive surface12, subtractive processes may be used to form a support structure according to the present invention therefrom, as shown inFIG. 13B. For example, and not to limit the scope of the present invention, a support structure (e.g., support ring40) may be formed by the use of photolithography processes to form amask310 and removal of material throughapertures312 in mask310 (e.g., with an etchant or solvent that is suitable for use in removing the material of preformed sheet300), photoablation (e.g., which is useful with polymer films), or otherwise, as known in the art and suitable for use with the material ofpreformed sheet300 and withsemiconductor substrate10 and semiconductor devices24 (FIGS. 1 and 2) that have been fabricated onactive surface12 thereof.Mask310 may then be removed by way of known resist strip processes.
• Of course, combinations of processes for forming support structures that incorporate teachings of the present invention are also within the scope of the present invention. For example, asupport ring40,40′,40a′,40b′,40c′,40″ may be formed separately from a semiconductor substrate10 (FIG. 1), in one or more pieces (e.g.,support ring40c′ may be formed in two or more pieces), then assembled with semiconductor substrate10 (and, in the case ofsupport ring40c′, pieces are assembled with one another) and secured (i.e., adhered) thereto (and, in the case ofsupport ring40c′, secured to one another), such as by stereolithography processes or with an uncured polymer (e.g., thermoset polymer or photopolymer) which is subsequently cured by exposure to radiation or heat.
• Turning now toFIGS. 14A and 14B, thinning ofback side16 ofsemiconductor substrate12 is schematically depicted. AlthoughFIGS. 14A and 14B illustrate backgrinding of asemiconductor substrate10 that includes asupport ring40 on at leastactive surface12 thereof, backgrinding may also be effected with another embodiment of support structure of the present invention on at leastactive surface12, as well as with another embodiment of semiconductor substrate (e.g.,semiconductor substrate10′, shown inFIG. 9).
• As shown inFIG. 14A,semiconductor substrate10 is positioned active surface12-down over acarrier400, for example, a vacuum chuck available from Semitool, Inc. of Kalispell, Mont. The support structure (e.g., support ring40) onactive surface12 ofsemiconductor substrate10 contacts asurface410 ofcarrier400 or a corresponding feature (e.g., an o-ring412) thereon, and may form a seal thereagainst. Known processes (e.g., application of a negative pressure N toactive surface12 of semiconductor substrate10) may be used to securesemiconductor substrate10 againstsurface410 or a feature (e.g., o-ring412) thereon and, optionally, to sealactive surface12 from exposure to conditions that are present at the exterior (e.g., backside16 and outer peripheral edge18) ofsemiconductor substrate10.
• Oncesemiconductor substrate10 has been secured tocarrier400, known techniques may be used to remove material from backside16 ofsemiconductor substrate10 and, thus, tothin semiconductor substrate10 to a desired thickness, as depicted inFIG. 14B. By way of example only, known mechanical backgrinding or polishing processes (e.g., mechanical lapping techniques), chemical backgrinding or polishing processes (e.g., wet etch processes, dry etch processes, such as that described in U.S. Pat. No. 6,498,074 to Siniaguine et al., the disclosure of which is hereby incorporated herein in its entirety by this reference, etc.), or a combination of mechanical and chemical backgrinding or polishing processes may be employed tothin semiconductor substrate10. Such thinning processes may be effected until the resulting thinnedsemiconductor substrate10″ has a desired thickness (e.g., a thickness of about 230 μm or less, a thickness of about 50 μm or less, etc.).
• A thinnedsemiconductor substrate10″, which includes a support structure, such assupport ring40, on at leastactive surface12 thereof, is shown inFIG. 14B.
• FIG. 15 schematically depicts thinnedsemiconductor substrates10″ of the present invention insubstrate cartridges510 of amulti-substrate cassette500. As shown,cassette500 includes a plurality ofsubstrate cartridges510, each of which is somewhat horizontally oriented and configured to receive a semiconductor substrate of standard dimensions (e.g., a 200 mm or 300 mm silicon wafer that has not been thinned). Substrates, including thinnedsemiconductor substrates10″ that incorporate teachings of the present invention, may be introduced into and removed fromsubstrate cartridges510, as known in the art (e.g., with robotic handling equipment).
• Once one or more thinnedsemiconductor substrates10″ have been positioned withinsubstrate cartridges510 ofcassette500, they may be transported from process equipment in which backgrinding or thinning is effected to equipment by which thinnedsemiconductor substrates10″ will be further processed.
• For example, thinnedsemiconductor substrates10″, such as those formed in accordance with teachings of the present invention, may be secured (e.g., with adhesive materials) to other substrates, such as insulators like ceramic, glass, or sapphire, to form silicon-on-insulator (SOI) type substrates, such as a silicon-on-ceramic (SOC), silicon-on-glass (SOG), silicon-on-sapphire (SOS), or similar substrates.
• As another example, as shown inFIG. 16,semiconductor devices24fthat are carried byactive surface12 of a thinnedsemiconductor substrate10″ may be packaged by known wafer level packaging (WLP) processes (e.g., by stereolithography, by use of known layer formation and patterning processes, etc.), which typically include the formation ofprotective structures28″ over eachsemiconductor device24f.
• FIGS. 17A through 17C are schematic representations of a method for removing a support structure of the present invention, such as asupport ring40,40′,40a′,40b′,40c′,40″, as shown inFIG. 17A, asupport member140, as shown inFIG. 17B, or asupport member140′, as shown inFIG. 17C, from a thinnedsemiconductor substrate10″.
• As shown inFIG. 17A, known dicing processes (e.g., the depicted wafer saw600, a laser, etc.) may be used tosingulate semiconductor devices24ffrom thinnedsemiconductor substrate10″. Sincesupport ring40,40′,40″ does not cover any of thesemiconductor devices24fthat are carried byactive surface12′ of thinnedsemiconductor substrate10″,support ring40,40′,40″ will remain on thefragments124p″ that result from the dicing process, with each of the resultingsemiconductor dice124′ being substantially bare (e.g.,active surfaces12′ thereof remaining exposed).
• Referring now toFIG. 17B, when the support structure comprises a support structure (e.g., support member140) that includes an interior portion (e.g., interior portion160) that covers portions of theactive surfaces12′ ofsemiconductor devices24f, dicing, or singulation, of thesemiconductor devices24ffrom one another proceeds through both the interior portion and thinnedsemiconductor substrate10″. The result of such dicing, or singulation, is a plurality of low-profile packagedsemiconductor devices123′.
• FIG. 17C illustrates dicing, or singulation, of a thinnedsemiconductor substrate10′ that includestrenches32 alongstreets30 betweenadjacent semiconductor devices24f, as well as asupport member140′substantially coveringactive surfaces12′ thereof. As shown, during the thinning process,trenches32 and material ofprotective structures28′ may be exposed through backside16 ofsemiconductor substrate10′, effectively separatingsemiconductor devices24ffrom one another. Nonetheless,protective structures28′, which comprise portions ofinterior portion160′ ofsupport member140′, remain connected to one another, preventing the physical separation ofsemiconductor devices24ffrom each another.Support member140′ may be diced, or singulated, as known in the art, such as by use of the illustrated wafer saw600. When the blade orblades602 of wafer saw600 are narrower than the distance acrosstrenches32,peripheral edges125 of each singulated semiconductor die124′ will be at least partially covered withperipheral portions129′ of singulatedprotective structures128′, each of these elements together forming a low-profile packagedsemiconductor device123′.
• Oncesemiconductor devices24f(FIGS. 17A through 17C) have been physically separated from one another, further processing may occur, such as the selection of known good dice (KGDs), the connection thereof to one or more other semiconductor device components (e.g., a carrier substrate, an interposer, another semiconductor device, etc.), the incorporation thereof into a stacked multi-chip module (MCM) of standard dimensions but increased chip density, or packaging thereof with one or more other semiconductor device components may be conducted, as known in the art.
• Although the foregoing description contains many specifics, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some of the presently preferred embodiments. Similarly, other embodiments may be devised without departing from the spirit or scope of the present invention. Features from different embodiments may be employed in combination. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents rather than by the foregoing description. All additions, deletions and modifications to the invention as disclosed herein which fall within the meaning and scope of the claims are to be embraced thereby.

Claims (21)

1. A method for optimizing a physical property of a structure formed with a photoimageable polymer, comprising mixing a filler material having the physical property into the photoimageable polymer prior to at least partial consolidation of the photoimageable polymer.

2. The method ofclaim 1, wherein mixing the filler material comprises mixing a filler material with a lower coefficient of thermal expansion than that of the photoimageable polymer into the photoimageable polymer.

3. The method ofclaim 1, wherein mixing the filler material comprises mixing a filler material with a greater rigidity than that of the photoimageable polymer into the photoimageable polymer.

4. The method ofclaim 1, wherein mixing the filler material comprises mixing a filler material with a greater fracture toughness than that of the photoimageable polymer into the photoimageable polymer.

5. The method ofclaim 1, wherein mixing the filler material comprises mixing a filler material with a greater thermal stability than that of the photoimageable polymer into the photoimageable polymer.

6. The method ofclaim 1, wherein mixing the filler material comprises mixing a filler material comprising at least one of particles and fibers into the photoimageable polymer.

7. The method ofclaim 1, wherein mixing the filler material comprises mixing a filler material comprising at least one of a silica, an alumina, a nitride, and a polymer into the photoimageable polymer.

8. The method ofclaim 1, wherein mixing the filler material comprises mixing a filler material comprising KEVLAR into the photoimageable polymer.

9. The method ofclaim 1, wherein mixing the filler material comprises forming a mixture that includes up to about 50%, by weight, of the filler material.

10. The method ofclaim 1, wherein mixing comprises mixing a plurality of filler materials with the photoimageable polymer.

11. A method for optimizing a physical property of a structure formed with a selectively consolidatable material, comprising mixing a filler material into the selectively consolidatable material prior to at least partial consolidation of the selectively consolidatable material, the filler material at least partially imparting a compound including the selectively consolidatable material and the filler material with the physical property.

12. The method ofclaim 11, wherein mixing the filler material comprises mixing a filler material with a lower coefficient of thermal expansion than that of the selectively consolidatable material into the selectively consolidatable material.

13. The method ofclaim 11, wherein mixing the filler material comprises mixing a filler material with a greater rigidity than that of the selectively consolidatable material into the selectively consolidatable material.

14. The method ofclaim 11, wherein mixing the filler material comprises mixing a filler material with a greater fracture toughness than that of the selectively consolidatable material into the selectively consolidatable material.

15. The method ofclaim 11, wherein mixing the filler material comprises mixing a filler material with a greater thermal stability than that of the selectively consolidatable material into the selectively consolidatable material.

16. The method ofclaim 11, wherein mixing the filler material comprises mixing a filler material comprising at least one of particles and fibers into the selectively consolidatable material.

17. The method ofclaim 11, wherein mixing the filler material comprises mixing a filler material comprising at least one of a silica, an alumina, a nitride, and a polymer into the selectively consolidatable material.

18. The method ofclaim 11, wherein mixing the filler material comprises mixing a filler material comprising KEVLAR into the selectively consolidatable material.

19. The method ofclaim 11, wherein mixing the filler material comprises forming a mixture that includes up to about 50%, by weight, of the filler material.

20. The method ofclaim 11, wherein mixing comprises mixing the filler material with a photoimageable material.

21. The method ofclaim 11, wherein mixing comprises mixing a plurality of filler materials with the selectively consolidatable material.

Images