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US20050286336A1 - Flash EEprom system - Google Patents

Flash EEprom systemDownload PDF

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Publication number
US20050286336A1
US20050286336A1US10/641,210US64121003AUS2005286336A1US 20050286336 A1US20050286336 A1US 20050286336A1US 64121003 AUS64121003 AUS 64121003AUS 2005286336 A1US2005286336 A1US 2005286336A1
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level memory
state
electrical value
parameter
volatile multi
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US10/641,210
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Eliyahou Harari
Robert Norman
Sanjay Mehrotra
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SanDisk Technologies LLC
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Assigned to SANDISK TECHNOLOGIES INC.reassignmentSANDISK TECHNOLOGIES INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: SANDISK CORPORATION
Assigned to SANDISK TECHNOLOGIES LLCreassignmentSANDISK TECHNOLOGIES LLCCHANGE OF NAME (SEE DOCUMENT FOR DETAILS).Assignors: SANDISK TECHNOLOGIES INC
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Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Description

Claims (15)

63. For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate from the channel of each of the plurality of non-volatile multi-level memory cell, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group being substantially flowing in a same direction, a method of operating the electrically alterable non-volatile multi-level memory device, comprising:
settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell,
verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state,
reading status of the one non-volatile multi-level memory cell by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter,
wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state,
wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state,
wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits,
wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, and
wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.
65. For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate from the channel of each of the plurality of non-volatile multi-level memory cell, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group being substantially flowing in a same direction, a method of operating the electrically alterable non-volatile multi-level memory device, comprising:
controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell,
verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states by comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value, a third verifying reference electrical value and a fourth verifying reference electrical value, and of repeating the operation for controlling the electrical value and the operation for verifying until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state,
reading status of the one non-volatile multi-level memory cell by comparing the electrical value with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value,
wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state,
wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state,
wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits,
wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and
wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
67. An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate from the channel of each of the plurality of non-volatile multi-level memory cell, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group being substantially flowing in a same direction:
wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell,
wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states is carried out by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter is carried out, and repeating the operation for settling the parameter and the operation for verifying are carried out until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state,
wherein an operation of reading status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter,
wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state,
wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state,
wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits,
wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, and
wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.
69. The electrically alterable non-volatile multi-level memory according toclaim 68, further comprising, a plurality of bit lines, including said first and said second bit line, each of which transfers information indicating data stored in a memory cell, wherein drain regions of said multi-level memory cells of said first group in said matrix are coupled to said first bit line of said plurality of bit lines, drain regions of said multi-level memory cells of said second group adjoining to said first group in said matrix are coupled to said second bit line adjoining to said first bit line in said plurality of bit lines and drain regions of multi-level memory cells of a third group adjoining to said second column in said matrix are coupled to a third bit line adjoining to said second bit line in said plurality of bit lines
70. An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate from the channel of each of the plurality of non-volatile multi-level memory cell, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group being substantially flowing in a same direction:
wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell,
wherein an operation for verifying whether the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state selected from the plurality of states is carried out by comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value is carried out, a third verifying reference electrical value and a fourth verifying reference electrical value, and repeating the operation for controlling the electrical value and the operation for verifying are carried out until it is verified by the operation for verifying that the electrical value of the one non-volatile multi-level memory cell has being controlled to the one state,
wherein an operation for reading status of the one non-volatile multi-level memory cell is carried out by comparing the electrical value with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value,
wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state,
wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state,
wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits,
wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and
wherein the first verifying reference electrical value is allocated below the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value, the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value and the fourth verifying reference electrical value is allocated above the third reading reference electrical value.
72. The electrically alterable non-volatile multi-level memory according toclaim 71, further comprising, a plurality of bit lines, including said first and said second bit line, each of which transfers information indicating data stored in a memory cell, wherein drain regions of said multi-level memory cells of said first group in said matrix are coupled to said first bit line of said plurality of bit lines, drain regions of said multi-level memory cells of said second group adjoining to said first group in said matrix are coupled to said second bit line adjoining to said first bit line in said plurality of bit lines and drain regions of multi-level memory cells of a third group adjoining to said second column in said matrix are coupled to a third bit line adjoining to said second bit line in said plurality of bit lines.
73. An electrically non-volatile multi-level memory device comprising:
a plurality of memory cells disposed in matrix having rows and columns,
wherein each of said plurality of memory cells has a threshold voltage corresponding to data of two bits,
wherein threshold voltages of said plurality of memory cells are allocated to one of a first, a second, a third and a fourth threshold range,
wherein said first threshold range indicates an erase state, and said second, said third, said fourth threshold range indicate program states different from said erase state,
wherein said second, said third and said fourth threshold range indicate mutually different programming states,
wherein a threshold voltage of a memory cell selected from said plurality of memory cells is allocated in one of said first, said second and said third threshold range, and
wherein control gates of memory cells on the same row in said matrix are coupled to a word line of a plurality of word lines,
a plurality of bit lines each of which transfers information indicating data stored in a memory cell, wherein drain regions of memory cells on a first column in said matrix are coupled to a first bit line of said plurality of bit lines, drain regions of memory cells on a second column adjoining to said first column in said matrix are coupled to a second bit line adjoining to said first bit line in said plurality of bit lines and drain regions of memory cells on a third column adjoining to said second column in said matrix are coupled to a third bit line adjoining to said second bit line in said plurality of bit lines,
a programming circuit programming ones of said plurality of memory cells to said programming states by using verify reference parameters,
a sense circuit which compares information indicating data stored in a memory cell with a first reference parameter, a second reference parameter and a third reference parameter in parallel, in a normal read operation,
wherein said first threshold range is lower than said second threshold range, said second threshold range is lower than said third threshold range, and said third threshold range is lower than said fourth threshold range,
wherein said third reference parameter is higher than said second reference parameter, and said second reference parameter is higher than said first reference parameter,
wherein said verify reference parameters have at least first and second verify reference parameters,
wherein said first verify reference parameter is allocated between said second threshold range and said third threshold range, and said second verify reference parameter is allocated between said first threshold range and said second threshold range, and
wherein said first verify reference parameter is settled between said second reference parameter and said third reference parameter, and said second verify reference parameter is settled between said first reference parameter and said second reference parameter
US10/641,2101989-04-132003-08-13Flash EEprom systemAbandonedUS20050286336A1 (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
US10/641,210US20050286336A1 (en)1989-04-132003-08-13Flash EEprom system

Applications Claiming Priority (7)

Application NumberPriority DateFiling DateTitle
US33756689A1989-04-131989-04-13
US07/963,838US5297148A (en)1989-04-131992-10-20Flash eeprom system
US08/174,768US5602987A (en)1989-04-131993-12-29Flash EEprom system
US08/771,708US5991517A (en)1989-04-131996-12-20Flash EEprom system with cell by cell programming verification
US09/188,417US6304485B1 (en)1989-04-131998-11-09Flash EEprom system
US09/759,119US20040080988A1 (en)1989-04-132001-01-11Flash EEprom system
US10/641,210US20050286336A1 (en)1989-04-132003-08-13Flash EEprom system

Related Parent Applications (1)

Application NumberTitlePriority DateFiling Date
US09/759,119DivisionUS20040080988A1 (en)1989-04-132001-01-11Flash EEprom system

Publications (1)

Publication NumberPublication Date
US20050286336A1true US20050286336A1 (en)2005-12-29

Family

ID=23321048

Family Applications (29)

Application NumberTitlePriority DateFiling Date
US07/963,851Expired - LifetimeUS5418752A (en)1989-04-131992-10-20Flash EEPROM system with erase sector select
US07/963,838Expired - LifetimeUS5297148A (en)1989-04-131992-10-20Flash eeprom system
US08/174,768Expired - LifetimeUS5602987A (en)1989-04-131993-12-29Flash EEprom system
US08/249,049Expired - LifetimeUS5671229A (en)1989-04-131994-05-25Flash eeprom system with defect handling
US08/407,916Expired - LifetimeUS5719808A (en)1989-04-131995-03-21Flash EEPROM system
US08/771,708Expired - Fee RelatedUS5991517A (en)1989-04-131996-12-20Flash EEprom system with cell by cell programming verification
US08/789,421Expired - Fee RelatedUS6149316A (en)1989-04-131997-01-29Flash EEprom system
US08/931,133Expired - LifetimeUS5936971A (en)1989-04-131997-09-16Multi-state flash EEprom system with cache memory
US08/999,472Expired - LifetimeUS5877986A (en)1989-04-131997-12-29Multi-state Flash EEprom system on a card that includes defective cell substitution
US08/999,489Expired - LifetimeUS5862080A (en)1989-04-131997-12-29Multi-state flash EEprom system with defect handling
US08/999,498Expired - LifetimeUS5999446A (en)1989-04-131997-12-29Multi-state flash EEprom system with selective multi-sector erase
US09/059,815Expired - Fee RelatedUS6373747B1 (en)1989-04-131998-04-14Flash EEprom system
US09/143,233Expired - Fee RelatedUS8040727B1 (en)1989-04-131998-08-28Flash EEprom system with overhead data stored in user data sectors
US09/188,417Expired - Fee RelatedUS6304485B1 (en)1989-04-131998-11-09Flash EEprom system
US09/351,829Expired - Fee RelatedUS6414876B1 (en)1989-04-131999-07-12Flash EEprom system
US09/657,482Expired - Fee RelatedUS6523132B1 (en)1989-04-132000-09-08Flash EEprom system
US09/759,119AbandonedUS20040080988A1 (en)1989-04-132001-01-11Flash EEprom system
US09/867,836Expired - Fee RelatedUS7266017B2 (en)1989-04-132001-05-30Method for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system
US10/000,155AbandonedUS20020046318A1 (en)1989-04-132001-10-30Flash eeprom system
US10/237,456Expired - Fee RelatedUS6757842B2 (en)1989-04-132002-09-06Flash EEprom system
US10/278,444AbandonedUS20030046603A1 (en)1989-04-132002-10-22Flash EEprom system
US10/290,564Expired - Fee RelatedUS7283397B2 (en)1989-04-132002-11-07Flash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks
US10/330,739Expired - Fee RelatedUS6763480B2 (en)1989-04-132002-12-24Flash EEprom system
US10/331,081Expired - Fee RelatedUS6914846B2 (en)1989-04-132002-12-26Flash EEprom system
US10/330,455Expired - Fee RelatedUS6684345B2 (en)1989-04-132002-12-26Flash EEprom system
US10/348,739Expired - Fee RelatedUS7397713B2 (en)1989-04-132003-01-21Flash EEprom system
US10/417,954Expired - Fee RelatedUS7362618B2 (en)1989-04-132003-04-16Flash EEprom system
US10/641,210AbandonedUS20050286336A1 (en)1989-04-132003-08-13Flash EEprom system
US11/923,505AbandonedUS20080158995A1 (en)1989-04-132007-10-24Flash EEPROM System

Family Applications Before (27)

Application NumberTitlePriority DateFiling Date
US07/963,851Expired - LifetimeUS5418752A (en)1989-04-131992-10-20Flash EEPROM system with erase sector select
US07/963,838Expired - LifetimeUS5297148A (en)1989-04-131992-10-20Flash eeprom system
US08/174,768Expired - LifetimeUS5602987A (en)1989-04-131993-12-29Flash EEprom system
US08/249,049Expired - LifetimeUS5671229A (en)1989-04-131994-05-25Flash eeprom system with defect handling
US08/407,916Expired - LifetimeUS5719808A (en)1989-04-131995-03-21Flash EEPROM system
US08/771,708Expired - Fee RelatedUS5991517A (en)1989-04-131996-12-20Flash EEprom system with cell by cell programming verification
US08/789,421Expired - Fee RelatedUS6149316A (en)1989-04-131997-01-29Flash EEprom system
US08/931,133Expired - LifetimeUS5936971A (en)1989-04-131997-09-16Multi-state flash EEprom system with cache memory
US08/999,472Expired - LifetimeUS5877986A (en)1989-04-131997-12-29Multi-state Flash EEprom system on a card that includes defective cell substitution
US08/999,489Expired - LifetimeUS5862080A (en)1989-04-131997-12-29Multi-state flash EEprom system with defect handling
US08/999,498Expired - LifetimeUS5999446A (en)1989-04-131997-12-29Multi-state flash EEprom system with selective multi-sector erase
US09/059,815Expired - Fee RelatedUS6373747B1 (en)1989-04-131998-04-14Flash EEprom system
US09/143,233Expired - Fee RelatedUS8040727B1 (en)1989-04-131998-08-28Flash EEprom system with overhead data stored in user data sectors
US09/188,417Expired - Fee RelatedUS6304485B1 (en)1989-04-131998-11-09Flash EEprom system
US09/351,829Expired - Fee RelatedUS6414876B1 (en)1989-04-131999-07-12Flash EEprom system
US09/657,482Expired - Fee RelatedUS6523132B1 (en)1989-04-132000-09-08Flash EEprom system
US09/759,119AbandonedUS20040080988A1 (en)1989-04-132001-01-11Flash EEprom system
US09/867,836Expired - Fee RelatedUS7266017B2 (en)1989-04-132001-05-30Method for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system
US10/000,155AbandonedUS20020046318A1 (en)1989-04-132001-10-30Flash eeprom system
US10/237,456Expired - Fee RelatedUS6757842B2 (en)1989-04-132002-09-06Flash EEprom system
US10/278,444AbandonedUS20030046603A1 (en)1989-04-132002-10-22Flash EEprom system
US10/290,564Expired - Fee RelatedUS7283397B2 (en)1989-04-132002-11-07Flash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks
US10/330,739Expired - Fee RelatedUS6763480B2 (en)1989-04-132002-12-24Flash EEprom system
US10/331,081Expired - Fee RelatedUS6914846B2 (en)1989-04-132002-12-26Flash EEprom system
US10/330,455Expired - Fee RelatedUS6684345B2 (en)1989-04-132002-12-26Flash EEprom system
US10/348,739Expired - Fee RelatedUS7397713B2 (en)1989-04-132003-01-21Flash EEprom system
US10/417,954Expired - Fee RelatedUS7362618B2 (en)1989-04-132003-04-16Flash EEprom system

Family Applications After (1)

Application NumberTitlePriority DateFiling Date
US11/923,505AbandonedUS20080158995A1 (en)1989-04-132007-10-24Flash EEPROM System

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US (29)US5418752A (en)
EP (6)EP0935255A2 (en)
JP (1)JP3226042B2 (en)
DE (5)DE69033262T2 (en)

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US5719808A (en)1998-02-17
US6149316A (en)2000-11-21
US6304485B1 (en)2001-10-16
EP0392895A3 (en)1993-01-07
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EP0675502A2 (en)1995-10-04
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US20040080988A1 (en)2004-04-29
US5418752A (en)1995-05-23
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US20030202377A1 (en)2003-10-30
US6684345B2 (en)2004-01-27
US7283397B2 (en)2007-10-16
EP0935255A2 (en)1999-08-11
EP0618535B1 (en)1999-08-25
EP0617363A3 (en)1995-03-08
US5297148A (en)1994-03-22
US6914846B2 (en)2005-07-05
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US20020046318A1 (en)2002-04-18
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US7266017B2 (en)2007-09-04
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US6523132B1 (en)2003-02-18
US20030014689A1 (en)2003-01-16
US5862080A (en)1999-01-19
US5877986A (en)1999-03-02
US5671229A (en)1997-09-23
US20010026472A1 (en)2001-10-04
US5991517A (en)1999-11-23
US5602987A (en)1997-02-11
US5936971A (en)1999-08-10
DE69034227T2 (en)2007-05-03
DE69024086D1 (en)1996-01-25
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US20030097609A1 (en)2003-05-22
US6763480B2 (en)2004-07-13
US7362618B2 (en)2008-04-22
EP1031992A2 (en)2000-08-30
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US5999446A (en)1999-12-07
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US6373747B1 (en)2002-04-16

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