US20050280072A1 - Test mode decoder in a flash memory - Google Patents

Abstract

Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

Description

RELATED APPLICATIONS
• This application is a Divisional of U.S. application Ser. No. 10/880,894 filed Jun. 30, 2004; which is a Divisional of U.S. application Ser. No. 10/192,334 filed Jul. 10, 2002 and issued as U.S. Pat. No. 6,785,162 on Aug. 31, 2004, which claims priority under 35 U.S.C. 119 from Italian Application No. RM2001A000556 filed Sep. 12, 2001, all of which applications are incorporated herein by reference.
FIELD OF THE INVENTION
• The present invention relates generally to memory devices, and more particularly, to a test mode decoder in a flash memory device.
BACKGROUND
• Electrically erasable and programmable read-only memory devices having arrays of what are known as flash cells, also called flash EEPROMs or flash memory devices, are found in a wide variety of electrical devices. A flash memory device is typically formed in an integrated circuit. A conventional flash cell, also called a floating gate transistor memory cell, is similar to a field effect transistor, having a channel region between a source and a drain in a substrate and a control gate over the channel region. In addition the flash cell has a floating gate between the control gate and the channel region. The floating gate is separated from the channel region by a layer of gate oxide, and an inter-poly dielectric layer,separates the control gate from the floating gate. Both the control gate and the floating gate are formed of doped polysilicon. The floating gate is floating or electrically isolated. The flash memory device has a large number of flash cells in an array where the control gate of each flash cell is connected to a word line and the drain is connected to a bit line, the flash cells being arranged in a grid of word lines and bit lines.
• A flash cell is programmed by applying approximately 10 volts to the control gate, between 5 and 7 volts to the drain, and grounding the source and the substrate to induce hot electron injection from the channel region to the floating gate through the gate oxide. The voltage at the control gate determines the amount of charge residing on the floating gate after programming. The charge affects current in the channel region by determining the voltage that must be applied to the control gate in order to allow the flash cell to conduct current between the source and the drain. This voltage is termed the threshold voltage of the flash cell, and is the physical form of the data stored in the flash cell. As the charge on the floating gate increases the threshold voltage increases.
• One type of flash memory device includes an array of multi-bit or multi-state flash cells. Multi-state flash cells have the same structure as ordinary flash cells and are capable of storing multiple bits of data in a single cell. A multi-bit or multi-state flash cell has multiple distinct threshold voltage levels over a voltage range. Each distinct threshold voltage level corresponds to a set of data bits, with the number of bits representing the amount of data which can be stored in the multi-state flash cell.
• Data is stored in conventional flash memory devices by programming flash cells that have been previously erased. A flash cell is erased by applying approximately −10 volts to the control gate, 5 volts to the source, grounding the substrate and allowing the drain to float. In an alternate method of erasure the control gate is grounded and 12 volts is applied to the source. The electrons in the floating gate are induced to pass through the gate oxide to the source by Fowler-Nordheim tunneling such that the charge in the floating gate is reduced and the threshold voltage of the flash cell is reduced. Flash cells in an array in a flash memory device are grouped into blocks, and the cells in each block are erased together.
• A flash cell is read by applying approximately 5 volts to the control gate, approximately 1 volt to the drain, and grounding the source and the substrate. The flash cell is rendered conductive and current between the source and the drain is sensed to determine data stored in the flash cell. The current is converted to a voltage that is compared with one or more reference voltages in a sense amplifier to determine the state of the flash cell. The current drawn by a flash cell being read depends on the amount of charge stored in the floating gate.
• A flash memory device is fabricated as an integrated circuit and then tested before being operated commercially by a user. Each flash memory device is slightly different from others of the same design because of the unique process conditions of its fabrication and other factors. As a result, each flash memory device has operating characteristics that are slightly different from the characteristics of other flash memory devices. For example, the flash cells of the flash memory device may be programmed at slightly lower control gate voltages than other flash cells.
• Programmable control parameters have been used to control the operation of a flash memory device, and the control parameters can be programmed into data storage units after a flash memory device has been fabricated. The control parameters have been used to determine operating parameters for a flash memory device to compensate for its unique operating characteristics determined during fabrication, and the use of control parameters improves its performance. The control parameters are programmed in a test mode of operation following fabrication. The flash memory device is subject to a series of tests during the test mode, and the control parameters are programmed to set operating parameters such as reference voltage levels and the magnitude and duration of voltage pulses.
• The control parameters can also be programmed to select operating modes and a configuration for the flash memory device. A wide variety of flash memory devices are used in electronic devices, and different flash memory devices have different configurations and different operating modes depending on the application. The control parameters make it possible to fabricate flash memory devices according to a single design, and then customize the configuration and operating modes of each individual flash memory device according to its application. Each flash memory device can be customized by programming its control parameters during the test mode.
• A flash memory device is operated in the test mode in response to specific signals that are decoded by a test mode decoder circuit in the flash memory device. The purpose of the test mode decoder circuit is to start the test mode in response to the appropriate signals, and to prevent the flash memory device from entering the test mode if the appropriate signals are not present. The test mode decoder circuit is a safety device that reduces the likelihood that the control parameters will be changed by accident or mishap. An unwanted change in the control parameters can disable the flash memory device in its application.
• The capacity of flash memory devices to store data is gradually being increased by reducing the size and increasing the number of flash cells in each integrated circuit. Other components, including the test mode decoder circuit, must also be reduced in size in order to improve the capacity of flash memory devices. There remains a need for a test mode decoder circuit that is smaller than conventional circuits.
SUMMARY OF THE INVENTION
• The above mentioned and other deficiencies are addressed in the following detailed description. Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors to reduce the size of the decoder. The decoder may be fabricated with a flexible placement of vias that gives the decoder the flexibility to be fabricated for a variety of applications and to decode a variety of commands.
• Advantages of the present invention will be apparent to one skilled in the art upon an examination of the detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a block diagram of a flash memory system according to an embodiment of the present invention.
• FIG. 2 is a cross-sectional view of a flash cell according to an embodiment of the present invention.
• FIG. 3 is an electrical schematic diagram of a block of flash cells in the memory system ofFIG. 1.
• FIG. 4 is a block diagram of a test mode decoder circuit according to an embodiment of the present invention.
• FIG. 5 is a timing diagram of signals according to an embodiment of the present invention.
• FIG. 6 is an electrical schematic diagram of a decoder circuit according to an embodiment of the present invention.
• FIG. 7A is a block diagram of a block of sub-circuits according to an embodiment of the present invention.
• FIG. 7B is an electrical schematic diagram of a decoder circuit according to an embodiment of the present invention.
• FIG. 7C is an electrical schematic diagram of a decoder circuit according to an embodiment of the present invention.
• FIG. 7D is an electrical schematic diagram of buffer circuits according to an embodiment of the present invention.
• FIG. 8 is a block diagram of a layout of a decoder circuit according to an embodiment of the present invention.
• FIG. 9 is a cross-sectional view of a portion of a test mode decoder circuit according to an embodiment of the present invention.
• FIG. 10 is a cross-sectional view of a portion of a test mode decoder circuit according to an embodiment of the present invention.
• FIG. 11 is a block diagram of an integrated circuit chip according to an embodiment of the present invention.
• FIG. 12 is block diagram of a compact flash memory card according to an embodiment of the present invention.
• FIG. 13 is a block diagram of an information-handling system according to an embodiment of the present invention.
DETAILED DESCRIPTION
• In the following detailed description of exemplary embodiments of the present invention, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific exemplary embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical, electrical and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.
• In this description, a threshold voltage of a transistor is the voltage that must be applied to a control gate of the transistor in order to allow the transistor to conduct current between a source and a drain. In this description, a transistor or a flash cell is described as being activated or switched on when it is rendered conductive by a control gate voltage that exceeds its threshold voltage, and the transistor or flash cell is described as being in an inactive state or switched off when the control gate voltage is below the threshold voltage and the transistor or flash cell is non-conductive. A digital signal of 1 may also be called a high signal and a digital signal of 0 may also be called a low signal. A grouping of lines will be represented symbolically by <x:y>, while a single line from that group will be represented as [x].
• The terms wafer and substrate may be used in the following description and include any structure having an exposed surface with which to form an integrated circuit (IC) according to embodiments of the present invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during fabrication, and may include other layers that have been fabricated thereupon. The term substrate includes doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor, or semiconductor layers supported by an insulator, as well as other semiconductor structures well known to one skilled in the art. The term insulator is defined to include any material that is less electrically conductive than materials generally referred to as conductors by those skilled in the art.
• The term “horizontal” as used in this application is defined as a plane substantially parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction substantially perpendicular to the horizonal as defined above. Prepositions, such as “on,” “upper,” “side” (as in “sidewall”), “higher,” “lower,” “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.
• The term “source/drain” refers generally to the terminals or diffusion regions of a field effect transistor. A terminal or a diffusion region may be more specifically described as a “source” or a “drain” on the basis of a voltage applied to it when the field effect transistor is in operation.
• P-type conductivity is conductivity associated with holes in a semiconductor material, and n-type conductivity is conductivity associated with electrons in a semiconductor material. Throughout this specification the designation “n+” refers to semiconductor material that is heavily doped n-type semiconductor material, e.g., monocrystalline silicon or polycrystalline silicon. Similarly, the designation “p+” refers to semiconductor material that is heavily doped p-type semiconductor material. The designations “n−” and “p−” refer to lightly doped n and p-type semiconductor materials, respectively.
• A diffusion region in a substrate described herein according to embodiments of the present invention may also be called a moat or a well or a tank. The diffusion region may be an n-type diffusion region or a p-type diffusion region, and the substrate may be a silicon substrate. Transistors and other devices described herein according to embodiments of the present invention may have moats or wells that may be formed in other moats or wells or tanks rather than substrates. Such moats or wells or tanks may be situated with other moats or wells or tanks, or within other moats or wells or tanks, in a larger substrate. The moats or wells or tanks may also be situated in a silicon-on-insulator (SOI) device.
• FIG. 1 is a block diagram of aflash memory system100 according to an embodiment of the present invention. Thememory system100 includes amemory controller105 and a flash memory integrated circuit (IC)110. Thecontroller105 includes a control device such as a microprocessor to provide interface signals to theIC110. The interface signals include address signals provided over multiple address lines A0-A20 to an address buffer andlatch116, and data signals communicated over multiple data lines data <7:0>. TheIC110 has more than 21 address lines, and more than 8 data lines in alternate embodiments of the present invention. The data lines data <7:0> comprise 8 separate conductive lines each capable of transmitting a voltage signal, and together the data lines data <7:0> may comprise a lower byte of a data bus. The data lines data <7:0> are coupled to aninput buffer118 which stores the data signals for transfer to an input data latch119 over multiple internal data lines120. Other interface signals provided by thecontroller105 include a write enable signal WE* atnode121, a chip enable signal CE* atnode122, a reset/power-down signal RP* atnode123, an output enable signal OE* atnode124, and a write protect signal WP* atnode125, all of which are active low signals. TheIC110 provides a status signal RY/BY* to thecontroller105 atnode128 to indicate the status of aninternal state machine130. TheIC110 also receives a positive power supply voltage V_CCatnode132, a write/erase supply or programming voltage V_PPatnode134, and a reference voltage such as a substrate ground voltage V_SSatnode136 which is approximately 0 Volts. Each of the address lines A0-A20, data lines data <7:0>, and nodes121-128 is terminated at a pin (not shown) in theIC110 that may be coupled to thecontroller105 by a line such as a control line.
• TheIC110 includes anarray138 of floating gate transistor memory cells or flash cells arranged in32 flash cell blocks. Each block in thearray138 contains 64 kilobytes of flash cells. Flash cells in each block are erased as a group at the same time. A commandexecution logic module140 receives the above-described interface signals from thecontroller105. Themodule140 controls thestate machine130 which controls individual acts necessary for programming, reading, and erasing the flash cells in thearray138. More specifically thestate machine130 controls detailed operations of theIC110 such as providing write and block erase timing sequences to thearray138 through anX-interface circuit145 and a Y-interface circuit150.
• The Y-interface circuit150 provides access to individual flash cells through data lines in thearray138. Data lines in the Y-interface circuit150 are connected to a bit line driver circuit (not shown). The Y-interface circuit150 includes a Y-decoder circuit152, Y-select gates154, and sense amplifiers and write/erase bit compare and verifycircuits156. TheX-interface circuit145 provides access to rows of flash cells through word lines in thearray138, which are electrically coupled to the control gates of the flash cells in thearray138. TheX-interface circuit145 includes decoding and control circuits for erasing the blocks of flash cells in thearray138. The write/erase bit compare and verifycircuits156 are coupled to exchange data with the input data latch119 over a set of internal data lines158.
• TheIC110 includes acharge pump circuit160 to generate an elevated voltage Vpump for programming, erasing, or reading the flash cells in thearray138. Thepump circuit160 is coupled to receive the positive power supply voltage V_CCfrom thenode132 and provides the voltage Vpump to theX-interface circuit145, the Y-decoder circuit152, and thestate machine130 over a plurality of lines. In an alternate embodiment of the present invention, thepump circuit160 may provide a different elevated voltage over each of the lines shown inFIG. 1. Thestate machine130 controls anaddress counter162 which is capable of providing a sequence of addresses on an internal set ofaddress lines164 coupled between the address buffer andlatch116, theX-interface circuit145, and the Y-decoder circuit152.
• TheIC110 also includes astatus register170 coupled to receive signals from thestate machine130, themodule140, and thepump circuit160. Bits in thestatus register170 indicate the status of theIC110, and thestatus register170 is read by thecontroller105. TheIC110 also includes anidentification register172 coupled to receive signals from themodule140.
• A cross-sectional view of aflash cell200 is shown inFIG. 2 according to an embodiment of the present invention. Theflash cell200 includes an n+-type source S and an n+-type drain D formed in a p-type silicon substrate210. The source S and the drain D are separated by achannel region212 in thesubstrate210. Theflash cell200 includes a floatinggate215 and acontrol gate220, both formed of doped polysilicon. The floatinggate215 is floating or electrically isolated. A layer ofgate oxide225 separates the floatinggate215 from thechannel region212 in thesubstrate210. An inter-polydielectric layer235 separates the floatinggate215 from thecontrol gate220. Thesubstrate210 may be silicon or another semiconductor material, or it may be a thin semiconductor surface layer formed on an underlying insulating portion, such as a semiconductor-on-insulator (SOI) structure or other thin film transistor technology. The source S and the drain D are formed by conventional complementary metal-oxide-semiconductor (CMOS) processing techniques.
• Theflash cell200 shown inFIG. 2 is an n-channel floating gate transistor memory cell. In another embodiment of the present invention, theflash cell200 may be a p-channel floating gate transistor memory cell with a p+-type source S and a p+-type drain D formed in an n-type silicon substrate210.
• FIG. 3 is an electrical schematic diagram of ablock300 offlash cells310A-310S in thearray138 according to an embodiment of the present invention. Some flash cells in theblock300 are omitted fromFIG. 3 for purposes of clarity. Theflash cells310 are arranged in rows and columns. All of theflash cells310 in a particular column have drains D connected to a common bit line BL and all of theflash cells310 in a particular row have control gates connected to a common word line WL. The bit lines BL are identified as BL0-BLM and the word lines WL are identified as WL0-WLN. All of theflash cells310 in theblock300 have sources S connected to a common source line SL. The remaining flash cells in thearray138 are arranged into separate blocks having separate source lines. The flash cells in different blocks are erased independently to reduce the required erase current. There may be more orless flash cells310 in theblock300, and in thearray138, according to alternate embodiments of the present invention.
• Theflash cells310 are arranged in column pairs, with eachflash cell310 of the pair sharing a common source S. For example, aflash cell pair310J and310K have a common source S connected to the source line SL. The drains D of theflash cells310 are connected to the bit line BL associated with the column in which theflash cells310 are located. For example, theflash cell pair310J and310K have their drains D connected to a common bit line BL1.
• A selected one of theflash cells310A-310S in theblock300 is programmed by holding the source line SL to the ground voltage V_SSor zero volts, coupling approximately 5-7 volts to the bit line BL connected to the flash cell, and applying a high positive voltage programming pulse of approximately 10 volts to the word line WL of the flash cell. A selected one of theflash cells310A-310S in theblock300 is read by holding the source line SL to the ground voltage V_SS, coupling approximately 1 volt to the bit line BL connected to the flash cell, applying approximately 5.4 volts to the word line WL of the flash cell, and sensing current in the flash cell through the bit line BL. The current is sensed by one of thesense amplifiers156 that is coupled to the bit line BL. The sensed current is inversely related to the threshold voltage of the flash cell. The higher the threshold voltage, the less current is sensed in the flash cell, and visa versa. Theflash cells310A-310S in theblock300 are erased by holding the word lines WL0-WLN to the ground voltage V_SS, allowing the bit lines BL0-BLM to float, and applying a high positive voltage erase pulse of approximately 12 volts to the sources S through the source line SL. Charge is removed from the floating gate of the flash cell when it is erased.
• Control parameters for theIC110 are programmed by being stored in non-volatile data storage units in theIC110 in a test mode of operation after it has been fabricated. The data storage units may comprise flash cells or latches, or a combination thereof. The control parameters determine operating parameters for theIC110 such as, for example, supply voltage levels, reference voltage levels, the magnitude and duration of voltage pulses. More specifically, control parameters may determine the magnitude and duration of programming pulses, heal pulses, and erase pulses for flash cells in theIC110. The control parameters may select a bus size for theIC110 to determine the length of words stored in thearray138. The control parameters may determine other operating parameters such as choosing bottom addressing or top addressing for theIC110. The control parameters may also determine the configuration of theIC100 by enabling selected circuits and/or disabling other circuits.
• TheIC110 is operated in the test mode in response to specific signals that are decoded by atest mode decoder400 circuit in theIC110. A block diagram of thetest mode decoder400 is shown inFIG. 4 according to an embodiment of the present invention. Thetest mode decoder400 includes a command user interface (CUI)410 circuit, anSPT decoder412 circuit, and anSPT control logic414 circuit. The write enable signal WE* and the data lines data <7:0> are coupled to theCUI410, and the reset/power-down signal RP* is coupled to theSPT decoder412 and to a highvoltage detector circuit420. TheCUI410 decodes user commands supplied on the data lines data <7:0> during various modes of operation of theIC110. TheIC110 is placed in the test mode of operation to program control parameters in theIC110, as well as for other events. TheCUI410 places theIC110 in the test mode of operation in response to the write enable signal WE*, the reset/power-down signal RP*, and specific commands on the data lines data <7:0> as will be described with reference to a timing diagram500 of signals shown inFIG. 5 according to an embodiment of the present invention.
• The timing diagram500 shows time on ahorizontal axis510 and a voltage level of various signals along avertical axis520. The test mode of operation may be entered only when the reset/power-down signal RP* is at a supervoltage that is higher than voltages present in theIC110 during modes of operation other than the test mode of operation. The level of the reset/power-down signal RP* is detected by the highvoltage detector circuit420 which couples asignal422 to theCUI410 when the reset/power-down signal RP* reaches or exceeds the supervoltage. InFIG. 5, the reset/power-down signal RP* is at a supervoltage after time t₀. In addition, theCUI410 places theIC110 in the test mode of operation only after receiving and decoding two specific commands, afirst command520 and asecond command522, in a sequence from the data lines data <7:0>. Thefirst command520 and thesecond command522 are decoded during successive pulses of the write enable signal WE*. For example, thefirst command520 is decoded between t₂and t₃and thesecond command522 is decoded between t₅and t₆. If theCUI410 accepts and decodes thecommands520 and522, and the reset/power-down signal RP* is at the supervoltage, theIC110 is in the test mode of operation, and theCUI410 begins to generate an SPT clock signal SPT_CLK that is coupled to theSPT decoder412. The SPT clock signal SPT_CLK is a high pulse signal that is coincident with pulses of the write enable signal WE*. A first SPT_CLK pulse is shown between t₈and t₉. The SPT clock signal SPT_CLK pulse can be widened or narrowed by changing the pulse of the write enable signal WE*. The SPT clock signal SPT_CLK pulse enables theSPT decoder412 as will be further described hereinbelow.
• Two sets of data lines are coupled between theCUI410 and theSPT decoder412, the data lines data <7:0> and a second set of data lines datab <7:0>. The data lines datab <7:0> carry signals that are the inverse of the signals carried on the data lines data <7:0>. TheCUI410 inverts commands on the data lines data <7:0> and sends them to theSPT decoder412 on the data lines datab <7:0>. TheSPT decoder412 uses signals from both of the sets of data lines data <7:0> and datab <7:0> to decode test commands.
• Atest command540 is received from the data lines data <7:0> following thesecond command522, and is coupled to theSPT decoder412 on the data lines data <7:0> along with an inverted version of thetest command540 on the data lines datab <7:0>. Thetest command540 will initiate a particular operation on theIC110, such as programming a control parameter in theIC110. Thetest command540 is decoded by theSPT decoder412 during the first SPT_CLK pulse between t₈and t₉, and theSPT decoder412 generates an SPT signal on one of a plurality of SPT lines that are coupled to theSPT control logic414. TheSPT control logic414 generates a series of control signals on a set of control lines CNTRL that are coupled to portions of theIC110 to carry out thetest command540. The test mode continues and successive test commands are decoded by theSPT decoder412 on successive pulses of the SPT clock signal SPT_CLK until the reset/power-down signal RP* falls below the supervoltage as detected by the highvoltage detector circuit420, or a command on the data lines data <7:0> controls theCUI410 to end the test mode. At the end of the test mode theCUI410 ceases to generate the SPT clock signal SPT_CLK to disable theSPT decoder412.
• An electrical schematic diagram of anSPT decoder600 circuit is shown inFIG. 6 according to an embodiment of the present invention. TheSPT decoder600 may comprise theSPT decoder412 shown inFIG. 4. TheSPT decoder600 includes three decodingsub-circuits610,612, and614. Each of thedecoding sub-circuits610,612, and614 has a substantially similar structure, and operates in a substantially similar manner, so only thedecoding sub-circuit610 will be described in detail for purposes of brevity.
• A test command on the data lines data <7:0> is decoded by 8 n-channel transistors620,622,624,626,628,630,632, and634 coupled in series in the sub-circuit610, each of the n-channel transistors620-634 having a source/drain diffusion region coupled to a source/drain diffusion region of an adjacent one of the n-channel transistors620-634. The source/drain diffusion regions of the n-channel transistors620-634 comprise an electrically coupledline640 that is conductive when all of the n-channel transistors620-634 are switched on and the coupledline640 carries a signal representing the decoded test command. The coupledline640 is coupled to the supply voltage V_CCthrough a p-channel transistor642 having a control gate coupled to theground voltage V_SS644. The sub-circuit610 is enabled by an n-channel transistor650 having source/drain diffusion regions coupled between a source/drain diffusion region of thetransistor620 and theground voltage V_SS644. A control gate of thetransistor650 is coupled to receive the SPT clock signal SPT_CLK. A control gate of each one of the n-channel transistors620-634 is connected to one line of the data lines data <7:0> and datab <7:0>. In alternate embodiments of the present invention, there may be more or less than 8 data lines carrying the test command, and more or less than 9 n-channel transistors in thesubcircuits610,612, and614.
• The coupledline640 carries a voltage signal indicating whether the sub-circuit610 has decoded a test command on the data lines data <7:0>, and this signal is inverted by aninverter656 and latched by a flip-flop circuit660 comprising two cross-coupled NOR gates. The flip-flop circuit660 receives the inverted signal on aSET line661 and is reset from aRESET line662. The flip-flop circuit660 has an output signal that is inverted by aninverter670 into an SPT signal.
• The sub-circuit610 decodes a test command on the data lines data <7:0> in the following manner. Most of the time the SPT clock signal SPT_CLK is low such that thetransistor650 is switched off, and the coupledline640 is charged to a high signal from the supply voltage V_CCthrough thetransistor642 that is switched on by theground voltage V_SS644. The high signal on the coupledline640 is inverted by theinverter656 into a low signal that does not change the state of the flip-flop circuit660. However, thetransistor650 is switched on during a high pulse of the SPT clock signal SPT_CLK (generated as described above) to couple the n-channel transistors620-634 to theground voltage V_SS644. Each of the n-channel transistors620-634 has a control gate coupled to one of the data lines data <7:0> and datab <7:0>. The data lines data <7:0> carry a command represented by a byte of 8 0's and 1's. Each of the n-channel transistors620-634 is switched on if its control gate is coupled to a data line carrying a 1. This transistor can be switched on by being coupled to a 1 on a line in the data lines data <7:0>. The transistor can also be switched on by being coupled to a 1 on one of the data lines datab <7:0> that has been inverted from a 0 on the corresponding line in the data lines data <7:0>. The connections of the control gates of the n-channel transistors620-634 form a pattern that recognizes a specific command on the data lines data <7:0>. If the pattern of connections of the control gates of the n-channel transistors620-634 is such that the test command on the data lines data <7:0> switches on all of the n-channel transistors620-634 during the high pulse of the SPT clock signal SPT_CLK, then the coupledline640 is discharged through thetransistor650 to theground voltage V_SS644, and goes to a low signal. The low signal on the coupledline640 is inverted by theinverter656 to a high signal that sets the output of the flip-flop circuit660 to a low signal. The low signal is inverted by theinverter670 to a high SPT signal that is coupled to theSPT control logic414 to cause the test command to be executed in theIC110. At the end of the high pulse of the SPT clock signal SPT_CLK, thetransistor650 is switched off and the coupledline640 is charged again to a high signal from the supply voltage V_CCthrough thetransistor642. The high signal is inverted by theinverter656 into a low signal that does not change the state of the flip-flop circuit660. A test command of 00010001 on the data lines data <7:0> is recognized and decoded by the sub-circuit610, and the receipt of the test command is latched in the flip-flop circuit660 until the flip-flop circuit660 is reset.
• The sub-circuit612 has an arrangement of n-channel transistors672,674,676,678,680,682,684,686, and688, a p-channel transistor690, and aninverter692 that is substantially the same as the arrangement of elements in the sub-circuit610, and is similarly coupled to a flip-flop circuit694 and an inverter696. However, control gates of the n-channel transistors674-688 are connected to the data lines data <7:0> and datab <7:0> in a different pattern such that the sub-circuit612 will recognize and decode a test command of 00010010 on the data lines data <7:0> that is different from the test command recognized by the sub-circuit610. The sub-circuit612 will cause its own high SPT signal to be generated from the inverter696 when it recognizes and decodes its own designated test command.
• The sub-circuit614 has the same arrangement of transistors and inverters as the sub-circuit610, but control gates of its transistors are connected only to the data lines datab <7:0>. The sub-circuit614 will generate a high signal to be coupled to an input of a single NORgate697 when a test command of only 0's is present on the data lines data <7:0>. The test command of 8 0's indicates that the flip-flop circuits660 and694 are to be reset by a high signal on theRESET line662. The high signal at the input of the NORgate697 causes the NORgate697 to generate a low signal that is inverted by aninverter698 to a high signal on theRESET line662. The high signal on theRESET line662 causes the SPT signals generated by the flip-flop circuits660 and694 and therespective inverters670 and696 to go low. The high signal on theRESET line662 erases the results of the decoded test commands that may have been previously latched by the flip-flop circuits660 and694.
• Aninverter699 in theSPT decoder600 has an input coupled to receive the reset/power-down signal RP*. An output of theinverter699 is coupled to an input of the NORgate697 and remains low as long as the reset/power-down signal RP* is high, such as at the supervoltage. However, when the reset/power-down signal RP* goes low theinverter699 couples a high signal to the input of the NORgate697 resulting in a low signal at the input of theinverter698 and a high signal on theRESET line662 that resets the flip-flop circuits660 and694.
• One of the advantages of theSPT decoder600 is that the test commands that arrive in succession, one after the other, on the data lines data <7:0> are decoded in succession, and the results of the decoded test commands are stored or latched in the flip-flop circuits660 and694 until they are reset by a high signal on theRESET line662. A record of the test commands received so far is thereby stored and made available to theSPT control logic414 in the form of the high SPT signals. The high SPT signals are available in parallel and concurrently.
• Another advantage of theSPT decoder600 is that there are more n-channel transistors than p-channel transistors in each of the sub-circuits610,612, and614. The sub-circuits610,612, and614 are fabricated with ratioed logic, which is logic that contains a ratio of n-channel transistors to p-channel transistors. The ratioed logic takes up a smaller space in an integrated circuit than logic that contains an equal number of p-channel and n-channel transistors. TheSPT decoder600 is therefore compact.
• TheSPT decoder600 may contain more than the threesub-circuits610,612, and614. In fact, theSPT decoder600 may contain dozens and even hundreds of sub-circuits similar to thesub-circuits610,612, and614 in alternate embodiments of the present invention. There may be as many sub-circuits as there are available test commands in theSPT decoder600. Some of the sub-circuits may not be used as the design of theSPT decoder600 is modular and employs a flexible placement of vias as will be described hereinbelow. The flexible placement of vias allow the design of theSPT decoder600 to be used in a variety of applications that require the decoding of different sets of test commands. The test commands to be decoded are selected by a via mask that is used in the fabrication of theSPT decoder600 as will be described hereinbelow. The unused sub-circuits are also available during debugging of a device with theSPT decoder600. Additional tests or functions can be made available by fabricating the same design of theSPT decoder600 with a new via mask that assigns new test commands to be decoded by the additional sub-circuits. Ablock710 of sub-circuits is shown inFIG. 7A according to an embodiment of the present invention. Theblock710 may include hundreds of sub-circuits. Each of the sub-circuits in theblock710 is similar to one of the sub-circuits610,612, and614 shown inFIG. 6. Some of the sub-circuits in theblock710 may have vias selected such that they are used to decode different test commands, and others of the sub-circuits may not be used.
• An electrical schematic diagram of anSPT decoder714 circuit is shown inFIG. 7B according to an embodiment of the present invention. TheSPT decoder714 includes ablock716 of sub-circuits similar to theblock710 shown inFIG. 7A. A sub-circuit718 and a sub-circuit720 are similar to thesub-circuits610,612, and614 shown inFIG. 6. A flip-flop circuit722 is coupled to the sub-circuit718 and is similar to the flip-flop circuits660 and694 shown inFIG. 6. A NORgate726 and aninverter728 are coupled to the sub-circuit720 to generate a high signal on aRESET line730. The NORgate726 and theinverter728 are coupled to the sub-circuit720 in a manner similar to the coupling of the NORgate697 and theinverter698 shown inFIG. 6. The sub-circuit720 causes a high signal on theRESET line730 by decoding a test command 11011001 on the data lines data <7:0>. The high signal on theRESET line730 resets the flip-flop circuit722 and flip-flop circuits in theblock716.
• An electrical schematic diagram of anSPT decoder734 circuit is shown inFIG. 7C according to an embodiment of the present invention. TheSPT decoder734 is similar to theSPT decoder600 shown inFIG. 6 and has a similar arrangement of sub-circuits and flip-flop circuits. One difference is that the bottom-most sub-circuit shown inFIG. 7C will decode a test command 11010111 that results in a high signal on a RESET line that resets flip-flop circuits in theSPT decoder734 coupled to the RESET line.
• An electrical schematic diagram ofbuffer circuits740 are shown inFIG. 7D according to an embodiment of the present invention. Thebuffer circuits740 may be used in any one of theSPT decoders600,714, and734 described above. The buffer circuits include inverters and NOR gates.
• A block diagram800 of a layout of theSPT decoder600 is shown inFIG. 8 according to an embodiment of the present invention. Portions of theSPT decoder600 that were shown inFIG. 6, such as many of the n-channel transistors, are not shown inFIG. 8 for purposes of brevity. Elements and devices that are common toFIG. 6 andFIG. 8 have been given the same reference numerals for purposes of brevity. Several layers of the layout are shown in the block diagram800 including n-type and p-type diffusion regions, doped polysilicon, two layers of metal, contacts, and vias. Contacts and vias described herein are structures of a conductive material such as metal that are formed in contact with elements in an integrated circuit to couple signals between the elements as is known to those skilled in the art. All of the elements shown inFIG. 8 are formed in or on a p-type silicon substrate. Symbols for a contact, a via, and doped polysilicon are shown at the bottom ofFIG. 8 and are followed inFIG. 8 to represent those elements without specific reference numerals.
• Thetransistors620,634,642,650,672,674,688, and690 shown inFIG. 6 are also shown in the layout ofFIG. 8, outlined by dashed lines. Doped polysilicon is shown as blocks with cross-hatching, and the control gates of the respective transistors may comprise a doped polysilicon gate or a doped polysilicon gate coupled through a contact to a metal gate. The control gates of thetransistors620 and674 are coupled by respective vias to a metal line which forms the data line datab [7]. The control gate of thetransistor634 is coupled by a via to a metal line which forms the data line data [0]. The control gate of thetransistor688 is coupled by a via to a metal line which forms the data line datab [0]. A break in the middle ofFIG. 8 indicates where other n-channel transistors shown inFIG. 6 would have been located in the layout ofFIG. 8, but have been removed for purposes of brevity. The n-channel transistors not shown inFIG. 8 for purposes of brevity have substantially the same structure as the n-channel transistors shown inFIG. 8.
• Source/drain diffusion regions of thetransistors642 and690 are formed in two p-type diffusion regions PMOAT802 and804 that have been formed in an n-type diffusion region NWELL806. Thetransistors642 and690 have a common doped polysilicon gate that is coupled to the ground voltage V_SS(not shown). ThePMOATs802 and804 are each formed in two sections on either side of, but not under, the doped polysilicon gate of thetransistors642 and690. One side of each of thePMOATs802 and804 is coupled through a contact to a metal line carrying the supply voltage V_CC.
• Adjacent source/drain diffusion regions in thetransistors620,634, and650 are formed in a n-typediffusion region NMOAT810 that is formed in sections between, but not under, the control gates of thetransistors620,634, and650. TheNMOAT810 comprises the coupledline640 shown inFIG. 6. Similarly, adjacent source/drain diffusion regions in thetransistors672,674, and688 are formed in a n-typediffusion region NMOAT812 that is formed in sections between, but not under, the control gates of thetransistors672,674, and688. A metal line carrying the SPT clock signal SPT_CLK is coupled by contacts to the control gates of thetransistors650 and672, and a metal line carrying theground voltage V_SS644 is coupled by contacts to theNMOATs810 and812 in source/drain diffusion regions of thetransistors650 and672. TheNMOAT810 is coupled to thePMOAT802 by contacts and a connectingmetal line820 that has ametal connection822 to an inverter (not shown). Similarly, theNMOAT812 is coupled to thePMOAT804 by contacts and a connectingmetal line830 that has ametal connection832 to an inverter (not shown). Those skilled in the art will understand that, in view of the layout of theSPT decoder600 shown inFIG. 8, that theSPT decoder600 is compact and takes up little space in a substrate.
• The separate layers shown inFIG. 8 are listed as follows. The NWELL806, theNMOATs810 and812, and thePMOATs802 and804 are separate layers. The doped polysilicon gates of thetransistors620,634,642,650,672,674,688, and690 are a separate layer. A first metal layer includes the line carrying the SPT clock signal SPT_CLK, the line carrying theground voltage V_SS644, the line carrying the supply voltage V_CC, the metal gates of thetransistors620,634,674, and688, thelines820 and830, and theconnections822 and832. Finally, a second metal layer includes the line carrying theground voltage V_SS644, the line carrying the supply voltage V_CC, and the data lines data [7], datab [7], data [0], and datab [0].
• The control gates of thetransistors620,634,674, and688 can each be connected to one of the data lines data <7:0> or one of the data lines datab <7:0> by using a selected placement of vias. The selection of the location of vias during the fabrication of theSPT decoder600 determines which test commands will be decoded by thesub-circuits610 and612 in theSPT decoder600, and also determines which sub-circuit,610 or612, will decode each test command. This is because the test command recognized and decoded by a sub-circuit to start the generation of an SPT signal is determined by the pattern of connections of the control gates of its n-channel transistors with the data lines data <7:0> and datab <7:0>, as described above.
• Across-sectional view1000 of a portion of theSPT decoder600 is shown inFIG. 9 according to an embodiment of the present invention. Thecross-sectional view1000 is taken along line9-9 shown inFIG. 8. Symbols for metal, a via, doped polysilicon, and a contact are shown at the bottom ofFIG. 9 and are followed inFIG. 9 to represent those elements without specific reference numerals. TheSPT decoder600 is fabricated with multiple layers on asilicon substrate1010. The layers shown inFIG. 9 are listed as follows. Layers of silicon dioxide (SiO₂)1020 on thesubstrate1010 are placed around a dopedpolysilicon gate1040 of thetransistor634 shown inFIG. 8. Ametal gate1050 of thetransistor634 is part of a first metal layer, and is coupled to the dopedpolysilicon gate1040 through acontact1052. Afirst metal line1060 forming the data line data [0] and asecond metal line1080 forming the data line datab [0] are part of a second metal layer. A via1082 is placed in contact with thefirst metal line1060 and themetal gate1050 of thetransistor634 to couple them such that thetransistor634 is switched on or off by a signal on the data line data [0]. Thesecond metal line1080 is separated from themetal gate1050 by the layers of silicon dioxide (SiO₂)1020. The removal of the silicon dioxide (SiO₂)1020 and the fabrication of the via1082 with metal is carried out in a manner known to those skilled in the art. A layer of silicon dioxide (SiO₂)1090 protects the second metal layer and separates thefirst metal line1060 from thesecond metal line1080.
• Across-sectional view1096 of a portion of theSPT decoder600 is shown inFIG. 10 according to another embodiment of the present invention. Thecross-sectional view1096 is taken along line9-9 shown inFIG. 8, and is similar to thecross-sectional view1000 shown inFIG. 9. Similar elements have been given the same reference numerals, and will not further described herein for purposes of brevity. Thecross-sectional view1096 ofFIG. 10 is modified in that the via1082 is placed in contact with thesecond metal line1080 and themetal gate1050 of thetransistor634 to couple them such that thetransistor634 is switched on or off by a signal on the data line datab [0]. Thefirst metal line1060 is separated from themetal gate1050 by the layers of silicon dioxide (SiO₂)1020.
• Thefirst metal line1060 and thesecond metal line1080 are located in proximity to themetal gate1050 such that the via1082 may be formed between thefirst metal line1060 and themetal gate1050 as shown inFIG. 9, or between the second-metal line1080 and themetal gate1050 as shown inFIG. 10. More specifically, both thefirst metal line1060 and thesecond metal line1080 are separated from themetal gate1050 by a thickness of the silicon dioxide (SiO₂)1020 that is substantially the same as a dimension of the via1082 to allow the formation of the via1082 between thefirst metal line1060 and themetal gate1050 as shown inFIG. 9, or between thesecond metal line1080 and themetal gate1050 as shown inFIG. 10. The via1082 is selectively placed to couple themetal gate1050 to either the data line data [0] or the data line datab [0]. This selection is made during a fabrication of theSPT decoder600. With respect to theentire SPT decoder600,FIGS. 8, 9, and10 illustrate a flexible placement of vias in the layout of theSPT decoder600. Corresponding pairs of data lines data <7:0> and datab <7:0> are located in proximity to control gates of multiple n-channel transistors in theSPT decoder600 to allow for a flexible placement of vias between the data lines data <7:0> and datab <7:0>.
• The flexible placement of vias in the layout of theSPT decoder600 provides for flexibility in several ways. Different systems may use different test commands to carry out the same tests and procedures on theIC110. The flexible placement of vias permit theSPT decoder600 to be customized during fabrication to respond to the test commands used by the system it will be coupled to. The flexible placement of vias make theSPT decoder600 useful in a library of semiconductor circuits that are available for use in a wide range of systems. A circuit designer may select theSPT decoder600 and choose the location of the vias to make it a useful part of a new system without having to go to the time and expense of designing a new decoder circuit from the ground up. The flexible placement of vias allow the use of fewer sub-circuits in theSPT decoder600 because they can be modified to recognize different test commands. Without the flexible placement of vias, more sub-circuits would be needed to accommodate a wider range of potential test commands. This advantage contributes to the small, compact size of theSPT decoder600. Finally, the flexible placement of vias allow for the addition of new test commands to trigger new, additional tests or other events if a test of theSPT decoder600 reveals the need for such additional measures. This situation occurs during “debugging” of theSPT decoder600 in a system.
• Anintegrated circuit chip1100 according to an embodiment of the present invention is shown inFIG. 11. Thechip1100 includes an embeddedflash memory1110 such as the flash memory integrated circuit (IC)110, and may include thetest mode decoder400 and one or more of theSPT decoders600,714, and734 according to the embodiments of the present invention described above. The embeddedflash memory1110 shares thechip1100 with anotherintegrated circuit1120 such as a processor, or possibly several other integrated circuits. The processor may also include thetest mode decoder400 and one or more of theSPT decoders600,714, and734. The embeddedflash memory1110 and theintegrated circuit1120 are coupled together by a suitable communication line orbus1130.
• One skilled in the art having the benefit of this description will understand that more than one flash memory integrated circuit (IC)110 according to the embodiments of the present invention described above may be included in various package configurations. For example, a compactflash memory card1200 according to an embodiment of the present invention is shown inFIG. 12. Thecard1200 includes a plurality of flash memory integrated circuits1210(1)-1210(X) each of which are similar to the flash memory integrated circuit (IC)110 shown inFIG. 1. Thecard1200 may be a single integrated circuit in which the flash memory integrated circuits1210(1)-1210(X) are embedded.
• FIG. 13 is a block diagram of an information-handling system1300 according to an embodiment of the present invention. The information-handling system1300 includes amemory system1308, aprocessor1310, adisplay unit1320, and an input/output (I/O)subsystem1330. Theprocessor1310 may be, for example, a microprocessor. Thememory system1308 is comprised of the flash memory integrated circuit (IC)110. Theprocessor1310 and/or thememory system1308 may include thetest mode decoder400 and one or more of theSPT decoders600,714, and734 according to the embodiments of the present invention described above. The I/O subsystem1330 may be a keyboard or other device to allow the user to communicate with thesystem1300. Theprocessor1310 and thememory system1308 may be embedded on a single integrated circuit chip such as thechip1100 shown inFIG. 11. Theprocessor1310, thedisplay unit1320, the I/O subsystem1330, and thememory system1308 are coupled together by a suitable communication line orbus1340.
• In various embodiments of the present invention, the information-handling system1300 is a computer system (such as, for example, a video game, a hand-held calculator, a television set-top box, a fixed-screen telephone, a smart mobile phone, a personal digital assistant (PDA), a network computer (NC), a hand-held computer, a personal computer, or a multiprocessor supercomputer), an information appliance (such as, for example, a cellular telephone, a pager, or a daily planner or organizer, or any wireless device), an information component (such as, for example, a magnetic disk drive or telecommunications modem), or other appliance (such as, for example, a television, a hearing aid, washing machine or microwave oven having an electronic controller).
• Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art having the benefit of this description that any equivalent arrangement may be substituted for the specific embodiments shown. For example, those skilled in the art having the benefit of this description will understand that thetest mode decoder400 and theSPT decoders600,714, and734 according to the embodiments of the present invention described above may be used in any type of circuit to put that circuit into a special mode and to decode special commands to be used by that circuit. For example, a memory device or a processor may include thetest mode decoder400 and one or more of theSPT decoders600,714, and734 according to the embodiments of the present invention described above. The present invention is therefore limited only by the claims and equivalents thereof.

Claims (29)

1. An integrated circuit fabrication method, comprising:

forming a dielectric layer on a substrate;

forming a control gate in the dielectric layer;

forming a metal, first line on the dielectric material such that the first line is spaced from the control gate by a dimension;

forming a conductive, second line on the dielectric material such that the second line is spaced from the control gate by the dimension; and

forming a signal connection between the control gate and the first line.

2. The method ofclaim 1, wherein forming a dielectric layer on a substrate comprises forming a silicon dioxide layer on a silicon substrate.

3. The method ofclaim 2, wherein forming a control gate in the dielectric layer includes forming a doped polysilicon gate in the silicon dioxide layer, forming a first metal layer in the silicon dioxide layer, and forming a contact between the doped polysilicon gate and the first metal layer to couple a signal from the first metal layer to the doped polysilicon gate.

4. The method ofclaim 3, wherein forming the signal connection includes forming a via having the dimension and filling the via with a metal.

5. The method ofclaim 4, wherein forming the silicon dioxide layer includes separating the first metal line from the second metal line.

6. A method of fabricating an integrated circuit, comprising:

forming a dielectric layer on a substrate;

forming a control gate in the dielectric layer;

forming a conductive, first line formed on the dielectric material layer above the control gate and separated from the control gate by a thickness of the dielectric layer;

forming a conductive, second line on the dielectric material layer above the control gate and separated from the control gate by the thickness of the dielectric layer; and

forming a signal connection in a via extending between and in contact with the control gate and one of the first line and the second line to couple signals between the control gate and the one of the first line and the second line, the via having a dimension substantially the same as the thickness of the dielectric layer.

7. The method ofclaim 6, wherein forming a dielectric layer on a substrate comprises forming a silicon dioxide layer on a silicon substrate.

8. The method ofclaim 6, wherein forming a control gate comprises:

forming a doped polysilicon gate in the dielectric layer;

forming a metal gate in the dielectric layer; and

forming a contact between the doped polysilicon gate and the metal gate.

9. The method ofclaim 6, wherein forming the signal connection includes forming a via in the dielectric layer and inserting a metal in the via.

10. The method ofclaim 6, wherein forming a dielectric layer includes electrically separating the first line and the second line.

11. The method ofclaim 6, wherein the dimension of the via is a height dimension extending vertically from the substrate.

12. The method ofclaim 11, wherein forming the signal connection in the via includes selectively placing the via during fabrication based on the required test commands to be decoded by the integrated circuit.

13. The method ofclaim 12, wherein forming the first line comprises coupling the first line to a first one of an inverted data line and a non-inverted data line, and wherein forming the second line comprises coupling the second line to a second one of an inverted data line and a non-inverted data line.

14. A method of operating a memory device, comprising:

storing control parameters for a memory device in a non-volatile data storage unit in response to receiving a test mode signal;

operating the memory device using the stored control parameters to adjust the operation of the memory device, including;

writing data to a selected one memory cell of a plurality of memory cells forming the memory device by holding a source of the memory cell at a reference voltage, holding a drain of the memory cell at a power voltage, and applying a high power voltage to a gate of the memory cell for a first predetermined time period;

reading data stored in the selected one memory cell by holding the source at the reference voltage, holding the drain at a low power voltage, and applying the power voltage to the gate for a second predetermined time period;

erasing data store in the selected one memory cell by holding the source to the high voltage level for a third predetermined time period, disconnecting the drain from voltage sources, and holding the gate to the reference voltage.

15. The method ofclaim 14, wherein receiving the test mode signal includes receiving a test mode signal pulse at a voltage level higher than signal voltages present in the memory device.

16. The method ofclaim 15, wherein receiving the test mode signal includes at least one of a reset/power down signal and a write enable signal.

17. The method ofclaim 15, wherein receiving the test mode signal includes detecting the voltage level of a reset/power down signal with a high voltage detector before receiving the signal at a command user interface.

18. The method ofclaim 15, wherein receiving the test mode signal includes detecting a super voltage level of the reset/power down signal, detecting a first coincident write enable pulse during the super voltage level and a first command signal, and detecting a second coincident enable pulse during the super voltage level and a second command signal;

placing the memory device in a test mode in response to the super voltage, the first command signal and the second command signal.

19. The method ofclaim 18, wherein placing the memory device in test mode includes generating a test mode clock signal, receiving a plurality of test mode command signals on a plurality of test mode input data lines, and decoding the plurality of test mode command signals.

20. The method ofclaim 14, wherein the reference voltage level is approximately ground, the low power voltage is about 1.0 volts, the power voltage is from about 5 to 7 volts, and the high power voltage is from 10 to 12 volts.

21. The method ofclaim 18, wherein the test mode command signals include at least one of:

reference voltage level, low power voltage level, power voltage level, high power voltage level, the length of time of the first, second and third predetermined time periods;

the magnitude and duration of programming pulses, read pulses, write pulses, erase pulses and heal pulses;

the word length of information stored in the plurality of memory cells forming the memory device;

top addressing and bottom addressing the information stored in the plurality of memory cells forming the memory device; and

the configuration of the plurality of memory cells forming the memory device.

22. A method of operating a memory device, comprising:

storing control parameters for a memory device in a non-volatile data storage unit in response to receiving a test mode signal;

operating the memory device using the stored control parameters to adjust the operation of the memory device;

receiving a plurality of test command signals on a plurality of input data lines after receiving the test mode signal;

decoding the test command signals during a first pulse of a test mode clock signal;

wherein receiving the test mode signal includes:

receiving a super voltage signal on a reset signal line;

receiving at least one write enable signal during a duration of the super voltage signal on the reset line;

receiving a first command during a first write enable pulse, and decoding the first command;

receiving a second command during a second write enable pulse, and decoding the second command; and

determining if the first and second command constitute a test mode signal.

23. The method ofclaim 22, wherein the test mode clock signal is coincident with at least one of the at least one write enable signals.

24. The method ofclaim 22, wherein decoding the test command signals includes:

coupling the test command signals on the plurality of input data lines after receiving the test mode signal to a plurality of non-inverting data lines to be non-inverted test command signals;

inverting the test command signals to generate a plurality of inverted test command signals and coupling to a plurality of inverted data lines;

coupling a voltage source through a p-channel transistor to a line connected to a plurality of source/drain diffuision regions of a first n-channel transistor, seven middle n-channel transistors and a last n-channel transistor, wherein all the n-channel transistors are coupled in a series of connected source/drain diffusion regions;

coupling the test mode clock signal to a gate region of the first n-channel transistor; and

coupling a selected one of the inverted or non-inverted test command signals to a selected one of the seven middle n-channel transistors and the last n-channel transistor forming a unique pattern of test command signals that will switch on all of the seven middle n-channel transistors and the last n-channel transistor to decode the command signal.

25. The method ofclaim 24, wherein switching on all of the seven middle n-channel transistors and the last n-channel transistor to decode the command signal includes setting one of a latch and a non-volatile memory cell to a preselected state to indicate that the test command signal has been decoded.

26. The method ofclaim 25, wherein the memory device exchanges signals with at least one of a processor, a memory controller, a display unit, a user interface, a bus, and an input/output system.

27. The method ofclaim 26, wherein the signals exchanged include at least one of an address signal, a data signal, a chip enable signal, a write protect signal, a refresh signal, a heal signal, an erase signal, a program signal, and output enable signal, a write enable signal, and a status signal.

28. The method ofclaim 27, wherein the signals are exchanged between devices embedded on the same integrated circuit chip as the memory device.

29. The method ofclaim 24, wherein the device comprises more n-channel devices than p-channel devices.

Images