US20050274994A1 - High dielectric constant spacer for imagers - Google Patents

Abstract

An imager having gates with spacers formed of a high dielectric material. The high dielectric spacer provides larger fringing fields for charge transfer and improves image lag and charge transfer efficiency.

Description

FIELD OF THE INVENTION
• The invention relates generally to a method and apparatus relating to a pixel array of an imager. In particular, the invention relates to imagers having pixels with an improved gate structure.
BACKGROUND
• Typically, a digital imager array includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, e.g. a photogate, photoconductor, or a photodiode. In a CMOS imager a readout circuit is connected to each pixel cell which typically includes a source follower output transistor. The photoconversion device converts photons to electrons which are typically transferred to a floating diffusion region connected to the gate of the source follower output transistor. A charge transfer device (e.g., transistor) can be included for transferring charge from the photoconversion device to the floating diffusion region. In addition, such imager cells typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as an output signal by a row select transistor.
• Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.
• FIG. 1 illustrates a block diagram of an exemplaryCMOS imager device308 having apixel array200 with each pixel cell being constructed as described above.Pixel array200 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row inarray200 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for theentire array200. The row lines are selectively activated by arow driver210 in response torow address decoder220. The column select lines are selectively activated by acolumn driver260 in response tocolumn address decoder270. Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the timing andcontrol circuit250, which controlsaddress decoders220,270 for selecting the appropriate row and column lines for pixel readout. Thecontrol circuit250 also controls the row andcolumn driver circuitry210,260 such that these apply driving voltages to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal (V_rst) and a pixel image signal (V_sig), are read by a sample and holdcircuit261 associated with thecolumn device260. A differential signal (V_rst−V_sig) is produced bydifferential amplifier262 for each pixel which is digitized by analog-to-digital converter275 (ADC). The analog-to-digital converter275 supplies the digitized pixel signals to animage processor280, which forms a digital image.
• In a digital CMOS imager, when incident light strikes the surface of a photoconversion device, e.g., a photodiode, electron/hole pairs are generated in the p-n junction of the photodiode. The generated electrons are collected in the n-type region of the photodiode. The photo charge moves from the initial charge accumulation region to the floating diffusion region or it may be transferred to the floating diffusion region via a transfer transistor. The charge at the floating diffusion region is typically converted to a pixel output voltage by a source follower transistor (described above).
• Image lag can be a problem for imagers, whether the imager is a CMOS, CCD or other type of imager. Image lag can occur, for example, in CMOS image sensor pixels using transfer transistors to transfer charge from the photodiode to the floating diffusion region. There is a potential barrier corresponding to the photodiode/transfer gate region. If this potential barrier is too high, a portion of the charge will be unable to move from the photodiode to the floating diffusion region. The greater the potential barrier, the less charge will be transferred to the floating diffusion region. A potential barrier in the photodiode/transfer gate region may cause incomplete charge transfer reducing the charge transfer efficiency (CTE) of the pixel cell. Charge remaining in the photodiode from a prior image can affect a subsequent image, causing image lag, where a ghost image from the initial charge is apparent in a subsequent image.
• Fringing fields improve charge transfer from a photoconversion device, e.g. a photodiode, to a charge collection region. Conventional imagers typically utilize low dielectric (K) oxide spacers for transistor gates, which create smaller fringing fields. A larger fringing field in, for example, a transfer gate of a CMOS imager would improve charge transfer from the photodiode to the floating diffusion region. This would thereby reduce image lag because more carriers are transferred. In CCD imagers, larger fringing fields improve charge transfer efficiency (CTE) in addition to improving image lag characteristics.
• CCD devices that use overlapping polysilicon1 and polysilicon2 electrodes achieve a high fringing field by applying high voltages to the polysilicon electrodes. This is not desireable on CMOS imagers which are advantageously low voltage devices so they will compatible with CMOS logic circuit and devices. Another imager device, the single polysilicon CCD imager does not have overlapping polysilicon electrodes and could also benefit from a method to achieve high fringing fields to achieve improved charge transfer. Thus, there is a desire and need to increase fringing fields and thereby improve charge transfer and reduce image lag in imager devices.
SUMMARY
• Embodiments of the invention provide an imager having gates with spacers formed of a high dielectric constant material. The high dielectric spacers provide larger fringing fields for charge transfer and also improve image lag and charge transfer efficiency.
DESCRIPTION OF THE DRAWINGS
• Additional features of the present invention will be apparent from the following detailed description and drawings which illustrate exemplary embodiments of the invention, in which:
• FIG. 1 is a block diagram of a conventional imager device having a pixel array;
• FIG. 2 is a cross-sectional view of a portion of a pixel of an image sensor according to an embodiment of the invention;
• FIG. 3 shows a cross-sectional view of a portion of theFIG. 2 photodiode during an initial stage of processing performed in accordance with a method of the invention;
• FIG. 4 shows a stage of processing subsequent to that shown inFIG. 3;
• FIG. 5 shows a stage of processing subsequent to that shown inFIG. 4;
• FIG. 6 shows a stage of processing subsequent to that shown inFIG. 5;
• FIG. 7 shows a stage of processing subsequent to that shown inFIG. 6;
• FIG. 8 shows a stage of processing subsequent to that shown inFIG. 7;
• FIG. 9 shows a stage of processing subsequent to that shown inFIG. 8;
• FIG. 10 shows a stage of processing subsequent to that shown inFIG. 9;
• FIG. 11 is a cross-sectional view of a portion of a pixel of an image sensor according to another embodiment of the invention;
• FIGS. 12a,12band12care cross-sectional views of a portion of a pixel of an image sensor according to another embodiment of the invention; and
• FIG. 13 is a schematic diagram of a processing system employing an imager constructed in accordance with any of the various embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
• In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and show by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical, and electrical changes may be made without departing from the spirit and scope of the present invention. The progression of processing steps described is exemplary of embodiments of the invention; however, the sequence of steps is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps necessarily occurring in a certain order.
• The terms “wafer” and “substrate,” as used herein, are to be understood as including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous processing steps may have been utilized to form regions, junctions, or material layers in or over the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, gallium arsenide or other semiconductors.
• The term “pixel,” as used herein, refers to a photo-element unit cell containing a photoconversion device and associated transistors for converting photons to an electrical signal. For purposes of illustration, a single representative pixel and its manner of formation is illustrated in the figures and description herein; however, typically fabrication of a plurality of like pixels proceeds simultaneously. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
• In the following description, the invention is described in relation to CMOS and CCD imagers for convenience; however, the invention has wider applicability to other solid state imagers. Now referring to the figures, where like reference numbers designate like elements,FIG. 2 illustrates a pixel sensor cell of a CMOS imager constructed in accordance with a first exemplary embodiment of the invention. Aphotoconversion device50 is formed in asubstrate60 having a doped layer or well61, which for exemplary purposes is a p-type well. The illustratedphotoconversion device50 is a photodiode and may be a p-n junction photodiode, npn photodiode, a photoconductor, a Schottky photodiode, or any other suitable photodiode, but for exemplary purposes is discussed as a p-n-p photodiode. In addition and for exemplary purposes only,substrate60 is a p-type substrate and well61 is a p-type well.
• The illustratedphotodiode50 consists of a p+region22 and an n-type region24. The remaining structures shown inFIG. 2 include a transfer transistor with associatedgate26 and a reset transistor with associatedgate28. Floatingdiffusion region16, source/drain region30 and shallow trench isolation (STI)regions55 are also shown. Asource follower transistor40 and rowselect transistor42 with associated gates are also included in the pixel sensor cell, but are depicted in electrical schematic form with the output of the rowselect transistor40 being connected with acolumn line31. Although shown inFIG. 2 as a four-transistor (4T) configuration with a transfer transistor and associatedgate26, the invention can also be utilized in a three-transistor (3T) configuration, without a transfer transistor, and in pixels with other transistor configurations (e.g., 2T, 5T, 6T, 7T, etc.).
• In the exemplary embodiment shown inFIG. 2, a high dielectric constant material is used for the spacer layers43 of the transfer transistor and associatedgate26. Although shown in this embodiment as being utilized in association with a transfer transistor, the high dielectric constant spacers may be used as spacer material for any other transistor in the image sensor. Any suitable material having a high dielectric constant may be used for thespacer layer43. The spacer material should be an insulator material and should have a dielectric constant higher than silicon dioxide. Examples of high dielectric constant materials which may be used to form thespacer layer43 are materials having a dielectric constant of greater than 3.9, and including but not limited to, aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), tantalum oxide (Ta₂O₃), barium strontium titanate ((BaSr)TiO₃also known as BST) and silicon nitride (Si₃N₄).
• FIGS. 3-10 show one exemplary method of forming a pixel sensor cell with a high dielectric constant spacer ofFIG. 2 of the invention at various stages of formation. For convenience, the same cross-sectional view ofFIG. 2 is utilized inFIGS. 3-10 for the ensuing description. In addition, for clarity purposes, the source follower and rowselect transistors40,42 (FIG. 2) are not illustrated but it should be appreciated that they are present in the final pixel sensor cell.
• Referring toFIG. 3, first a p-type silicon substrate60 is provided.Isolation regions55 are formed to electrically isolate regions of the substrate where pixel cells will later be formed. Theisolation regions55, can be formed by any known technique such as thermal oxidation of the underlying silicon in a LOCOS process, or by etching trenches and filling them with oxide in an STI (shallow trench isolation) process.
• FIG. 4 shows a blanket deposition of agate oxide layer38 oversubstrate60.FIGS. 4-9 show the formation of oneexemplary gate stack15 for a transfer transistor which has high dielectric constant (high K) spacers according to an embodiment of the invention. However, more than one gate stack with high K spacers constructed according to the invention may also be formed. For example, embodiments of the invention may be employed on storage transistors, high dynamic range transistors, source follower transistors, row select transistors or global shutter transistors. Gate stacks15 and19 are formed overgate oxide layer38 by conventional methods and have aninsulator layer34 andconductor layer36.Conductor layer36 may be formed of any conductive material andinsulator layer34 may be formed of any insulating material known in the art. Theconductor36 is, for example, poly, polysilicide, poly/WSix₂, poly TiSi₂, poly/WNx/W. The insulator layer may be oxide or a high K material or a sandwich structure of these insulators. Theinsulator layer34 is not required.
• As shown inFIG. 5, if the p-type well61 has not yet been formed, it may be formed by blanket implantation or by masked implantation. P-type well61 may be formed before or after the formation ofisolation regions55 andgate stack15. The p-well implant may be conducted so that the pixel array well61 and a p-type periphery logic well, which will contain logic circuits for controlling the pixel array, have different doping profiles. As known in the art, multiple high energy implants may be used to tailor the profile and position of the p-type well61. The p-type well shown inFIG. 5 is shown as a p-type well formed using a masked ion implantation.
• Formed floatingdiffusion region16 and source/drain region30 are depicted inFIG. 6. The dopedregions16,30 are formed in the p-well61 and are doped to an n-type conductivity in this embodiment. For exemplary purposes,regions16,30 are n+ doped to form an n-channel gate transistor, however,regions16 and30 may also be p-type doped to form a p-channel gate transistor.Regions16,30 may be formed by applying a mask to the substrate and doping theregions16,30 by ion implantation.FIG. 6 also shows n-type implantation ofregion24 by methods known in the art.Doped region16 could also be a n-implanted region.
• FIG. 7 shows the deposition of a high Kdielectric layer43 over gate stacks15,19 andgate oxide layer38.Layer43 may be formed of any material having high dielectric constant properties, including for example, aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), silicon nitride (Si₃N₄), tantalum oxide (Ta₂O₃), and barium strontium titanate ((BaSr)TiO₃). A dual high dielectric constant material spacer may also be used. The thickness of the high Kdielectric layer43 may be in the range of about 100 Å to about 1500 Å, preferably in the range of about 200 Å to about 800 Å. A high dielectric constant material used on the spacers of a transistor, in this embodiment a transfer transistor, creates a larger fringing field in the gate channel of the transistor. The larger fringing field produced by the high dielectric constant spacer on thetransfer transistor gate26 improves charge transfer from thephotodiode50 to the floatingdiffusion region16 and reduces image lag.
• FIG. 8 shows implantation of p-type region22 ofphotodiode50. The implantation of p-type region22 may occur by methods known in the art. A masked spacer etch withmask45, as illustrated inFIG. 9, is performed to remove the high dielectric constant material, except for areas covered bymask45, including a portion of gate stacks15,19 on one side and on a sidewall of gate stacks15,19 on the opposite side. The masked spacer etch step leaves areas of the transfer transistor and associatedgate26 and a sidewall covered with the high dielectricconstant layer43, as shown inFIG. 10. Although described above in conjunction withFIGS. 9 and 10 as a masked spacer etch step, the spacer etch could also be performed without amask45.FIG. 10 also shows a formed reset transistor and associatedgate28.
• The reset transistor or any other transistor may also be formed with or without a high dielectric constant spacers. Alternatively, some transistors of a pixel sensor cell may be formed with a high dielectric constant spacers, while other transistors of the same pixel sensor cell may be formed according to conventional methods with conventional spacers known in the art. In addition, although described above in reference to a CMOS image sensor, the method of forming a gate stack having a high dielectric constant spacer may also be performed on other types of imagers such as for example, a charge coupled device (CCD).
• The pixel sensor cell is essentially complete at this stage, and conventional processing methods may be used to form insulating, shielding, and metallization layers to connect gate lines and other connections to the pixel sensor cells. For example, the entire surface may be covered with apassivation layer88 of, for example, silicon dioxide, BSG, PSG, or BPSG, which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts. Conventional layers of conductors and insulators may also be used to interconnect the structures and to connect the pixel to peripheral circuitry.
• FIG. 11 shows another embodiment of the invention which is similar to the embodiment described above in relation toFIGS. 3-10 except that a blanket spacer etch step is used to remove thedielectric layer43, rather than the masked step shown above inFIG. 9.
• FIG. 12a-cshow embodiments of the invention as applied to a CCD imager. For simplicity, only the transistors are shown.FIGS. 12aand12bdepict a single gate CCD imager with a vertical or horizontal shift register. In the embodiment ofFIG. 12a, the high dielectric material is employed asspacers25, as described above in relation toFIGS. 3-10 except that a blanket spacer etch step is used to remove thedielectric layer43, rather than the masked step shown above inFIG. 9.FIG. 12bshows a single gate CCD imager having high dielectric material assidewalls27.
• FIG. 12cshows an embodiment according to the invention having an overlappinggate32 between two transistor gates on a CCD imager. The embodiment ofFIG. 12chas a firstgate oxide layer35 and a secondgate oxide layer33. High dielectricconstant spacers25 are formed as described above in reference toFIGS. 3-10 with the exception of a blanket spacer etch step instead of the masked step shown inFIG. 9. The gate stacks also have aconductive layer36 and aninsulator layer34, as described above.
• FIG. 13 shows aprocessor system300, which includes an imager device308 (FIG. 1) constructed in accordance with an embodiment of the invention; that is, theimager device308 uses a pixel array having pixels constructed in accordance with the various embodiments of the invention. Theimager device308 may receive control or other data fromsystem300.System300 includes aprocessor302 having a central processing unit (CPU) that communicates with various devices over abus304. Some of the devices connected to thebus304 provide communication into and out of thesystem300; an input/output (I/O)device306 andimager device308 are such communication devices. Other devices connected to thebus304 provide memory, illustratively including a random access memory (RAM)310,hard drive312, and one or more peripheral memory devices such as afloppy disk drive314 and compact disk (CD)drive316. Theimager device308 may be constructed as shown inFIG. 1 with thepixel array200 having the characteristics of the invention as described above in connection withFIGS. 2-12. The invention provides an imager having gates with spacers formed of a high dielectric material. The high dielectric spacers provide larger fringing fields for charge transfer and also improve image lag and charge transfer efficiency. Theimager device308 may, in turn, be coupled toprocessor302 for image processing, or other image handling operations.
• The processes and devices described above illustrate preferred methods and typical devices of many that could be used and produced. The above description and drawings illustrate embodiments, which achieve the objects, features, and advantages of the present invention. However, it is not intended that the present invention be strictly limited to the above-described and illustrated embodiments. Any modifications, though presently unforeseeable, of the present invention that come within the spirit and scope of the following claims should be considered part of the present invention.

Claims (93)

1. A pixel sensor cell comprising:

a photoconversion device; and

at least one gate stack, said at least one gate stack having at least one portion covered by a spacer layer comprising high dielectric constant material.

2. The pixel sensor cell ofclaim 1, wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.

3. The pixel sensor cell ofclaim 1, wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.

4. The pixel sensor cell ofclaim 3, wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.

5. The pixel sensor cell ofclaim 1, wherein said pixel sensor cell is part of a CCD sensor.

6. The pixel sensor cell ofclaim 5, wherein the CCD sensor is a single gate CCD sensor.

7. The pixel sensor cell ofclaim 5, wherein the CCD sensor is an overlapping gate sensor.

8. The pixel sensor cell ofclaim 1, wherein the photoconversion device is selected from the group consisting of a photodiode, a photogate and a photosensor.

9. The pixel sensor cell ofclaim 8, wherein said photodiode is a pnp photodiode.

10. The pixel sensor cell ofclaim 8, wherein said photodiode is an npn photodiode.

11. The pixel sensor cell ofclaim 1, wherein said gate stack is part of an n-channel transistor.

12. The pixel sensor cell ofclaim 1, wherein said gate stack is part of a p-channel transistor.

13. The pixel sensor cell ofclaim 1, wherein said gate stack is formed of a gate oxide layer and a conductor layer.

14. The pixel sensor cell ofclaim 1, wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.

15. The pixel sensor cell ofclaim 13, wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.

16. The pixel sensor cell ofclaim 14, wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.

17. The pixel sensor cell ofclaim 13, wherein said gate oxide layer is a grown layer.

18. The pixel sensor cell ofclaim 17 wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.

19. The pixel sensor cell ofclaim 13, wherein said gate oxide layer is a deposited layer.

20. The pixel sensor cell ofclaim 19, wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.

21. The pixel sensor cell ofclaim 1, wherein said high dielectric constant material spacer has a thickness of about 100 Åto about 1500 Å.

22. The pixel sensor cell ofclaim 1, wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.

23. The pixel sensor cell ofclaim 1, wherein said pixel sensor cell is part of a CMOS imager.

24. An imager integrated circuit comprising:

a doped layer formed in a substrate;

an array of pixel sensor cells formed in said doped layer, wherein each pixel sensor cell has at least one gate stack, said at least one gate stack having at least one portion covered by a spacer layer of high dielectric constant material; and

signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing pixel signals representing an image acquired by the array and for providing output data representing said image.

25. The imager integrated circuit ofclaim 24, wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.

26. The imager integrated circuit ofclaim 24, wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.

27. The imager integrated circuit ofclaim 26, wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.

28. The imager integrated circuit ofclaim 24, wherein said pixel sensor cell is part of a CCD sensor.

29. The imager integrated circuit ofclaim 28, wherein the CCD sensor is a single gate CCD sensor.

30. The imager integrated circuit ofclaim 28, wherein the CCD sensor is an overlapping gate sensor.

31. The imager integrated circuit ofclaim 24, wherein the photoconversion device is selected from the group consisting of a photodiode, a photogate and a photosensor.

32. The imager integrated circuit ofclaim 31, wherein said photodiode is a pnp photodiode.

33. The imager integrated circuit ofclaim 31, wherein said photodiode is an npn photodiode.

34. The imager integrated circuit ofclaim 24, wherein said gate stack is part of an n-channel transistor.

35. The imager integrated circuit ofclaim 24, wherein said gate stack is part of a p-channel transistor.

36. The imager integrated circuit ofclaim 24, wherein said gate stack is formed of a gate oxide layer and a conductor layer.

37. The imager integrated circuit ofclaim 24, wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.

38. The imager integrated circuit ofclaim 36, wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.

39. The imager integrated circuit ofclaim 37, wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.

40. The imager integrated circuit ofclaim 36, wherein said gate oxide layer is a grown layer.

41. The imager integrated circuit ofclaim 40, wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.

42. The imager integrated circuit ofclaim 36, wherein said gate oxide layer is a deposited layer.

43. The imager integrated circuit ofclaim 42, wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.

44. The imager integrated circuit ofclaim 24, wherein said high dielectric constant material spacer has a thickness of about 100 Å to about 1500 Å.

45. The imager integrated circuit ofclaim 24, wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.

46. The imager integrated circuit ofclaim 24, wherein said pixel sensor cell is part of a CMOS imager.

47. A processing system comprising:

a processor; and

an imager coupled to said processor, having pixel sensor cells, wherein each pixel sensor cell has at least one gate stack, said at least one gate stack having at least one portion covered by a spacer layer of high dielectric constant material.

48. The system ofclaim 47, wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.

49. The system ofclaim 47, wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.

50. The system ofclaim 49, wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.

51. The system ofclaim 47, wherein said pixel sensor cell is part of a CCD sensor.

52. The system ofclaim 51, wherein the CCD sensor is a single gate CCD sensor.

53. The system ofclaim 51, wherein the CCD sensor is an overlapping gate sensor.

54. The system ofclaim 47, wherein the photoconversion device is selected from the group consisting of a photodiode, a photogate and a photo sensor.

55. The system ofclaim 54, wherein said photodiode is a pnp photodiode.

56. The system ofclaim 54, wherein said photodiode is an npn photodiode.

57. The system ofclaim 47, wherein said gate stack is part of an n-channel transistor.

58. The system ofclaim 47, wherein said gate stack is part of a p-channel transistor.

59. The system ofclaim 47, wherein said gate stack is formed of a gate oxide layer and a conductor layer.

60. The system ofclaim 47, wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.

61. The system ofclaim 59, wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.

62. The system ofclaim 60, wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.

63. The system ofclaim 59, wherein said gate oxide layer is a grown layer.

64. The system ofclaim 63, wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.

65. The system ofclaim 59, wherein said gate oxide layer is a deposited layer.

66. The system ofclaim 65, wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.

67. The system ofclaim 47, wherein said high dielectric constant material spacer has a thickness of about 100 Å to about 1500 Å.

68. The system ofclaim 47, wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.

69. The system ofclaim 47, wherein said pixel sensor cell is part of a CMOS imager.

70. A method of forming a pixel sensor cell comprising:

forming at least one gate stack;

forming a spacer over at least one portion of said at least one gate stack, wherein said spacer is comprised of a high dielectric constant material.

71. The method ofclaim 70, wherein said forming a spacer step comprises forming the spacer with a thickness of about 100 Å to about 1500 Å.

72. The method ofclaim 70, wherein said forming a spacer step comprises forming the spacer with a thickness of about 200 Å to about 600 Å.

73. The method ofclaim 70, further comprising etching said spacer layer.

74. The method ofclaim 73, wherein said pixel sensor cell is masked before said etching step.

75. The method ofclaim 70, wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.

76. The method ofclaim 70, wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.

77. The method ofclaim 76, wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.

78. The method ofclaim 70, wherein said pixel sensor cell is part of a CCD sensor.

79. The method ofclaim 78, wherein the CCD sensor is a single gate CCD sensor.

80. The method ofclaim 78, wherein the CCD sensor is an overlapping gate sensor.

81. The method ofclaim 70, wherein said gate stack is part of an n-channel transistor.

82. The method ofclaim 70, wherein said gate stack is part of a p-channel transistor.

83. The method ofclaim 70, wherein said gate stack is formed of a gate oxide layer and a conductor layer.

84. The method ofclaim 70, wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.

85. The method ofclaim 84, wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.

86. The method ofclaim 84, wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.

87. The method ofclaim 83, wherein said gate oxide layer is a grown layer.

88. The method ofclaim 87, wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.

89. The method ofclaim 83, wherein said gate oxide layer is a deposited layer.

90. The method ofclaim 89, wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.

91. The method ofclaim 70, wherein said high dielectric constant material spacer has a thickness of about 100 Å to about 1500 Å.

92. The method ofclaim 70, wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.

93. The method ofclaim 70, wherein said pixel sensor cell is part of a CMOS imager.

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