US20050266682A1 - Methods and apparatus for forming barrier layers in high aspect ratio vias - Google Patents

Abstract

In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.

Description

• This application is a division of U.S. patent application Ser. No. 10/241,373 filed Sep. 11, 2002, which is hereby incorporated by reference herein in its entirety.
FIELD OF THE INVENTION
• The present invention relates to semiconductor device manufacturing, and more particularly to methods and apparatus for forming barrier layers in high aspect ratio vias employed within semiconductor devices.
BACKGROUND OF THE INVENTION
• A typical integrated circuit contains a plurality of metal pathways that provide electrical power to the various semiconductor devices forming the integrated circuit, and that allow these semiconductor devices to share/exchange electrical information. Within integrated circuits, metal layers are stacked on top of one another by using intermetal or “interlayer” dielectrics that insulate the metal layers from each other.
• Generally, each metal layer must form electrical contact to at least one additional metal layer. Such metal-layer-to-metal-layer electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers, and by filling the resulting via with a metal to create an interconnect as described further below. Metal layers typically occupy etched pathways or “lines” in the interlayer dielectric. For simplicity, as used herein, the term “via” refers to any feature such as a hole, line or other similar feature formed within a dielectric layer that assists in establishing an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer.
• Because copper has a lower resistivity than aluminum, copper metals layers and interconnects have gained popularity in contrast to more conventional aluminum metal layers and interconnects. Copper atoms, however, are highly mobile in silicon dioxide and may create electrical defects in silicon. Accordingly, copper metal layers and copper interconnect vias conventionally are encapsulated with a barrier material (e.g., to prevent copper atoms from creating leakage paths in silicon dioxide or similar interlayers and/or defects in the silicon substrate on which the copper layers and interconnects are formed).
• Barrier layers typically are deposited on via sidewalls and bottoms prior to copper seed layer deposition, and may include materials such as tungsten, titanium, tantalum, nitrides thereof, etc. Tantalum nitride is particularly popular due its lower resistivity and favorable adhesion properties.
• As is well known, an increase in device performance is typically accompanied by a decrease in device area or an increase in device density. An increase in device density requires a decrease in the via dimensions used to form interconnects (e.g., a larger depth-to-width ratio or a larger “aspect ratio”). As via dimensions decrease, and aspect ratios increase, forming adequately thick and uniform barrier layers on the sidewalls of vias has become difficult. This problem is exacerbated within low K dielectric interlayers, as sidewall barrier layers often serve the additional role of providing mechanical strength to such low K dielectric interlayers.
• Accordingly, a need exists for improved methods and apparatus for forming barrier layers in high aspect ratio vias.
SUMMARY OF THE INVENTION
• In first, second and third embodiments of the invention, methods are provided for forming a barrier layer on a substrate having a metal feature, a dielectric layer formed over the metal feature, and a via having sidewalls and a bottom. The via extends through the dielectric layer to expose the metal feature.
• In the first embodiment, a method includes forming a barrier layer over the sidewalls and bottom of the via using atomic layer deposition. The barrier layer has sufficient thickness to serve as a diffusion barrier to at least one of atoms of the metal feature and atoms of a seed layer formed over the barrier layer. The method further includes removing at least a portion of the barrier layer from the bottom of the via by sputter etching the substrate within a high density plasma physical vapor deposition (HDPPVD) chamber having a plasma ion density of at least 10¹⁰ions/cm³and configured for seed layer deposition. A bias is applied to the substrate during at least a portion of the sputter etching. The method also includes depositing a seed layer on the sidewalls and bottom of the via within the HDPPVD chamber.
• In the second embodiment, the method includes forming a first barrier layer over the sidewalls and bottom of the via using atomic layer deposition. At least a portion of the first barrier layer is removed from the bottom of the via by sputter etching the substrate within a high density plasma physical vapor deposition (HDPPVD) chamber having a plasma ion density of at least 10¹⁰ions/cm³and configured for depositing a second barrier layer. A bias is applied to the substrate during at least a portion of the sputter etching. The method also includes depositing a second barrier layer on the sidewalls and bottom of the via within the HDPPVD chamber.
• In the third embodiment, the method includes the steps of (1) forming a first barrier layer over the sidewalls and bottom of the via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching the substrate; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects of the invention. Each computer program product described herein may be carried by a medium readable by a computer (e.g., a carrier wave signal, a floppy disc, a compact disc, a DVD, a hard drive, a random access memory, etc.).
• Other features and aspects of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a schematic top-view of an exemplary multi-chamber processing system that may be adapted to perform the inventive processes described herein;
• FIG. 2 is a schematic, partial cross sectional view of an exemplary atomic layer deposition (ALD) chamber that may be employed with embodiments of the present invention;
• FIG. 3A is a schematic cross sectional view of a first exemplary high density plasma physical vapor deposition (HDPPVD) chamber that may be employed with embodiments of the present invention;
• FIG. 3B is a schematic cross-sectional view of a second HDPPVD chamber that may be employed with embodiments of the present invention;
• FIG. 3C is a schematic cross-sectional view of a third HDPPVD chamber that may be employed with embodiments of the present invention;
• FIG. 4 is a schematic cross-sectional view of a fourth HDPPVD chamber that may be employed with embodiments of the present invention;
• FIG. 5 is a flow chart of a first exemplary process for forming a barrier layer in a via in accordance with the present invention;
• FIGS. 6A-6E are cross-sectional views illustrating the formation of an exemplary interconnect formed in accordance with the process ofFIG. 5;
• FIG. 7 is a flow chart of a second exemplary process for forming a barrier layer in a via in accordance with the present invention;
• FIGS. 8A-8F are cross-sectional views illustrating the formation of an exemplary interconnect formed in accordance with the process ofFIG. 7;
• FIG. 9 is a flow chart of a third exemplary process for forming a barrier layer in a via in accordance with the present invention;
• FIGS. 10A-10F are cross-sectional views illustrating the formation of an exemplary interconnect formed in accordance with the process ofFIG. 9; and
• FIG. 11 is a schematic top-view of another exemplary multi-chamber processing system that may be adapted to perform one or more of the inventive processes described herein.
DETAILED DESCRIPTION
• Embodiments of the present invention provide methods and apparatus for forming barrier layers in high aspect ratio vias (e.g., vias having aspect ratios of 3:1, 4:1, 5:1 or higher) and/or vias having via widths of about 0.065-0.2 microns or below. It will be understood that the invention also may be employed to form barrier layers in lower aspect ratio and/or wider vias. Each embodiment allows a relatively thick barrier layer to be deposited on the sidewalls of a via with little or no barrier layer coverage on the bottom of the via. Adequate diffusion resistance and/or mechanical strength thereby may be provided without significantly increasing the contact resistance of the interconnect formed with the via.
• In a first embodiment of the invention, a conformal barrier layer is formed in an integrated system that includes at least (1) an atomic layer deposition (ALD) chamber for depositing the barrier layer; and (2) a high density plasma (HDP) physical vapor deposition (PVD) chamber for depositing a metal seed layer (e.g., a copper seed layer). As used herein, an HDPPVD chamber may include any PVD chamber capable of sustaining a plasma having an ion density of at least 10¹⁰ions/cm³in a bulk region of the plasma (e.g., a region, between a target/cathode and substrate support pedestal, that is not immediately adjacent the target/cathode; although an area immediately adjacent the target/cathode also may have an ion density of at least 10¹⁰ions/cm³).
• In accordance with the first embodiment and employing atomic layer deposition, the conformal barrier layer is deposited on the sidewalls and bottom of a via formed in a dielectric layer on a substrate. The substrate then is transferred to the HDPPVD seed chamber. Within the HDPPVD seed chamber, the portion of the barrier layer formed on the bottom of the via is thinned and/or removed by sputter etching the substrate (e.g., by “resputtering” the barrier layer), and a seed layer is formed on the bottom and sidewalls of the via. Resputtering of the bottom barrier layer and deposition of the seed layer may be performed sequentially or simultaneously within the HDPPVD seed chamber. Thereafter, the via may be filled (e.g., by electroplating) and/or planarized.
• By performing resputtering within the seed layer deposition chamber, the need for a separate sputtering chamber is eliminated and system throughput is increased. The use of only ALD barrier layers also improves overall barrier layer uniformity, and decreases deposition on field regions of the substrate. Post metallization process times, such as chemical mechanical polishing times, thereby may be reduced.
• In at least one aspect of the invention, the barrier layer comprises tantalum nitride, and the seed layer comprises copper. Other barrier layers and seed layers may be employed. These and other aspects of the first embodiment of the invention are described further below with reference toFIGS. 1-6E.
• In a second embodiment of the invention, a conformal barrier layer is formed in an integrated system that includes at least (1) an atomic layer deposition (ALD) chamber for depositing a first barrier layer; and (2) a high density plasma (HDP) physical vapor deposition (PVD) chamber for depositing a second barrier layer.
• In accordance with the second embodiment and employing atomic layer deposition, the conformal, first barrier layer is deposited on the sidewalls and bottom of a via formed in a dielectric layer on a substrate. The substrate then is transferred to the HDPPVD barrier layer chamber. Within the HDPPVD chamber, the portion of the first barrier layer formed on the bottom of the via is thinned and/or removed by sputter etching the substrate (e.g., by resputtering the first barrier layer), and a second barrier layer is formed on the sidewalls, and in some cases the bottom, of the via. Resputtering of the bottom, first barrier layer and deposition of the second barrier layer may be performed sequentially or simultaneously within the HDPPVD barrier layer chamber. Thereafter, the via may be coated with a seed layer and filled and/or planarized.
• By employing atomic layer deposition to deposit the first barrier layer, adequate sidewall coverage may be achieved, even within high aspect ratio vias, to ensure diffusion resistance and mechanical strength (e.g., when a low K dielectric interlayer is employed). By employing HDPPVD to deposit the second barrier layer following ALD, a thin (or no) bottom barrier layer may be obtained despite the presence of thick sidewall coverage.
• In at least one aspect of the invention, the first barrier layer comprises tantalum nitride, and the second barrier layer comprises tantalum. Other barrier layers may be employed. These and other aspects of the second embodiment of the invention are described further below with reference toFIGS. 1-4 and7-8F.
• In a third embodiment of the invention, a conformal barrier layer is formed in an integrated system that includes at least (1) an atomic layer deposition (ALD) chamber for depositing a first barrier layer; and (2) a sputter etch chamber for etching the first barrier layer. The sputter etch chamber may be a dedicated etch chamber, such as a Preclean™ or Reactive Preclean™ chamber manufactured by Applied Materials, Inc. of Santa Clara, Calif., or a chamber capable of performing sputter etching such as an HDPPVD chamber or the like.
• In accordance with the third embodiment and employing atomic layer deposition within the ALD chamber, the conformal, first barrier layer is deposited on the sidewalls and bottom of a via formed in a dielectric layer on a substrate. The substrate then is transferred to the sputter etch chamber. Within the sputter etch chamber, the portion of the first barrier layer formed on the bottom of the via is thinned and/or removed by sputter etching the substrate. The substrate then is transferred back to the ALD chamber, and a second barrier layer is formed on the bottom and sidewalls of the via. In at least one aspect of the invention, the second barrier layer is thinner than the first barrier layer (e.g., so that the portion of the second barrier layer on the bottom of the via does not significantly increase the contact resistance through the via). Thereafter, the via may be coated with a seed layer and filled and/or planarized.
• By employing atomic layer deposition to deposit the first barrier layer, adequate sidewall coverage may be achieved, even within high aspect ratio vias, to ensure diffusion resistance and mechanical strength (e.g., when a low K dielectric interlayer is employed). Sputter etching the first ALD barrier layer from the bottom of the via and employing a second, thinner ALD barrier layer allows a thin bottom barrier layer to be obtained despite the presence of thick sidewall coverage. The use of only ALD barrier layers also improves overall barrier layer uniformity, and decreases deposition on field regions of the substrate. Post metallization process times, such as chemical mechanical polishing times, thereby may be reduced.
• In at least one aspect of the invention, the first and second barrier layers comprise tantalum nitride. Other barrier layers may be employed. These and other aspects of the third embodiment of the invention are described further below with reference toFIGS. 1-4 and9-10F.
Integrated System Overview
• Before describing the above embodiments of the present invention, various apparatus that may be employed in accordance with these embodiments are described below with references toFIGS. 1-4. For example,FIG. 1 is a schematic top-view of an exemplarymulti-chamber processing system100 that may be adapted to perform the inventive processes described herein. Such a processing system may be an Endura™ system, commercially available from Applied Materials, Inc. A similar multi-chamber processing system is disclosed in U.S. Pat. No. 5,186,718, entitled “Stage Vacuum Wafer Processing System and Method,” issued on Feb. 16, 1993, which is hereby incorporated by reference herein in its entirety. Other processing systems may be similarly employed.
• Theprocessing system100 generally includesload lock chambers102,104 for transferring substrates into and out of thesystem100. Typically, since thesystem100 is under vacuum, theload lock chambers102,104 are adapted to “pump down” substrates introduced into thesystem100 to a suitable vacuum condition. As shown inFIG. 1, theload lock chambers102,104 are coupled to afirst transfer chamber106 which houses afirst robot110.
• Thefirst robot110 is adapted to transfer substrates between theload lock chambers102,104, and a first set of one or moresubstrate processing chambers112,114,116,118 (four are shown, although other numbers may be employed). Eachprocessing chamber112,114,116,118, may be adapted to perform substrate processing operations such as cyclical layer deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, degas, cool down, orientation and other substrate processes. Thefirst robot110 also transfers substrates to/from one or more pass-throughchambers122,124. The pass-throughchambers122,124 are coupled to asecond transfer126 which houses asecond robot130.
• Thesecond robot130 is adapted to transfer substrates between the pass-throughchambers122,124 and a second set of one ormore processing chambers132,134,136,138. Similar to processingchambers112,114,116,118, theprocessing chambers132,134,136,138 can be outfitted to perform a variety of substrate processing operations, such as cyclical layer deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, degas, and orientation, for example. Any of thesubstrate processing chambers112,114,116,118,132,134,136,138 may be removed from thesystem100 if not necessary for a particular process to be performed by thesystem100 as described further below.
• Thesystem100 also may include acontroller140 adapted to control, for example, substrate transfer operations within thetransfer chambers106,126 and/or the pass-throughchambers122,124, substrate processing performed within one or more of the chambers112-118 and132-138, and the like. In at least one embodiment, thecontroller140 is programmed to perform one or more of the inventive processes described herein that may be implemented, for example, as one or more computer program products. Thecontroller140 may be a system controller, a dedicated hardware circuit, an appropriately programmed general purpose computer, or any other equivalent electronic, mechanical or electromechanical device.
• As described above, embodiments of the present invention employ atomic layer deposition (ALD) and/or high density plasma physical vapor deposition (HDPPVD). Accordingly, one or more of the chambers112-118 and132-138 may be an ALD chamber and/or a HDPPVD chamber.
Atomic Layer Deposition Chamber
• FIG. 2 illustrates a schematic, partial cross sectional view of an exemplary atomic layer deposition (ALD)chamber200 that may be employed with embodiments of the present invention. Such achamber200 is available from Applied Materials, Inc., and a brief description thereof follows. A more detailed description may be found in commonly assigned U.S. patent application Ser. No. 10/032,284, entitled “Gas Delivery Apparatus and Method For Atomic Layer Deposition”, filed on Dec. 21, 2001, which is hereby incorporated by reference herein in its entirety.
• Referring toFIG. 2, theALD chamber200 includes achamber body202 having aslit valve208 formed in asidewall204 thereof (e.g., for introducing asubstrate210 into the chamber200) and asubstrate support212 disposed therein (e.g., for supporting thesubstrate210 during processing). Thesubstrate support212 is mounted to alift motor214 to raise and lower thesubstrate support212 and thesubstrate210 disposed thereon. Thesubstrate support212 may also include a vacuum chuck, an electrostatic chuck, or a clamp ring for securing thesubstrate210 to thesubstrate support212 during processing. Further, thesubstrate support212 may be heated using an embedded heating element (not shown), such as a resistive heater, or may be heated using radiant heat, such as heating lamps (not shown) disposed above thesubstrate support212. Apurge ring222 may be disposed on thesubstrate support212 to define apurge channel224 that provides a purge gas to prevent deposition on a peripheral portion of thesubstrate210.
• Agas delivery apparatus230 is disposed at an upper portion of thechamber body202 to provide a gas, such as a process gas and/or a purge gas, to thechamber200. Avacuum system278 is in communication with apumping channel279 to evacuate gases from thechamber200 and to help maintain a desired pressure or a desired pressure range inside apumping zone266 of thechamber200.
• Thegas delivery apparatus230 includes achamber lid232 having an expandingchannel234 formed within a central portion thereof. Thechamber lid232 also includes abottom surface260 extending from the expandingchannel234 to a peripheral portion of thechamber lid232. Thebottom surface260 is sized and shaped to substantially cover thesubstrate210 disposed on thesubstrate support212. The expandingchannel234 has an inner diameter that gradually increases from anupper portion237 to alower portion235 adjacent thebottom surface260 of thechamber lid232. The velocity of a gas flowing therethrough decreases as the gas flows through the expandingchannel234 due to the expansion of the gas. The decreased gas velocity reduces the likelihood that reactants adsorbed on the surface of thesubstrate210 will be blown off of the substrate surface by the gas.
• Thegas delivery apparatus230 also includes at least two highspeed actuating valves242A,242B having one or more ports. At least onevalve242A,242B is dedicated to each reactive compound. For example, a first valve is dedicated to a refractory metal-containing compound, such as tantalum or titanium, and a second valve is dedicated to a nitrogen-containing compound. When a ternary material is desired, a third valve is dedicated to an additional compound. For example, if a silicide is desired, the additional compound may be a silicon-containing compound.
• Thevalves242A,242B may comprise any valve capable of precisely and repeatedly delivering short pulses of compounds into thechamber body202. In some cases, the on/off cycles or pulses of thevalves242A,242B may be as fast as about 100 msec or less. Thevalves242A,242B can be directly controlled by a system computer (e.g., thecontroller140 ofFIG. 1), such as a mainframe for example, or controlled by a chamber/application specific controller, such as a programmable logic computer (PLC) which is described in more detail in co-pending U.S. patent application Ser. No. 09/800,881, entitled “Valve Control System For ALD Chamber”, filed on Mar. 7, 2001, which is hereby incorporated by reference herein in its entirety. For example, thevalves242A,242B may be electronically controlled (EC) valves, which are commercially available from Fujikin of Japan as part number FR-21-6.35 UGF-APD.
• The expandingchannel234 hasgas inlets236A,236B to provide gas flows from thevalves242A,242B. The gas flows from thevalves242A,242B may be provided together and/or separately.
• In one configuration,valve242A andvalve242B are coupled to separate reactant gas sources but are preferably coupled to the same purge gas source. For example,valve242A is coupled toreactant gas source238 andvalve242B is coupled toreactant gas source239, and bothvalves242A,242B are coupled to purgegas source240. Eachvalve242A,242B includes adelivery line243A,243B having avalve seat assembly244A,244B and includes apurge line245A,245B. Thedelivery line243A,243B is in communication with thereactant gas source238,239 and is in communication with thegas inlet236A,236B of the expandingchannel234.
• Thevalve seat assembly244A,244B of thedelivery line243A,243B controls the flow of the reactant gas from thereactant gas source238,239 to the expandingchannel234. Thepurge line245A,245B is in communication with thepurge gas source240 and intersects thedelivery line243A,243B downstream of thevalve seat assembly244A,244B of thedelivery line243A,243B.
• Separate valve seat assemblies (not shown) may be employed to control the flow of the purge gas from thepurge gas source240 to thedelivery line243A,243B. If a carrier gas is used to deliver reactant gases from thereactant gas source238,239, preferably the same gas is used as a carrier gas and a purge gas (e.g., an argon gas used as a carrier gas and a purge gas).
• Each valve seat assembly may comprise a diaphragm and a valve seat. The diaphragm may be biased open or closed and may be actuated closed or open respectively. The diaphragms may be pneumatically actuated or may be electrically actuated. Examples of pneumatically actuated valves include pneumatically actuated valves available from Fujiken and Veriflow. Examples of electrically actuated valves include electrically actuated valves available from Fujiken.
• Programmable logic controllers248A,248B may be coupled to thevalves242A,242B to control actuation of the diaphragms of the valve seat assemblies of thevalves242A,242B. Pneumatically actuated valves may provide pulses of gases in time periods as low as about 0.020 seconds. Electrically actuated valves may provide pulses of gases in time periods as low as about 0.005 seconds. An electrically actuated valve typically requires the use of a driver coupled between the valve and the programmable logic controller. Additional details regarding thevalves242A,242B and operation thereof are provided in previously incorporated U.S. patent application Ser. No. 10/032,284, entitled “Gas Delivery Apparatus and Method For Atomic Layer Deposition”, filed on Dec. 21, 2001.
• The delivery lines243A,243B of thevalves242A,242B may be coupled to thegas inlets236A,236B throughgas conduits250A,250B. Thegas conduits250A,250B may be integrated or may be separate from thevalves242A,242B. In one aspect, thevalves242A,242B are coupled in close proximity to the expandingchannel234 to reduce any unnecessary volume of thedelivery line243A,243B and thegas conduits250A,250B between thevalves242A,242B and thegas inlets236A,236B.
• In a particular embodiment, a TaN barrier layer is formed by cyclically introducing PDMAT and ammonia to the substrate surface. Other exemplary tantalum-containing compounds include: t-butylimino tris(diethylamino) tantalum (TBTDET); pentakis (ethylmethylamino); tantalum (PEMAT); pentakis (diethylamino) tantalum (PDEAT); t-butylimino tris(diethyl methylamino) tantalum(TBTMET); t-butylimino tris(dimethyl amino) tantalum (TBTDMT); bis (cyclopentadienyl) tantalum trihydride ((Cp)₂TaH₃); bis(methylcyclopentadienyl) tantalum trihydride ((CpMe)₂TaH₃); derivatives thereof; and combinations thereof. Other exemplary nitrogen-containing compounds include: hydrazine; methylhydrazine; dimethylhydrazine; t-butylhydrazine; phenylhydrazine; azoisobutane; ethylazide; derivatives thereof; and combinations thereof.
• To initiate the cyclical deposition of the TaN layer, a carrier/inert gas such as argon is introduced into theALD chamber200 to stabilize the pressure and temperature therein. The carrier gas is allowed to flow continuously during the deposition process such that only the argon flows between pulses of each compound. A first pulse of PDMAT is provided from thegas source238 at a flow rate between about 100 sccm and about 400 sccm, with a pulse time of about 0.6 seconds or less after the chamber temperature and pressure have been stabilized at about 200° C. to about 300° C. and about 1 Torr to about 5 Torr. A pulse of ammonia is then provided from thegas source239 at a flow rate between about 200 sccm and about 600 sccm, with a pulse time of about 0.6 seconds or less. Other flow rate ranges may be employed such as about 50 to 200 sccm for the Ta-containing compound and about 1000-3000 sccm for the nitrogen containing compound. Other pulse times, temperature ranges and pressures also may be employed.
• A pause between pulses of PDMAT and ammonia is about 1.0 second or less, preferably about 0.5 seconds or less, more preferably about 0.1 seconds or less. In various aspects, a reduction in time between pulses at least provides higher throughput. As a result, a pause after the pulse of ammonia is also about 1.0 second or less, about 0.5 seconds or less, or about 0.1 seconds or less. Argon gas flowing between about 100 sccm and about 1000 sccm, such as between about 100 sccm and about 400 sccm, is continuously provided from thegas source240 through eachvalve242A,242B. In one aspect, a pulse of PDMAT may still be in the chamber when a pulse of ammonia enters. In general, the duration of the carrier gas and/or pump evacuation should be long enough to prevent the pulses of PDMAT and ammonia from mixing together in the reaction zone.
• The heater temperature is maintained between about 100° C. and about 300° C. at a chamber pressure between about 1.0 and about 5.0 Torr. Each cycle (which includes a pulse of PDMAT, a pause, a pulse of ammonia, and a pause) provides a tantalum nitride layer having a thickness between about 0.3 Å and about 1.0 Å. The alternating sequence cycles may be repeated until the desired thickness is achieved, which in at least one embodiment of the invention is less than about 20 Å, such as about 10 Å. Accordingly, the deposition method requires between about 10 and 70 cycles, more typically between about 20 and 30 cycles. In one or more other embodiments of the invention, the desired thickness may be greater than about 50 Å, such as about 60 Å-65 Å or more. Accordingly, the deposition method requires significantly more cycles (e.g., between about 50 and 220 cycles). Other barrier layers, including ternary barrier layers such as titanium silicon nitride may be similarly deposited, as described for example, in U.S. patent application Ser. No. 10/193,333, filed Jul. 10, 2002 and titled “Integration of ALD Tantalum Nitride and Alpha-Phase Tantalum for Copper Metallization Application” (Attorney Docket No. 6640) which is hereby incorporated by reference herein in its entirety.
First Exemplary High Density Plasma Physical Vapor Deposition Chamber
• FIG. 3A illustrates a schematic cross sectional view of a first exemplary high density plasma physical vapor deposition (HDPPVD)chamber300 that may be employed with embodiments of the present invention. Thechamber300 is of a type sometimes referred to as a self ionizing plasma (SIP™) chamber, available from Applied Materials, Inc.
• With reference toFIG. 3A, thechamber300 includes asealable chamber312, and atarget314 installed at the top of thechamber312. Thetarget314 comprises a material, usually a metal, to be sputter deposited on asubstrate316 held on apedestal318. For example, in the first embodiment of the invention described below with reference toFIGS. 5-6E, thetarget314 may comprise copper, a copper alloy, ruthenium, a ruthenium alloy, etc. (e.g., for forming a seed layer). In the second embodiment of the invention described below with reference toFIGS. 7-8F, thetarget314 may comprise tantalum, tungsten, titanium, etc. (e.g., for forming a barrier layer).
• Ashield320 installed within thechamber312 protects walls of thechamber312 from material sputtered from thetarget314 and provides a grounding anode. A variable (DC)power supply322 is connected to thetarget314 for supplying power thereto.
• A workinggas supply323, which includes a workinggas source324 and a firstmass flow controller326, supplies a working gas (typically the chemically inactive gas argon) to thechamber312. (Though not required for the present invention, if reactive sputtering is to be performed to sputter-deposit a metal nitride layer, such as TaN, asecond gas supply325 may be provided, including anitrogen gas source327 and a secondmass flow controller329.) Thechamber312 is shown as receiving argon (and nitrogen) near the top of thechamber312, but may be reconfigured to receive such gases at other locations, such as near the bottom of thechamber312. Apump328 is provided to pump out thechamber312 to a pressure at which sputtering is performed; and anRF power source332 is connected to thepedestal318 through a coupling capacitor334 (e.g., for biasing thesubstrate316 during sputtering).
• Acontroller330 is provided to control operation of thechamber300. Thecontroller330 is operatively connected to control theDC power supply322, the firstmass flow controller326, the secondmass flow controller329, thepump328, and theRF power supply332. Thecontroller330 similarly may be coupled to control the position and/or temperature of thepedestal318. For example, thecontroller330 may control the distance between thepedestal318 and thetarget314, as well as heating and/or cooling of thepedestal318. Thecontroller330 may be implemented as thecontroller140 of thesystem100 ofFIG. 1 or as a separate controller (which may or may not communicate with the controller140).
• To promote efficient sputtering, amagnetron336 may be rotationally mounted above thetarget314 to shape the plasma. Themagnetron336 may be of a type which produces an asymmetric magnetic field which extends deep into the chamber312 (e.g., toward the pedestal318), to enhance the ionization density of the plasma, as disclosed in U.S. Pat. No. 6,183,614. U.S. Pat. No. 6,183,614 is incorporated herein by reference in its entirety. Typical ionized metal densities may reach 10¹⁰to 10¹¹metal ions/cm³(e.g., in a bulk region of the plasma) when such asymmetric magnetic fields are employed. In such systems, ionized metal atoms follow the magnetic field lines which extend into thechamber312, and thus coat thesubstrate316 with greater directionality and efficiency. Themagnetron336 may rotate, for example, at 60-100 rpm. Stationary magnetic rings may be used instead of therotating magnetron336.
• In operation, argon is admitted into thechamber312 from the workinggas supply323 and theDC power supply322 is turned on to ignite the argon into a plasma. Positive argon ions thereby are generated, and thetarget314 is biased negatively relative to the groundedshield320. These positively charged argon ions are attracted to the negatively chargedtarget314, and may strike thetarget314 with sufficient energy to cause target atoms to be sputtered from thetarget314. Some of the sputtered atoms strike thesubstrate316 and are deposited thereon thereby forming a film of the target material on thesubstrate316.
• A DC self bias of thesubstrate316 results from operation of theRF power supply332, and enhances efficiency of sputter deposition (e.g., by attracting ionized target atoms which strike thesubstrate316 with more directionality). As stated, the use of asymmetric magnetic fields increases ionized metal densities. A larger fraction of sputtered target atoms thereby strike the substrate316 (with greater directionality).
• Within thechamber300, sputtering typically is performed at a pressure of about 0.1-2 milliTorr. Other pressure ranges may be employed. The power applied to thetarget314 may be, for example, about 18 kW and the RF bias signal applied to thepedestal318 may be about 250 W or less (although other target powers and RF biases may be used).
• If reactive sputtering is to be performed, nitrogen is flowed into thechamber312 from thesecond gas supply325 together with argon provided from the workinggas supply323. Nitrogen reacts with thetarget314 to form a nitrogen film on thetarget314 so that metal nitride is sputtered therefrom. Additionally, non-nitrided atoms are also sputtered from thetarget314. These atoms can combine with nitrogen to form metal nitride in flight or on thesubstrate316.
Second Exemplary High Density Plasma Physical Vapor Deposition Chamber
• FIG. 3B is a schematic cross-sectional view of asecond HDPPVD chamber300′ that may be employed with embodiments of the present invention. Thechamber300′ ofFIG. 3B may have all of the components described above in connection with thechamber300 ofFIG. 3A. In addition thechamber300′ includes acoil338 which is disposed within thechamber312 and surrounds a portion of the interior volume of thechamber312. Thecoil338 may comprise a plurality of coils, a single turn coil, a single turn material strip, or any other similar configuration. Thecoil338 is positioned along the inner surface of thechamber312, between thetarget314 and thepedestal318.
• AnRF power source340 is connected to thecoil338 and is controlled by thecontroller330. During sputter-deposition operation of thechamber300′, theRF power source340 is operated to energize thecoil338, to enhance the plasma within the chamber312 (by ionizing target atoms sputtered from the target314). In at least one embodiment, thecoil338 may be energized at a frequency of about 2 MHz at a power level of about 1-3 kW. Other frequencies and/or powers may be used. As with thechamber300 ofFIG. 3A, metal ion densities can reach about 10¹⁰-10¹¹metal ions/cm³(e.g., in a bulk region of the plasma). However, because of the energy provided by thecoil338, high metal ion densities may be provided over a wider region of the plasma of thechamber300′ ofFIG. 3B than for the plasma of thechamber300 ofFIG. 3A. The chamber pressures employed in thechamber300′ ofFIG. 3B may be similar to those described above in connection with thechamber300 ofFIG. 3A. As was the case with thechamber300 ofFIG. 3A, stationary ring magnets may be used in thechamber300′ ofFIG. 3B in place of therotating magnetron336. A chamber similar to thechamber300′ is available from Applied Materials, Inc., under the name EnCoRe or SIP™ EnCoRe.
Third Exemplary High Density Plasma Physical Vapor Deposition Chamber
• FIG. 3C is a schematic cross-sectional view of athird HDPPVD chamber300″ that may be employed with embodiments of the present invention. Thechamber300″ ofFIG. 3C may have all the components of thechamber300′ ofFIG. 3B, except that in place of theasymmetric magnetron336 shown inFIG. 3B, a balanced magnetron342 (FIG. 3C) may be provided. The magnetic field provided by thebalanced magnetron342 does not extend as far into thechamber312 as the magnetic field provided by theasymmetric magnetron336. Thechamber300″ ofFIG. 3C therefore is operated at a higher pressure (e.g., about 10-100 milliTorr) so that metal atoms sputtered from thetarget314 thermalize and have a greater opportunity for ionization. That is, at the higher pressure at which thechamber300″ operates, metal atoms sputtered from thetarget314 experience more collisions (e.g., have a smaller mean free path between collisions) and due to increased collisions have more random motion or a longer transit time within the plasma of thechamber300″ and thus more opportunity to ionize. Metal ion densities within thechamber300″ may reach about 10¹⁰-10¹¹metal ions/cm³(e.g., in a bulk region of the plasma), but over a larger volume than in thechamber300 ofFIG. 3A.
• As in the case of thechambers300,300′, stationary ring magnets may be employed in thechamber300″ ofFIG. 3C. Thechamber300″ may be similar to an Ionized Metal Plasma (IMP) Vectra™ chamber, available from Applied Materials, Inc.
Fourth Exemplary High Density Plasma Physical Vapor Deposition Chamber
• FIG. 4 is a schematic cross-sectional view of afourth HDPPVD chamber400 that may be employed with embodiments of the present invention. Thechamber400 includes a specially shapedtarget402 and amagnetron404. Thetarget402 or at least its interior surface is composed of the material to be sputter deposited (e.g., copper, ruthenium, tantalum, titanium, tungsten or other materials). Reactive sputtering of materials like TiN and TaN can be accomplished by using a Ti or Ta target and including gaseous nitrogen in the plasma. In such a case, the nitrogen is introduced into thechamber400 from a nitrogen gas source which is not shown inFIG. 4. Other combinations of metal targets and reactive gases may be employed.
• Thetarget402 includes an annularly shaped downwardly facingvault406 facing asubstrate408 which is to be sputter coated. The vault could alternatively be characterized as an annular roof. Thevault406 has an aspect ratio of its depth to radial width of at least 1:2 and preferably at least 1:1. Thevault406 has anouter sidewall422 outside of the periphery of thesubstrate408, aninner sidewall424 overlying thesubstrate408, and a generally flat vault top wall or roof426 (which forms the bottom of the downwardly facing vault406). Thetarget402 includes a central portion forming apost427 including theinner sidewall424 and a generallyplanar face428 in parallel opposition to thesubstrate408. A cylindrical central well436 of thetarget402 is formed between opposed portions of theinner target sidewall424. Thetarget402 also includes aflange438 that is vacuum sealed to a groundedchamber body450 of thechamber400 through adielectric target isolator452.
• Thesubstrate408 is clamped to aheater pedestal electrode454 by, for example, aclamp ring456 although electrostatic chucking may alternatively be employed. An electrically groundedshield458 acts as an anode with respect to thecathode target402, which is negatively energized by apower supply460. As an alternative to DC sputtering, RF sputtering can also be employed, and may be particularly useful for sputtering non-metallic targets.
• An electrically floatingshield462 is supported on the electrically groundedshield458 orchamber body450 by adielectric shield isolator464. A cylindrical knob466 extending downwardly from theouter target sidewall422 and positioned inwardly of the uppermost part of the floatingshield462 protects the upper portion of the floatingshield462 and thetarget isolator452 from sputter deposition from the strong plasma disposed within thetarget vault406. The gap between the upper portion of the floatingshield462 and the target knob466 and theflange438 is small enough to act as a dark space (preventing a plasma from propagating into the gap).
• A working gas such as argon is supplied into thechamber400 from agas source468 through amass flow controller470. Avacuum pumping system472 maintains the chamber at a reduced pressure, typically a base pressure of about 10⁻⁸Torr. AnRF power supply474 RF biases thepedestal electrode454 through an isolation capacitor (not shown), to produce a negative DC self-bias. Alternatively, the RF power supply may be omitted and thepedestal electrode454 may be allowed to float to develop a negative self-bias. Acontroller476 regulates the power supplies460,474,mass flow controller470, and vacuum system472 (e.g., according to a sputtering recipe stored in the controller476). Thecontroller476 also may control the position and/or temperature of thepedestal electrode454. Thecontroller476 may be implemented as thecontroller140 of thesystem100 ofFIG. 1 or as a separate controller (which may or may not communicate with the controller140).
• Themagnetron404 includes inner and outertop magnets478,480 overlying thevault roof426.Side magnets482,484 disposed outside of the vault sidewalls422,424 have opposed vertical magnetic polarities but are largely decoupled from thetop magnets478,480 because they are supported on amagnetic yoke485 bynon-magnetic supports486,488. As a result, theside magnets482,484 create a magnetic field B in thevault406 that has two generally anti-parallel components extending radially across thevault406 as well as two components extending generally parallel to the vault sidewalls422,424. Thus the magnetic field B extends over a substantial depth of thevault406 and repels electrons from thesidewalls422,424. A magnetic field B′ is formed bytop magnets478,480.
• Amotor490 is supported on thechamber body450 by means of acylindrical sidewall492 and aroof494, which are preferably electrically isolated from thebiased target flange438. Themotor490 has a motor shaft connected to theyoke485 at a central axis C of thetarget402. Themotor490 may rotate themagnetron404 about the axis C at a suitable rate (e.g., a few hundred rpm). Theyoke485 is asymmetric and may be shaped as a sector. Mechanical counterbalancing may be provided to reduce vibration in the rotation of the axially offsetmagnetron404.
• Some or all of the magnets of themagnetron404 may be replaced by stationary ring magnets.
• The pressure level employed during sputtering in thechamber400 ofFIG. 4 may be similar to the pressure level employed during sputtering in thechamber300 ofFIG. 3A. Thechamber400 ofFIG. 4 produces ionized metal densities in the range of 10¹-10¹¹metal ions/cm³(e.g., in a bulk region of the plasma) without requiring a coil and over a larger volume than in thechamber300 ofFIG. 3A. Target power may be in the range of about 20-40 kW, although other power ranges may be employed.
• A chamber of the type shown inFIG. 4 is disclosed in U.S. Pat. No. 6,277,249 and is available from Applied Materials, Inc., under the name SIP+™. U.S. Pat. No. 6,277,249 is hereby incorporated by reference herein in its entirety. U.S. Pat. No. 6,251,242 is related to U.S. Pat. No. 6,277,249 and is also incorporated by reference herein in its entirety.
• Any other high density plasma physical vapor deposition chamber may be similarly employed with embodiments of the present invention.
First Exemplary Inventive Process for Forming a Barrier Layer in a Via
• FIG. 5 is a flow chart of a firstexemplary process500 for forming a barrier layer in a via.FIGS. 6A-6E are cross-sectional views illustrating the formation of an exemplary interconnect formed in accordance with theprocess500.
• Theprocess500 may be performed, for example, with theprocessing system100 using theALD chamber200 ofFIG. 2 and one of theHDPPVD chambers300,300′,300″,400 ofFIGS. 3A-4; and for convenience will be described with reference thereto. For example, processingchamber132 ofFIG. 1 may be a processing chamber such as theALD chamber200 ofFIG. 2 configured for atomic layer deposition of a barrier layer. Theprocessing chamber134 ofFIG. 1 may be a processing chamber such as one of theHDPPVD chambers300,300′,300″,400 ofFIGS. 3A-4 configured for seed layer deposition. Processingchambers136 and138 need not be employed. Other processing system configurations and/or processing chamber layouts may be employed.
• With reference toFIG. 5, theprocess500 begins withstep501. Instep502, a substrate600 (FIG. 6A) is loaded into theprocessing chamber132/ALD chamber200 (e.g., via the second robot130 (FIG. 1) of the second transfer chamber126). As shown inFIG. 6A, thesubstrate600 includes abulk region602, ametal feature604 formed over thebulk region602 and adielectric layer606 formed over themetal feature604. A via608 extends through thedielectric layer606 to expose themetal feature604. For convenience, the via608 is shown as a single damascene feature. It will be understood that more complicated features, such as dual or triple damascene features, similarly may be employed.
• Thebulk region602 may comprise, for example, a silicon or other semiconductor region with or without device features (e.g., sources, drains, channels, p-n or n-p junctions, etc.) formed therein. Themetal feature604 may comprise a metal or otherwise conductive feature such as a line, contact, etc., formed from any suitable material such as aluminum, copper or the like. Thedielectric layer606 may comprise silicon dioxide, a low K material such as fluorinated silicon glass or oxide (FSG), carbon doped oxide (e.g., SiOC), polymer spin on (e.g., a spin on glass), etc., or any other suitable dielectric material.
• Referring again toFIG. 5, followingstep502 isstep503. Instep503, a conformal barrier layer610 (FIG. 6B) such as a tantalum nitride layer is deposited on thesubstrate600 by atomic layer deposition so as to coat the bottom and sidewalls of thevia608. In at least one embodiment of the invention, thebarrier layer610 is deposited with sufficient thickness to serve as a diffusion barrier to metal atoms of theunderlying metal feature604 and/or of the seed layer to be deposited over the barrier layer610 (as described below).
• As an example, if thebarrier layer610 comprises tantalum nitride, the thickness of the barrier layer preferably is in the range of about 15 to 100 angstroms, although a range of about 50-60 angstroms may be more preferred. Such thickness ranges are particularly well suited for via widths of less than about 0.095 microns, or even less than about 0.065 microns, and/or within vias having aspect ratios of 4:1 or greater. An ALD tantalum nitride barrier layer may be deposited, for example, employing a pressure range of about 1-5 Torr, a substrate temperature of about 250-300° C. and tantalum-carrier and ammonia flow rates of about 50-200 sccm and 1000-3000 sccm, respectively, for the appropriate number of cycles (as previously described). Other processing conditions may be employed. Other barrier layers similarly may be deposited.
• Followingstep503, instep504 thesubstrate600 is transferred from theprocessing chamber132/ALD chamber200 to an HDPPVD seed chamber (e.g., theprocessing chamber134 which may be, for example, one of theHDPPVD chambers300,300′,300″ or400 configured for seed layer deposition through appropriate target material selection). For convenience, it will be assumed that theHDPPVD chamber300′ ofFIG. 3B (e.g., an EnCoRe chamber available from Applied Materials, Inc.) is employed, although any other suitable HDPPVD chamber may be used. Thesubstrate600 is placed on thesupport pedestal318.
• Instep505, the portion of thebarrier layer610 that coats the bottom of thevia608 is sputter etched (or “re-sputtered”) within the HDPPVD chamber so as to thin or completely remove thebarrier layer610 from the bottom of thevia608. Assuming theHDPPVD chamber300′ ofFIG. 3B is employed, sputter etching may be performed, for example, by flowing an inert gas such as argon into thechamber300′ via thegas supply323. Once pressure within thechamber300′ stabilizes, typically at about 0.5-30 milliTorr although other ranges may be employed, thetarget314, thepedestal318 and thecoil338 are suitably biased to generate a plasma within thechamber300′. For example, a power signal may be applied to thecoil338 via theRF power supply340, little or no power may be applied to thetarget314 via theDC power supply322; and a negative bias may be applied to the pedestal318 (e.g., via the RF power supply332). The RF power signal applied to thecoil338 causes argon atoms within thechamber300′ to ionize and form a plasma. By adjusting the duty cycle and/or magnitude of the RF power signal applied to thepedestal318, a negative bias may be created between thepedestal318 and the plasma. The negative bias between thepedestal318 and the plasma causes argon ions to accelerate toward thepedestal318 and thesubstrate600 supported thereon. Accordingly, thesubstrate600 is sputter-etched by the argon ions.
• Under the influence of the negative bias applied to thepedestal318, the argon ions strike thesubstrate600 substantially perpendicularly. Further, the high ion density of theHDPPVD chamber300′, typically greater than 10¹⁰, 10¹¹or 10¹²ions/cm³, increases the anisotropic nature of the sputter etch process. Such a high degree of anisotropy is especially beneficial, and in some cases essential, for narrow width, high aspect ratio features, as it allows removal of barrier layers from the bottom of narrow and deep vias (e.g., vias having aspect ratios of about 4:1 or greater and/or via widths of about 0.095 microns or less).
• Because little or no power is applied to the target314 (e.g., 0 to about 500 Watts), little or no material is sputtered from thetarget314 and deposits on thesubstrate600 during sputter etching. The portion of thebarrier layer610 formed on the bottom of the via608 thereby may be thinned or removed as shown inFIG. 6C. Note that thebarrier layer610 will be similarly etched from other horizontal regions of the substrate600 (e.g., field regions, although for clarity thebarrier layer610 is not shown as being removed from these regions inFIGS. 6C and 6D).
• In at least one embodiment of the invention, sputter etching is performed within thechamber300′ by employing a chamber pressure of about 0.5-30 milliTorr, a pedestal bias of about 400-1000 Watts at about 13.56 MHz, a coil power of about 1-5 kwatts at about 2 MHz, a target power of less than about 500 Watts and a target/substrate spacing of about 400 mm. Other processing parameters similarly may be employed, as may other HDPPVD chambers such as thechambers300,300″ and400 ofFIGS. 3A, 3C and4.
• Referring again toFIG. 5, followingstep505, a seed layer612 (FIG. 6D) is deposited over thesubstrate600 within theprocessing chamber134/HDPPVD chamber300′ (step506). The seed layer may comprise copper, a copper alloy, ruthenium, a ruthenium alloy or any other suitable seed layer material. In at least one embodiment, the seed layer comprises about 1000-1500 angstroms of copper, although other thicknesses may be employed. Such a seed layer may be deposited, for example, by employing a chamber pressure of about 0.5-30 milliTorr, a pedestal bias of about 250 Watts or less at about 13.56 MHz, a coil power of about 1-5 kWatts at about 2 MHz, a target power of about 500 Watts to 5 kWatts and a target/substrate spacing of about 400 mm. Other processing parameters similarly may be employed.
• Whilesteps505 and506 have been shown as occurring sequentially, it will be understood that through appropriate manipulation of target power, coil power and/or pedestal bias (e.g., pedestal power and/or duty cycle), thebarrier layer610 may be removed from the bottom of the via608 at the same time or during at least a portion of the time that theseed layer612 is deposited within thevia608. For example, simultaneous deposition of a copper seed layer and removal of a tantalum nitride barrier layer may be performed in thechamber300′ by employing a chamber pressure of about 0.5-30 milliTorr, a pedestal bias of about 400-1000 Watts at about 13.56 MHz, a coil power of about 1-5 kWatts at about 2 MHz, a target power of about 500 Watts to 5 kWatts and a target/substrate spacing of about 400 mm. Other processing parameters similarly may be employed.
• After theseed layer612 has been deposited within the via608, instep507 thesubstrate600 may be transferred to a fill chamber and instep508 the via608 may be filled. Thesubstrate600 then may be planarized as shown inFIG. 6E. For example, thesubstrate600 may be transferred to a fill chamber, such as an electrochemical plating (ECP) chamber, and filled (e.g., with copper or another suitable material, referred to byreference numeral614 inFIG. 6E). Thereafter, thesubstrate600 may be transferred to a planarization tool and planarized, such as via chemical-mechanical polishing. Separate transfer and/or planarization steps are not shown inFIG. 5. Followingstep508, theprocess500 ends atstep509.
• Via filling may be performed, for example, in an electro-chemical plating tool such as the Electra™ Cu ECP system, available from Applied Materials, Inc. The Electra™ Cu ECP system may be integrated into an Endura™ platform also available from Applied Materials, Inc. (e.g., a processing system such as theprocessing system100 ofFIG. 1). Chemical mechanical polishing (CMP) may be performed, for example, in a Mirra™ System available from Applied Materials.
• By performing sputter etching (e.g., resputtering) with the seed chamber, the need for a separate sputtering chamber is eliminated and system throughput is increased. The use of only ALD barrier layers also improves overall barrier layer uniformity, and decreases deposition on field regions of the substrate. Post metallization process times, such as chemical mechanical polishing times, thereby may be reduced.
Second Exemplary Inventive Process for Forming a Barrier Layer in a Via
• FIG. 7 is a flow chart of a secondexemplary process700 for forming a barrier layer in a via.FIGS. 8A-8F are cross-sectional views illustrating the formation of an exemplary interconnect formed in accordance with theprocess700.
• Theprocess700 may be performed, for example, with theprocessing system100 ofFIG. 1 using (1) theALD chamber200 ofFIG. 2; (2) one of theHDPPVD chambers300,300′,300″,400 ofFIGS. 3A-4 configured for barrier layer deposition; and (3) a seed layer deposition chamber (which may or may not be one of theHDPPVD chambers300,300′,300″,400); For convenience, theprocess700 will be described with reference to theprocessing system100. For example, theprocessing chamber132 ofFIG. 1 may be a processing chamber such as theALD chamber200 ofFIG. 2 configured for atomic layer deposition of a barrier layer. Theprocessing chamber134 ofFIG. 1 may be a processing chamber such as one of theHDPPVD chambers300,300′,300″,400 configured for barrier layer deposition. Theprocessing chamber136 ofFIG. 1 may be a seed layer deposition chamber.Processing chamber138 need not be employed. Other processing system configurations and/or processing chamber layouts may be used.
• With reference toFIG. 7, theprocess700 begins withstep701. Instep702, a substrate800 (FIG. 8A) is loaded into theprocessing chamber132/ALD chamber200 (e.g., via the second robot130 (FIG. 1) of the second transfer chamber126). As shown inFIG. 8A, thesubstrate800 includes abulk region802, ametal feature804 formed over thebulk region802 and adielectric layer806 formed over themetal feature804. A via808 extends through thedielectric layer806 to expose themetal feature804. For convenience, the via808 is shown as a single damascene feature. It will be understood that more complicated features, such as dual or triple damascene features, similarly may be employed.
• Thebulk region802 may comprise, for example, a silicon or other semiconductor region with or without device features (e.g., sources, drains, channels, p-n or n-p junctions, etc.) formed therein. Themetal feature804 may comprise a metal or otherwise conductive feature such as a line, contact, etc., formed from any suitable material such as aluminum, copper or the like. Thedielectric layer806 may comprise silicon dioxide, a low K material such as fluorinated silicon glass or oxide (FSG), carbon doped oxide (e.g., SIOC), polymer spin on (e.g., a spin on glass), etc., or any other suitable dielectric material.
• Referring again toFIG. 7, followingstep702 isstep703. Instep703, a conformal, first barrier layer810 (FIG. 7B) such as a tantalum nitride layer is deposited on thesubstrate800 by atomic layer deposition so as to coat the bottom and sidewalls of thevia808. Thefirst barrier layer810 may or may not be deposited with sufficient thickness to serve as a diffusion barrier to metal atoms of theunderlying metal feature804 and/or of the seed layer to be deposited within the via808 (as described below). In at least one embodiment, wherein thedielectric layer806 comprises a low K dielectric material, thefirst barrier layer810 preferably is deposited with sufficient thickness to provide mechanical stability to the low K dielectric during subsequent processing (e.g., enhanced low K dielectric stress migration and electro-migration performance).
• As an example, if thefirst barrier layer810 comprises tantalum nitride, the thickness of the barrier layer preferably is in the range of about 5 to 50 angstroms, although a range of about 10-20 angstroms may be more preferred. Such thickness ranges are particularly well suited for via widths of less than about 0.2 microns, or even 0.15 or 0.1 microns or below, and/or within vias having aspect ratios of 4:1 or greater. Such an ALD tantalum nitride barrier layer may be deposited, for example, as previously described with reference to FIGS.2 and/or5. Other barrier layers similarly may be deposited.
• Followingstep703 isstep704 wherein thesubstrate800 is transferred from theprocessing chamber132/ALD chamber200 to an HDPPVD barrier layer chamber (e.g., theprocessing chamber134 which may be, for example, one of theHDPPVD chambers300,300′,300″ or400 configured for deposing a second barrier layer through appropriate target material selection). For convenience, it will be assumed that theHDPPVD chamber300′ ofFIG. 3B (e.g., an EnCoRe chamber available from Applied Materials, Inc.) is employed, although any other suitable HDPPVD chamber may be used. Thesubstrate800 is placed on thesupport pedestal318.
• Instep705, the portion of thefirst barrier layer810 that coats the bottom of thevia808 is sputter etched (or “re-sputtered”) within theHDPPVD chamber300 so as to thin or completely remove the first barrier layer from the bottom of thevia808. Sputter etching may be performed, for example, through appropriate manipulation of target power, coil power and pedestal bias as previously described with reference to theprocess500 ofFIG. 5, using similar processing conditions.
• For example, assuming theHDPPVD chamber300′ ofFIG. 3B is employed, resputtering may be performed by flowing an inert gas such as argon into thechamber300′ via thegas supply323. Once pressure within thechamber300′ stabilizes, typically at about 0.5-30 milliTorr although other ranges may be employed, thetarget314, thepedestal318 and thecoil338 are suitably biased to generate a plasma within thechamber300′. For example, a power signal may be applied to thecoil338 via theRF power supply340, little or no power may be applied to thetarget314 via theDC power supply322; and a negative bias may be applied to the pedestal318 (e.g., via the RF power supply332). The RF power signal applied tocoil338 causes argon atoms within thechamber300′ to ionize and form a plasma. By adjusting the duty cycle and/or magnitude of the RF power signal applied to thepedestal318, a negative bias may be created between thepedestal318 and the plasma. The negative bias between thepedestal318 and the plasma causes argon ions to accelerate toward thepedestal318 and thesubstrate800 supported thereon. Accordingly, thesubstrate800 is sputter-etched by the argon ions.
• Under the influence of the negative bias applied to thepedestal318, the argon ions strike thesubstrate800 substantially perpendicularly. Further, the high ion density of theHDPPVD chamber300′, typically greater than 10¹⁰, 10¹¹or 10¹²ions/cm³, increases the anisotropic nature of the sputter etch process. As previously described, such a high degree of anisotropy is especially beneficial, and in some cases essential, for narrow width, high aspect ratio features, as it allows removal of barrier layers from the bottom of narrow and deep vias.
• Because little or no power is applied to the target314 (e.g., 0 to about 500 Watts), little or no material is sputtered from thetarget314 and deposits on thesubstrate800 during sputter etching. The portion of thefirst barrier layer810 formed on the bottom of the via808 thereby may be thinned or removed as shown inFIG. 8C. Note that thebarrier layer810 will be similarly etched from other horizontal regions of the substrate800 (e.g., field regions, although for clarity thebarrier layer810 is not shown as being removed from these regions inFIGS. 8C-8E).
• Referring again toFIG. 7, followingstep705, a second barrier layer812 (FIG. 8D) is deposited over thesubstrate800 within theprocessing chamber134/HDPPVD chamber300′ (step706). Thesecond barrier layer812 may comprise any suitable barrier layer such as tantalum, titanium, tungsten, nitrides thereof, etc. In at least one embodiment wherein thefirst barrier layer810 comprises tantalum nitride, thesecond barrier layer812 may comprise about 10 to 50 angstroms of tantalum as measured on the sidewalls of thevia808. Because of the directionality of high density plasma physical vapor deposition employing pedestal biasing, only a fraction of the material deposited on the field regions and via bottom of thesubstrate800 is deposited on the sidewalls. For example, depending on the aspect ratio and/or via width of the via808, about 50-60% of the barrier material deposited on a field region of the substrate800 (e.g.,region806a inFIG. 8D) is deposited on the bottom region of the via808 (e.g.,region808a inFIG. 8D). Likewise, only about 5% of the barrier material deposited on thefield region806aof thesubstrate800 is deposited on the sidewall region of the via808 (e.g.,region806binFIG. 8D). A suitable tantalum barrier layer may be deposited, for example, employing the processing parameters discussed previously with reference toFIGS. 3A-3B. Other processing parameters similarly may be employed.
• Whilesteps705 and706 have been shown as occurring sequentially, it will be understood that through appropriate manipulation of target power, coil power and/or pedestal bias (e.g., pedestal power and/or duty cycle), thefirst barrier layer810 may be removed from the bottom of the via808 at the same time or during at least a portion of the time that thesecond barrier layer812 is deposited within the via808 (e.g., in a manner similar to the seed deposition described with reference toFIG. 5). Other processing parameters may be employed, for example, such as those described in commonly owned U.S. Pat. No. 6,287,977, issued Sep. 11, 2001 and titled “Method and Apparatus for Forming Improved Metal Interconnects”, which is hereby incorporated by reference herein in its entirety. Likewise, thesecond barrier layer812 may be resputtered from the bottom of the via808 to thin or remove the bottom barrier layer.
• Instep707, thesubstrate800 is transferred from theprocessing chamber134/HDPPVD chamber300′ to a seed layer deposition chamber (e.g., theprocessing chamber136 inFIG. 1 which may or may not be configured in a manner similar tochambers300,300′,300″,400 ofFIGS. 3A-4). Instep708, a seed layer814 (FIG. 8E) is deposited on thesubstrate808. Theseed layer814 may comprise copper, a copper alloy, ruthenium, a ruthenium alloy or any other suitable seed layer material. In at least one embodiment, theseed layer814 comprises about 1000-1500 angstroms of copper, although other thicknesses may be employed. Such a seed layer may be deposited, for example, employing the parameters discussed previously with reference toFIG. 5. If desired, the portion of thesecond barrier layer812 that coats thebottom region808aof the via808 may be thinned and/or removed prior to and/or during seed layer deposition as described previously with reference toFIG. 5.
• After theseed layer814 has been deposited within the via808, instep709 thesubstrate800 may be transferred to a fill chamber and instep710 the via808 may be filled. Thesubstrate800 then may be planarized as shown inFIG. 8F. For example, thesubstrate800 may be transferred to a fill chamber, such as an electro-chemical plating (ECP) chamber, and filled (e.g., with copper or another suitable material, referred to byreference numeral816 inFIG. 8F). Thereafter, thesubstrate800 may be planarized (separate step not shown inFIG. 7), such as via chemical-mechanical polishing. Separate transfer and/or planarization steps are not shown inFIG. 7. Followingstep710, theprocess700 ends atstep711.
• By employing atomic layer deposition to deposit the first barrier layer, adequate sidewall coverage may be achieved, even within high aspect ratio vias, to ensure diffusion resistance and mechanical strength (e.g., even when a low K dielectric interlayer is employed). By employing HDPPVD to deposit the second barrier layer following ALD, a thin (or no) bottom barrier layer may be obtained despite the presence of thick sidewall coverage.
Third Exemplary Inventive Process for Forming a Barrier Layer in a Via
• FIG. 9 is a flow chart of a third exemplary process900 for forming a barrier layer in a via.FIGS. 10A-10F are cross-sectional views illustrating the formation of an exemplary interconnect formed in accordance with the process900.
• The process900 may be performed, for example, with theprocessing system100 using (1) theALD chamber200 ofFIG. 2; (2) a sputter etch chamber (which may or may not be one of theHDPPVD chambers300,300′,300″,400 of FIGS.3A-4); and (3) a seed layer deposition chamber (which may or may not be one of theHDPPVD chambers300,300′,300″,400 ofFIGS. 3A-4). For convenience, the process900 will be described with reference to theprocessing system100. For example, theprocessing chamber132 ofFIG. 1 may be a processing chamber such as theALD chamber200 ofFIG. 2 configured for atomic layer deposition of a barrier layer. Theprocessing chamber134 ofFIG. 1 may be a dedicated sputter etch chamber (such as a pre-clean chamber described below), or one of theHDPPVD chambers300,300′,300″,400 ofFIGS. 3A-4 configured for barrier layer or seed layer deposition. Theprocessing chamber136 ofFIG. 1 may be a seed layer deposition chamber.Processing chamber138 need not be employed. Other processing system configurations and/or processing chamber layouts may be used.
• With regard to any of the first, second and third embodiments described herein, prior to depositing a barrier layer, a patterned or etched substrate dielectric layer (e.g., having vias formed therein) may be cleaned to remove native oxides or other contaminants from the surfaces thereof. For example, reactive gases may be excited into a plasma within a remote plasma source chamber such as a Reactive Pre-clean™ chamber available from Applied Materials, Inc. and employed to remove such native oxides/contaminants as is known in the art. Likewise, a non-chemical, sputter-only system such as a Pre-clean™ chamber also available from Applied Materials, Inc., may be similarly employed. As used herein, a “sputter etch” chamber may include a Pre-clean™ or Reactive Pre-clean™ chamber or any other chamber capable of sputter etching. In at least one embodiment of the invention, the dedicated sputter etching chamber described above may comprise a Pre-clean™ chamber.
• With reference toFIG. 9, the process900 begins withstep901. Instep902, a substrate1000 (FIG. 10A) is loaded into theprocessing chamber132/ALD chamber200 (e.g., via the second robot130 (FIG. 1) of the second transfer chamber126). As shown in.FIG. 10A, thesubstrate1000 includes abulk region1002, ametal feature1004 formed over thebulk region1002 and adielectric layer1006 formed over themetal feature1004. A via1008 extends through thedielectric layer1006 to expose themetal feature1004. For convenience, the via1008 is shown as a single damascene feature. It will be understood that more complicated features, such as dual or triple damascene features, similarly may be employed.
• Thebulk region1002 may comprise, for example, a silicon or other semiconductor region with or without device features (e.g., sources, drains, channels, p-n or n-p junctions, etc.) formed therein. Themetal feature1004 may comprise a metal or otherwise conductive feature such as a line, contact, etc., formed from any suitable material such as aluminum, copper or the like. Thedielectric layer1006 may comprise silicon dioxide, a low K material such as fluorinated silicon glass or oxide (FSG), carbon doped oxide (e.g., SiOC), polymer spin on (e.g., a spin on glass), etc., or any other suitable dielectric material.
• Referring again toFIG. 9, followingstep902 isstep903. Instep903, a conformal, first barrier layer1010 (FIG. 9B) such as a tantalum nitride layer is deposited on thesubstrate1000 by atomic layer deposition so as to coat the bottom and sidewalls of the via1008. In at least one embodiment of the invention, thefirst barrier layer1010 may (but need not) be deposited with sufficient thickness to serve as a diffusion barrier to metal atoms of theunderlying metal feature1004 and/or of the seed layer to be deposited within the via1008 (as described below). If thedielectric layer1006 comprises a low K dielectric material, thefirst barrier layer1010 may be deposited with sufficient thickness to provide mechanical stability to the low K dielectric layer during subsequent processing (e.g., enhanced low K dielectric stress migration and electro-migration performance).
• As an example, if thefirst barrier layer1010 comprises tantalum nitride, the thickness of thefirst barrier layer1010 preferably is in the range of about 20 to 100 angstroms, although a range of about 50-65 angstroms may be preferred. Such thickness ranges are particularly well suited for via widths of less than about 0.2 microns, or even 0.15 or 0.1 microns or below, and/or within vias having aspect ratios of 4:1 or greater. Such an ALD tantalum nitride barrier layer may be deposited, for example, as previously described with reference to FIGS.2 and/or5. Other barrier layers similarly may be deposited.
• Followingstep903 isstep904 wherein thesubstrate1000 is transferred from theprocessing chamber132/ALD chamber200 to a sputter etch chamber (e.g., theprocessing chamber134 which may be, for example, a dedicated sputter etch chamber or an HDPPVD chamber such as one of theHDPPVD chambers300,300′,300″ or400 configured for seed layer deposition). For convenience, the sputter etch chamber will be referred to only as the processing chamber134 (FIG. 1).
• Instep905, the portion of thefirst barrier layer1010 that coats the bottom of the via1008 is sputter etched (or “re-sputtered”) within theprocessing chamber134 so as to thin or completely remove thefirst barrier layer1010 from the bottom of the via1008. Sputter etching may be performed, for example, by any conventional technique or if one of theHDPPVD chambers300,300′,300″,400 is employed through appropriate manipulation of target power, coil power and/or pedestal bias as previously described with reference to the process ofFIG. 5. The portion of thefirst barrier layer1010 formed on the bottom of the via1008 is shown as being thinned or removed inFIG. 10C. Thebarrier layer1010 may be similarly etched from other horizontal regions of the substrate1000 (e.g., field regions, although for clarity thebarrier layer1010 is not shown as being removed from these regions inFIGS. 10C-10E). As stated, rather than employing a dedicated sputter etch chamber, the sputter etch step (step905) may be performed, for example, in an HDPPVD seed chamber as described previously with reference toFIG. 5.
• Referring again toFIG. 9, followingstep905, thesubstrate1000 is transferred back into theprocessing chamber132/ALD chamber200 (step906) and a second barrier layer1012 (FIG. 10D) is deposited over thesubstrate1000 by atomic layer deposition instep907. Thesecond barrier layer1012 may comprise any suitable barrier layer such as tantalum, titanium, tungsten, nitrides thereof, etc. In at least one embodiment wherein thefirst barrier layer1010 comprises tantalum nitride having a thickness range of about 20 to 100 angstroms, thesecond barrier layer1012 may comprise about 5 to 20 angstroms of tantalum nitride, and preferably about 10 angstroms. As described in U.S. patent application Ser. No. 10/199,415, filed Jul. 18, 2002 and titled “ENHANCED COPPER GROWTH WITH ULTRATHIN BARRIER LAYER FOR HIGH PERFORMANCE INTERCONNECTS” (Attorney Docket No. 6463), which is hereby incorporated by reference herein in its entirety, refractory metal nitride barrier layers in this thickness range (below about 20 angstroms) may provide adequate barrier properties while allowing grain growth of a first metal layer to continue across the barrier layer into a second metal layer, thereby enhancing the electrical performance of an interconnect. A suitable tantalum nitride barrier layer may be deposited, for example, employing the processing parameters discussed previously with reference toFIG. 2. Other processing parameters similarly may be employed.
• Instep908, thesubstrate1000 is transferred from theprocessing chamber132/ALD chamber200 to a seed layer deposition chamber (e.g., processingchamber136 inFIG. 1 which may or may not be configured in a manner similar tochambers300,300′,300″,400 ofFIGS. 3A-4). Instep909, a seed layer1014 (FIG. 10E) is deposited on thesubstrate1000. Theseed layer1014 may comprise copper, a copper alloy, ruthenium, a ruthenium alloy or any other suitable seed layer material. In at least one embodiment, theseed layer1014 comprises about 1000-1500 angstroms of copper, although other thicknesses may be employed. Such a seed layer may be deposited, for example, employing the parameters discussed previously with reference toFIG. 5. If desired, the portion of thesecond barrier layer1012 that coats the bottom region of the via1008 may be thinned and/or removed prior to and/or during seed layer deposition as described previously with reference toFIG. 5.
• After theseed layer1014 has been deposited within the via1008, the via1008 may be filled and thesubstrate1000 may be planarized as shown inFIG. 10F. For example, thesubstrate1000 may be transferred to a fill chamber (step910), such as an electro-chemical plating (ECP) chamber, and filled (e.g., with copper or another suitable material, referred to byreference numeral1016 inFIG. 10F) instep911. Thereafter, thesubstrate1000 may be planarized (separate substrate transfer and planarization steps not shown inFIG. 9), such as via chemical-mechanical polishing. Followingstep911, the process900 ends atstep912.
• By employing atomic layer deposition to deposit the first barrier layer, adequate sidewall coverage may be achieved, even within high aspect ratio vias, to ensure diffusion resistance and mechanical strength (e.g., even when a low K dielectric interlayer is employed). Sputter etching the first barrier layer and employing a second, thinner ALD barrier layer allows a thin bottom barrier layer may be obtained despite the presence of thick sidewall coverage. The use of only ALD barrier layers also improves overall barrier layer uniformity, and decreases deposition on field regions of the substrate. Post metallization process times, such as chemical mechanical polishing times, thereby may be reduced.
• The foregoing description discloses only exemplary embodiments of the invention. Modifications of the above disclosed apparatus and methods which fall within the scope of the invention will be readily apparent to those of ordinary skill in the art. For instance, other processes than those described herein may be employed during barrier layer, seed layer or fill layer formation, and/or during planarization. Other processing systems than those described herein may be employed.
• It will be understood that theprocesses500,700 and900 are merely exemplary interconnect formation processes that may be performed within theinventive system100 ofFIGS. 1-4. Other interconnect formation processes also may be performed by thesystem100.
• The controller140 (and/or thecontrollers330,476) may contain computer program code, computer program products and/or data structures for performing one or more of the steps ofprocesses500,700 or900.
• In the third embodiment of the invention described with reference toFIGS. 9-10F, the first and second ALD deposited barrier layers need not comprise the same material and/or may be deposited in different ALD chambers. In at least one embodiment, the second ALD barrier layer may be thicker or thinner than, or the same thickness as, the first ALD barrier layer.
• In any of the embodiments described herein, a thin “flash” layer may be deposited on via sidewalls and/or bottoms prior to seed layer deposition (e.g., about 20-40 angstroms of Ta). Any form of substrate pedestal biasing may be employed (e.g., RF, pulsed DC, DC, etc.).
• FIG. 11 is a schematic top-view of another exemplarymulti-chamber processing system100′ that may be adapted to perform one or more the inventive processes described herein. For example, theprocessing system100′ may be employed to perform a process similar to theprocess500 described previously with reference toFIGS. 5-6E, as well as other processes.
• Theprocessing system100′ is similar to the Endura™ Integrated Cu Barrier/Seed (iCuB/S™) System available from Applied Materials, Inc. Other processing systems may be similarly employed.
• Theprocessing system100′ generally includesload lock chambers102′,104′ for transferring substrates into and out of thesystem100′. Typically, since thesystem100′ is under vacuum, theload lock chambers102′,104′ are adapted to “pump down” substrates introduced into thesystem100 to a suitable vacuum condition. As shown inFIG. 11, theload lock chambers102′,104′ are coupled to afirst transfer chamber106′ and to afactory interface108′.
• Thetransfer chamber106′ includes afirst robot110′ that is adapted to transfer substrates between theload lock chambers102′,104′, degas chambers112a′ and112b′ and pre-clean chambers114a′ and114b′. Thefirst robot110′ also transfers substrates to/from one or more pass-throughchambers122′,124′.
• The degas chambers112a′,112b′ and the pre-clean chambers114a′,114b′ may comprise any conventional degas and pre-clean chambers, respectively. In at least one embodiment of the invention, the pre-clean chambers114a′,114b′ comprise Preclean™ XTe chambers available from Applied Materials, Inc.
• The pass-throughchambers122′,124′ are coupled to asecond transfer126′ which houses asecond robot130′. Thesecond robot130′ is adapted to transfer substrates between the pass-throughchambers122′,124′, high density plasma physical vapor deposition (HDPPVD) chambers132a′ and132b′ (both of which are adapted to deposit metal seed layers) and atomic layer deposition (ALD)chambers134a′ and134b′ (both of which are adapted to deposit barrier layers).
• The HDPPVD chambers132a′,132b′ and theALD chambers134a′,134b′ may comprise any conventional HDPPVD seed and ALD barrier layer chambers, respectively. In at least one embodiment of the invention, the HDPPVD chambers132a′,132b′ comprise SIP™ EnCoRe chambers configured for copper seed layer deposition (SIP™ EnCoRe Cu chambers) and available from Applied Materials, Inc.; and theALD chambers134a′,134b′ comprise Altra™ ALD chambers configured for tantalum nitride layer deposition (Altra™ ALD TaN chambers) and also available from Applied Materials, Inc. Other chambers, seed layer materials and/or barrier layer materials may be employed.
• Eachrobot110′,130′ may be adapted to transfer multiple substrates simultaneously and in an independent manner (e.g., a dual blade robot having independently controllable blades) or in a coordinated manner (e.g., a dual blade robot in which one blade retracts as the other blade extends). Such robots are described in U.S. Pat. Nos. 5,789,878 and 6,379,095, both of which are hereby incorporated by reference herein in their entirety. For example, theprocessing system100′ may be based on an Endura™ XP mainframe and employ XP dual blade robots, available from Applied Materials, Inc.
• Thefactory interface108′ includes abuffer chamber135′ which houses a third robot137′ and which is coupled to a plurality of loadports139a′,139b′. Each loadport may or may not be configured with pod opening capability for opening sealed substrate carriers. It will understood that in general, any number of robots may be located within thebuffer chamber135′, and that any number of loadports may be coupled to thebuffer chamber135′.
• Thesystem100′ also may include acontroller140′ adapted to control, for example, substrate transfer operations within thetransfer chambers106′,126′ and/or the pass-throughchambers122′,124′, substrate processing performed within one or more of the chambers112a′,112b′,114a′,114b′,132a′,132b′,134a′,134b′, and the like. In at least one embodiment, thecontroller140′ is programmed to perform one or more of the inventive processes described herein that may be implemented, for example, as one or more computer program products. Thecontroller140′ may be a system controller, a dedicated hardware circuit, an appropriately programmed general purpose computer, or any other equivalent electronic, mechanical or electro-mechanical device.
• Thesystem100′ allows simultaneous processing of multiple substrates. For example, a process, such as theprocess500 ofFIG. 5, may be performed on a first substrate using one or more of the chambers112a′,114a′,132a′ and134a′ while the process is simultaneously performed on a second substrate using one or more of thechambers112b′,114b′,132b′ and134b′. That is, a process may be performed on the first substrate during at least a portion of the time that the same process is performed on the second substrate. Use of independently controllable, dual blade robots increases throughput by allowing substrate transfers for the first substrate to be independent from substrate transfers for the second substrate. Similar systems may be employed with the processes described previously with reference toFIGS. 7-10F.
• Accordingly, while the present invention has been disclosed in connection with exemplary embodiments thereof, it should be understood that other embodiments may fall within the spirit and scope of the invention, as defined by the following claims.

Claims (32)

1-57. (canceled)

58. A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising:

(a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;

(b) etching through at least part of the first portion of the diffusion barrier at the bottoms of a plurality of vias to expose at least part of an underlying metal layer while simultaneously depositing a second portion of the diffusion barrier on at least field regions of the wafer substrate;

(c) depositing a third portion of the diffusion barrier, which covers at least the bottoms of the vias; and

(d) depositing the metal conductive layer over the surface of the wafer substrate.

59. The method ofclaim 58, wherein (b) and (c) are performed in the same processing chamber.

60. The method ofclaim 59, wherein the processing chamber is a plasma physical vapor deposition (PVD) chamber.

61. The method ofclaim 58, further comprising a degas operation prior to (a).

62. The method ofclaim 58, wherein (a) comprises depositing the first portion of diffusion barrier to a thickness of between about 5 and 100 angstroms over field regions on the surface of the wafer substrate.

63. The method ofclaim 58, wherein (b) comprises depositing the second portion of diffusion barrier elsewhere on the wafer to between about 10 and 50 Å at least as on sidewalls of the plurality of vias.

64. The method ofclaim 63, wherein (b) further comprises depositing the second portion of diffusion barrier elsewhere on the wafer to between about 200 and 1000 Å on field regions of the wafer substrate and a plurality of horizontal trench surfaces of the wafer substrate.

65. The method ofclaim 58, wherein (c) comprises depositing the third portion of diffusion barrier to between about 20 and 40 Å on bottoms of the plurality of vias.

66. The method ofclaim 58, wherein (a) comprises sputtering a metal from a target having an applied DC power of between about 10 and 50 kilowatts, without significantly biasing the wafer substrate.

67. The method ofclaim 58, wherein (a) comprises using

chemical vapor deposition (CVD),

physical vapor deposition (PVD), or

atomic layer deposition (ALD).

68. The method ofclaim 58, wherein at least one portion of the diffusion barrier comprises a material selected from the group consisting of

tantalum,

nitrogen-doped tantalum,

tantalum nitride,

titanium nitride,

tungsten nitride and

silicon containing versions of any of these.

69. The method ofclaim 58, wherein (b) comprises sputtering a metal from a target having an applied DC power of less than about 0.5 kilo Watts, while applying a bias to the wafer substrate.

70. The method ofclaim 69, wherein the bias comprises RF power of between about 400 and 1000 Watts

71. The method ofclaim 58, wherein (b) is performed under conditions having an etch-to-deposition ratio of greater than 1 at the bottoms of the vias.

72. The method ofclaim 58, wherein (c) comprises a process selected from the group consisting of

chemical vapor deposition (CVD),

physical vapor deposition (PVD), and

atomic layer deposition (ALD).

73. The method ofclaim 58, further comprising, after (c) but prior to (d), etching through some of the third portion of the diffusion barrier at the bottoms of a plurality of vias, without etching to expose an underlying metal structure.

74. The method ofclaim 58, wherein (d) comprises depositing copper containing metal over the surface of the wafer substrate.

75. The method ofclaim 74, wherein the metal is a copper seed layer.

76. The method ofclaim 58, wherein at least (b) and (c) are performed in the same processing chamber.

77. The method ofclaim 58, wherein at least (a) through (c) are all performed in the same processing chamber.

78. A method for depositing a diffusion barrier and a metal conductive layer on a partially fabricated integrated circuit containing a plurality of unlanded vias, the method comprising:

(a) depositing a first portion of the diffusion barrier on the surface of the partially fabricated integrated circuit;

(b) etching through at least part of the first portion of the diffusion barrier at the bottoms of a plurality of unlanded and landed vias to expose at least part of an underlying metal layer while simultaneously depositing a second portion of the diffusion barrier on at least field regions of the surface of the partially fabricated integrated circuit;

(c) depositing a third portion of the diffusion barrier, which covers at least the bottoms of the vias; and

(d) depositing the metal conductive layer over the surface of the wafer substrate.

79. The method ofclaim 78, wherein (b) and (c) are performed in the same processing chamber.

80. The method ofclaim 79, wherein the processing chamber is a plasma physical vapor deposition (PVD) chamber.

81. The method ofclaim 78, wherein (a) and/or (c) comprise a processes selected from the group consisting of

chemical vapor deposition (CVD),

physical vapor depositon (PVD), and

atomic layer deposition (ALD).

82. The method ofclaim 78, wherein at least one portion of the diffusion barrier comprises a material selected from the group consisting of

tantalum,

nitrogen-doped tantalum,

tantalum nitride,

titanium nitride,

tungsten nitride and

silicon containing versions of any of these.

83. The method ofclaim 78, wherein (b) comprises sputtering a metal from a target having an applied DC power of less than about 0.5 kilo Watts, while applying a bias to the wafer substrate.

84. The method ofclaim 78, wherein (d) comprises depositing copper-containing metal over the surface partially fabricated integrated circuit.

85. The method ofclaim 84, wherein the metal is a copper seed layer.

86. The method ofclaim 78, wherein at least (a) and (b) are performed in the same processing chamber.

87. The method ofclaim 78, wherein at least (b) and (c) are performed in the same processing chamber.

88. The method ofclaim 78, wherein at least (a) through (c) are all performed in the same processing chamber.

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