US20050260804A1 - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

Description

CROSS-REFERENCE TO RELATED APPLICATION
• This application claims priority to and the benefit of Korean Patent Application No. 10-2004-0037052, filed May 24, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTIONFIELD OF THE INVENTION
• The present invention relates to a semiconductor device and method of fabricating the same and, more particularly, to a semiconductor device and method of fabricating the same, wherein a contact hole, a via hole and a via contact hole have multiple profiles with various taper angles.
DISCUSSION OF THE BACKGROUND
• Generally, thin film transistors (TFT) are utilized in flat panel displays, image sensors, copiers, printers, scanners, and so forth.
• Examples of a flat panel display include a Liquid Crystal Display (LCD), an organic electro-luminescence (EL) device, etc. A representative technology of the flat panel display is the organic EL device, which is may be classified into an active matrix (AM) organic EL device and a passive matrix (PM) organic EL device. An active device such as a TFT controls each pixel in the AM organic EL device. Hence, the AM organic EL device may be superior to the PM organic EL device in terms of speed, viewing angle, and contrast ratio, and it may have a very high resolution.
• Silicon TFTs are often used for organic EL devices because they may be fabricated at a low temperature of 400° C. or less, stability of the device characteristics may be excellent, and they may be easily integrated on a large-area glass substrate.
• FIG. 1A andFIG. 1B are cross-sectional views showing a conventional method of fabricating a contact hole of a TFT.
• FIG. 1A is a cross-sectional view showing a process of forming a buffer layer, a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric on a substrate. As shown inFIG. 1A, a silicon oxide or siliconnitride buffer layer12 may be formed on aninsulating substrate11 such as plastic or glass, and then an amorphous silicon layer is formed thereon. The amorphous silicon layer may be crystallized to form a polycrystalline silicon layer, which is then patterned to form asemiconductor layer13. Agate insulating layer14 may be formed on the entire surface of the substrate, and a material for forming a gate electrode is deposited and patterned to form thegate electrode15. An interlayer dielectric16, which protects or insulates elements therebelow and may be made of a silicon oxide layer or a silicon nitride layer, may be formed on the entire surface of the substrate.
• FIG. 1B is a cross-sectional view showing a process of forming the contact hole using a photoresist pattern on the substrate. AsFIG. 1B shows, aphotoresist pattern17 may be formed and the photoresist is dry etched using the photoresist pattern as a mask to form acontact hole18. Thephotoresist pattern17 is then removed, thecontact hole18 may be filled with a conductive material, and source and drain electrodes (not shown) are formed on the interlayer dielectric16.
• However, in the above-mentioned method of forming the contact hole, asFIG. 2 shows, the dry etching may cause apolymer21 to be formed below thecontact hole18, which penetrates the interlayer dielectric17 and thegate insulating layer14 and exposes a surface of thesemiconductor layer13. Hence, a specific polymer removal solution may be required to remove thepolymer21, which adds an additional process. Further, the surface of thesemiconductor layer13 may be damaged by overetching22, thereby making contact resistance non-uniform.
SUMMARY OF THE INVENTION
• The present invention provides a semiconductor device and method of fabricating the same, which performs dry etching employing at least one of high etch rate dry etching and high selectivity dry etching and performs wet etching in a final etching process when forming a contact hole of a semiconductor layer and source and drain electrodes, a via hole of a positive electrode and source and drain electrodes, a via hole between metal interconnection lines, or a via contact hole. Consequently, the contact hole, the via hole or the via contact hole may have multiple profiles with various taper angles, and an etch residue caused by etching may be completely removed during wet etching.
• Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.
• The present invention discloses a semiconductor device including a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of a wet etch profile and a dry etch profile.
• The present invention also discloses a method of fabricating a semiconductor device including forming a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric on a substrate, performing at least one of a dry etching process and a wet etching process on a portion of the interlayer dielectric and the gate insulating layer to form a contact hole to a predetermined depth, and wet etching the contact hole to complete the contact hole and expose a portion of the semiconductor layer.
• The present invention also discloses a semiconductor device including a substrate, a thin film transistor (TFT) formed on the substrate and having a source electrode and a drain electrode, a passivation layer and a planarization layer formed on the TFT, and a via hole penetrating the passivation layer and the planarization layer and exposing a portion of either the source electrode or the drain electrode. The via hole has a multiple profile in which an upper portion of the via hole has a wet etch profile and a lower portion has at least one of a wet etch profile and a dry etch profile.
• The present invention also discloses a method of fabricating a semiconductor device including forming a thin film transistor (TFT) including source and drain electrodes on a substrate, forming a passivation layer and a planarization layer on the TFT, performing at least one of a dry etching process and a wet etching process on a portion of the passivation layer and the planarization layer to form a via hole with a predetermined depth, and wet etching the via hole to complete the via hole and expose a portion of either the source or drain electrode.
• The present invention also discloses a semiconductor device including a substrate, a metal interconnection line formed on the substrate, an interlayer dielectric layer formed on the metal interconnection line, and a via hole penetrating the interlayer dielectric and exposing a portion of the metal interconnection line. The via hole has a multiple profile in which an upper portion of the via hole has a wet etch profile and a lower portion has at least one of a wet etch profile and a dry etch profile.
• The present invention also discloses a method of fabricating a semiconductor device including forming a metal interconnection line and an interlayer dielectric on a substrate, performing at least one of a dry etching process and a wet etching process on a portion of the interlayer dielectric to form a via hole to a predetermined depth, and wet etching the via hole to complete the via hole and expose a portion of the metal interconnection line.
• The present invention also discloses a semiconductor device including a substrate, a semiconductor layer, a gate insulating layer, and a gate electrode formed on the substrate, a planarization layer formed on the substrate, and a via contact hole penetrating the planarization layer and the gate insulating layer and exposing a portion of the semiconductor layer. The via contact hole has a multiple profile in which an upper portion of the via contact hole has a wet etch profile and a lower portion has at least one of a wet etch profile and a dry etch profile.
• The present invention also discloses a method of fabricating a semiconductor device including forming a semiconductor layer, a gate insulating layer, and a gate electrode on a substrate, forming a planarization layer on the substrate, performing at least one of a dry etching process and a wet etching process on a portion of the gate insulating layer and the planarization layer to form a via contact hole to a predetermined depth, and wet etching the via contact hole to complete the via contact hole and expose a portion of the semiconductor layer.
• The present invention also discloses a semiconductor device including a substrate; a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric formed on the substrate; and a thin film transistor (TFT) region including a contact hole, the contact hole penetrating the gate insulating layer and the interlayer dielectric, exposing a portion of the semiconductor layer, and having a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of a wet etch profile and a dry etch profile. A metal interconnection line and an insulating layer are formed on the substrate and spaced apart from the TFT region by a predetermined interval, and a via hole penetrates the insulating layer and has a multiple profile in which an upper portion of the via hole has a wet etch profile and a lower portion of the via hole has at least one of a wet etch profile and a dry etch profile.
• The present invention also discloses a method of fabricating a semiconductor device including forming a semiconductor layer, a gate insulating layer, and a gate electrode in a thin film transistor (TFT) region of a substrate, and forming a metal interconnection line in a metal interconnection line region spaced apart from the TFT region by a predetermined interval. An interlayer dielectric is formed in the TFT region, and an insulating layer is formed in the metal interconnection line region. At least one of a dry etching process and a wet etching process is performed on a portion of the insulating layer in the metal interconnection line region, and on the interlayer dielectric and the gate insulating layer in the TFT region, to form a contact hole and a via hole each having a predetermined depth. The contact hole and the via hole are wet etched to complete the contact hole and the via hole and expose a portion of the semiconductor layer in the TFT region and a portion of the metal interconnection line in the metal interconnection line region.
• It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
• The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
• FIG. 1A andFIG. 1B are cross-sectional views showing a conventional method of forming a contact hole of a TFT.
• FIG. 2 is a cross-sectional view showing a problem that may be associated with a conventional contact hole.
• FIG. 3A,FIG. 3B,FIG. 3C,FIG. 3D andFIG. 3E are cross-sectional views showing a method of forming a contact hole and a device having the contact hole in accordance with embodiments of the present invention.
• FIG. 4A,FIG. 4B,FIG. 4C,FIG. 4D,FIG. 4E,FIG. 4F andFIG. 4G are cross-sectional views showing a method of forming a contact hole, and cross-sectional views and a cross-sectional photograph of a device having the contact hole in accordance with embodiments of the present invention.
• FIG. 5A,FIG. 5B,FIG. 5C,FIG. 5D andFIG. 5E are cross-sectional views showing a method of forming a via hole and a device having the via hole in accordance with embodiments of the present invention.
• FIG. 6A,FIG. 6B,FIG. 6C,FIG. 6D andFIG. 6E are cross-sectional views showing a method of forming a via hole and a device having the via hole in accordance with embodiments of the present invention.
• FIG. 7A,FIG. 7B,FIG. 7C,FIG. 7D andFIG. 7E are cross-sectional views showing a method of forming a via hole and a device having the via hole in accordance with embodiments of the present invention.
• FIG. 8A,FIG. 8B,FIG. 8C,FIG. 8D andFIG. 8E are cross-sectional views showing a method of forming a via hole and a device having the via hole in accordance with embodiments of the present invention.
• FIG. 9A,FIG. 9B,FIG. 9C,FIG. 9D andFIG. 9E are cross-sectional views showing a method of forming a via contact hole and a device having the via contact hole in accordance with embodiments of the present invention.
• FIG. 10A,FIG. 10B,FIG. 10C,FIG. 10D andFIG. 10E are cross-sectional views showing a method of forming a via contact hole and a device having the via contact hole in accordance with embodiments of the present invention.
• FIG. 11 is a cross-sectional view showing a method of simultaneously forming a contact hole and a via hole, and a device having the contact and via holes in accordance with embodiments of the present invention.
• FIG. 12 is a cross-sectional view showing a method of simultaneously forming a contact hole and a via hole, and a device having the contact hole and the via hole in accordance with embodiments of the present invention.
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
• The present invention will be described below with reference to the accompanying drawings showing exemplary embodiments of the invention.
<First Embodiment>
• FIG. 3A,FIG. 3B,FIG. 3C,FIG. 3D andFIG. 3E are cross-sectional views showing a method of forming a contact hole and a device having the contact hole in accordance with embodiments of the present invention.
• First,FIG. 3A is a cross-sectional view showing a process of forming a buffer layer, a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric on a substrate. AsFIG. 3A shows, abuffer layer102 may be formed on an insulatingsubstrate101, which may be made of a material such as, for example, plastic or glass. Thebuffer layer102 may prevent moisture or impurities from the insulating substrate from diffusing, and it may facilitate crystallization of the semiconductor layer by adjusting a heat transfer speed during crystallization.
• Next, an amorphous silicon layer may be formed on thebuffer layer102, crystallized to be a polycrystalline silicon layer or a single crystalline silicon layer, and then patterned to form asemiconductor layer103. A chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method, for example, may be used to form the amorphous silicon layer. Additionally, the amorphous silicon layer may be dehydrated to reduce the presence of hydrogen during or after the layer's formation.
• Next, agate insulating layer104 may be formed on the entire surface of the substrate including thesemiconductor layer103, and a material for forming a gate electrode may then be formed on thegate insulating layer104 and patterned to form agate electrode105. After forming thegate electrode105, impurity ions may be implanted in thesemiconductor layer103, using the gate electrode as a mask, thereby defining source, drain, and channel regions in thesemiconductor layer103.
• Aninterlayer dielectric106, which protects or electrically insulates elements formed therebelow from each other, may then be formed on the entire surface of the substrate.
• In this case, thebuffer layer102, thegate insulating layer104, and theinterlayer dielectric106 may be formed of, for example, an oxide layer such as a silicon oxide layer or a nitride layer such as a silicon nitride layer.
• Next,FIG. 3B is a cross-sectional view showing the step of forming a photoresist pattern for forming a contact hole on the substrate. AsFIG. 3B shows, aphotoresist pattern107 for forming the contact hole may be formed on the substrate including thebuffer layer102, thesemiconductor layer103, thegate insulating layer104, thegate electrode105, and theinterlayer dielectric106.
• Thephotoresist pattern107 may be formed by coating a photoresist on the substrate using a spin method or a spray method. Subsequent exposure and development processes are then carried out.
• Next,FIG. 3C is a cross-sectional view showing the step of forming a contact hole with a predetermined depth by dry etching a portion of the interlayer dielectric and the gate insulating layer by means of the photoresist pattern. AsFIG. 3C shows, theinterlayer dielectric106 and thegate insulating layer104 may be dry etched using thephotoresist pattern107 as a mask to thereby form acontact hole108 with a predetermined depth.
• In this case, as shown in regions A and B ofFIG. 3C, respectively, theinterlayer dielectric106 may be penetrated and a portion of thegate insulating layer104 may be ethced, or a portion of theinterlayer dielectric106 may be etched. Alternatively, although not shown, theinterlayer dielectric106 may be penetrated without etching thegate insulating layer104. In other words, thecontact hole108 may be formed by the dry etching process to have a desired depth so that thesemiconductor layer103 is not damaged by the dry etching process, thesemiconductor layer103 is not exposed, thereby preventing residues such as a polymer from attaching thereto, and thecontact hole108 may have a profile in a desired shape.
• Additionally, when dry etching, theinterlayer dielectric106 and thegate insulating layer104 may be etched at a high etch rate to adjust thetaper angle109 and depth of thecontact hole108, and the contact hole may be dry etched to have an angle almost perpendicular to formed layers. In this case, thetaper angle109 of thecontact hole108 may be in a range of about 60° to about 90°, preferably in a range of about 75° to about 90°.
• In this case, an ion etching process such as, for example, an ion beam etching process and a radio frequency (RF) sputter etching process, or a reactive etching process such as, for example, a reactive ion etching process may be utilized for the dry etching.
• Next,FIG. 3D is a cross-sectional view showing the step of wet etching the contact hole formed to a predetermined depth to expose the surface of the semiconductor layer, thereby completing the contact hole. AsFIG. 3D shows, the dry etchedcontact hole108 is wet etched to expose the surface of thesemiconductor layer103.
• In this case, as shown in region A ofFIG. 3D, a photoresist pattern may not be removed, thecontact hole108 formed by the dry etching may be wet etched to expose the surface of the semiconductor layer, and alow taper angle110 of thecontact hole114 may be formed by isotropic wet etching. Alternatively, as shown in region B ofFIG. 3D, a photoresist pattern may be removed and a small taper angle of the contact hole may be formed using isotropic wet etching. When wet etching after removing the photoresist pattern, the surface of theinterlayer dielectric106 is etched, which may reduce the thickness of theinterlayer dielectric106. This does not pose a problem, however, when theinterlayer dielectric106 is appropriately formed considering this consequence.
• In this case, thetaper angle110 of thecontact hole114 formed by wet etching may have a range of about 5° to about 60°, preferably a range of about 5° to about 45°. Additionally, the wet etching may be carried out such that the theinterlayer dielectric106 and thegate insulating layer104 are wet etched using an etching solution having high selectivity against etching thesemiconductor layer103, so that thesemiconductor layer103 may not be damaged by the wet etching solution, even when the surface of the semiconductor layer is exposed or already exposed, and polymer residues thereon may also be removed.
• Accordingly, a doubleprofile contact hole114 is formed such that an upper portion of thecontact hole114 has aprofile111 formed by wet etching and a lower portion of the contact hole114 has aprofile112 formed by dry etching.
• FIG. 3E is a cross-sectional view showing a process of forming a TFT having the above-mentioned double profile contact hole. AsFIG. 3E shows, a material for forming source and drain electrodes may be deposited on the entire surface of the substrate having thecontact hole114 and then patterned to form source and drainelectrodes113, thereby completing the TFT. Consequently, thecontact hole114 between the source and drainelectrodes113 and thesemiconductor layer103 has an upper portion with a wet etch profile and a lower portion with a dry etch profile. Therefore, polymer residues may be removed so that they do not cause any contact resistance, and the surface of thesemiconductor layer103 may not be damaged during etching. Further, the contact hole's double profile facilitates filling the contact hole with the material for forming the source and drain electrodes.
<Second Embodiment>
• FIG. 4A,FIG. 4B,FIG. 4C,FIG. 4D,FIG. 4E,FIG. 4F andFIG. 4G are cross-sectional views showing a method of forming a contact hole, and cross-sectional views and a cross-sectional photograph of a device having the contact hole in accordance with embodiments of the present invention.
• First,FIG. 4A is a cross-sectional view showing the step of forming a buffer layer, a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric on a substrate. AsFIG. 4A shows, abuffer layer152 may be formed on an insulatingsubstrate151, which may be made of a material such as, for example, plastic or glass. Thebuffer layer152 may prevent moisture or impurities from the insulatingsubstrate151 from diffusing, and it may facilitate crystallization of the semiconductor layer by adjusting a heat transfer speed during crystallization.
• Next, an amorphous silicon layer may be formed on thebuffer layer152, crystallized to form a polycrystalline silicon layer or a single crystalline silicon layer, and then patterned to form asemiconductor layer153. In this case, a CVD method or a PVD method, for example, may be used to form the amorphous silicon layer. Additionally, the amorphous silicon layer may be dehydrated to reduce the presence of hydrogen during or after the layer's formation.
• Next, agate insulating layer154 may be formed on the entire surface of the substrate having thesemiconductor layer153, and a material for forming a gate electrode may be formed on thegate insulating layer154 and patterned to form agate electrode155. After forming thegate electrode155, impurity ions may be implanted in thesemiconductor layer153, using thegate electrode155 as a mask, thereby defining source, drain, and channel regions in thesemiconductor layer153.
• Next, aninterlayer dielectric156, which may protect or electrically insulate elements formed therebelow from each other, may then be formed on the entire surface of the substrate.
• In this case, thebuffer layer152, thegate insulating layer154, and theinterlayer dielectric156 may be formed of an oxide layer such as, for example, a silicon oxide layer or a nitride layer such as, for example, a silicon nitride layer.
• Thebuffer layer152 may be omitted under appropriate circumstances.
• Next,FIG. 4B is a cross-sectional view showing the step of forming a photoresist pattern for forming a contact hole on the substrate. AsFIG. 4B shows, aphotoresist pattern157 for forming the contact hole may be formed on the substrate including thebuffer layer152, thesemiconductor layer153, thegate insulating layer154, thegate electrode155, and theinterlayer dielectric156.
• Thephotoresist pattern157 may be formed by coating a photoresist on the substrate using a spin method or a spray method. Subsequent exposure and development processes are then carried out.
• Next,FIG. 4C is a cross-sectional view showing the step of dry etching a portion of the interlayer dielectric and the gate insulating layer at a high etch rate to have a first depth. AsFIG. 4C shows, theinterlayer dielectric156 and thegate insulating layer154 may be dry etched at a high etch rate using thephotoresist pattern157 as a mask to thereby form afirst contact hole158 to a first depth.
• In this case, as shown in regions A and B ofFIG. 4C, respectively, theinterlayer dielectric156 may be penetrated and a portion of thegate insulating layer154 may be etched, or a portion of theinterlayer dielectric156 may be etched. Alternatively, although not shown, theinterlayer dielectric156 may be penetrated without etching thegate insulating layer154. In other words, thecontact hole158 may be formed by high etch rate dry etching to have a desired depth so that thesemiconductor layer153 is not damaged by the dry etching process, thesemiconductor layer153 is not exposed, thereby preventing residues such as a polymer from attaching thereto, and thecontact hole158 may have a profile in a desired shape.
• Additionally, theinterlayer dielectric156 and thegate insulating layer154 may be dry etched at a fast speed because of the high etch rate. In this case, ataper angle159 of thefirst contact hole158 may be in a range of about 30° to about 70°, preferably in a range of about 30° to about 50°.
• In this case, an ion etching process such as, for example, an ion beam etching process and a RF sputter etching process, or a reactive etching process such as, for example, a reactive ion etching process and an induced coupled plasma etching process, may be used for the high etch rate dry etching.
• Next,FIG. 4D is a cross-sectional view showing the step of dry etching the gate insulating layer and the interlayer dielectric etched to the first depth with high selectivity against etching the semiconductor layer to thereby have a second depth. AsFIG. 4D shows, thegate insulating layer154 and theinterlayer dielectric156 of thefirst contact hole158 having the first depth etched at a high etch rate dry etching may be etched by high selectivity etching against etching thesemiconductor layer153 to thereby form asecond contact hole160 having the second depth. In this case, the profile of thefirst contact hole158 may be maintained in the lower portion of thesecond contact hole160, which results from the fact that the etching speed in the high selectivity etching is slow while an etch for etching thegate insulating layer154 and theinterlayer dielectric156 is high.
• In this case, the high selectivity dry etching means that the etch rate for thegate insulating layer154 and theinterlayer dielectric156 is high, and the etch rate for thesemiconductor layer153 is low. Consequently, thegate insulating layer154 and theinterlayer dielectric156 are etched by high selectivity dry etching while thesemiconductor layer153 is minimally etched, and ataper angle161 of thesecond contact hole160 may have a profile nearly perpendicular to adjacent layers because the photoresist pattern is not much recessed, and the taper angle may be higher than that of the first contact hole having the first depth. In other words, thetaper angle161 of thesecond contact hole160 having the second depth formed by high selectivity dry etching may be in a range of about 60° to about 90°. In this case, thetaper angle161 is preferably in a range of about 70° to about 90°.
• Thesecond contact hole160 having the second depth may be formed to a depth where it does not expose thesemiconductor layer153, as shown in region A ofFIG. 4D, or it may be formed to a depth where it exposes thesemiconductor layer153, as shown in region B ofFIG. 4D. This is possible because the high selectivity dry etching etches thegate insulating layer154 and theinterlayer dielectric156, but it may minimally etch thesemiconductor layer153, which may minimize damage to the surface of thesemiconductor layer153. However, since high selectivity dry etching may affect thesemiconductor layer153, thegate insulating layer154 may be etched to the depth where thesemiconductor layer153 is not exposed, as shown in region A, thereby preventing the semiconductor layer from being damaged or over-etched.
• In this case, for example, an ion beam etching process such as the high etch rate dry etching process, an ion etching process such as an RF sputter etching process, or a reactive etching process such as a reactive ion etching process and an induced coupled plasma etching process may be used for the high selectivity dry etching process. Additionally, CF₄/O₂or SF₆/O₂gas may be used for high etch rate dry etching, and C₄F₈, CHF₃, or C₂HF₅gas, which has a high CF ratio, may be used for high selectivity dry etching.
• Next,FIG. 4E is a cross-sectional view showing the step of wet etching the region etched to the second depth to form a third contact hole. AsFIG. 4E shows, the first and second contact holes158 and160 formed by high etch rate dry etching and high selectivity dry etching, respectively, may be wet etched to form athird contact hole162, which completes the contact hole. The wet etching may use a wet etching solution such as, for example, a dilute hydrofluoric acid (DHF) or a buffered hydroFluoric acid (BHF), which may not etch thesemiconductor layer153. The surface of thesemiconductor layer153 and sides of the contact holes are etched using the etching solution to remove impurities or polymer residues thereon, so that there are no impurities on thesemiconductor layer153.
• In this case, as shown in region A ofFIG. 4E, thephotoresist pattern157 may not be removed, the first and second contact holes158 and160 formed by high etch rate dry etching and high selectivity dry etching may be wet etched to expose the surface of the semiconductor layer153 (or each width of the first and second contact holes increases if the surface is already exposed), and alow taper angle163 of thethird contact hole162 may be formed by isotropic wet etching. Alternatively, as shown in region B ofFIG. 4E, thephotoresist pattern157 may be removed and a small taper angle of thethird contact hole162 may be formed by isotropic wet etching. When wet etching after removing the photoresist pattern, the surface of theinterlayer dielectric156 is etched, which may reduce the thickness of theinterlayer dielectric156. This does not pose a problem, however, when theinterlayer dielectric156 is formed considering this consequence.
• In this case, thetaper angle163 of the third contact hole formed by wet etching may be in a range of about 5° to about 50°, preferably in a range of about 5° to about 35°. Additionally, the wet etching may be carried out such that theinterlayer dielectric106 and thegate insulating layer104 may be wet etched with an etching solution having high selectivity against etching thesemiconductor layer153, so that thesemiconductor layer153 may not be damaged by the wet etching solution, even when the surface of the semiconductor layer is exposed or already exposed, and polymer residues thereon may also be removed.
• As a result, a triple profile contact hole including the first, second, and third contact holes158,160 and162 is completed, where an upper portion of the triple profile contact hole has a wet etch profile, its middle portion has a high selectivity dry etch profile having a high taper angle, and its lower portion has a high etch rate dry etch profile having a low taper angle.
• Next,FIG. 4F is a cross-sectional view showing a process of forming a TFT having the above-mentioned triple profile contact hole. AsFIG. 4F shows, a material for forming source and drain electrodes may be deposited on the entire surface of the substrate including the tripleprofile contact hole165, and then patterned to form source and drainelectrodes164, thereby completing the TFT. Consequently, the tripleprofile contact hole165 between the source and drainelectrodes164 and thesemiconductor layer153 has an upper portion with a wet etch profile, a middle portion with a high selectivity dry etch profile with a high taper angle, and a lower portion with a high etch rate dry etch profile with a low taper angle. Therefore, contact resistance due to polymer residues may be minimized since the residues may be removed, and the surface of thesemiconductor layer153 may not be damaged during etching. Further, the contact hole's triple profile facilitates filling the contact hole with the material for forming the source and drain electrodes, and natural oxide layers that may occur during the process may be removed by the wet etching, which reduces the contact resistance due to the natural oxide layers.
• Next,FIG. 4G is a cross-sectional photograph showing a source/drain electrode formed using the triple profile contact hole. Referring toFIG. 4G, which is an enlarged photograph of region A ofFIG. 4F, afirst buffer layer172 and asecond buffer layer173 are formed of an oxide or nitride layer on aglass substrate171, and asemiconductor layer174 is formed on thesecond buffer layer173.
• Next, agate insulating layer175 is formed on thesemiconductor layer174, a gate electrode, which is not shown in the photograph, and aninterlayer dielectric176 are sequentially formed.
• Theinterlayer dielectric176 and thegate insulating layer175 were etched by high etch rate dry etching, high selectivity dry etching, and wet etching, as described in the second embodiment of the present invention, to thereby form a tripleprofile contact hole177 and a source/drain electrode178. Here, the dottedline179 denotes the triple profile shape.
• Next, apassivation layer180 is formed on the entire surface of the substrate, and a subsequent process may be carried out to form an organic light emitting device, which may be used to form a display device.
• In this case, since the source and drain electrodes are formed in the triple profile contact hole including afirst contact hole177ahaving a high etch rate dry etch profile, asecond contact hole177bhaving a high selectivity dry etch profile, and athird contact hole177chaving a wet etch profile, the photograph shows that the source and drain electrodes may be gently formed by the triple profile contact hole having gentle step coverage. Additionally, a first depth181aof thefirst contact hole177a, a second depth181bof thesecond contact hole177b, and a third depth181cof thethird contact hole177cmay be adjusted to readily adjust the step coverage of the triple profile contact hole. The third depth181cmay be obtained by subtracting the first and second depths from the depth of the contact hole.
<Third Embodiment>
• FIG. 5A,FIG. 5B,FIG. 5C,FIG. 5D andFIG. 5E are cross-sectional views showing a method of forming a via hole and a device having the via hole in accordance with10 embodiments of the present invention.
• First,FIG. 5A is a cross-sectional view showing the step of forming a buffer layer, a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer dielectric, and source and drain electrodes on a substrate. AsFIG. 5A shows, abuffer layer202 may be formed on an insulatingsubstrate201, which may be made of a material such as, for example, plastic or glass.
• Next, an amorphous silicon layer may be formed on thebuffer layer202, crystallized to be a polycrystalline silicon layer or a single crystalline silicon layer, and then patterned to form asemiconductor layer203. In this case, a CVD method or a PVD method may be used to form the amorphous silicon layer.
• Next, agate insulating layer204 may be formed on the entire surface of the substrate having thesemiconductor layer203, and a material for forming a gate electrode may be formed on thegate insulating layer204 and then patterned to form agate electrode205. After forming thegate electrode205, impurity ions may be implanted in thesemiconductor layer203, using thegate electrode205 as a mask, thereby defining source, drain and channel regions in thesemiconductor layer203.
• Aninterlayer dielectric206 may then be formed on the entire surface of the substrate. In this case, thebuffer layer202, thegate insulating layer204, and theinterlayer dielectric206 may be formed of, for example, an oxide layer such as a silicon oxide layer or a nitride layer such as a silicon nitride layer.
• Next, a double profile contact hole may be formed in theinterlayer dielectric206 and thegate insulating layer204 using the method described in the first embodiment, or the contact hole may be formed using a typical process. Source anddrain electrodes207 may then be formed, which completes the TFT.
• Next,FIG. 5B is a cross-sectional view showing the step of forming a passivation layer and a planarization layer on the TFT. AsFIG. 5B shows, apassivation layer208 and aplanarization layer209 may be sequentially formed on the substrate including the TFT.
• Photoresist may be coated on theplanarization layer209, and aphotoresist pattern210 for forming the via hole may be formed by exposure and development processes.
• Next,FIG. 5C is a cross-sectional view showing the step of dry etching portions of thepassivation layer208 and theplanarization layer209 using thephotoresist pattern210 as a mask to form the via hole with a predetermined depth. AsFIG. 5C shows, portions of thepassivation layer208 and theplanarization layer209 are dry etched at a high etch rate using thephotoresist pattern210 as a mask to thereby form a viahole211. In this case, the viahole211 may be formed by penetrating theplanarization layer209 and etching a portion of thepassivation layer208, as shown inFIG. 5C. Alternatively, the viahole211 may be formed by only penetrating theplanarization layer209 or by etching a portion of theplanarization layer209, as similarly described with regard toFIG. 3C of the first embodiment. Additionally, the dry etching may be carried out by a dry etching process having a low selectivity and a high etch rate.
• The viahole211 may have a taper angle that is nearly perpendicular to adjacent layers. Specifically, the taper angle may be in a range of about 60° to about 90°, preferably in a range of about 75° to about 90°. In this case, the ion etching process or the reactive etching process, as carried out in the first embodiment, may be used for the dry etching.
• Next,FIG. 5D is a cross-sectional view showing the step of wet etching the via hole having a predetermined depth so as to expose either the source or drain electrode to thereby complete the via hole. AsFIG. 5D shows, the viahole211 etched to a predetermined depth by the dry etching may be wet etched to expose the surface of either the source ordrain electrode207. In this case, the taper angle of the viahole214 formed by wet etching may be less than that formed by dry etching. Specifically, the taper angle may be in a range of about 5° to about 60°, preferably in a range of about 5° to about 45°. In this case, as described in the first embodiment, the wet etching process may be carried out after removing thephotoresist pattern210.
• Additionally, similar to the first embodiment, theplanarization layer209 and thepassivation layer208 may be wet etched using an etching solution having high selectivity against etching the source or drain electrode below, so that the surface of the source or drain electrode is not etched. Furthermore, the wet etching process may remove impurities, such as a polymer, which prevents an increase of contact resistance due to the impurities.
• Consequently, a double profile viahole214, which may be formed by sequential dry and wet etching, penetrates thepassivation layer208 and theplanarization layer209 to expose either the source ordrain electrode207. The double profile viahole214 has an upper portion with awet etch profile212 and a lower portion with adry etch profile213.
• Next,FIG. 5E is a cross-sectional view showing a process of forming a display device having the above-mentioned double profile via hole. AsFIG. 5E shows, a device such as a TFT is already formed on the substrate. The double profile viahole214 may expose either the source or drain electrode, and a transparent electrode, namely, apixel electrode215, may be formed on the substrate. Subsequent steps of forming an emission layer and a negative electrode are not shown, however, the emission layer and the negative electrode are formed to thereby form a display device such as an organic EL device.
• Depositing the transparent electrode on theplanarization layer209 having the double profile viahole214 may lead to a more uniformly formed transparent electrode, thereby overcoming the problem where the taper angle of the via hole is too large to uniformly form the transparent electrode.
<Fourth Embodiment>
• FIG. 6A,FIG. 6B,FIG. 6C,FIG. 6D andFIG. 6E are cross-sectional views showing a method of forming a via hole and a device having the via hole in accordance with other embodiments of the present invention.
• First,FIG. 6A is a cross-sectional view showing the step of forming a buffer layer, a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer dielectric, source and drain electrodes, a passivation layer, and a planarization layer on a substrate. In this case, the passivation layer may also act as the planarization layer in addition to its own function, so that the planarization layer may be omitted as appropriate. AsFIG. 6A shows, abuffer layer252 may be formed on an insulatingsubstrate251, which may be made of a material such as, for example, plastic or glass.
• Next, an amorphous silicon layer may be formed on thebuffer layer252, crystallized to be a polycrystalline silicon layer or a single crystalline silicon layer, and then patterned to form asemiconductor layer253. In this case, a CVD method or a PVD method may be used to form the amorphous silicon layer.
• Next, agate insulating layer254 may be formed on the entire surface of the substrate having thesemiconductor layer253, and a material for forming a gate electrode may be formed on thegate insulating layer254 and patterned to form agate electrode255. After forming thegate electrode255, impurity ions may be implanted in thesemiconductor layer253, using thegate electrode255 as a mask, thereby defining source, drain, and channel regions in the semiconductor layer. Thebuffer layer252 may be omitted as appropriate.
• Next, aninterlayer dielectric256 may then be formed on the entire surface of the substrate. In this case, thebuffer layer252, thegate insulating layer254, and theinterlayer dielectric256 may be formed of, for example, an oxide layer such as a silicon oxide layer or a nitride layer such as a silicon nitride layer.
• Next, a triple profile contact hole may be formed in theinterlayer dielectric256 and thegate insulating layer254 using the method as described in the second embodiment, or a typical process may be carried out to form the contact hole. Source anddrain electrodes257 may then be formed, which completes the TFT.
• Apassivation layer258 and aplanarization layer259 may then be sequentially deposited on the substrate including the TFT.
• Photoresist may then be coated on theplanarization layer259, and aphotoresist pattern260 for forming the via hole may be formed by exposure and development processes.
• Next,FIG. 6B is a cross-sectional view showing the step of dry etching a portion of the planarization layer at a high etch rate using the photoresist pattern to form a via hole with a first depth. AsFIG. 6B shows, theplanarization layer259 may be dry etched at a high etch rate using thephotoresist pattern260 as a mask to thereby form a first viahole261. In this case, a first depth of the first viahole261 may be formed in the planarization layer259by a depth that the planarization layer is etched, as shown inFIG. 6B. Alternatively, the first viahole261 may penetrate theplanarization layer259 and a portion of thepassivation layer258 may be etched, similar to region A ofFIG. 4C of the second embodiment, or theplanarization layer259 may be penetrated without etching thepassivation layer258. Additionally, the high etch rate dry etching may be carried out by a dry etching process having a low selectivity and a high etch rate.
• Ataper angle262 of the first viahole261 formed by high etch rate dry etching may be in a range of about 30° to about 70°, preferably in a range of about 30° to about 50°. In this case, the ion etching process or the reactive etching process as carried out in the second embodiment may be employed for the dry etch.
• Next,FIG. 6C is a cross-sectional view showing the step of dry etching the first via hole having the first depth with high selectivity to form a second via hole. AsFIG. 6C shows, the first viahole261 etched to the first depth may be further etched by high selectivity dry etching of theplanarization layer259 and thepassivation layer258 with high selectivity against etching the source ordrain electrode257, thereby forming a second viahole263 having a second depth, which may expose a surface of the either the source or drain electrode, as described in the second embodiment.
• In this case, the high selectivity dry etching allows the etch rate for theplanarization layer259 and thepassivation layer258 to be high and that for the source ordrain electrode257 to be low. Consequently, theplanarization layer259 and thepassivation layer258 may be etched by high selectivity dry etching while the source ordrain electrode257 is minimally etched or not etched at all, and ataper angle264 of the second viahole263 may be higher than that of the first viahole261. In other words, thetaper angle264 of the second viahole263 may be in a range of about 60° to about 90°, preferably in a range of about 70° to about 90°.
• Next,FIG. 6D is a cross-sectional view showing the step of wet etching a region etched to the second depth to form a third via hole. AsFIG. 6D shows, the first and second viaholes261 and263, formed by high etch rate dry etching and high selectivity dry etching, may be wet etched to form a third viahole265, thereby completing the via holes.
• In this case, as shown inFIG. 6D, thephotoresist pattern260 may not be removed, and the first and second viaholes261 and263 may be wet etched to expose a surface of either the source or drain electrode257 (or each width of the first and second via holes may be increased when the electrode surface is already exposed) and alow taper angle266 of the third viahole265 may be formed by isotropic wet etching. Alternatively, although not shown inFIG. 6D, thephotoresist pattern260 may be removed and a low taper angle of the third viahole265 may be formed by isotropic wet etching, as similarly described in the second embodiment.
• The wet etching may be carried out using a wet etching solution that may not etch the source ordrain electrode257. The etching solution may be used so as to leave no natural oxide layer, impurity or polymer residue on the surface of the source ordrain electrode257 or on side walls of the via holes, so that the surface of the source or drain electrode has no impurities.
• In this case, thetaper angle266 of the third viahole265 formed by wet etching may be in a range of about 5° to about 50°, preferably in a range of about 5° to about 35°. Additionally, the wet etching may be carried out using a wet etching solution such that theplanarization layer259 and thepassivation layer258 are wet etched with a wet etching solution having high selectivity against etching the source ordrain electrode257, so that an exposed surface of the source ordrain electrode257 may not be damaged by the wet etching solution, and polymer residues thereon may also be removed.
• As a result, a triple profile via hole including the first, second, and third viaholes261,263 and265 is completed, where an upper portion of the triple profile via hole has a wet etch profile, its middle portion has a high selectivity dry etch profile having a high taper angle, and its lower portion has a high etch rate dry etch profile having a low taper angle.
• FIG. 6E is a cross-sectional view showing a process of forming a display device having the above-mentioned triple profile via hole. AsFIG. 6E shows, a device such as a TFT is already formed on the substrate, a triple profile viahole267 may expose either the source ordrain electrode257, and a transparent electrode, namely, apixel electrode268, may be formed on the substrate. In this case, a contact for electrically connecting the source ordrain electrode257 to thepixel electrode268 may be formed in the triple profile viahole267.
• Subsequent steps of forming an emission layer and a negative electrode are not shown, however, the emission layer and the negative electrode may be formed to thereby form a display device such as an organic EL device. Depositing the transparent electrode on theplanarization layer259 having the triple profile viahole267 may lead to a more uniformly formed transparent electrode, thereby overcoming the problem where the taper angle of the via hole is too large to uniformly form the transparent electrode. Further, impurities such as polymer residues may be removed, and an organic EL device may be fabricated in which an exposed surface of the source or drain electrode may not be damaged.
<Fifth Embodiment>
• FIG. 7A,FIG. 7B,FIG. 7C,FIG. 7D andFIG. 7E are cross-sectional views showing a method of forming a via hole and a device having the via hole in accordance with other embodiments of the present invention.
• First,FIG. 7A is a cross-sectional view showing the step of forming a metal interconnection line and an interlayer dielectric on a substrate. AsFIG. 7A shows, ametal interconnection line302 and aninterlayer dielectric303 may be formed on an insulatingsubstrate301, which may be made of a material such as, for example, plastic or glass. In this case, various devices including a TFT may already be formed or may be formed on the substrate. Additionally, themetal interconnection line302 delivers electrical signals for driving a display device such as an organic EL device. Theinterlayer dielectric303 may be formed of, for example, one silicon oxide layer, one silicon nitride layer, or a stacked layer thereof, and it may be formed by a single process, or it may be formed of insulating layers formed by several processes.
• Next,FIG. 7B is a cross-sectional view showing the step of forming a photoresist pattern for forming a via hole on the substrate. AsFIG. 7B shows, a photoresist may be coated on the substrate including theinterlayer dielectric303, and aphotoresist pattern304 may be formed by exposure and development processes.
• Next,FIG. 7C is a cross-sectional view showing the step of dry etching a portion of the interlayer dielectric using the photoresist pattern to form the via hole with a predetermined depth. AsFIG. 7C shows, a portion of theinterlayer dielectric303 may be dry etched using thephotoresist pattern304 as a mask to thereby form a viahole305. In this case, theinterlayer dielectric303 may be dry etched at a high etch rate so as to allow a taper angle of the viahole305 to be nearly perpendicular to adjacent layers. Specifically, the taper angle of the viahole305 may be in a range of about 60° to about 90°, preferably in a range of about 75° to about 90°.
• Next,FIG. 7D is a cross-sectional view showing the step of wet etching the via hole having a predetermined depth to expose the metal interconnection line, thereby completing the via hole. AsFIG. 7D shows, theinterlayer dielectric303 may be wet etched with an etching solution having high selectivity against etching themetal interconnection line302 to thereby complete the viahole308 with a predetermined depth. In this case, the via hole may have a double profile such that an upper portion of the viahole308 has awet etch profile306 and its lower portion has adry etch profile307. Alternatively, thephotoresist pattern304 may be removed prior to the wet etching process.
• In this case, a taper angle of the viahole308 may be less than that of the viahole305 formed by the dry etching. More specifically, the taper angle of the viahole308 may be in a range of about 5° to about 60°, preferably in a range of about 5° to about 45°.
• Additionally, by means of the wet etching, theinterlayer dielectric303 may be etched with high selectivity against etching themetal interconnection line302, as similarly described in the first embodiment, so that the surface of themetal interconnection line302 is not etched when etching theinterlayer dielectric303. Furthermore, an impurity such as a polymer may be removed by the wet etching process, thereby preventing the problem of increased contact resistance due to the impurity.
• Consequently, the via hole formed by sequentially dry etching and wet etching may penetrate theinterlayer dielectric303 and expose themetal interconnection line302, and it may have a double profile such that its upper portion has a wet etch profile and its lower portion has a dry etch profile.
• Next,FIG. 7E is a cross-sectional view showing a process of forming a display device having the above-mentioned via hole. AsFIG. 7E shows, ametal interconnection line302 may be formed on asubstrate301, and aninterlayer dielectric303 may be formed on themetal interconnection line302. Dry etching and wet etching may be sequentially carried out to form a double profile viahole308, which has an upper portion with a wet etch profile and a lower portion with a dry etch profile, and a conductive material may be deposited and patterned thereon, thereby forming an uppermetal interconnection line309. Alternatively, if necessary, an upper metal interconnection line having a uniform thickness may be formed, as shown by the dotted line310 ofFIG. 7E.
<Sixth Embodiment>
• FIG. 8A,FIG. 8B,FIG. 8C,FIG. 8D andFIG. 8E are cross-sectional views showing a method of forming a via hole and a device having the via hole in accordance with other embodiments of the present invention.
• First,FIG. 8A is a cross-sectional view showing a process of forming a metal interconnection line and an interlayer dielectric on a substrate and forming a photoresist pattern for forming a via hole on the interlayer dielectric. AsFIG. 8A shows, ametal interconnection line352 and aninterlayer dielectric353 may be sequentially formed on an insulatingsubstrate351 such as plastic or glass, and aphotoresist pattern354 for forming the via hole may be formed on the interlayer dielectric353.
• In this case, a photoresist may be first coated on the substrate, and subsequent exposure and development processes may be carried out to form thephotoresist pattern354.
• Next,FIG. 8B is a cross-sectional view showing the step of dry etching a portion of the interlayer dielectric at a high etch rate using the photoresist pattern as a mask to form a first via hole with a first depth. AsFIG. 8B shows, a portion of theinterlayer dielectric353 may be dry etched at a high etch rate using thephotoresist pattern354 as a mask to thereby form a first viahole355 with a first depth. In this case, the dry etching may be carried out using a dry etching process having a low selectivity and a high etch rate.
• Ataper angle356 of the first viahole355 may be in a range of about 30° to about 70°, preferably in a range of about 30° to about 50°. In this case, the ion etching process or the reactive etching process as carried out in the second embodiment may be used for the high etch rate dry etching.
• Next,FIG. 8C is a cross-sectional view showing the step of dry etching the first via hole having the first depth with high selectivity to form a second via hole. AsFIG. 8C shows, the first viahole355 etched to the first depth may be further etched to a second depth by high selectivity dry etching to form a second viahole357 that may or may not expose a surface of themetal interconnection line352, similar to the method described in the second embodiment. In this case, the high selectivity dry etching allows an etch rate for theinterlayer dielectric353 to be high and that for themetal interconnection line352 to be low. Consequently, theinterlayer dielectric353 is etched by the high selectivity dry etching while themetal interconnection line352 is minimally etched, or not etched at all, and ataper angle358 of the second viahole357 may be higher than that of the first viahole355. Specifically, thetaper angle358 of the second viahole357 may be in a range of about 60° to about 90°, preferably in a range of about 70° to about 90°.
• Next,FIG. 8D is a cross-sectional view showing the step of wet etching a region etched to the second depth to form a third via hole. AsFIG. 8D shows, the first and second viaholes355 and357 formed by high etch rate dry etching and high selectivity dry etching, respectively, may be wet etched to form a third viahole359, thereby completing the via hole.
• In this case, thephotoresist pattern354 may not be removed, and the first and second viaholes355 and357 may be wet etched to expose a surface of the metal interconnection line352 (or widen the first and second viaholes355 and357 if the surface is already exposed), and alow taper angle360 of the third viahole359 may be formed by isotropic wet etching. Alternatively, although not shown inFIG. 8D, thephotoresist pattern354 may be removed and the low taper angle of the third via hole may be formed by isotropic wet etching, as described in the second embodiment.
• The wet etching may be carried out with a wet etching solution that does not etch themetal interconnection line352. The etching solution may be used to leave no natural oxide layer, impurity, or polymer residues on the surface of themetal interconnection line352 or sidewalls of the via holes, so that the surface of meal interconnection line may have no impurities.
• In this case, thetaper angle360 of the third viahole359 formed by wet etching may be in a range of about 5° to about 50°, or in a range of about 5° to about 35°. Additionally, the wet etching may be carried out such that theinterlayer dielectric353 is wet etched with a wet etching solution having high selectivity against etching themetal interconnection line352, so that a surface of themetal interconnection line352 which may be exposed, or is already exposed, may not be damaged by the wet etching solution.
• As a result, a triple profile via hole including the first, second, and third viaholes355,357 and359 is completed, where an upper portion of the triple profile via hole has a wet etch profile, its middle portion has a high selectivity dry etch profile having a high taper angle, and its lower portion has a high etch rate dry etch profile having a low taper angle.
• FIG. 8E is a cross-sectional view showing a process of forming a display device having the above-mentioned triple profile via hole. AsFIG. 8E shows, themetal interconnection line352 and theinterlayer dielectric353 may be sequentially formed on thesubstrate351, the triple profile viahole361 may expose a portion of themetal interconnection line352, and an uppermetal interconnection line362 may be formed on the entire surface of the substrate. Consequently, a contact for electrically connecting themetal interconnection line352 to the uppermetal interconnection line362 is formed in the triple profile viahole361.
• In this case, high etch rate dry etching, high selectivity dry etching, and wet etching may be sequentially carried out to form the triple profile viahole361 having an upper portion with a wet etch profile and its lower portion with a dry etch profile, which may lead to formation of the uppermetal interconnection line362, as shown inFIG. 8E. Additionally, an uppermetal interconnection line362 having a uniform thickness may be formed if necessary, as shown by the dottedline363 ofFIG. 8E.
<Seventh Embodiment>
• FIG. 9A,FIG. 9B,FIG. 9C,FIG. 9D andFIG. 9E are cross-sectional views showing a method of forming a via contact hole and a device having the via contact hole in accordance with other embodiments of the present invention.
• First,FIG. 9A is a cross-sectional view showing the step of forming a buffer layer, a semiconductor layer, a gate insulating layer, and a gate electrode on a substrate. AsFIG. 9A shows, abuffer layer402 may be formed on an insulatingsubstrate401, which may be made of a material such as, for example, plastic or glass. Thebuffer layer402 may prevent moisture or impurities from the insulating substrate from diffusing, and it may facilitate crystallization of the semiconductor layer by adjusting a heat transfer speed during crystallization.
• Next, an amorphous silicon layer may be formed on thebuffer layer402, crystallized to be a polycrystalline silicon layer or a single crystalline silicon layer, and then patterned to form asemiconductor layer403. In this case, a CVD method or a PVD method may be used to form the amorphous silicon layer. Additionally, the amorphous silicon layer may be dehydrated to reduce the presence of hydrogen during or after the layer's formation.
• Next, agate insulating layer404 may be formed on the entire surface of the substrate including thesemiconductor layer403, and a material for forming a gate electrode may be formed on thegate insulating layer404 and patterned to form agate electrode405. After forming thegate electrode405, impurity ions may be implanted in thesemiconductor layer403 using the gate electrode as a mask, thereby defining source, drain, and channel regions in thesemiconductor layer403.
• Next,FIG. 9B is a cross-sectional view showing the step of forming a planarization layer and a photoresist pattern on the substrate. As shown in region A ofFIG. 9B, aplanarization layer406 may be formed on the substrate, and aphotoresist pattern407 for forming a via contact hole may be formed on theplanarization layer406. Alternatively, as shown in region B ofFIG. 9B, aninterlayer dielectric408 may be formed on the substrate before forming theplanarization layer406 and thephotoresist pattern407. In other words, theinterlayer dielectric408 may be included as necessary.
• Theinterlayer dielectric408 and theplanarization layer406 may be formed of an insulating layer such as, for example, a silicon oxide or silicon nitride layer.
• Thephotoresist pattern407 may be formed by coating a photoresist on the substrate by a spin method or a spray method. Subsequent exposure and development processes are then carried out.
• Next,FIG. 9C is a cross-sectional view showing the step of dry etching portions of the planarization layer to form a via contact hole with a predetermined depth. AsFIG. 9C shows, thephotoresist pattern407 may dry etched along with theplanarization layer406 in region A and region B to thereby form a viacontact hole409 with a predetermined depth.
• Alternatively, theplanarization layer406 may be penetrated without etching thegate insulating layer404, or theplanarization layer406 may be penetrated and a portion of thegate insulating layer404 may be etched in region A. Similarly, theplanarization layer406, theinterlayer dielectric408, or thegate insulating layer404 may be etched by a desired depth using the same method in region B, thereby forming a viacontact hole409.
• In other words, the viacontact hole409 may be formed by dry etching allowing a desired etching depth to be etched. Additionally, the dry etching may etch theplanarization layer406 or thegate insulating layer404, or may etch theplanarization layer406, theinterlayer dielectric408 or thegate insulating layer404 at a high etch rate, to adjust a taper angle and depth of the viacontact hole409. In this case, ataper angle410 of the viacontact hole409 may be in a range of about 60° to about 90°, preferably in a range of about 75° to about 90°.
• In this case, an ion etching process or a reactive etching process may be used for the dry etching.
• Next,FIG. 9D is a cross-sectional view illustrating the step of wet etching the via contact hole with a predetermined depth to expose a surface of the semiconductor layer, thereby completing the via contact hole. AsFIG. 9D shows, the viacontact hole409 with a predetermined depth etched by dry etching may be wet etched to complete the via contact hole and expose the surface of thesemiconductor layer403.
• In this case, as shown in region A ofFIG. 9D, thephotoresist pattern407 may be removed, the viacontact hole409 formed by dry etching may be wet etched to expose the surface of thesemiconductor layer403, and alow taper angle411 of the viacontact hole414 may be formed by isotropic wet etching, or as shown in region B ofFIG. 9D, thephotoresist pattern407 may not be removed and a low taper angle of the viacontact hole414 may be formed by isotropic wet etching.
• In this case, thetaper angle411 of the viacontact hole414 formed by means of wet etching may be in a range of about 5° to about 60°, preferably in a range of about 5° to about 45°. Additionally, the wet etching may be carried out such that the planarization layer and the gate insulating layer or the planarization layer, the interlayer dielectric, and the gate insulating layer are wet etched with an etching solution having high selectivity against etching thesemiconductor layer403, so that thesemiconductor layer403 may not be damaged by the wet etching solution even when the surface of the semiconductor layer is exposed, and polymer residues thereon may also be removed.
• As a result, the viacontact hole414 has a double profile where its upper portion has awet etch profile412 and its lower portion has adry etch profile413.
• Next,FIG. 9E is a cross-sectional view showing a process of forming a display device or a TFT having the above-mentioned double profile via contact hole. As shown in region A ofFIG. 9E, a material for forming a positive electrode may be formed on the entire surface of the substrate including the double profile viacontact414 and then patterned to form apositive electrode415, which which may contact with thesemiconductor layer403. Although not shown inFIG. 9E, an emission layer and a negative electrode may be subsequently formed to thereby form a display device such as an organic EL device.
• Additionally, as shown in region B ofFIG. 9E, a material for forming a metal interconnection line may be formed on the entire surface of the substrate and patterned to form ametal interconnection line416, so that the TFT may have the double profile viacontact hole414 that directly connects thesemiconductor layer403 to themetal interconnection line416 without requiring a source or drain electrode.
• Consequently, the double profile viacontact hole414 has an upper portion with a wet etch profile and a lower portion with a dry etch profile, so that polymer residue may be removed so that it does not cause contact resistance, and the surface of thesemiconductor layer403 may not be damaged. Further, the double profile of the via contact hole facilitates filling the viacontact hole414 with the material for forming the positive electrode or with the material for forming the metal interconnection line.
<Eighth Embodiment>
• FIG. 10A,FIG. 10B,FIG. 10C,FIG. 10D andFIG. 10E are cross-sectional views showing a method of forming a via contact hole and a device having the via contact hole in accordance with other embodiments of the present invention.
• First,FIG. 10A is a cross-sectional view showing the step of forming a buffer layer, a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer dielectric, and20 a photoresist pattern on a substrate. AsFIG. 10A shows, abuffer layer452 may be formed on an insulatingsubstrate451, such as plastic or glass.
• Next, an amorphous silicon layer may be formed on thebuffer layer452, crystallized to be a polycrystalline silicon layer or a single crystalline silicon layer, and then patterned to form asemiconductor layer453. In this case, a CVD method or a PVD method may be used to form the amorphous silicon layer. Additionally, the amorphous silicon layer may be dehydrated to reduce the presence of hydrogen during or after formation of the amorphous silicon layer.
• Next, agate insulating layer454 may be formed on the entire surface of the substrate including thesemiconductor layer453, and a material for forming a gate electrode may then be formed on thegate insulating layer454 and patterned to form agate electrode455. After forming thegate electrode455, impurity ions may be implanted in thesemiconductor layer453 using thegate electrode455 as a mask, thereby defining source, drain, and channel regions in thesemiconductor layer453.
• Next, as shown in region A ofFIG. 10A, aplanarization layer456 may be formed on the substrate, and aphotoresist pattern457 for forming a via contact hole may be formed on theplanarization layer456. Alternatively, as shown in region B ofFIG. 10A, aninterlayer dielectric458 may be formed on the substrate before forming theplanarization layer456 and thephotoresist pattern457. In other words, theinterlayer dielectric458 may be formed as necessary.
• In this case, theinterlayer dielectric458 and theplanarization layer456 may be formed of an insulating layer such as, for example, a silicon oxide or silicon nitride layer.
• Thephotoresist pattern457 may be formed by coating a photoresist on the substrate using a spin method or a spray method. Subsequent exposure and development processes may then be carried out.
• Next,FIG. 10B is a cross-sectional view showing the step of dry etching a portion of the planarization layer at a high etch rate to form a first via contact hole having a first depth. AsFIG. 10B shows, using thephotoresist pattern457 as a mask, theplanarization layer456 in region A, or theplanarization layer456 and theinterlayer dielectric458 in region B, may be dry etched to thereby form a first viacontact hole459 with a first depth.
• Alternatively, theplanarization layer456 may be penetrated without etching thegate insulating layer454, or the planarization layer may be penetrated and a portion of thegate insulating layer454 may be etched in region A. Similarly, theplanarization layer456, theinterlayer dielectric458, or thegate insulating layer454 may be etched by a desired depth using the same method as that in region A, thereby forming the first viacontact hole459 in region B.
• In other words, the first viacontact hole459 may be formed by dry etching allowing a first depth to be etched at a high etch rate. Additionally, the high etch rate dry etching may etch theplanarization layer456 or thegate insulating layer454, or may etch theplanarization layer456, theinterlayer dielectric458 or thegate insulating layer454 at a high etch rate, to adjust a taper angle and depth of the first viacontact hole459. In this case, ataper angle460 of the first viacontact hole459 may be in a range of about 30° to about 70°, preferably in a range of about 30° to about 50°.
• In this case, an ion etching process or a reactive etching process may be used for the high etch rate dry etching.
• Next,FIG. 10C is a cross-sectional view showing the step of dry etching the first via contact hole having a first depth using high selectivity etching to form a second via contact hole. AsFIG. 10C shows, theplanarization layer456 and thegate insulating layer454 in region A, or theplanarization layer456, theinterlayer dielectric458, and thegate insulating layer454 in region B, may be dry etched with high selectivity to form a second viacontact hole461 to a second depth, which may or may not expose thesemiconductor layer453.
• In this case, the high selectivity dry etching allows an etch rate for theplanarization layer456, theinterlayer dielectric458 and thegate insulating layer454 to be high and that for thesemiconductor layer453 to be low. As a result, theplanarization layer456, theinterlayer dielectric458, and thegate insulating layer454 may be etched by the high selectivity dry etching while thesemiconductor layer453 is minimally etched, and ataper angle462 of the second viacontact hole461 having the second depth formed by high selectivity dry etching may be higher than that of the first viacontact hole459 having the first depth.
• In other words, thetaper angle462 of the second viacontact hole461 having the second depth may be nearly perpendicular to adjacent layers. Specifically, it may be in a range of about 60° to about 90°, preferably in a range of about 70° to about 90°.
• The second viacontact hole461 having the second depth may be formed to a depth where it does not expose thesemiconductor layer453 as shown in region A ofFIG. 10C, or it may be formed to a depth exposing thesemiconductor layer453, as shown in region B ofFIG. 10C. This results from the fact that only thegate insulating layer454 and theinterlayer dielectric458 are etched while the surface of thesemiconductor layer453 is minimally etched by the high selectivity dry etching, so that the surface of thesemiconductor layer453 may be minimally damaged even when thesemiconductor layer453 is exposed as shown in region B. However, since high selectivity dry etching may affect thesemiconductor layer453, the second viacontact hole461 may be etched to a depth that does not expose thesemiconductor layer453, as shown in region A, to prevent it from being damaged or over-etched.
• FIG. 10D is a cross-sectional view showing the step of wet etching a region etched to the second depth to form a third via contact hole. AsFIG. 10D shows, the second viacontact hole461 dry etched to the second depth may be wet etched to expose the surface of thesemiconductor layer453, thereby forming a third viacontact hole463.
• In this case, as shown in region A ofFIG. 10D, thephotoresist pattern457 may be removed and the first and second via contact holes459 and461 formed by high etch rate dry etching and high selectivity dry etching, respectively, may be wet etched to form alow taper angle464 of the third viacontact hole463 by isotropic wet etching, thereby exposing the surface of the semiconductor layer453 (or increasing the widths of the first and second via contact holes when the surface is already exposed). Alternatively, as shown in region B ofFIG. 10D, thephotoresist pattern457 may not be removed and a low taper angle of the third via contact hole may be formed by isotropic wet etching.
• In this case, thetaper angle464 of the third viacontact hole463 formed by wet etching may be in a range of about 5° to about 50°, however, it may be in a range of about 5° to about 35°. Additionally, the wet etching may be carried out with a wet etching solution such that theplanarization layer456 and thegate insulating layer454, or theplanarization layer456, theinterlayer dielectric458, and thegate insulating layer454 are wet etched with high selectivity against etching thesemiconductor layer453, so that thesemiconductor layer453 may not be damaged by the wet etching solution even when the surface of the semiconductor layer is already exposed, and polymer residue thereon may also be removed.
• As a result, a triple profile via contact hole including the first, second, and third via contact holes459,461 and463 is completed, where an upper portion of the triple profile via contact hole has a wet etch profile, a middle portion thereof has a high selectivity dry etch profile having a high taper angle, and a lower portion thereof has a high etch rate dry etch profile having a low taper angle.
• Next,FIG. 10E is a cross-sectional view showing a process of forming a display device or a TFT having the above-mentioned triple profile via contact hole. As shown in region A ofFIG. 10E, a material for forming a pixel electrode may be formed on the substrate including the triple profile viacontact hole467, and it may be patterned to form apixel electrode465, which may contact thesemiconductor layer453. Although not shown inFIG. 10E, an emission layer and a common electrode may be formed on thepixel electrode465 to form a display device such as an organic EL device. Additionally, as shown in region B ofFIG. 10E, a material for forming a metal interconnection line may be formed on the entire surface of the substrate and patterned to form ametal interconnection line466, so that the TFT may be fabricated where the triple profile viacontact hole467 directly connects thesemiconductor layer453 with themetal interconnection line466 without requiring a source or drain electrode.
• As a result, the triple profile viacontact hole467 has an upper portion with a wet etch profile, a middle portion with a high selectivity dry etch profile with a high taper angle, and a lower portion with a high etch rate dry etch profile with a low taper angle, so that polymer residue may be removed so that it does not cause contact resistance, and the surface of thesemiconductor layer453 may not be damaged during etching. Further, the via contact hole's triple profile facilitates filling the via contact hole with the material for forming the pixel electrode or with the material for forming the metal interconnection line.
<Ninth Embodiment>
• FIG. 11 is a cross-sectional view showing a method of simultaneously forming a contact hole and a via hole, and a semiconductor device having the same in accordance with other embodiments of the present invention.
• AsFIG. 11 show, region A denotes a TFT in which source and drain electrodes are formed using a double profile contact hole of the first embodiment, and region B denotes a metal interconnection line region in which a metal interconnection line is formed using the double profile via hole of the fifth embodiment. Regions A and B may be simultaneously formed.
• Referring toFIG. 11, abuffer layer502 may be formed on an insulatingsubstrate501, such as plastic or glass, and asemiconductor layer503 may be formed in a predetermined region of the substrate, such as region A, using the method as described in the first embodiment. Agate insulating layer504 may be formed on the substrate, and a material for forming a gate electrode may be formed on the substrate and then patterned to form agate electrode505.
• In this case, a firstmetal interconnection line506 may be formed in region B, which is spaced from region A by a predetermined interval. The firstmetal interconnection line506 may be formed using the pattern when patterning the gate electrode material to form thegate electrode505. In other words, thegate electrode505 and the firstmetal interconnection line506 may be simultaneously formed of the same material. Additionally, layers, which are stacked when thebuffer layer502 and thegate insulating layer504 are formed in region A, may not be removed from the substrate in region B, even thoughFIG. 11 shows them as removed.
• Aninterlayer dielectric507 may then be formed in region A, and aninterlayer dielectric508 may also be formed in region B. Interlayer dielectrics507 and508 may be formed simultaneously.
• The same methods as those described in the first and fifth embodiments may be employed, so that theinterlayer dielectric507 and thegate insulating layer504 of region A are dry etched at a high etch rate and wet etched with a selectivity, thereby forming a doubleprofile contact hole509, and theinterlayer dielectric508 of region B is dry etched at a high etch rate and wet etched with a selectivity, thereby forming a double profile viahole510. In this case, the dry etching for the regions A and B and the wet etching for the regions A and B may be carried out simultaneously, thereby simultaneously forming the doubleprofile contact hole509 and the double profile viahole510. The taper angle of the dry etch profile may be in a range of about 60° to about 90°, preferably in a range of about 75° to about 90°, and the taper angle of the wet etch profile may be in a range of about 5° to about 60°, preferably in a range of about 5° to about 45°.
• Next, a material for forming source and drain electrodes may be formed in region A and patterned to form source and drainelectrodes511, and a material for forming a second metal interconnection line may be formed in the region B and patterned to form a secondmetal interconnection line512. In this case, the material for forming the source and drain electrodes may be coated on the entire surface of the substrate, and source and drain electrode and second metal interconnection line patterns may be used to simultaneously form the source and drainelectrodes511 and the secondmetal interconnection line512. In other words, the source and drainelectrodes511 and the secondmetal interconnection line512 may be formed of the same material carrying out one process.
• Next, although not shown inFIG. 11, a passivation layer and a planarization layer may be formed on the substrate, and a positive electrode, an emission layer, and a negative electrode may be formed thereon to thereby form a display device such as an organic EL device.
<Tenth Embodiment>
• FIG. 12 is a cross-sectional view showing a method of simultaneously forming a contact hole and a via hole, and a device having the contact hole and the via hole in accordance with other embodiments of the present invention. AsFIG. 12 shows, region A denotes a TFT in which source and drain electrodes are formed using a triple profile contact hole of the second embodiment, and region B denotes a metal interconnection line region in which a metal interconnection line is formed using a triple profile via hole of the sixth embodiment. Regions A and B may be simultaneously formed.
• Referring toFIG. 12, abuffer layer552 may be formed on an insulatingsubstrate551, such as plastic or glass, and asemiconductor layer553 may be formed in a predetermined region of the substrate, such as region A, using the method as described in the first embodiment. Agate insulating layer554 may be formed on the substrate, and a material for forming a gate electrode may be formed on the substrate and patterned to form agate electrode555.
• In this case, a firstmetal interconnection line556 may be formed in region B, which is spaced from region A by a predetermined interval. The firstmetal interconnection line556 may be formed using the pattern when patterning the gate electrode material to form thegate electrode555. In other words, thegate electrode555 and the firstmetal interconnection line556 may be simultaneously formed of the same material. Additionally, layers, which are stacked when thebuffer layer552 and thegate insulating layer554 are formed in region A, may not be removed from the substrate in region B, even thoughFIG. 12 shows them as removed.
• Aninterlayer dielectric557 may then be formed in region A, and aninterlayer dielectric558 may also be formed in region B. Theinterlayer dielectrics557 and558 may be formed simultaneously.
• The same methods as described in the second and sixth embodiments may be employed, so that theinterlayer dielectric557 and thegate insulating layer554 of region A are etched by means of high etch rate dry etching, high selectivity dry etching, and wet etching with a selectivity, thereby forming a tripleprofile contact hole559, and theinterlayer dielectric558 of region B is etched by means of high etch rate dry etching, high selectivity dry etching, and wet etching with a selectivity, thereby forming a triple profile viahole560. In this case, the high etch rate dry etching and the high selectivity dry etching for regions A and B, and the wet etching for regions A and B, may be carried out simultaneously, so that the tripleprofile contact hole559 and the triple profile viahole560 may be simultaneously formed. The taper angle of the high etch rate dry etch profile may be in a range of about 30° to about 70°, preferably in a range of about 30° to about 50°, the taper angle of the high selectivity dry etch profile may be in a range of about 60° to about 90°, preferably in a range of about 70° to about 90°, and the taper angle of the wet etch profile may be in a range of about 5° to about 50°, preferably in a range of about 5° to about 35°.
• Next, a material for forming source and drain electrodes may be formed in region A and then patterned to form source and drainelectrodes561, and a material for forming a second metal interconnection line may be formed in region B and then patterned to form a secondmetal interconnection line562. In this case, the material for forming the source and drain electrodes may be coated on the entire surface of the substrate, and source and drain electrode and second metal interconnection line patterns may be used to simultaneously form the source and drainelectrodes561 and the secondmetal interconnection line562. In other words, the source and drainelectrodes561 and the secondmetal interconnection line562 may be formed of the same materials carrying out one process.
• Next, although not shown inFIG. 12, a passivation layer, a planarization layer, and so forth may be formed on the substrate, and a pixel electrode, an emission layer, and a common electrode may also be formed thereon to thereby form a display device such as an organic EL device.
• While the embodiments discussed above include double and triple profile contact, via, and via contact holes, it is also possible to form a contact hole, a via hole, or a via contact hole having a quadruple or multiple profile by repeatedly performing wet etching or dry etching. However, a wet etching process may be employed for the final etching process to remove etching residues or impurities, which may form the contact hole, the via hole, or the via contact hole with excellent characteristics.
• Accordingly, the semiconductor device and method of fabricating the same in accordance with the present invention may prevent contact non-uniformity and polymer residues from occurring in a contact portion of the contact hole, the via hole, or the via contact hole. Additionally, the surface of the semiconductor layer, the source and drain electrodes, and the metal interconnection line, which are exposed by the contact hole, the via hole, or the via contact hole, may not be damaged.
• It will be apparent to those skilled in the art that various modifications and variation can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (37)

1. A semiconductor device, comprising:

a substrate;

a thin film transistor formed on the substrate and including a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric; and

a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer, and having a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of a wet etch profile and a dry etch profile.

2. The semiconductor device ofclaim 1, wherein the wet etch profile in the upper portion of the contact hole has a taper angle in a range of about 5° to about 60°.

3. The semiconductor device ofclaim 1, wherein the wet etch profile in the upper portion of the contact hole has a taper angle in a range of about 5° to about 45°.

4. The semiconductor device ofclaim 1, wherein the dry etch profile has a taper angle in a range of about 60° to about 90°.

5. The semiconductor device ofclaim 1, wherein the dry etch profile has a taper angle in a range of about 75° to about 90°.

6. The semiconductor device ofclaim 1, wherein the dry etch profile includes a high selectivity dry etch profile and a high etch rate dry etch profile.

7. A method of fabricating a semiconductor device, comprising:

forming a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric on a substrate;

performing at least one of a dry etching process and a wet etching process on a portion of the interlayer dielectric and the gate insulating layer to form a contact hole to a predetermined depth; and

wet etching the contact hole to complete the contact hole and expose a portion of the semiconductor layer.

8. The method ofclaim 7, wherein the dry etching process includes any one of an ion etching process and a reactive etching process.

9. The method ofclaim 7, further comprising removing a photoresist pattern before carrying out the wet etching that completes the contact hole.

10. The method ofclaim 7, wherein the dry etching process includes at least one of a high etch rate dry etching process and a high selectivity dry etching process.

11. A semiconductor device, comprising:

a substrate;

a thin film transistor (TFT) formed on the substrate and having a source electrode and a drain electrode;

a passivation layer and a planarization layer formed on the TFT; and

a via hole penetrating the passivation layer and the planarization layer and exposing a portion of either the source electrode and or the drain electrode, and having a multiple profile in which an upper portion of the via hole has a wet etch profile and a lower portion of the via hole has at least one of a wet etch profile and a dry etch profile.

12. A method of fabricating a semiconductor device, comprising:

forming a thin film transistor (TFT) including a source electrode and a drain electrode on a substrate;

forming a passivation layer and a planarization layer on the TFT;

performing at least one of a dry etching process and a wet etching process on a portion of the passivation layer and the planarization layer to form a via hole to a predetermined depth; and

wet etching the via hole to complete the via hole and expose a portion of either the source electrode or the drain electrode.

13. The method ofclaim 12, wherein the dry etching process includes any one of an ion etching process and a reactive etching process.

14. The method ofclaim 12, further comprising removing a photoresist pattern before carrying out the wet etching that completes the contact hole.

15. The method ofclaim 12, wherein the dry etching process includes at least one of a high etch rate dry etching process and a high selectivity dry etching process.

16. A semiconductor device, comprising:

a substrate;

a metal interconnection line formed on the substrate;

an interlayer dielectric formed on the metal interconnection line; and

a via hole penetrating the interlayer dielectric and exposing a portion of the metal interconnection line, and having a multiple profile in which an upper portion of the via hole has a wet etch profile and a lower portion of the via hole has at least one of a wet etch profile and a dry etch profile.

17. The semiconductor device ofclaim 16, further comprising an upper metal interconnection line contacting the metal interconnection line through the via hole.

18. A method of fabricating a semiconductor device, comprising:

forming a metal interconnection line and an interlayer dielectric on a substrate;

performing at least one of a dry etching process and a wet etching process on a portion of the interlayer dielectric to form a via hole to a predetermined depth; and

wet etching the via hole to complete the via hole and expose a portion of the metal interconnection line.

19. A semiconductor device, comprising:

a substrate;

a semiconductor layer, a gate insulating layer, and a gate electrode formed on the substrate;

a planarization layer formed on the substrate; and

a via contact hole penetrating the planarization layer and the gate insulating layer and exposing a portion of the semiconductor layer, and having a multiple profile in which an upper portion of the via contact hole has a wet etch profile and a lower portion of the via contact hole has at least one of a wet etch profile and a dry etch profile.

20. The semiconductor device ofclaim 19, wherein a metal interconnection line or a pixel electrode contacts the exposed portion of the semiconductor layer through the via contact hole.

21. A method of fabricating a semiconductor device, comprising:

forming a semiconductor layer, a gate insulating layer, and a gate electrode on a substrate;

forming a planarization layer on the substrate;

performing at least one of a dry etching process and a wet etching process on a portion of the gate insulating layer and the planarization layer to form a via contact hole to a predetermined depth; and

wet etching the via contact hole to complete the via contact hole and expose a portion of the semiconductor layer.

22. A semiconductor device, comprising:

a substrate;

a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric formed on the substrate;

a thin film transistor (TFT) region including a contact hole, the contact hole penetrating the gate insulating layer and the interlayer dielectric, exposing a portion of the semiconductor layer, and having a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of a wet etch profile and a dry etch profile;

a metal interconnection line and an insulating layer formed on the substrate and spaced apart from the TFT region by a predetermined interval; and

a via hole penetrating the insulating layer and having a multiple profile in which an upper portion of the via hole has a wet etch profile and a lower portion of the via hole has at least one of a wet etch profile and a dry etch profile.

23. The semiconductor device ofclaim 22, wherein an electrode contacts the exposed portion of the semiconductor layer through the contact hole, and an upper metal interconnection contacts the metal interconnection line through the via hole.

24. A method of fabricating a semiconductor device, comprising:

forming a semiconductor layer, a gate insulating layer, and a gate electrode in a thin film transistor (TFT) region of a substrate;

forming a metal interconnection line in a metal interconnection line region spaced apart from the TFT region by a predetermined interval;

forming an interlayer dielectric in the TFT region, and forming an insulating layer in the metal interconnection line region;

performing at least one of a dry etching process and a wet etching process on a portion of the insulating layer in the metal interconnection line region, and on the interlayer dielectric and the gate insulating layer in the TFT region to form a contact hole having a predetermined depth in the TFT region and a via hole having a predetermined depth in the metal interconnection line region; and

wet etching the contact hole and the via hole to complete the contact hole and the via hole and expose a portion of the semiconductor layer in the TFT region and a portion of the metal interconnection line in the metal interconnection line region.

25. A semiconductor device, comprising:

a substrate;

a thin film transistor formed on the substrate and including a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric; and

a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer, the contact hole including an upper portion having a first taper angle and a lower portion having a second taper angle,

wherein the second taper angle is steeper than the first taper angle.

26. The semiconductor device ofclaim 25, wherein the upper portion of the contact hole is formed by wet etching and the first taper angle is in a range of about 5° to about 60°.

27. The semiconductor device ofclaim 25, wherein the upper portion of the contact hole is formed by wet etching and the first taper angle is in a range of about 5° to about 45°.

28. The semiconductor device ofclaim 25, wherein the lower portion of the contact hole is formed by dry etching and the second taper angle is in a range of about 60° to about 90°.

29. The semiconductor device ofclaim 25, wherein the lower portion of the contact hole is formed by dry etching and the second taper angle is in a range of about 75° to about 90°.

30. The semiconductor device ofclaim 25, wherein the contact hole further includes a lowest portion having a third taper angle, and the second taper angle is steeper than the third taper angle.

31. A semiconductor device, comprising:

a substrate;

a thin film transistor (TFT) formed on the substrate and having a source electrode and a drain electrode;

a passivation layer and a planarization layer formed on the TFT; and

a via hole penetrating the passivation layer and the planarization layer and exposing a portion of either the source electrode and or the drain electrode, the via hole including an upper portion having a first taper angle and a lower portion having a second taper angle,

wherein the second taper angle is steeper than the first taper angle.

32. A semiconductor device, comprising:

a substrate;

a metal interconnection line formed on the substrate;

an interlayer dielectric formed on the metal interconnection line; and

a via hole penetrating the interlayer dielectric and exposing a portion of the metal interconnection line, the via hole including an upper portion having a first taper angle and a lower portion having a second taper angle,

wherein the second taper angle is steeper than the first taper angle.

33. The semiconductor device ofclaim 32, further comprising an upper metal interconnection line contacting the metal interconnection line through the via hole.

34. A semiconductor device, comprising:

a substrate;

a semiconductor layer, a gate insulating layer, and a gate electrode formed on the substrate;

a planarization layer formed on the substrate; and

a via contact hole penetrating the planarization layer and the gate insulating layer and exposing a portion of the semiconductor layer, the via hole including an upper portion having a first taper angle and a lower portion having a second taper angle,

wherein the second taper angle is steeper than the first taper angle.

35. The semiconductor device ofclaim 34, wherein a metal interconnection line or a pixel electrode contacts the exposed portion of the semiconductor layer through the via contact hole.

36. A semiconductor device, comprising:

a substrate;

a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric formed on the substrate;

a thin film transistor (TFT) region including a contact hole, the contact hole penetrating the gate insulating layer and the interlayer dielectric, exposing a portion of the semiconductor layer, and including an upper portion having a first taper angle and a lower portion having a second taper angle;

a metal interconnection line and an insulating layer formed on the substrate and spaced apart from the TFT region by a predetermined interval; and

a via hole penetrating the insulating layer and including an upper portion having a third taper angle and a lower portion having a fourth taper angle,

wherein the second taper angle is steeper than the first taper angle, and

wherein the fourth taper angle is steeper than the third taper angle.

37. The semiconductor device ofclaim 36, wherein an electrode contacts the exposed portion of the semiconductor layer through the contact hole, and an upper metal interconnection contacts the metal interconnection line through the via hole.

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