US20050253167A1 - Wide bandgap field effect transistors with source connected field plates - Google Patents
Wide bandgap field effect transistors with source connected field platesDownload PDFInfo
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- US20050253167A1 US20050253167A1US10/958,945US95894504AUS2005253167A1US 20050253167 A1US20050253167 A1US 20050253167A1US 95894504 AUS95894504 AUS 95894504AUS 2005253167 A1US2005253167 A1US 2005253167A1
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
- H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
- H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
Definitions
- the present inventionrelates to transistors and particularly to field effect transistors utilizing field plates.
- AlGaN/GaN semiconductor materialshave helped advance the development of AlGaN/GaN transistors, such as high electron mobility transistors (HEMTs) for high frequency, high temperature and high power applications.
- HEMTshigh electron mobility transistors
- AlGaN/GaNhas large bandgaps, high peak and saturation electron velocity values [B. Gelmont, K. Kim and M. Shur, Monte Carlo Simulation of Electron Transport in Gallium Nitride , J. Appl. Phys. 74, (1993), pp. 1818-1821].
- SiN passivationhas been successfully employed to alleviate this trapping problem resulting in high performance devices with power densities over 10 W/mm at 10 Ghz.
- SiNSilicon nitride
- U.S. Pat. No. 6,586,781which is incorporated herein by reference in its entirety discloses methods and structures for reducing the trapping effect in GaN-based transistors. However, due to the high electric fields existing in these structures, charge trapping is still an issue.
- the present inventionprovides improved field effect transistors having a field plate connected to the source electrode.
- a field effect transistor according to the present inventioncomprises a metal semiconductor field effect transistor (MESFET) having a buffer layer on a substrate and a channel layer on the buffer layer with the buffer layer sandwiched between the channel layer and substrate.
- a source electrodeis included in electrical contact with said plurality of the channel layer, along with a drain electrode in electrical contact with said channel layer.
- a gateis included in electrical contact with the channel layer and between the source and drain electrodes.
- a spacer layeris over at least a portion of the channel layer between the gate and the drain electrode.
- a field plateis formed on the spacer layer and electrically isolated from the channel layer and gate, with the field plate electrically connected to the source electrode by at least one conductive path.
- Another embodiment of a field effect transistor according to the present inventioncomprises a buffer layer and channel layer formed successively on a substrate.
- a source electrode, drain electrode, and gateare all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes.
- a spacer layeris formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is separately formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the transistor.
- Still another embodiment of a transistor according to the present inventioncomprises a metal semiconductor field effect transistor (MESFET) having a buffer layer and channel layer formed successively on a substrate.
- Source electrode, drain electrode, and gateare all formed in electrical contact with the channel layer with the gate between the source and drain electrodes.
- a field plateextends a distance L f from the edge of the gate to the drain electrode with the field plate isolated from the gate and active layers.
- At least one conductive pathelectrically connects the field plate to the source electrode, with the at least one conductive path covering less than all of the topmost surface between the gate and source electrode.
- FIG. 1is a plan view of one embodiment of a MESFET according to the present invention.
- FIG. 2is a sectional view of the MESFET in FIG. 1 ;
- FIG. 3is a plan view of another embodiment of a MESFET according to the present invention.
- FIG. 4is a sectional view of the MESFET in FIG. 3 .
- FIG. 5is a sectional view of another embodiment of a MESFET according to the present invention having a gamma gate
- FIG. 6is a sectional view of still another embodiment of a MESFET according to the present invention having a recessed gate.
- Wide bandgap transistor structuresgenerally include an active region, with metal source and drain electrodes formed in electrical contact with the active region, and a gate electrode formed between the source and drain electrodes for modulating electric fields within the active region.
- a spacer layeris formed above the active region.
- the spacer layercan comprise a dielectric layer, or a combination of multiple dielectric layers.
- a conductive field plateis formed on the spacer layer and extends a distance L f from the edge of the gate electrode toward the drain electrode.
- the field platecan be electrically connected to the source electrode.
- This field plate arrangementcan reduce the peak electric field in the device, resulting in increased breakdown voltage and reduced trapping. The reduction of the electric field can also yield other benefits such as reduced leakage currents and enhanced reliability.
- the field plate electrically connected to the source electrodeBy having the field plate electrically connected to the source electrode, the reduced gain and instability resulting from gate connected field plates is reduced.
- the shielding effect of a source-connected field platecan reduce C gd , which enhances input-output isolation.
- One type of transistor that can utilize the field plate arrangement according to the present inventionis a field effect transistor and particularly a metal semiconductor field effect transistor (MESFET), which typically includes a buffer layer and a channel layer on the buffer layer. A gate electrode is formed on the channel layer between source and drain electrodes.
- MESFETmetal semiconductor field effect transistor
- a spacer layeris formed on the channel layer covering at least a portion of the channel layer between the gate and drain electrode such that a field plate can be formed on the spacer layer in electric isolation from the channel layer.
- the spacer layercan also cover all or some of the gate such that the field plate can overlap the gate while remaining in electrical isolation from the gate and the channel layer.
- the spacer layercovers the gate and the surface of the barrier layer between the gate and the source and drain electrodes.
- the spacer layercan comprise a dielectric layer, or a combination of multiple dielectric layers. Different dielectric materials can be used such as a SiN, SiO2, Si, Ge, MgOx, MgNx, ZnO, SiNx, SiOx, alloys or layer sequences thereof, or epitaxial materials as further described below.
- a conductive field plateis formed on the spacer layer and extends a distance L f as measured from the edge of the gate towards the drain electrode, with the field plate and gate electrode typically being formed during separate deposition steps.
- the field plateis electrically connected to the source electrode typically by conductive paths arranged in different ways.
- FIGS. 1 and 2show one embodiment of a MESFET 10 according to the present invention that can be made from many different semiconductor material systems, with a preferred MESFET 10 being silicon carbide based.
- MESFET 10comprises a substrate 12 that can be made of many different materials capable of supporting growth of a silicon carbide.
- the preferred substrate materialis silicon carbide and in some embodiments, the substrate 12 can comprise semi-insulating 4H-SiC commercially available from Cree, Inc. of Durham, N.C.
- the MESFET 10further comprises a silicon carbide buffer layer 14 formed on the substrate 12 with a silicon carbide channel layer 16 formed on the buffer, with the buffer layer 14 sandwiched between the channel layer 16 and substrate 12 .
- the buffer and channel layers 14 , 16can be formed on the substrate 12 using known semiconductor growth techniques such as Metal Oxide Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE) or Molecular Beam Epitaxy (MBE).
- MOCVDMetal Oxide Chemical Vapor Deposition
- HVPEHydride Vapor Phase Epitaxy
- MBEMolecular Beam Epitaxy
- a nucleation layer(not shown) can be included between the substrate 12 and the buffer 14 to reduce any lattice mismatch between the two.
- the nucleation layercan comprise many different materials, can also be formed on the substrate 12 using MOCVD, HVPE or MBE. The formation of the nucleation layer can depend on the material used for the substrate 12 . For example, methods of forming a nucleation layer on various substrates are taught in U.S. Pat. Nos. 5,290,393 and 5,686,738, each of which are incorporated by reference as if fully set forth herein. Methods of forming nucleation layers on silicon carbide substrates are disclosed in U.S. Pat. Nos. 5,393,993, 5,523,589, and 5,739,554 each of which is incorporated herein by reference as if fully set forth herein.
- Metal source and drain electrodes 18 , 20are formed in contact with the channel layer 16 and a gate 22 is formed on the channel layer 16 between the source and drain electrodes 18 , 20 . Electric current can flow between the source and drain electrodes 18 , 20 through the channel layer 16 when the gate 22 is biased at the appropriate level.
- the source and drain contacts 18 , 20can be made of different materials including but not limited to alloys of titanium, aluminum, gold or nickel, nickel, gold, platinum, titanium, chromium, alloys of titanium and tungsten, or platinum silicide.
- the gate 24can have many different lengths, with a preferred gate length (L g ) being approximately 0.5 microns. As best shown in FIG. 1 , the gate 22 is connected to and contacted at a gate contact 24 .
- a first spacer layer 26is formed over the gate 22 and the surface of the channel layer 16 between the gate 22 and the source and drain electrodes 18 , 20 .
- the spacer layer 26can cover less of the channel layer and the gate as long as enough of a spacer layer is provided to isolate the field plate from the gate and channel layer.
- the spacer layer 26can comprise many of the different materials above, alone or in combination, but preferably comprises a layer of one of the dielectric materials listed above, or a number of different layers of dielectric materials.
- the spacer layer 26can be many different thicknesses, with a suitable range of thicknesses be approximately 0.05 to 2 microns. Electric isolation between the devices is done with mesa etch or ion implementation outside the active area of the MESFET.
- the spacer layer 26can comprise an epitaxial material such a Group III nitride material having different Group III elements such as alloys of Al, Ga, or In, with a suitable spacer layer material being Al x Ga 1-x N (0 ⁇ x ⁇ 1).
- the spacer layer 26can be grown using the same epitaxial growth method.
- the spacer layer 26is then etched such that the gate 24 , source electrode 20 and drain electrode 22 can be properly formed in contact with the buffer layer 18 and the 2DEG 17 .
- a field platecan then be deposited on the spacer layer between the gate 24 and drain electrode 22 . In those embodiments where the field plate overlaps the gate, an additional spacer layer of dielectric material should be included at least partially over the gate to isolate the gate from the field plate.
- a field plate 30is formed on the spacer layer 26 between the gate 22 and the drain electrode 20 , with the field plate 30 being in close proximity to the gate 22 but not overlapping it.
- a space between the gate 22 and field plate (L gf )remains and should be wide enough to isolate from the field plate 30 , while being small enough to maximize the field effect provided by the field plate 30 . If L gf is too wide the field effect can be reduced. In one embodiment according to the present invention L gf can be approximately 0.4 microns or less, although larger and smaller spaces can also be used.
- the field plate 30can extend different distances L f from the edge of the gate 24 , with a suitable range of distances being approximately 0.1 to 2 microns.
- the field plate 30can comprise many different conductive materials with a suitable material being a metal, or combinations of metals, deposited using standard metallization methods.
- the field plate 30comprises titanium/gold or nickel/gold.
- FIG. 1shows two connection structures that can be used according to the present invention, although it is understood that other connection structures can also be used.
- conductive buses 32can be formed on the spacer layer 26 to extend between the field plate 30 and the source electrode 18 . Different numbers of buses 32 can be used although the greater the number of buses the greater the unwanted capacitance that can be introduced by the buses.
- the busesshould have a sufficient number so that current effectively spreads between the source contact 18 and the field plate 30 while not covering too much of the MESFET's active region, with a suitable number of buses 32 being two.
- the conductive pathsdo not cover all of the topmost layers between the gate and source electrode, which will preferable be the spacer layer 26 .
- the spacer layer 26can cover only the surface of the channel layer in strips (not shown) between the gate and source electrode, with the strips having a width sufficient to support the conductive busses 32 .
- the busses 32would then extend from the field plate 30 over those spacer layer areas that cover the channel layer.
- the field plate 30can also be electrically connected to the source contact 20 through a conductive path 34 that runs outside of the active regions and spacer layer 26 of the MESFET 10 and is coupled to the source contact 20 .
- This arrangementcan be used in other embodiments but it is particularly adapted for use in embodiments where the spacer layer 26 does not cover the channel layer 16 between the gate 22 and the source 18 .
- the path 34runs outside the active area of the MESFET at the side opposite the gate 24 .
- the conductive pathcould run outside the active area of the MESFET 10 on the side of the gate 24 , or the MESFET 10 could include two or more conductive paths running out the same or different sides of the MESFET 10 .
- the active structurecan be covered by a dielectric passivation layer (not shown), such as silicon nitride.
- the passivation layercan be formed using known growth methods.
- FIGS. 3 and 4show another embodiment of a MESFET 40 according to the present invention having many features that are similar to those in MESFET 10 .
- the same reference numeralsare used and the features are introduced without full description with the understanding that the description of the features above applies equally to the MESFET 40 .
- the MESFET 40is preferably silicon carbide based and comprises a silicon carbide substrate 12 , silicon carbide buffer layer 14 , silicon carbide channel layer 16 , source contact 18 , drain contact 20 , gate 22 , gate contact 24 and spacer layer 26 .
- the MESFET 40also comprises a field plate 42 that is formed on the spacer layer 26 primarily between the gate 22 and the drain contact 20 , but also overlapping a portion of the gate 22 .
- L gfis small, which can present some difficulties during fabrication.
- the HEMT 40can be fabricated without having to meet the tolerances of L gf .
- the overlapping section of the field plate 42can introduce additional unwanted capacitance. In determining whether to use a field plate 30 or 42 the ease of manufacturing using field plate 42 must be balanced with the reduced capacitance provided by field plate 30 in FIGS. 1 and 2 .
- the MESFET 40also comprises either buses 44 or a conductive path 34 to electrically connect the field plate 42 to the source contact 18 .
- FIG. 5shows another embodiment of a MESFET 50 according to the present invention that has many features similar to those in MESFETs 10 and 40 , including a substrate 12 , buffer layer 14 , channel layer 16 , source electrode 18 , and drain electrode 20 .
- MESFET 80has a gamma ( ⁇ ) shaped gate 52 that is particularly adapted to high frequency operation.
- Gate length (L g )is one of the important device dimensions in determining device speed, and with higher frequency devices the gate length is shorter. Shorter gate length can lead to high resistance that can negatively impact high frequency operation.
- T-gatesare commonly used in high frequency operation, but it can be difficult to achieve a well-coupled placement of a field plate with a T-gate.
- the gamma gate 52provides for low gate resistance and allows for controlled definition of the gate footprint.
- a spacer layer 54is included that covers the gamma gate 52 and the surface of barrier layer 16 between the gamma gate 52 and the source and drain electrodes 18 , 20 .
- a spacecan remain between the horizontal portion of the gamma gate 52 and the top of the spacer layer 54 between the gate 52 and the source electrode.
- the MESFET 50also includes a field plate 56 on the spacer layer 54 that overlaps that gamma gate 52 , with the field plate 56 preferably deposited on the side of the gamma gate 52 not having a horizontal overhanging section. This arrangement allows for tight placement and effective coupling between the field plate 56 and the active layers below it.
- the field platecan be similarly arranged to field plate 56 , but instead of overlapping the gate, there can be a space between the edge of the gate and the field plate similar to space L gf shown in FIG. 2 .
- the field plate 56can be electrically connected to the source electrode 18 in many different ways. Because of the space between the lower surface of the horizontal section of the gate 52 and the spacer layer 54 , it can be difficult to provide a conductive path directly between the field plate 56 and the source electrode 18 . Instead, a conductive path can be included between the field plate 56 and the source electrode 18 that runs outside the active area of the MESFET 50 . Alternatively, the gamma gate 52 can be completely covered by the spacer layer 54 with the space under the gate's horizontal section filled. Conductive paths can then run directly from the field plate 56 to the source electrode over the spacer layer 54 . The active structure can then be covered by a dielectric passivation layer (not shown).
- FIG. 6shows still another MESFET 60 according to the present invention that can also be arranged with a source connected field plate.
- MESFET 60also has many features similar to those in MESFETs 10 and 40 in FIGS. 1-4 , including a substrate 12 , buffer layer 14 , channel layer 16 , source electrode 18 , and drain electrode 20 .
- the gate 62is recessed in the channel layer 16 , and is covered by a spacer layer 64 . In other embodiments the bottom surface of the gate can be only partially recessed or different portions of the gate can be recessed to different depths in the channel layer 16 .
- a field plate 66is arranged on the spacer layer 64 and is electrically connected to the source electrode 18 and the active structure can be covered by a dielectric passivation layer (not shown). Like above of the MESFET 60 , the field plate 66 can be arranged so that there is a space Lgf between the edge of the gate and the field plate.
- the embodiments aboveprovide wide bandgap transistors, particularly MESFETs, with improved power at microwave and millimeter wave frequencies.
- the MESFETsexhibit simultaneous high gain, high power, and more stable operation due to higher input-output isolation.
- the structurecould be extended to larger dimensions for high voltage applications at lower frequencies.
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Abstract
Description
- This application claims the benefit of provisional application Ser. No. 60/571,342 to Wu et al., which was filed on May 13, 2004.
- 1. Field of the Invention
- The present invention relates to transistors and particularly to field effect transistors utilizing field plates.
- 2. Description of the Related Art
- Improvements in the manufacturing of AlGaN/GaN semiconductor materials have helped advance the development of AlGaN/GaN transistors, such as high electron mobility transistors (HEMTs) for high frequency, high temperature and high power applications. AlGaN/GaN has large bandgaps, high peak and saturation electron velocity values [B. Gelmont, K. Kim and M. Shur,Monte Carlo Simulation of Electron Transport in Gallium Nitride, J. Appl. Phys. 74, (1993), pp. 1818-1821].
- Electron trapping and the resulting difference between DC and RF characteristics have been a limiting factor in the performance of these devices. Silicon nitride (SiN) passivation has been successfully employed to alleviate this trapping problem resulting in high performance devices with power densities over 10 W/mm at 10 Ghz. For example, U.S. Pat. No. 6,586,781 which is incorporated herein by reference in its entirety discloses methods and structures for reducing the trapping effect in GaN-based transistors. However, due to the high electric fields existing in these structures, charge trapping is still an issue.
- Field plates (FP) have been used to enhance the performance of GaN-based HEMTs at microwave frequencies [See S Kamalkar and U. K. Mishra,Very High Voltage AlGaN/GaN High Electron Mobility Transistors Using a Field Plate Deposited on a Stepped Insulator, Solid State Electronics 45, (2001), pp. 1645-1662]. These approaches, however, have involved a field plate connected to the gate of the transistor with the field plate on top of the drain side of the channel. This can result in a significant field plate to drain capacitance and the field plate connected to the gate adds additional gate-to-drain capacitance (Cgd) to the device. This can not only reduce gain, but can also cause instability due to poorer input-output isolation.
- The present invention provides improved field effect transistors having a field plate connected to the source electrode. One embodiment of a field effect transistor according to the present invention comprises a metal semiconductor field effect transistor (MESFET) having a buffer layer on a substrate and a channel layer on the buffer layer with the buffer layer sandwiched between the channel layer and substrate. A source electrode is included in electrical contact with said plurality of the channel layer, along with a drain electrode in electrical contact with said channel layer. A gate is included in electrical contact with the channel layer and between the source and drain electrodes. A spacer layer is over at least a portion of the channel layer between the gate and the drain electrode. A field plate is formed on the spacer layer and electrically isolated from the channel layer and gate, with the field plate electrically connected to the source electrode by at least one conductive path.
- Another embodiment of a field effect transistor according to the present invention comprises a buffer layer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is separately formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the transistor.
- Still another embodiment of a transistor according to the present invention comprises a metal semiconductor field effect transistor (MESFET) having a buffer layer and channel layer formed successively on a substrate. Source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer with the gate between the source and drain electrodes. A field plate extends a distance Lffrom the edge of the gate to the drain electrode with the field plate isolated from the gate and active layers. At least one conductive path electrically connects the field plate to the source electrode, with the at least one conductive path covering less than all of the topmost surface between the gate and source electrode.
- These and other further features and advantages of the invention would be apparent to those skilled in the art from the following detailed description, taking together with the accompanying drawings, in which:
FIG. 1 is a plan view of one embodiment of a MESFET according to the present invention;FIG. 2 is a sectional view of the MESFET inFIG. 1 ;FIG. 3 is a plan view of another embodiment of a MESFET according to the present invention; andFIG. 4 is a sectional view of the MESFET inFIG. 3 .FIG. 5 is a sectional view of another embodiment of a MESFET according to the present invention having a gamma gate; andFIG. 6 is a sectional view of still another embodiment of a MESFET according to the present invention having a recessed gate.- The field plate arrangements according to the present invention can be used with many different transistor structures. Wide bandgap transistor structures generally include an active region, with metal source and drain electrodes formed in electrical contact with the active region, and a gate electrode formed between the source and drain electrodes for modulating electric fields within the active region. A spacer layer is formed above the active region. The spacer layer can comprise a dielectric layer, or a combination of multiple dielectric layers. A conductive field plate is formed on the spacer layer and extends a distance Lffrom the edge of the gate electrode toward the drain electrode.
- The field plate can be electrically connected to the source electrode. This field plate arrangement can reduce the peak electric field in the device, resulting in increased breakdown voltage and reduced trapping. The reduction of the electric field can also yield other benefits such as reduced leakage currents and enhanced reliability. By having the field plate electrically connected to the source electrode, the reduced gain and instability resulting from gate connected field plates is reduced. When arranged according to the present invention, the shielding effect of a source-connected field plate can reduce Cgd, which enhances input-output isolation.
- One type of transistor that can utilize the field plate arrangement according to the present invention is a field effect transistor and particularly a metal semiconductor field effect transistor (MESFET), which typically includes a buffer layer and a channel layer on the buffer layer. A gate electrode is formed on the channel layer between source and drain electrodes.
- According to the present invention, a spacer layer is formed on the channel layer covering at least a portion of the channel layer between the gate and drain electrode such that a field plate can be formed on the spacer layer in electric isolation from the channel layer. In other embodiments the spacer layer can also cover all or some of the gate such that the field plate can overlap the gate while remaining in electrical isolation from the gate and the channel layer. In a preferred embodiment the spacer layer covers the gate and the surface of the barrier layer between the gate and the source and drain electrodes. The spacer layer can comprise a dielectric layer, or a combination of multiple dielectric layers. Different dielectric materials can be used such as a SiN, SiO2, Si, Ge, MgOx, MgNx, ZnO, SiNx, SiOx, alloys or layer sequences thereof, or epitaxial materials as further described below.
- A conductive field plate is formed on the spacer layer and extends a distance Lfas measured from the edge of the gate towards the drain electrode, with the field plate and gate electrode typically being formed during separate deposition steps. The field plate is electrically connected to the source electrode typically by conductive paths arranged in different ways.
FIGS. 1 and 2 show one embodiment of aMESFET 10 according to the present invention that can be made from many different semiconductor material systems, with apreferred MESFET 10 being silicon carbide based.MESFET 10 comprises asubstrate 12 that can be made of many different materials capable of supporting growth of a silicon carbide. The preferred substrate material is silicon carbide and in some embodiments, thesubstrate 12 can comprise semi-insulating 4H-SiC commercially available from Cree, Inc. of Durham, N.C.- The
MESFET 10 further comprises a siliconcarbide buffer layer 14 formed on thesubstrate 12 with a siliconcarbide channel layer 16 formed on the buffer, with thebuffer layer 14 sandwiched between thechannel layer 16 andsubstrate 12. The buffer and channel layers14,16 can be formed on thesubstrate 12 using known semiconductor growth techniques such as Metal Oxide Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE) or Molecular Beam Epitaxy (MBE). - A nucleation layer (not shown) can be included between the
substrate 12 and thebuffer 14 to reduce any lattice mismatch between the two. The nucleation layer can comprise many different materials, can also be formed on thesubstrate 12 using MOCVD, HVPE or MBE. The formation of the nucleation layer can depend on the material used for thesubstrate 12. For example, methods of forming a nucleation layer on various substrates are taught in U.S. Pat. Nos. 5,290,393 and 5,686,738, each of which are incorporated by reference as if fully set forth herein. Methods of forming nucleation layers on silicon carbide substrates are disclosed in U.S. Pat. Nos. 5,393,993, 5,523,589, and 5,739,554 each of which is incorporated herein by reference as if fully set forth herein. - Metal source and drain
electrodes channel layer 16 and agate 22 is formed on thechannel layer 16 between the source and drainelectrodes electrodes channel layer 16 when thegate 22 is biased at the appropriate level. The source anddrain contacts gate 24 can have many different lengths, with a preferred gate length (Lg) being approximately 0.5 microns. As best shown inFIG. 1 , thegate 22 is connected to and contacted at agate contact 24. - As best shown in
FIG. 2 , afirst spacer layer 26 is formed over thegate 22 and the surface of thechannel layer 16 between thegate 22 and the source and drainelectrodes spacer layer 26 can cover less of the channel layer and the gate as long as enough of a spacer layer is provided to isolate the field plate from the gate and channel layer. Thespacer layer 26 can comprise many of the different materials above, alone or in combination, but preferably comprises a layer of one of the dielectric materials listed above, or a number of different layers of dielectric materials. Thespacer layer 26 can be many different thicknesses, with a suitable range of thicknesses be approximately 0.05 to 2 microns. Electric isolation between the devices is done with mesa etch or ion implementation outside the active area of the MESFET. - When the
spacer layer 26 is formed before device metallization thespacer layer 26 can comprise an epitaxial material such a Group III nitride material having different Group III elements such as alloys of Al, Ga, or In, with a suitable spacer layer material being AlxGa1-xN (0≦x≦1). After epitaxial growth of thechannel layer 16, thespacer layer 26 can be grown using the same epitaxial growth method. Thespacer layer 26 is then etched such that thegate 24,source electrode 20 anddrain electrode 22 can be properly formed in contact with thebuffer layer 18 and the 2DEG17. A field plate can then be deposited on the spacer layer between thegate 24 anddrain electrode 22. In those embodiments where the field plate overlaps the gate, an additional spacer layer of dielectric material should be included at least partially over the gate to isolate the gate from the field plate. - A
field plate 30 is formed on thespacer layer 26 between thegate 22 and thedrain electrode 20, with thefield plate 30 being in close proximity to thegate 22 but not overlapping it. A space between thegate 22 and field plate (Lgf) remains and should be wide enough to isolate from thefield plate 30, while being small enough to maximize the field effect provided by thefield plate 30. If Lgfis too wide the field effect can be reduced. In one embodiment according to the present invention Lgfcan be approximately 0.4 microns or less, although larger and smaller spaces can also be used. - The
field plate 30 can extend different distances Lffrom the edge of thegate 24, with a suitable range of distances being approximately 0.1 to 2 microns. Thefield plate 30 can comprise many different conductive materials with a suitable material being a metal, or combinations of metals, deposited using standard metallization methods. In some embodiments according to the present invention thefield plate 30 comprises titanium/gold or nickel/gold. - The
field plate 30 is electrically connected to thesource contact 18 andFIG. 1 shows two connection structures that can be used according to the present invention, although it is understood that other connection structures can also be used. In those embodiments where the spacer layer covers the gate and the surface of the channel layer between thegate 22 andsource electrode 18,conductive buses 32 can be formed on thespacer layer 26 to extend between thefield plate 30 and thesource electrode 18. Different numbers ofbuses 32 can be used although the greater the number of buses the greater the unwanted capacitance that can be introduced by the buses. The buses should have a sufficient number so that current effectively spreads between thesource contact 18 and thefield plate 30 while not covering too much of the MESFET's active region, with a suitable number ofbuses 32 being two. In one embodiment, the conductive paths do not cover all of the topmost layers between the gate and source electrode, which will preferable be thespacer layer 26. - Alternatively, the
spacer layer 26 can cover only the surface of the channel layer in strips (not shown) between the gate and source electrode, with the strips having a width sufficient to support the conductive busses32. Thebusses 32 would then extend from thefield plate 30 over those spacer layer areas that cover the channel layer. - The
field plate 30 can also be electrically connected to thesource contact 20 through aconductive path 34 that runs outside of the active regions andspacer layer 26 of theMESFET 10 and is coupled to thesource contact 20. This arrangement can be used in other embodiments but it is particularly adapted for use in embodiments where thespacer layer 26 does not cover thechannel layer 16 between thegate 22 and thesource 18. As shown inFIG. 1 , thepath 34 runs outside the active area of the MESFET at the side opposite thegate 24. In alternative embodiments according to the present invention, the conductive path could run outside the active area of theMESFET 10 on the side of thegate 24, or theMESFET 10 could include two or more conductive paths running out the same or different sides of theMESFET 10. - After deposition of the
field plate 30 and its connection to thesource contact 20, the active structure can be covered by a dielectric passivation layer (not shown), such as silicon nitride. The passivation layer can be formed using known growth methods. FIGS. 3 and 4 show another embodiment of aMESFET 40 according to the present invention having many features that are similar to those inMESFET 10. For the similar features the same reference numerals are used and the features are introduced without full description with the understanding that the description of the features above applies equally to theMESFET 40.- The
MESFET 40 is preferably silicon carbide based and comprises asilicon carbide substrate 12, siliconcarbide buffer layer 14, siliconcarbide channel layer 16,source contact 18,drain contact 20,gate 22,gate contact 24 andspacer layer 26. TheMESFET 40 also comprises afield plate 42 that is formed on thespacer layer 26 primarily between thegate 22 and thedrain contact 20, but also overlapping a portion of thegate 22. For theMESFET 10 inFIGS. 1 and 2 , Lgfis small, which can present some difficulties during fabrication. By having thefield plate 42 overlap thegate 22 theHEMT 40 can be fabricated without having to meet the tolerances of Lgf. The overlapping section of thefield plate 42, however, can introduce additional unwanted capacitance. In determining whether to use afield plate field plate 42 must be balanced with the reduced capacitance provided byfield plate 30 inFIGS. 1 and 2 . TheMESFET 40 also comprises eitherbuses 44 or aconductive path 34 to electrically connect thefield plate 42 to thesource contact 18. - The source connected field plate arrangement according to the present invention can be used in many different MESFETs beyond those described above. For example,
FIG. 5 shows another embodiment of aMESFET 50 according to the present invention that has many features similar to those inMESFETs substrate 12,buffer layer 14,channel layer 16,source electrode 18, and drainelectrode 20. MESFET80, however, has a gamma (Γ) shapedgate 52 that is particularly adapted to high frequency operation. Gate length (Lg) is one of the important device dimensions in determining device speed, and with higher frequency devices the gate length is shorter. Shorter gate length can lead to high resistance that can negatively impact high frequency operation. T-gates are commonly used in high frequency operation, but it can be difficult to achieve a well-coupled placement of a field plate with a T-gate. - The
gamma gate 52 provides for low gate resistance and allows for controlled definition of the gate footprint. Aspacer layer 54 is included that covers thegamma gate 52 and the surface ofbarrier layer 16 between thegamma gate 52 and the source and drainelectrodes gamma gate 52 and the top of thespacer layer 54 between thegate 52 and the source electrode. TheMESFET 50 also includes afield plate 56 on thespacer layer 54 that overlaps thatgamma gate 52, with thefield plate 56 preferably deposited on the side of thegamma gate 52 not having a horizontal overhanging section. This arrangement allows for tight placement and effective coupling between thefield plate 56 and the active layers below it. In other gamma gate embodiments the field plate can be similarly arranged tofield plate 56, but instead of overlapping the gate, there can be a space between the edge of the gate and the field plate similar to space Lgfshown inFIG. 2 . - The
field plate 56 can be electrically connected to thesource electrode 18 in many different ways. Because of the space between the lower surface of the horizontal section of thegate 52 and thespacer layer 54, it can be difficult to provide a conductive path directly between thefield plate 56 and thesource electrode 18. Instead, a conductive path can be included between thefield plate 56 and thesource electrode 18 that runs outside the active area of theMESFET 50. Alternatively, thegamma gate 52 can be completely covered by thespacer layer 54 with the space under the gate's horizontal section filled. Conductive paths can then run directly from thefield plate 56 to the source electrode over thespacer layer 54. The active structure can then be covered by a dielectric passivation layer (not shown). FIG. 6 shows still anotherMESFET 60 according to the present invention that can also be arranged with a source connected field plate.MESFET 60 also has many features similar to those inMESFETs FIGS. 1-4 , including asubstrate 12,buffer layer 14,channel layer 16,source electrode 18, and drainelectrode 20. Thegate 62, however, is recessed in thechannel layer 16, and is covered by aspacer layer 64. In other embodiments the bottom surface of the gate can be only partially recessed or different portions of the gate can be recessed to different depths in thechannel layer 16. Afield plate 66 is arranged on thespacer layer 64 and is electrically connected to thesource electrode 18 and the active structure can be covered by a dielectric passivation layer (not shown). Like above of theMESFET 60, thefield plate 66 can be arranged so that there is a space Lgf between the edge of the gate and the field plate.- The embodiments above provide wide bandgap transistors, particularly MESFETs, with improved power at microwave and millimeter wave frequencies. The MESFETs exhibit simultaneous high gain, high power, and more stable operation due to higher input-output isolation. The structure could be extended to larger dimensions for high voltage applications at lower frequencies.
- Although the present invention has been described in considerable detail with reference to certain preferred configurations thereof, other versions are possible. The field plate arrangement can be used in many different devices. The field plates can also have many different shapes and can be connected to the source contact in many different ways. The spirit and scope of the invention should not be limited to the preferred versions of the invention described above.
Claims (29)
1. A metal semiconductor field effect transistor (MESFET), comprising:
a buffer layer on a substrate;
a channel layer on said buffer layer with said buffer layer sandwiched between said channel layer and substrate;
a source electrode in electrical contact with said channel layer;
a drain electrode also in electrical contact with said channel layer;
a gate in electrical contact with said channel layer between said source and drain electrodes;
a spacer layer over at least a portion of said channel layer between said gate and said drain electrode; and
a field plate separately on said spacer layer and isolated from said channel layer and gate, said field plate electrically connected to said source electrode by at least one conductive path.
2. The MESFET ofclaim 1 , wherein said at least one conductive path covers less than all of the topmost surface between said gate and source electrode.
3. The MESFET ofclaim 1 , wherein said field plate extends on said spacer layer a distance Lffrom the edge of said gate toward said drain electrode.
4. The MESFET ofclaim 1 , wherein said spacer layer at least partially covers said gate and said field plate at least partially overlaps said gate and extends on said spacer layer a distance Lffrom the edge of said gate toward said drain electrode.
5. The MESFET ofclaim 1 , wherein said at least one conductive path runs between said field plate and source electrode, each said path running outside of said spacer layer and providing said field plate electrical connection with said source electrode.
6. The MESFET ofclaim 1 , wherein said spacer layer is further formed on the surface of said channel layer between said gate and said source electrode.
7. The MESFET ofclaim 6 , wherein said at least one conductive path runs between said field plate and source electrode over said spacer layer and providing said field plate electrical connection with said source electrode.
8. The MESFET ofclaim 1 , wherein said buffer and channel layers are silicon carbide based.
9. The MESFET ofclaim 1 , wherein said spacer layer comprises a dielectric material, or multiple layers of dielectric material.
10. The MESFET ofclaim 1 , wherein said gate is gamma shaped
11. The MESFET ofclaim 1 , wherein said gate is at least partially recessed in said barrier layer.
12. A field effect transistor, comprising:
a buffer layer and channel layer formed successively on a substrate;
source electrode, drain electrode, and gate all formed in electrical contact with said channel layer with said gate between said source and drain electrodes;
a spacer layer formed on at least a portion of a surface of said channel layer between said gate and drain electrode; and
a field plate formed on said spacer layer isolated from said gate and channel layer and electrically connected by at least one conductive path to said source electrode, wherein said field plate reduces the peak operating electric field in said transistor.
13. The transistor ofclaim 12 , wherein said reduction in peak operating electric field increases the breakdown voltage of said transistor.
14. The transistor ofclaim 12 , wherein said reduction in peak operating electric field reduces trapping in said transistor.
15. The transistor ofclaim 12 , wherein said reduction in peak operating electric field reduces leakage currents in said transistor.
16. The transistor ofclaim 12 , wherein said spacer layer covers at least partially covers said gate and extending on the at least part of the surface of said channel layer between said gate and drain electrode, said field plate at least partially overlapping said gate and extending on said spacer layer toward said drain electrode.
17. The transistor ofclaim 12 , wherein said at least one conductive path runs between said field plate and source electrode, each said path running outside of said spacer layer and providing said field plate electrical connection with said source electrode.
18. The transistor ofclaim 12 , wherein said spacer layer is further formed on the surface of the said active semiconductor layers, between said gate and said source electrode.
19. The transistor ofclaim 18 , wherein said at least one conductive path runs between said field plate and source electrode over said spacer layer to provide said field plate electrical connection with said source electrode.
20. The transistor ofclaim 12 , wherein said spacer layer comprises a dielectric material, or multiple layers of dielectric material.
21. A metal semiconductor field effect transistor (MESFET), comprising:
a buffer layer and channel layer formed successively on a substrate;
source electrode, drain electrode, and gate all formed in electrical contact with said channel layer with said gate between said source and drain electrodes;
a field plate extending a distance Lffrom the edge of said gate to said drain electrode, said field plate isolated from said gate and active layers; and
at least one conductive path electrically connecting said field plate to said source electrode, said at least one conductive path covering less than all of the topmost surface between said gate and source electrode.
22. The MESFET ofclaim 21 , further comprising a spacer layer between said field plate and said gate and active layer to provide said field plate isolation.
23. The MESFET ofclaim 21 , wherein said field plate reduces the peak operating electric field in said HEMT.
24. The MESFET ofclaim 23 , wherein said reduction in peak operating electric field increases the breakdown voltage of said MESFET.
25. The MESFET ofclaim 23 , wherein said reduction in peak operating electric field reduces trapping in said MESFET.
26. The MESFET ofclaim 23 , wherein said reduction in peak operating electric field reduces leakage currents in said MESFET.
27. A transistor, comprising:
an active region having a channel;
source electrode, drain electrode, and gate all in electrical contact with said active region with said gate between said source and drain electrodes on said active region;
a spacer layer over at least a portion of said active region between said gate and said drain electrode; and
a field plate on said spacer layer and isolated from said active region and gate, said field plate electrically connected to said source electrode by at least one conductive path, said field plate extending on said spacer layer a distance Lfas measured from the edge of said gate to said drain electrode.
28. The transistor ofclaim 27 , wherein said at least one conductive path electrically connecting said field plate to said source electrode covers less than all the topmost surface between said gate and source electrode.
29. The transistor ofclaim 27 , further comprising a spacer layer between said field plate and said gate and active region to provide said field plate isolation.
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| EP12171403.4AEP2515339B1 (en) | 2004-05-13 | 2005-04-21 | Wide bandgap field effect transistors with source connected field plates |
| EP05756258.9AEP1754263B1 (en) | 2004-05-13 | 2005-04-21 | Wide bandgap field effect transistors with source connected field plates |
| EP12171401AEP2515338A3 (en) | 2004-05-13 | 2005-04-21 | Wide bandgap field effect transistors with source connected field plates |
| CA2564955ACA2564955C (en) | 2004-05-13 | 2005-04-21 | Wide bandgap field effect transistors with source connected field plates |
| KR1020067026207AKR101142555B1 (en) | 2004-05-13 | 2005-04-21 | Wide bandgap field effect transistors with source connected field plates |
| BRPI0510960-4ABRPI0510960A (en) | 2004-05-13 | 2005-04-21 | transistor |
| PCT/US2005/013725WO2005114747A2 (en) | 2004-05-13 | 2005-04-21 | Wide bandgap field effect transistors with source connected field plates |
| JP2007513167AJP5611509B2 (en) | 2004-05-13 | 2005-04-21 | Wide band gap field effect transistor having a source region connected to a field plate |
| CN2005800148667ACN1998089B (en) | 2004-05-13 | 2005-04-21 | Wide bandgap field effect transistors with source connected field plates |
| AU2005246697AAU2005246697B2 (en) | 2004-05-13 | 2005-04-21 | Wide bandgap field effect transistors with source connected field plates |
| TW101131917ATWI502738B (en) | 2004-05-13 | 2005-05-09 | Transistor, field effect transistor and metal semiconductor field effect transistor |
| TW094114829ATWI452695B (en) | 2004-05-13 | 2005-05-09 | Transistor, field effect transistor and metal semiconductor field effect transistor |
| TW103120237ATWI620320B (en) | 2004-05-13 | 2005-05-09 | Transistor, field effect transistor and metal semiconductor field effect transistor |
| JP2014126655AJP5982430B2 (en) | 2004-05-13 | 2014-06-19 | Wide band gap field effect transistor having a source region connected to a field plate |
| US15/696,050US11664429B2 (en) | 2004-05-13 | 2017-09-05 | Wide bandgap field effect transistors with source connected field plates |
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| US10/958,945US9773877B2 (en) | 2004-05-13 | 2004-10-04 | Wide bandgap field effect transistors with source connected field plates |
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Cited By (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090230429A1 (en)* | 2005-06-10 | 2009-09-17 | Nec Corporation | Field effect transistor |
| US20090230430A1 (en)* | 2005-06-10 | 2009-09-17 | Nec Corproration | Field effect transistor |
| US20100025737A1 (en)* | 2008-07-29 | 2010-02-04 | Nec Electronics Corporation | Field-effect transistor |
| US20100163930A1 (en)* | 2008-12-26 | 2010-07-01 | Nobuo Kaneko | Semiconductor device and its manufacturing method |
| US20110006351A1 (en)* | 2009-07-13 | 2011-01-13 | Mitsubishi Electric Corporation | Semiconductor device |
| US20110169054A1 (en)* | 2004-05-11 | 2011-07-14 | Cree, Inc. | Wide bandgap hemts with source connected field plates |
| US20110291203A1 (en)* | 2010-05-31 | 2011-12-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US20120126287A1 (en)* | 2010-11-19 | 2012-05-24 | Sanken Electric Co., Ltd. | Compound semiconductor device having insulation film with different film thicknesses beneath electrodes |
| WO2014200643A1 (en) | 2013-06-09 | 2014-12-18 | Cree, Inc. | Cascode structures for gan hemts |
| WO2014200820A1 (en) | 2013-06-09 | 2014-12-18 | Cree, Inc | Cascode structures with gan cap layers |
| WO2014200753A2 (en) | 2013-06-09 | 2014-12-18 | Cree, Inc. | Recessed field plate transistor structures |
| US20160035422A1 (en)* | 2014-07-29 | 2016-02-04 | Macronix International Co., Ltd. | Transistor and circuit using same |
| US9397173B2 (en) | 2003-09-09 | 2016-07-19 | Cree, Inc. | Wide bandgap transistor devices with field plates |
| US20160247792A1 (en)* | 2015-02-25 | 2016-08-25 | Electronics And Telecommunications Research Institute | Switch circuit of cascode type having high speed switching performance |
| CN106328523A (en)* | 2015-06-15 | 2017-01-11 | 北大方正集团有限公司 | Method of manufacturing radio-frequency lateral double-diffused MOS (Metal Oxide Semiconductor) device |
| US9666664B2 (en) | 2012-09-28 | 2017-05-30 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
| US9773877B2 (en) | 2004-05-13 | 2017-09-26 | Cree, Inc. | Wide bandgap field effect transistors with source connected field plates |
| US20180026105A1 (en)* | 2013-08-01 | 2018-01-25 | Dynax Semiconductor, Inc. | Semiconductor device and method of manufacturing the same |
| CN109786233A (en)* | 2019-01-17 | 2019-05-21 | 中国电子科技集团公司第十三研究所 | The preparation method and power device of asymmetric surface slot field-effect transistor |
| US10396166B2 (en) | 2016-03-11 | 2019-08-27 | Mediatek Inc. | Semiconductor device capable of high-voltage operation |
| US10418480B2 (en)* | 2016-03-11 | 2019-09-17 | Mediatek Inc. | Semiconductor device capable of high-voltage operation |
| US10541328B2 (en) | 2016-03-11 | 2020-01-21 | Mediatek Inc. | Semiconductor device capable of high-voltage operation |
| CN112993018A (en)* | 2019-12-02 | 2021-06-18 | 吴俊鹏 | Method for reducing parasitic capacitance of III-V semiconductor device and III-V semiconductor device structure |
| CN113644129A (en)* | 2021-08-12 | 2021-11-12 | 电子科技大学 | A reverse resistance HEMT with stepped P-type GaN drain structure |
| US20220130985A1 (en)* | 2020-10-27 | 2022-04-28 | Cree, Inc. | Field effect transistor with enhanced reliability |
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| US11791385B2 (en) | 2005-03-11 | 2023-10-17 | Wolfspeed, Inc. | Wide bandgap transistors with gate-source field plates |
| US20230369480A1 (en)* | 2022-05-11 | 2023-11-16 | Taiwan Semiconductor Manufacturing Company | Electronic device employing two-dimensional electron gas with reduced leakage current |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| JP5866773B2 (en)* | 2011-02-25 | 2016-02-17 | 富士通株式会社 | Compound semiconductor device and manufacturing method thereof |
| CN104882483B (en)* | 2015-05-05 | 2018-06-26 | 西安电子科技大学 | Field-effect transistor with Γ grid and recess buffer layer and preparation method thereof |
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| CN106876323B (en)* | 2017-02-04 | 2019-08-30 | 智瑞佳（苏州）半导体科技有限公司 | A kind of power device and its manufacturing method |
| US12382699B2 (en) | 2022-06-07 | 2025-08-05 | Macom Technology Solutions Holdings, Inc. | Plasma-based barrier layer removal method for increasing peak transconductance while maintaining on-state resistance and related devices |
Citations (88)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4290077A (en)* | 1979-05-30 | 1981-09-15 | Xerox Corporation | High voltage MOSFET with inter-device isolation structure |
| US4551905A (en)* | 1982-12-09 | 1985-11-12 | Cornell Research Foundation, Inc. | Fabrication of metal lines for semiconductor devices |
| US4766474A (en)* | 1980-05-30 | 1988-08-23 | Sharp Kabushiki Kiasha | High voltage MOS transistor |
| US4876213A (en)* | 1988-10-31 | 1989-10-24 | Motorola, Inc. | Salicided source/drain structure |
| US4947232A (en)* | 1980-03-22 | 1990-08-07 | Sharp Kabushiki Kaisha | High voltage MOS transistor |
| US5053348A (en)* | 1989-12-01 | 1991-10-01 | Hughes Aircraft Company | Fabrication of self-aligned, t-gate hemt |
| US5187552A (en)* | 1979-03-28 | 1993-02-16 | Hendrickson Thomas E | Shielded field-effect transistor devices |
| US5192987A (en)* | 1991-05-17 | 1993-03-09 | Apa Optics, Inc. | High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions |
| US5196359A (en)* | 1988-06-30 | 1993-03-23 | Texas Instruments Incorporated | Method of forming heterostructure field effect transistor |
| US5290393A (en)* | 1991-01-31 | 1994-03-01 | Nichia Kagaku Kogyo K.K. | Crystal growth method for gallium nitride-based compound semiconductor |
| US5399886A (en)* | 1993-01-27 | 1995-03-21 | Fujitsu Limited | Heterojunction FET with a high potential barrier layer and gate structure |
| US5470767A (en)* | 1992-08-06 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Method of making field effect transistor |
| US5569937A (en)* | 1995-08-28 | 1996-10-29 | Motorola | High breakdown voltage silicon carbide transistor |
| US5643811A (en)* | 1993-01-07 | 1997-07-01 | Fujitsu Limited | Method of making field effect transistor for high-frequency operation |
| US5652179A (en)* | 1996-04-24 | 1997-07-29 | Watkins-Johnson Company | Method of fabricating sub-micron gate electrode by angle and direct evaporation |
| US5701019A (en)* | 1993-03-12 | 1997-12-23 | Hitachi, Ltd. | Semiconductor device having first and second stacked semiconductor layers, with electrical contact to the first semiconductor layer |
| US5710455A (en)* | 1996-07-29 | 1998-01-20 | Motorola | Lateral MOSFET with modified field plates and damage areas |
| US5780900A (en)* | 1996-01-26 | 1998-07-14 | Matsushita Electric Works, Inc. | Thin film silicon-on-insulator transistor having an improved power dissipation, a high break down voltage, and a low on resistance |
| US5885860A (en)* | 1995-06-30 | 1999-03-23 | Motorola, Inc. | Silicon carbide transistor and method |
| US5929467A (en)* | 1996-12-04 | 1999-07-27 | Sony Corporation | Field effect transistor with nitride compound |
| US5956590A (en)* | 1995-05-25 | 1999-09-21 | United Microelectronics Corp. | Process of forming a field effect transistor without spacer mask edge defects |
| US5959307A (en)* | 1995-11-06 | 1999-09-28 | Nichia Chemical Industries Ltd. | Nitride semiconductor device |
| US6033948A (en)* | 1995-12-02 | 2000-03-07 | Lg Semicon Co., Ltd. | Method of making high voltage metal oxide silicon field effect transistor |
| US6057564A (en)* | 1997-07-30 | 2000-05-02 | Kabushiki Kaisha Toshiba | Semiconductor device having a GaNO region intermediate a GaN-based contact region and an electrode |
| US6100571A (en)* | 1998-06-16 | 2000-08-08 | Nec Corporation | Fet having non-overlapping field control electrode between gate and drain |
| US6100549A (en)* | 1998-08-12 | 2000-08-08 | Motorola, Inc. | High breakdown voltage resurf HFET |
| US6127703A (en)* | 1999-08-31 | 2000-10-03 | Philips Electronics North America Corporation | Lateral thin-film silicon-on-insulator (SOI) PMOS device having a drain extension region |
| US6242766B1 (en)* | 1999-03-19 | 2001-06-05 | Fujitsu Quantum Devices Limited | High electron mobility transistor |
| US20010015442A1 (en)* | 1997-12-15 | 2001-08-23 | You Kondoh | Semiconductor light emitting device having a silver p-contact |
| US20010023964A1 (en)* | 2000-02-04 | 2001-09-27 | Yifeng Wu | Group III nitride based FETs and hemts with reduced trapping and method for producing the same |
| US6307232B1 (en)* | 1997-06-06 | 2001-10-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having lateral high breakdown voltage element |
| US6346451B1 (en)* | 1997-12-24 | 2002-02-12 | Philips Electronics North America Corporation | Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode |
| US20020017648A1 (en)* | 2000-06-29 | 2002-02-14 | Kensuke Kasahara | Semiconductor device |
| US6355951B1 (en)* | 1997-07-24 | 2002-03-12 | Mitsubishi Denki Kabushiki Kaisha | Field effect semiconductor device |
| US20020033508A1 (en)* | 2000-09-19 | 2002-03-21 | Hitachi, Ltd. | Semiconductor device and method for fabricating the same |
| US20020105028A1 (en)* | 1996-01-22 | 2002-08-08 | Tatsuhiko Fujihira | Semiconductor device |
| US6445038B1 (en)* | 1998-01-09 | 2002-09-03 | Infineon Technologies Ag | Silicon on insulator high-voltage switch |
| US20020137318A1 (en)* | 2001-03-23 | 2002-09-26 | Koninklijke Philips Electronics N.V. | Field effect transistor structure and method of manufacture |
| US20020139995A1 (en)* | 2001-03-27 | 2002-10-03 | Kaoru Inoue | Semiconductor device |
| US20020145172A1 (en)* | 2001-03-12 | 2002-10-10 | Naoto Fujishima | High withstand voltage semiconductor device |
| US6475857B1 (en)* | 2001-06-21 | 2002-11-05 | Samsung Electronics Co., Ltd. | Method of making a scalable two transistor memory device |
| US6483135B1 (en)* | 1998-09-22 | 2002-11-19 | Nec Compound Semiconductor Devices, Ltd. | Field effect transistor |
| US6495409B1 (en)* | 1999-01-26 | 2002-12-17 | Agere Systems Inc. | MOS transistor having aluminum nitride gate structure and method of manufacturing same |
| US20030075719A1 (en)* | 2001-10-24 | 2003-04-24 | Saptharishi Sriram | Delta doped silicon carbide metal-semiconductor field effect transistors and methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure |
| US6559513B1 (en)* | 2002-04-22 | 2003-05-06 | M/A-Com, Inc. | Field-plate MESFET |
| US6586813B2 (en)* | 2000-07-17 | 2003-07-01 | Fujitsu Quantum Devices Limited | High-speed compound semiconductor device operable at large output power with minimum leakage current |
| US20030132463A1 (en)* | 2002-01-08 | 2003-07-17 | Yosuke Miyoshi | Schottky gate field effect transistor |
| US6621121B2 (en)* | 1998-10-26 | 2003-09-16 | Silicon Semiconductor Corporation | Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes |
| US6620688B2 (en)* | 2001-12-12 | 2003-09-16 | Electronics And Telecommunications Research Institute | Method for fabricating an extended drain metal oxide semiconductor field effect transistor with a source field plate |
| US6624488B1 (en)* | 2000-08-07 | 2003-09-23 | Advanced Micro Devices, Inc. | Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices |
| US6627473B1 (en)* | 1999-11-16 | 2003-09-30 | Nec Compound Semiconductor Devices, Ltd. | Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof |
| US20030183886A1 (en)* | 2002-03-29 | 2003-10-02 | Fujitsu Quantum Devices Limited | Semiconductor device and method of fabricating the same |
| US6686616B1 (en)* | 2000-05-10 | 2004-02-03 | Cree, Inc. | Silicon carbide metal-semiconductor field effect transistors |
| US20040021152A1 (en)* | 2002-08-05 | 2004-02-05 | Chanh Nguyen | Ga/A1GaN Heterostructure Field Effect Transistor with dielectric recessed gate |
| US20040021175A1 (en)* | 2002-07-31 | 2004-02-05 | Motorola, Inc. | Field effect transistor and method of manufacturing same |
| US6690042B2 (en)* | 2000-09-27 | 2004-02-10 | Sensor Electronic Technology, Inc. | Metal oxide semiconductor heterostructure field effect transistor |
| US20040029330A1 (en)* | 2002-08-05 | 2004-02-12 | Tahir Hussain | Ohmic metal contact and channel protection in GaN devices using an encapsulation layer |
| US6740535B2 (en)* | 2002-07-29 | 2004-05-25 | International Business Machines Corporation | Enhanced T-gate structure for modulation doped field effect transistors |
| US20040124435A1 (en)* | 2002-12-27 | 2004-07-01 | General Electric Company | Homoepitaxial gallium-nitride-based electronic devices and method for producing same |
| US6787817B2 (en)* | 2002-03-06 | 2004-09-07 | Renesas Technology Corporation | Compound semiconductor having a doped layer between the gate and an ohmic contact of an active region |
| US20040227211A1 (en)* | 2003-05-16 | 2004-11-18 | Wataru Saito | Power semiconductor device used for power control |
| US6838325B2 (en)* | 2002-10-24 | 2005-01-04 | Raytheon Company | Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor |
| US20050051800A1 (en)* | 2003-09-09 | 2005-03-10 | Cree, Inc. | Cascode amplifier structures including wide bandgap field effect transistor with field plates |
| US20050051796A1 (en)* | 2003-09-09 | 2005-03-10 | Cree, Inc. | Wide bandgap transistor devices with field plates |
| US20050062069A1 (en)* | 2003-09-19 | 2005-03-24 | Wataru Saito | Power semiconductor device |
| US6891235B1 (en)* | 2000-11-15 | 2005-05-10 | International Business Machines Corporation | FET with T-shaped gate |
| US20050124100A1 (en)* | 2003-12-04 | 2005-06-09 | Robinson Kevin L. | Electronic device comprising enhancement mode pHEMT devices, depletion mode pHEMT devices, and power pHEMT devices on a single substrate and method of creation |
| US20050133818A1 (en)* | 2003-12-17 | 2005-06-23 | Johnson Jerry W. | Gallium nitride material devices including an electrode-defining layer and methods of forming the same |
| US6933544B2 (en)* | 2003-01-29 | 2005-08-23 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| US20050208722A1 (en)* | 2002-05-31 | 2005-09-22 | Koninklijke Phillips Electronics N.V. | Trench-gate semiconductor device and method of manufacturing |
| US20050253168A1 (en)* | 2004-05-11 | 2005-11-17 | Cree, Inc. | Wide bandgap transistors with multiple field plates |
| US20060006412A1 (en)* | 2002-02-22 | 2006-01-12 | Sharp Kabushiki Kaisha | Semiconductor substrate, method of manufacturing the same and semiconductor device |
| US20060006415A1 (en)* | 2004-05-11 | 2006-01-12 | Cree, Inc. | Wide bandgap HEMTs with source connected field plates |
| US20060011915A1 (en)* | 2004-07-14 | 2006-01-19 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
| US20060043416A1 (en)* | 2004-08-25 | 2006-03-02 | P Li Hsin-Hua | Recessed semiconductor device |
| US7012286B2 (en)* | 2001-09-27 | 2006-03-14 | Murata Manufacturing Co., Ltd. | Heterojunction field effect transistor |
| US20060081877A1 (en)* | 2004-10-14 | 2006-04-20 | Hitachi Cable, Ltd. | Semiconductor epitaxial wafer and field effect rtansistor |
| US7038252B2 (en)* | 2004-02-27 | 2006-05-02 | Kabushiki Kaisha Toshiba | Semiconductor device using a nitride semiconductor |
| US7041541B2 (en)* | 2002-05-11 | 2006-05-09 | United Monolithic Semiconductors Gmbh | Method for producing a semiconductor component, and semiconductor component produced by the same |
| US20060202272A1 (en)* | 2005-03-11 | 2006-09-14 | Cree, Inc. | Wide bandgap transistors with gate-source field plates |
| US20070102727A1 (en)* | 2005-11-02 | 2007-05-10 | Sharp Kabushiki Kaisha | Field-effect transistor |
| US7465967B2 (en)* | 2005-03-15 | 2008-12-16 | Cree, Inc. | Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions |
| US7800131B2 (en)* | 2005-06-10 | 2010-09-21 | Nec Corporation | Field effect transistor |
| US7812369B2 (en)* | 2003-09-09 | 2010-10-12 | The Regents Of The University Of California | Fabrication of single or multiple gate field plates |
| US20100314666A1 (en)* | 2009-06-11 | 2010-12-16 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
| US7863648B2 (en)* | 2005-06-10 | 2011-01-04 | Nec Corporation | Field effect transistor |
| US8120066B2 (en)* | 2006-10-04 | 2012-02-21 | Selex Sistemi Integrati S.P.A. | Single voltage supply pseudomorphic high electron mobility transistor (PHEMT) power device and process for manufacturing the same |
| US20120235156A1 (en)* | 2011-03-17 | 2012-09-20 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
Family Cites Families (109)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8103218A (en) | 1981-07-06 | 1983-02-01 | Philips Nv | FIELD-EFFECT TRANSISTOR WITH INSULATED HANDLEBAR ELECTRODE. |
| JPS62237763A (en) | 1986-04-08 | 1987-10-17 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JPS6387773A (en) | 1986-09-30 | 1988-04-19 | Nec Corp | Schottky barrier type field effect transistor |
| JPH035536A (en) | 1989-05-31 | 1991-01-11 | Sekisui Chem Co Ltd | Coupling structure for balcony unit |
| JPH0335536A (en) | 1989-06-30 | 1991-02-15 | Fujitsu Ltd | Field effect type semiconductor device |
| WO1992016966A1 (en) | 1991-03-18 | 1992-10-01 | Boston University | A method for the preparation and doping of highly insulating monocrystalline gallium nitride thin films |
| US5374843A (en) | 1991-05-06 | 1994-12-20 | Silinconix, Inc. | Lightly-doped drain MOSFET with improved breakdown characteristics |
| JPH0521793A (en) | 1991-07-09 | 1993-01-29 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| JP3188346B2 (en) | 1993-06-10 | 2001-07-16 | ローム株式会社 | Field effect transistor |
| JPH0738108A (en) | 1993-07-21 | 1995-02-07 | Nippon Telegr & Teleph Corp <Ntt> | MOS field effect transistor having field electrode layer |
| US5393993A (en) | 1993-12-13 | 1995-02-28 | Cree Research, Inc. | Buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices |
| JP2658860B2 (en) | 1993-12-20 | 1997-09-30 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| US5543253A (en) | 1994-08-08 | 1996-08-06 | Electronics & Telecommunications Research Inst. | Photomask for t-gate formation and process for fabricating the same |
| US5523589A (en) | 1994-09-20 | 1996-06-04 | Cree Research, Inc. | Vertical geometry light emitting diode with group III nitride active layer and extended lifetime |
| JP3051817B2 (en) | 1995-01-31 | 2000-06-12 | シャープ株式会社 | Method for manufacturing semiconductor device |
| US5739554A (en) | 1995-05-08 | 1998-04-14 | Cree Research, Inc. | Double heterojunction light emitting diode with gallium nitride active layer |
| JPH09232827A (en) | 1996-02-21 | 1997-09-05 | Oki Electric Ind Co Ltd | Semiconductor device and transmission / reception switching type antenna switch circuit |
| JPH118256A (en) | 1997-06-13 | 1999-01-12 | Oki Electric Ind Co Ltd | Manufacture of field-effect transistor |
| TW334632B (en) | 1997-07-24 | 1998-06-21 | Mitsubishi Electric Corp | Field effective semiconductor |
| US5898198A (en) | 1997-08-04 | 1999-04-27 | Spectrian | RF power device having voltage controlled linearity |
| JP3249446B2 (en) | 1997-09-18 | 2002-01-21 | 株式会社東芝 | Method for manufacturing field effect transistor |
| JP3127874B2 (en) | 1998-02-12 | 2001-01-29 | 日本電気株式会社 | Field effect transistor and method of manufacturing the same |
| JP3233207B2 (en) | 1998-03-20 | 2001-11-26 | 日本電気株式会社 | Method for manufacturing field effect transistor |
| JP3534624B2 (en) | 1998-05-01 | 2004-06-07 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
| KR100260075B1 (en) | 1998-06-02 | 2000-07-01 | 손욱 | Full conjugated electroluminescent polymers containing fluorinated aryl group and a process for producing the polymers |
| JP2000082671A (en) | 1998-06-26 | 2000-03-21 | Sony Corp | Nitride based iii-v compound semiconductor device and its manufacture |
| US6042975A (en) | 1998-07-08 | 2000-03-28 | Lucent Technologies Inc. | Alignment techniques for photolithography utilizing multiple photoresist layers |
| JP2000164926A (en) | 1998-11-24 | 2000-06-16 | Sony Corp | Selective etching method for compound semiconductor, selective etching method for nitride-based compound semiconductor, semiconductor device, and method for manufacturing semiconductor device |
| JP4182376B2 (en) | 1998-12-02 | 2008-11-19 | 富士通株式会社 | Semiconductor device |
| JP3497406B2 (en) | 1999-03-25 | 2004-02-16 | 株式会社クボタ | Paddy working machine |
| JP3438133B2 (en) | 1999-09-27 | 2003-08-18 | 富士通株式会社 | Field effect semiconductor device and method of manufacturing the same |
| JP2001160656A (en) | 1999-12-01 | 2001-06-12 | Sharp Corp | Nitride compound semiconductor device |
| US6639255B2 (en) | 1999-12-08 | 2003-10-28 | Matsushita Electric Industrial Co., Ltd. | GaN-based HFET having a surface-leakage reducing cap layer |
| JP2001189324A (en) | 1999-12-28 | 2001-07-10 | Ricoh Co Ltd | Semiconductor device |
| JP4198339B2 (en) | 2000-07-17 | 2008-12-17 | ユーディナデバイス株式会社 | Compound semiconductor device |
| JP2002118122A (en) | 2000-10-06 | 2002-04-19 | Nec Corp | Schottky gate field effect transistor |
| TWI288435B (en) | 2000-11-21 | 2007-10-11 | Matsushita Electric Industrial Co Ltd | Semiconductor device and equipment for communication system |
| US6548333B2 (en) | 2000-12-01 | 2003-04-15 | Cree, Inc. | Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment |
| US6791119B2 (en) | 2001-02-01 | 2004-09-14 | Cree, Inc. | Light emitting diodes including modifications for light extraction |
| US6468878B1 (en) | 2001-02-27 | 2002-10-22 | Koninklijke Philips Electronics N.V. | SOI LDMOS structure with improved switching characteristics |
| US7622322B2 (en) | 2001-03-23 | 2009-11-24 | Cornell Research Foundation, Inc. | Method of forming an AlN coated heterojunction field effect transistor |
| US6849882B2 (en) | 2001-05-11 | 2005-02-01 | Cree Inc. | Group-III nitride based high electron mobility transistor (HEMT) with barrier/spacer layer |
| JP3744381B2 (en) | 2001-05-17 | 2006-02-08 | 日本電気株式会社 | Field effect transistor |
| US7230284B2 (en) | 2001-07-24 | 2007-06-12 | Cree, Inc. | Insulating gate AlGaN/GaN HEMT |
| GB0122122D0 (en) | 2001-09-13 | 2001-10-31 | Koninkl Philips Electronics Nv | Trench-gate semiconductor devices and their manufacture |
| JP2003100775A (en) | 2001-09-20 | 2003-04-04 | Nec Compound Semiconductor Devices Ltd | Semiconductor device and manufacturing method thereof |
| AU2002339582A1 (en) | 2001-11-01 | 2003-05-12 | Koninklijke Philips Electronics N.V. | Lateral soi field-effect transistor |
| JP2003188189A (en) | 2001-12-20 | 2003-07-04 | Nec Compound Semiconductor Devices Ltd | Method for manufacturing semiconductor device |
| KR100438895B1 (en) | 2001-12-28 | 2004-07-02 | 한국전자통신연구원 | Pseudomorphic high electron mobility transistor power device and method for manufacturing the same |
| JP2003203923A (en) | 2002-01-10 | 2003-07-18 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| GB0202437D0 (en) | 2002-02-02 | 2002-03-20 | Koninkl Philips Electronics Nv | Cellular mosfet devices and their manufacture |
| DE10206739C1 (en) | 2002-02-18 | 2003-08-21 | Infineon Technologies Ag | transistor device |
| JP3908572B2 (en) | 2002-03-18 | 2007-04-25 | 株式会社東芝 | Semiconductor element |
| JP3705431B2 (en) | 2002-03-28 | 2005-10-12 | ユーディナデバイス株式会社 | Semiconductor device and manufacturing method thereof |
| US7253486B2 (en)* | 2002-07-31 | 2007-08-07 | Freescale Semiconductor, Inc. | Field plate transistor with reduced field plate resistance |
| TWI230978B (en) | 2003-01-17 | 2005-04-11 | Sanken Electric Co Ltd | Semiconductor device and the manufacturing method thereof |
| JP4077731B2 (en) | 2003-01-27 | 2008-04-23 | 富士通株式会社 | Compound semiconductor device and manufacturing method thereof |
| WO2004068590A1 (en) | 2003-01-29 | 2004-08-12 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| US9773877B2 (en) | 2004-05-13 | 2017-09-26 | Cree, Inc. | Wide bandgap field effect transistors with source connected field plates |
| JP2005340417A (en) | 2004-05-26 | 2005-12-08 | Mitsubishi Electric Corp | Heterojunction field effect semiconductor device |
| DE102005039564B4 (en) | 2004-09-02 | 2011-03-31 | Fuji Electric Systems Co., Ltd. | Method for producing a semiconductor device |
| US7312481B2 (en) | 2004-10-01 | 2007-12-25 | Texas Instruments Incorporated | Reliable high-voltage junction field effect transistor and method of manufacture therefor |
| US7709859B2 (en) | 2004-11-23 | 2010-05-04 | Cree, Inc. | Cap layers including aluminum nitride for nitride-based transistors |
| US7456443B2 (en) | 2004-11-23 | 2008-11-25 | Cree, Inc. | Transistors having buried n-type and p-type regions beneath the source region |
| US7161194B2 (en) | 2004-12-06 | 2007-01-09 | Cree, Inc. | High power density and/or linearity transistors |
| US7951316B2 (en) | 2005-04-05 | 2011-05-31 | Exxonmobil Chemical Patents Inc. | Process for pipe seal manufacture |
| US7385273B2 (en) | 2005-06-10 | 2008-06-10 | International Rectifier Corporation | Power semiconductor device |
| US7679111B2 (en) | 2005-09-16 | 2010-03-16 | International Rectifier Corporation | Termination structure for a power semiconductor device |
| US7566918B2 (en) | 2006-02-23 | 2009-07-28 | Cree, Inc. | Nitride based transistors for millimeter wave operation |
| JP5307973B2 (en) | 2006-02-24 | 2013-10-02 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device |
| US7388236B2 (en) | 2006-03-29 | 2008-06-17 | Cree, Inc. | High efficiency and/or high power density wide bandgap transistors |
| US7629627B2 (en) | 2006-04-18 | 2009-12-08 | University Of Massachusetts | Field effect transistor with independently biased gates |
| JP5065616B2 (en) | 2006-04-21 | 2012-11-07 | 株式会社東芝 | Nitride semiconductor device |
| JP5036233B2 (en) | 2006-07-06 | 2012-09-26 | シャープ株式会社 | Semiconductor switching element and semiconductor circuit device |
| JP4304198B2 (en) | 2006-09-15 | 2009-07-29 | 株式会社東芝 | Semiconductor device |
| US8823057B2 (en) | 2006-11-06 | 2014-09-02 | Cree, Inc. | Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices |
| EP1921669B1 (en) | 2006-11-13 | 2015-09-02 | Cree, Inc. | GaN based HEMTs with buried field plates |
| US7692263B2 (en) | 2006-11-21 | 2010-04-06 | Cree, Inc. | High voltage GaN transistors |
| US8212290B2 (en) | 2007-03-23 | 2012-07-03 | Cree, Inc. | High temperature performance capable gallium nitride transistor |
| US8502323B2 (en) | 2007-08-03 | 2013-08-06 | The Hong Kong University Of Science And Technology | Reliable normally-off III-nitride active device structures, and related methods and systems |
| US7915643B2 (en) | 2007-09-17 | 2011-03-29 | Transphorm Inc. | Enhancement mode gallium nitride power devices |
| US7985986B2 (en) | 2008-07-31 | 2011-07-26 | Cree, Inc. | Normally-off semiconductor devices |
| JP5597921B2 (en) | 2008-12-22 | 2014-10-01 | サンケン電気株式会社 | Semiconductor device |
| WO2010082272A1 (en) | 2009-01-16 | 2010-07-22 | 日本電気株式会社 | Semiconductor device and method for producing the same |
| US7884394B2 (en) | 2009-02-09 | 2011-02-08 | Transphorm Inc. | III-nitride devices and circuits |
| JP2010278333A (en) | 2009-05-29 | 2010-12-09 | Furukawa Electric Co Ltd:The | Semiconductor device and manufacturing method thereof |
| US20110241020A1 (en) | 2010-03-31 | 2011-10-06 | Triquint Semiconductor, Inc. | High electron mobility transistor with recessed barrier layer |
| JP5548909B2 (en) | 2010-04-23 | 2014-07-16 | 古河電気工業株式会社 | Nitride semiconductor device |
| JP5688556B2 (en) | 2010-05-25 | 2015-03-25 | パナソニックＩｐマネジメント株式会社 | Field effect transistor |
| US8445961B2 (en) | 2010-09-20 | 2013-05-21 | International Business Machines Corporation | Measuring floating body voltage in silicon-on-insulator (SOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) |
| US8860120B2 (en) | 2010-09-22 | 2014-10-14 | Nxp, B.V. | Field modulating plate and circuit |
| JP5845568B2 (en) | 2010-11-02 | 2016-01-20 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| WO2012063329A1 (en) | 2010-11-10 | 2012-05-18 | 三菱電機株式会社 | Semiconductor device, and method for producing semiconductor device |
| US20120175679A1 (en) | 2011-01-10 | 2012-07-12 | Fabio Alessio Marino | Single structure cascode device |
| JP5874173B2 (en) | 2011-02-25 | 2016-03-02 | 富士通株式会社 | Compound semiconductor device and manufacturing method thereof |
| US9024357B2 (en) | 2011-04-15 | 2015-05-05 | Stmicroelectronics S.R.L. | Method for manufacturing a HEMT transistor and corresponding HEMT transistor |
| ITTO20120675A1 (en) | 2011-08-01 | 2013-02-02 | Selex Sistemi Integrati Spa | PHEMT DEVICE FOR ENRICHMENT / EMPTYING AND ITS MANUFACTURING METHOD |
| US8901604B2 (en) | 2011-09-06 | 2014-12-02 | Transphorm Inc. | Semiconductor devices with guard rings |
| JP5591776B2 (en) | 2011-09-21 | 2014-09-17 | 株式会社東芝 | Nitride semiconductor device and circuit using the same |
| JP5908692B2 (en) | 2011-09-29 | 2016-04-26 | トランスフォーム・ジャパン株式会社 | Compound semiconductor device and manufacturing method thereof |
| JP2013157407A (en) | 2012-01-27 | 2013-08-15 | Fujitsu Semiconductor Ltd | Compound semiconductor device and manufacturing method of the same |
| US8975664B2 (en) | 2012-06-27 | 2015-03-10 | Triquint Semiconductor, Inc. | Group III-nitride transistor using a regrown structure |
| US9024324B2 (en) | 2012-09-05 | 2015-05-05 | Freescale Semiconductor, Inc. | GaN dual field plate device with single field plate metal |
| JP5949527B2 (en) | 2012-12-21 | 2016-07-06 | 富士通株式会社 | Semiconductor device and manufacturing method thereof, power supply device, and high-frequency amplifier |
| US8946779B2 (en) | 2013-02-26 | 2015-02-03 | Freescale Semiconductor, Inc. | MISHFET and Schottky device integration |
| US9425267B2 (en) | 2013-03-14 | 2016-08-23 | Freescale Semiconductor, Inc. | Transistor with charge enhanced field plate structure and method |
| JP6220161B2 (en) | 2013-06-03 | 2017-10-25 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| US9755059B2 (en) | 2013-06-09 | 2017-09-05 | Cree, Inc. | Cascode structures with GaN cap layers |
| US9679981B2 (en) | 2013-06-09 | 2017-06-13 | Cree, Inc. | Cascode structures for GaN HEMTs |
- 2004
- 2004-10-04USUS10/958,945patent/US9773877B2/ennot_activeExpired - Lifetime
- 2005
- 2005-04-21CACA2564955Apatent/CA2564955C/ennot_activeExpired - Lifetime
- 2005-04-21EPEP12171401Apatent/EP2515338A3/ennot_activeCeased
- 2005-04-21EPEP05756258.9Apatent/EP1754263B1/ennot_activeExpired - Lifetime
- 2005-04-21EPEP12171403.4Apatent/EP2515339B1/ennot_activeExpired - Lifetime
- 2005-04-21JPJP2007513167Apatent/JP5611509B2/ennot_activeExpired - Lifetime
- 2005-04-21KRKR1020067026207Apatent/KR101142555B1/ennot_activeExpired - Lifetime
- 2005-04-21WOPCT/US2005/013725patent/WO2005114747A2/enactiveApplication Filing
- 2005-04-21CNCN2005800148667Apatent/CN1998089B/ennot_activeExpired - Lifetime
- 2005-04-21AUAU2005246697Apatent/AU2005246697B2/ennot_activeExpired
- 2005-04-21BRBRPI0510960-4Apatent/BRPI0510960A/ennot_activeApplication Discontinuation
- 2005-05-09TWTW094114829Apatent/TWI452695B/ennot_activeIP Right Cessation
- 2005-05-09TWTW103120237Apatent/TWI620320B/ennot_activeIP Right Cessation
- 2005-05-09TWTW101131917Apatent/TWI502738B/ennot_activeIP Right Cessation
- 2014
- 2014-06-19JPJP2014126655Apatent/JP5982430B2/ennot_activeExpired - Lifetime
- 2017
- 2017-09-05USUS15/696,050patent/US11664429B2/ennot_activeExpired - Lifetime
Patent Citations (104)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5187552A (en)* | 1979-03-28 | 1993-02-16 | Hendrickson Thomas E | Shielded field-effect transistor devices |
| US4290077A (en)* | 1979-05-30 | 1981-09-15 | Xerox Corporation | High voltage MOSFET with inter-device isolation structure |
| US4947232A (en)* | 1980-03-22 | 1990-08-07 | Sharp Kabushiki Kaisha | High voltage MOS transistor |
| US4766474A (en)* | 1980-05-30 | 1988-08-23 | Sharp Kabushiki Kiasha | High voltage MOS transistor |
| US4551905A (en)* | 1982-12-09 | 1985-11-12 | Cornell Research Foundation, Inc. | Fabrication of metal lines for semiconductor devices |
| US5196359A (en)* | 1988-06-30 | 1993-03-23 | Texas Instruments Incorporated | Method of forming heterostructure field effect transistor |
| US4876213A (en)* | 1988-10-31 | 1989-10-24 | Motorola, Inc. | Salicided source/drain structure |
| US5053348A (en)* | 1989-12-01 | 1991-10-01 | Hughes Aircraft Company | Fabrication of self-aligned, t-gate hemt |
| US5290393A (en)* | 1991-01-31 | 1994-03-01 | Nichia Kagaku Kogyo K.K. | Crystal growth method for gallium nitride-based compound semiconductor |
| US5192987A (en)* | 1991-05-17 | 1993-03-09 | Apa Optics, Inc. | High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions |
| US5470767A (en)* | 1992-08-06 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Method of making field effect transistor |
| US5643811A (en)* | 1993-01-07 | 1997-07-01 | Fujitsu Limited | Method of making field effect transistor for high-frequency operation |
| US5399886A (en)* | 1993-01-27 | 1995-03-21 | Fujitsu Limited | Heterojunction FET with a high potential barrier layer and gate structure |
| US5701019A (en)* | 1993-03-12 | 1997-12-23 | Hitachi, Ltd. | Semiconductor device having first and second stacked semiconductor layers, with electrical contact to the first semiconductor layer |
| US5956590A (en)* | 1995-05-25 | 1999-09-21 | United Microelectronics Corp. | Process of forming a field effect transistor without spacer mask edge defects |
| US5885860A (en)* | 1995-06-30 | 1999-03-23 | Motorola, Inc. | Silicon carbide transistor and method |
| US5569937A (en)* | 1995-08-28 | 1996-10-29 | Motorola | High breakdown voltage silicon carbide transistor |
| US5959307A (en)* | 1995-11-06 | 1999-09-28 | Nichia Chemical Industries Ltd. | Nitride semiconductor device |
| US6033948A (en)* | 1995-12-02 | 2000-03-07 | Lg Semicon Co., Ltd. | Method of making high voltage metal oxide silicon field effect transistor |
| US20020105028A1 (en)* | 1996-01-22 | 2002-08-08 | Tatsuhiko Fujihira | Semiconductor device |
| US5780900A (en)* | 1996-01-26 | 1998-07-14 | Matsushita Electric Works, Inc. | Thin film silicon-on-insulator transistor having an improved power dissipation, a high break down voltage, and a low on resistance |
| US5652179A (en)* | 1996-04-24 | 1997-07-29 | Watkins-Johnson Company | Method of fabricating sub-micron gate electrode by angle and direct evaporation |
| US5710455A (en)* | 1996-07-29 | 1998-01-20 | Motorola | Lateral MOSFET with modified field plates and damage areas |
| US5929467A (en)* | 1996-12-04 | 1999-07-27 | Sony Corporation | Field effect transistor with nitride compound |
| US6140169A (en)* | 1996-12-04 | 2000-10-31 | Sony Corporation | Method for manufacturing field effect transistor |
| US6307232B1 (en)* | 1997-06-06 | 2001-10-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having lateral high breakdown voltage element |
| US6355951B1 (en)* | 1997-07-24 | 2002-03-12 | Mitsubishi Denki Kabushiki Kaisha | Field effect semiconductor device |
| US6057564A (en)* | 1997-07-30 | 2000-05-02 | Kabushiki Kaisha Toshiba | Semiconductor device having a GaNO region intermediate a GaN-based contact region and an electrode |
| US20010015442A1 (en)* | 1997-12-15 | 2001-08-23 | You Kondoh | Semiconductor light emitting device having a silver p-contact |
| US6346451B1 (en)* | 1997-12-24 | 2002-02-12 | Philips Electronics North America Corporation | Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode |
| US6445038B1 (en)* | 1998-01-09 | 2002-09-03 | Infineon Technologies Ag | Silicon on insulator high-voltage switch |
| US6100571A (en)* | 1998-06-16 | 2000-08-08 | Nec Corporation | Fet having non-overlapping field control electrode between gate and drain |
| US6100549A (en)* | 1998-08-12 | 2000-08-08 | Motorola, Inc. | High breakdown voltage resurf HFET |
| US6483135B1 (en)* | 1998-09-22 | 2002-11-19 | Nec Compound Semiconductor Devices, Ltd. | Field effect transistor |
| US20030006437A1 (en)* | 1998-09-22 | 2003-01-09 | Nec Corporation | Field effect transistor |
| US6621121B2 (en)* | 1998-10-26 | 2003-09-16 | Silicon Semiconductor Corporation | Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes |
| US6495409B1 (en)* | 1999-01-26 | 2002-12-17 | Agere Systems Inc. | MOS transistor having aluminum nitride gate structure and method of manufacturing same |
| US6242766B1 (en)* | 1999-03-19 | 2001-06-05 | Fujitsu Quantum Devices Limited | High electron mobility transistor |
| US6127703A (en)* | 1999-08-31 | 2000-10-03 | Philips Electronics North America Corporation | Lateral thin-film silicon-on-insulator (SOI) PMOS device having a drain extension region |
| US6627473B1 (en)* | 1999-11-16 | 2003-09-30 | Nec Compound Semiconductor Devices, Ltd. | Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof |
| US20010023964A1 (en)* | 2000-02-04 | 2001-09-27 | Yifeng Wu | Group III nitride based FETs and hemts with reduced trapping and method for producing the same |
| US6686616B1 (en)* | 2000-05-10 | 2004-02-03 | Cree, Inc. | Silicon carbide metal-semiconductor field effect transistors |
| US20020017648A1 (en)* | 2000-06-29 | 2002-02-14 | Kensuke Kasahara | Semiconductor device |
| US6586813B2 (en)* | 2000-07-17 | 2003-07-01 | Fujitsu Quantum Devices Limited | High-speed compound semiconductor device operable at large output power with minimum leakage current |
| US6624488B1 (en)* | 2000-08-07 | 2003-09-23 | Advanced Micro Devices, Inc. | Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices |
| US20020033508A1 (en)* | 2000-09-19 | 2002-03-21 | Hitachi, Ltd. | Semiconductor device and method for fabricating the same |
| US6707102B2 (en)* | 2000-09-19 | 2004-03-16 | Renesas Technology Corp. | Semiconductor device including an insulated gate type field effect transistor and method for fabricating the same |
| US6690042B2 (en)* | 2000-09-27 | 2004-02-10 | Sensor Electronic Technology, Inc. | Metal oxide semiconductor heterostructure field effect transistor |
| US6891235B1 (en)* | 2000-11-15 | 2005-05-10 | International Business Machines Corporation | FET with T-shaped gate |
| US7282423B2 (en)* | 2000-11-15 | 2007-10-16 | International Business Machines Corporation | Method of forming fet with T-shaped gate |
| US20020145172A1 (en)* | 2001-03-12 | 2002-10-10 | Naoto Fujishima | High withstand voltage semiconductor device |
| US20020137318A1 (en)* | 2001-03-23 | 2002-09-26 | Koninklijke Philips Electronics N.V. | Field effect transistor structure and method of manufacture |
| US20020139995A1 (en)* | 2001-03-27 | 2002-10-03 | Kaoru Inoue | Semiconductor device |
| US6475857B1 (en)* | 2001-06-21 | 2002-11-05 | Samsung Electronics Co., Ltd. | Method of making a scalable two transistor memory device |
| US7012286B2 (en)* | 2001-09-27 | 2006-03-14 | Murata Manufacturing Co., Ltd. | Heterojunction field effect transistor |
| US20030075719A1 (en)* | 2001-10-24 | 2003-04-24 | Saptharishi Sriram | Delta doped silicon carbide metal-semiconductor field effect transistors and methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure |
| US6902964B2 (en)* | 2001-10-24 | 2005-06-07 | Cree, Inc. | Methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure |
| US6620688B2 (en)* | 2001-12-12 | 2003-09-16 | Electronics And Telecommunications Research Institute | Method for fabricating an extended drain metal oxide semiconductor field effect transistor with a source field plate |
| US20030132463A1 (en)* | 2002-01-08 | 2003-07-17 | Yosuke Miyoshi | Schottky gate field effect transistor |
| US20060006412A1 (en)* | 2002-02-22 | 2006-01-12 | Sharp Kabushiki Kaisha | Semiconductor substrate, method of manufacturing the same and semiconductor device |
| US6787817B2 (en)* | 2002-03-06 | 2004-09-07 | Renesas Technology Corporation | Compound semiconductor having a doped layer between the gate and an ohmic contact of an active region |
| US20030183886A1 (en)* | 2002-03-29 | 2003-10-02 | Fujitsu Quantum Devices Limited | Semiconductor device and method of fabricating the same |
| US6559513B1 (en)* | 2002-04-22 | 2003-05-06 | M/A-Com, Inc. | Field-plate MESFET |
| US7041541B2 (en)* | 2002-05-11 | 2006-05-09 | United Monolithic Semiconductors Gmbh | Method for producing a semiconductor component, and semiconductor component produced by the same |
| US20050208722A1 (en)* | 2002-05-31 | 2005-09-22 | Koninklijke Phillips Electronics N.V. | Trench-gate semiconductor device and method of manufacturing |
| US6740535B2 (en)* | 2002-07-29 | 2004-05-25 | International Business Machines Corporation | Enhanced T-gate structure for modulation doped field effect transistors |
| US6972440B2 (en)* | 2002-07-29 | 2005-12-06 | International Business Machines Corporation | Enhanced T-gate structure for modulation doped field effect transistors |
| US6870219B2 (en)* | 2002-07-31 | 2005-03-22 | Motorola, Inc. | Field effect transistor and method of manufacturing same |
| US20040021175A1 (en)* | 2002-07-31 | 2004-02-05 | Motorola, Inc. | Field effect transistor and method of manufacturing same |
| US20040021152A1 (en)* | 2002-08-05 | 2004-02-05 | Chanh Nguyen | Ga/A1GaN Heterostructure Field Effect Transistor with dielectric recessed gate |
| US20040029330A1 (en)* | 2002-08-05 | 2004-02-12 | Tahir Hussain | Ohmic metal contact and channel protection in GaN devices using an encapsulation layer |
| US6838325B2 (en)* | 2002-10-24 | 2005-01-04 | Raytheon Company | Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor |
| US20040124435A1 (en)* | 2002-12-27 | 2004-07-01 | General Electric Company | Homoepitaxial gallium-nitride-based electronic devices and method for producing same |
| US6933544B2 (en)* | 2003-01-29 | 2005-08-23 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| US6940090B2 (en)* | 2003-05-16 | 2005-09-06 | Kabushiki Kaisha Toshiba | Wideband gap having a low on-resistance and having a high avalanche capability |
| US20040227211A1 (en)* | 2003-05-16 | 2004-11-18 | Wataru Saito | Power semiconductor device used for power control |
| US7126426B2 (en)* | 2003-09-09 | 2006-10-24 | Cree, Inc. | Cascode amplifier structures including wide bandgap field effect transistor with field plates |
| US7812369B2 (en)* | 2003-09-09 | 2010-10-12 | The Regents Of The University Of California | Fabrication of single or multiple gate field plates |
| US7501669B2 (en)* | 2003-09-09 | 2009-03-10 | Cree, Inc. | Wide bandgap transistor devices with field plates |
| US20050051800A1 (en)* | 2003-09-09 | 2005-03-10 | Cree, Inc. | Cascode amplifier structures including wide bandgap field effect transistor with field plates |
| US20120132959A1 (en)* | 2003-09-09 | 2012-05-31 | Cree, Inc. | Wide bandgap transistor devices with field plates |
| US20050051796A1 (en)* | 2003-09-09 | 2005-03-10 | Cree, Inc. | Wide bandgap transistor devices with field plates |
| US20050062069A1 (en)* | 2003-09-19 | 2005-03-24 | Wataru Saito | Power semiconductor device |
| US7075125B2 (en)* | 2003-09-19 | 2006-07-11 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| US20050124100A1 (en)* | 2003-12-04 | 2005-06-09 | Robinson Kevin L. | Electronic device comprising enhancement mode pHEMT devices, depletion mode pHEMT devices, and power pHEMT devices on a single substrate and method of creation |
| US20050133818A1 (en)* | 2003-12-17 | 2005-06-23 | Johnson Jerry W. | Gallium nitride material devices including an electrode-defining layer and methods of forming the same |
| US7071498B2 (en)* | 2003-12-17 | 2006-07-04 | Nitronex Corporation | Gallium nitride material devices including an electrode-defining layer and methods of forming the same |
| US7508015B2 (en)* | 2004-02-27 | 2009-03-24 | Kabushiki Kaisha Toshiba | Semiconductor device using a nitride semiconductor |
| US7038252B2 (en)* | 2004-02-27 | 2006-05-02 | Kabushiki Kaisha Toshiba | Semiconductor device using a nitride semiconductor |
| US20060006415A1 (en)* | 2004-05-11 | 2006-01-12 | Cree, Inc. | Wide bandgap HEMTs with source connected field plates |
| US20050253168A1 (en)* | 2004-05-11 | 2005-11-17 | Cree, Inc. | Wide bandgap transistors with multiple field plates |
| US7550783B2 (en)* | 2004-05-11 | 2009-06-23 | Cree, Inc. | Wide bandgap HEMTs with source connected field plates |
| US20060011915A1 (en)* | 2004-07-14 | 2006-01-19 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
| US7229903B2 (en)* | 2004-08-25 | 2007-06-12 | Freescale Semiconductor, Inc. | Recessed semiconductor device |
| US20060043416A1 (en)* | 2004-08-25 | 2006-03-02 | P Li Hsin-Hua | Recessed semiconductor device |
| US20060081877A1 (en)* | 2004-10-14 | 2006-04-20 | Hitachi Cable, Ltd. | Semiconductor epitaxial wafer and field effect rtansistor |
| US20060202272A1 (en)* | 2005-03-11 | 2006-09-14 | Cree, Inc. | Wide bandgap transistors with gate-source field plates |
| US7465967B2 (en)* | 2005-03-15 | 2008-12-16 | Cree, Inc. | Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions |
| US7800131B2 (en)* | 2005-06-10 | 2010-09-21 | Nec Corporation | Field effect transistor |
| US7863648B2 (en)* | 2005-06-10 | 2011-01-04 | Nec Corporation | Field effect transistor |
| US20070102727A1 (en)* | 2005-11-02 | 2007-05-10 | Sharp Kabushiki Kaisha | Field-effect transistor |
| US8120066B2 (en)* | 2006-10-04 | 2012-02-21 | Selex Sistemi Integrati S.P.A. | Single voltage supply pseudomorphic high electron mobility transistor (PHEMT) power device and process for manufacturing the same |
| US20100314666A1 (en)* | 2009-06-11 | 2010-12-16 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
| US20120235156A1 (en)* | 2011-03-17 | 2012-09-20 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
Cited By (55)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9397173B2 (en) | 2003-09-09 | 2016-07-19 | Cree, Inc. | Wide bandgap transistor devices with field plates |
| US8592867B2 (en)* | 2004-05-11 | 2013-11-26 | Cree, Inc. | Wide bandgap HEMTS with source connected field plates |
| US20110169054A1 (en)* | 2004-05-11 | 2011-07-14 | Cree, Inc. | Wide bandgap hemts with source connected field plates |
| US9773877B2 (en) | 2004-05-13 | 2017-09-26 | Cree, Inc. | Wide bandgap field effect transistors with source connected field plates |
| US11791385B2 (en) | 2005-03-11 | 2023-10-17 | Wolfspeed, Inc. | Wide bandgap transistors with gate-source field plates |
| US20090230429A1 (en)* | 2005-06-10 | 2009-09-17 | Nec Corporation | Field effect transistor |
| US20090230430A1 (en)* | 2005-06-10 | 2009-09-17 | Nec Corproration | Field effect transistor |
| US7800131B2 (en)* | 2005-06-10 | 2010-09-21 | Nec Corporation | Field effect transistor |
| US7863648B2 (en)* | 2005-06-10 | 2011-01-04 | Nec Corporation | Field effect transistor |
| US20100025737A1 (en)* | 2008-07-29 | 2010-02-04 | Nec Electronics Corporation | Field-effect transistor |
| US8164118B2 (en)* | 2008-12-26 | 2012-04-24 | Sanken Electric Co., Ltd. | Semiconductor device and its manufacturing method |
| US20100163930A1 (en)* | 2008-12-26 | 2010-07-01 | Nobuo Kaneko | Semiconductor device and its manufacturing method |
| US8232609B2 (en) | 2009-07-13 | 2012-07-31 | Mitsubishi Electric Corporation | Semiconductor device including field effect transistor with reduced electric field concentration |
| US20110006351A1 (en)* | 2009-07-13 | 2011-01-13 | Mitsubishi Electric Corporation | Semiconductor device |
| US20110291203A1 (en)* | 2010-05-31 | 2011-12-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US8530937B2 (en)* | 2010-11-19 | 2013-09-10 | Sanken Electric Co., Ltd. | Compound semiconductor device having insulation film with different film thicknesses beneath electrodes |
| US20120126287A1 (en)* | 2010-11-19 | 2012-05-24 | Sanken Electric Co., Ltd. | Compound semiconductor device having insulation film with different film thicknesses beneath electrodes |
| US9666664B2 (en) | 2012-09-28 | 2017-05-30 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
| US9679981B2 (en) | 2013-06-09 | 2017-06-13 | Cree, Inc. | Cascode structures for GaN HEMTs |
| US9847411B2 (en) | 2013-06-09 | 2017-12-19 | Cree, Inc. | Recessed field plate transistor structures |
| EP3522231A1 (en) | 2013-06-09 | 2019-08-07 | Cree, Inc. | Multi-gate transistor |
| TWI560877B (en)* | 2013-06-09 | 2016-12-01 | Cree Inc | Recessed field plate transistor structures |
| WO2014200643A1 (en) | 2013-06-09 | 2014-12-18 | Cree, Inc. | Cascode structures for gan hemts |
| TWI624945B (en)* | 2013-06-09 | 2018-05-21 | 科銳公司 | Recessed field plate transistor structure |
| WO2014200820A1 (en) | 2013-06-09 | 2014-12-18 | Cree, Inc | Cascode structures with gan cap layers |
| WO2014200753A2 (en) | 2013-06-09 | 2014-12-18 | Cree, Inc. | Recessed field plate transistor structures |
| US9755059B2 (en) | 2013-06-09 | 2017-09-05 | Cree, Inc. | Cascode structures with GaN cap layers |
| US10566429B2 (en)* | 2013-08-01 | 2020-02-18 | Dynax Semiconductor, Inc. | Semiconductor device and method of manufacturing the same |
| US20180026105A1 (en)* | 2013-08-01 | 2018-01-25 | Dynax Semiconductor, Inc. | Semiconductor device and method of manufacturing the same |
| US20160035422A1 (en)* | 2014-07-29 | 2016-02-04 | Macronix International Co., Ltd. | Transistor and circuit using same |
| US9466371B2 (en)* | 2014-07-29 | 2016-10-11 | Macronix International Co., Ltd. | Transistor and circuit using same |
| US9666569B2 (en)* | 2015-02-25 | 2017-05-30 | Electronics And Telecommunications Research Institute | Switch circuit of cascode type having high speed switching performance |
| US20160247792A1 (en)* | 2015-02-25 | 2016-08-25 | Electronics And Telecommunications Research Institute | Switch circuit of cascode type having high speed switching performance |
| CN106328523A (en)* | 2015-06-15 | 2017-01-11 | 北大方正集团有限公司 | Method of manufacturing radio-frequency lateral double-diffused MOS (Metal Oxide Semiconductor) device |
| US10879389B2 (en) | 2016-03-11 | 2020-12-29 | Mediatek Inc | Semiconductor device capable of high-voltage operation |
| US10541328B2 (en) | 2016-03-11 | 2020-01-21 | Mediatek Inc. | Semiconductor device capable of high-voltage operation |
| US10418480B2 (en)* | 2016-03-11 | 2019-09-17 | Mediatek Inc. | Semiconductor device capable of high-voltage operation |
| US10396166B2 (en) | 2016-03-11 | 2019-08-27 | Mediatek Inc. | Semiconductor device capable of high-voltage operation |
| CN109786233A (en)* | 2019-01-17 | 2019-05-21 | 中国电子科技集团公司第十三研究所 | The preparation method and power device of asymmetric surface slot field-effect transistor |
| CN112993018A (en)* | 2019-12-02 | 2021-06-18 | 吴俊鹏 | Method for reducing parasitic capacitance of III-V semiconductor device and III-V semiconductor device structure |
| US20220130985A1 (en)* | 2020-10-27 | 2022-04-28 | Cree, Inc. | Field effect transistor with enhanced reliability |
| US11502178B2 (en) | 2020-10-27 | 2022-11-15 | Wolfspeed, Inc. | Field effect transistor with at least partially recessed field plate |
| US12408403B2 (en) | 2020-10-27 | 2025-09-02 | Macom Technology Solutions Holdings, Inc. | Field effect transistor with stacked unit subcell structure |
| US11658234B2 (en)* | 2020-10-27 | 2023-05-23 | Wolfspeed, Inc. | Field effect transistor with enhanced reliability |
| US11749726B2 (en) | 2020-10-27 | 2023-09-05 | Wolfspeed, Inc. | Field effect transistor with source-connected field plate |
| US12266721B2 (en) | 2020-10-27 | 2025-04-01 | Wolfspeed, Inc. | Field effect transistor with multiple stepped field plate |
| EP4428926A2 (en) | 2020-10-27 | 2024-09-11 | Wolfspeed, Inc. | Field effect transistor with at least partially recessed field plate |
| US11869964B2 (en) | 2021-05-20 | 2024-01-09 | Wolfspeed, Inc. | Field effect transistors with modified access regions |
| US12402348B2 (en) | 2021-05-20 | 2025-08-26 | Wolfspeed, Inc. | Field effect transistor with selective channel layer doping |
| US11621672B2 (en) | 2021-08-05 | 2023-04-04 | Wolfspeed, Inc. | Compensation of trapping in field effect transistors |
| CN113644129A (en)* | 2021-08-12 | 2021-11-12 | 电子科技大学 | A reverse resistance HEMT with stepped P-type GaN drain structure |
| US12113114B2 (en) | 2021-10-22 | 2024-10-08 | Wolfspeed, Inc. | Transistor with ohmic contacts |
| US12438103B2 (en) | 2022-04-29 | 2025-10-07 | Wolfspeed, Inc. | Transistor including a discontinuous barrier layer |
| US20230369480A1 (en)* | 2022-05-11 | 2023-11-16 | Taiwan Semiconductor Manufacturing Company | Electronic device employing two-dimensional electron gas with reduced leakage current |
| US12176431B2 (en)* | 2022-05-11 | 2024-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electronic device employing two-dimensional electron gas with reduced leakage current |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2564955A1 (en) | 2005-12-01 |
| KR20070007967A (en) | 2007-01-16 |
| US9773877B2 (en) | 2017-09-26 |
| EP1754263B1 (en) | 2019-01-16 |
| JP2014209647A (en) | 2014-11-06 |
| TW201438227A (en) | 2014-10-01 |
| CA2564955C (en) | 2016-08-23 |
| EP2515338A2 (en) | 2012-10-24 |
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| US11664429B2 (en) | 2023-05-30 |
| TWI620320B (en) | 2018-04-01 |
| CN1998089A (en) | 2007-07-11 |
| TWI502738B (en) | 2015-10-01 |
| JP5982430B2 (en) | 2016-08-31 |
| JP5611509B2 (en) | 2014-10-22 |
| AU2005246697B2 (en) | 2011-04-28 |
| EP2515338A3 (en) | 2012-12-12 |
| TWI452695B (en) | 2014-09-11 |
| TW200620660A (en) | 2006-06-16 |
| EP2515339B1 (en) | 2021-03-10 |
| WO2005114747A3 (en) | 2006-06-01 |
| BRPI0510960A (en) | 2007-11-20 |
| CN1998089B (en) | 2010-09-01 |
| AU2005246697A1 (en) | 2005-12-01 |
| EP2515339A3 (en) | 2012-12-12 |
| US20170365670A1 (en) | 2017-12-21 |
| TW201301510A (en) | 2013-01-01 |
| EP1754263A2 (en) | 2007-02-21 |
| JP2007537596A (en) | 2007-12-20 |
| EP2515339A2 (en) | 2012-10-24 |
| KR101142555B1 (en) | 2012-05-08 |
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