US20050241954A1

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Info

Publication number: US20050241954A1
Application number: US10/960,271
Authority: US
Inventors: Keiichi Iwanami
Original assignee: Samsung Electro Mechanics Co Ltd
Current assignee: Samsung Electro Mechanics Co Ltd
Priority date: 2004-05-03
Filing date: 2004-10-07
Publication date: 2005-11-03
Also published as: CN1694603A; KR20050105849A; KR100632577B1; JP2005322868A

Abstract

Disclosed is an electrolytic gold plating method of a PCB, which includes (A) forming an electrolytic copper-plated layer, corresponding to a predetermined copper plating resist pattern, on a substrate, (B) forming an electrolytic gold-plated layer, corresponding to a predetermined gold plating resist pattern, on the substrate using an outer layer of the substrate as a first incoming line for electrolytic gold plating use, and (C) removing a portion of the outer layer of the substrate, on which the electrolytic copper-plated layer is not coated.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention pertains, in general, to an electrolytic gold plating method of a printed circuit board (PCB) and, in particular, to an electrolytic gold plating method of a PCB, in which a copper outer layer or an electroless copper-plated layer of a substrate is used as an incoming line for plating use to form an electrolytic gold-plated layer.

2. Description of the Prior Art

Generally, a process of mounting passive components, active integrated circuits, and the like on a PCB according to a wire bonding manner is classified into an electrolytic gold plating process and an electroless gold plating process.

In this regard, the electroless gold plating process has a disadvantage of a separation occurring at an interface between copper and nickel during a wire bonding process of the PCB, and thus, the electrolytic gold plating process is more frequently used than the electroless gold plating process. Unlike other processes of surface-treating the PCB without using electricity, the electrolytic gold plating process is advantageous in that an electrolytic gold-plated layer is thick, the productivity is relatively high, and a relatively high peel strength reliability is secured.

The electrolytic gold plating process may be classified into an electrolytic soft gold plating process and an electrolytic hard gold plating process. In this respect, the electrolytic soft gold plating process is applied to the wire bonding process of typical semiconductor package products because gold particles plated on the PCB are relatively large, porous, and have a relatively low density. On the other hand, the electrolytic hard gold plating process is applied to produce a contact terminal for a battery of a mobile phone because the gold particles plated on the PCB are densely arranged, and have a relatively high density and excellent strength.

In order to better understand the background of the present invention, a description will be given of the production of a conventional PCB, below.

FIGS. 1ato1kare sectional views illustrating the production of the conventional PCB, andFIG. 2 is a plan view of the conventional PCB produced according to a procedure ofFIGS. 1ato1k. At this time,FIGS. 1ato1kare the sectional views taken along the line a-a′ ofFIG. 2.

With reference toFIG. 1a, upper and lowercopper foil layers11bare coated on upper and lower sides of aninsulating resin layer11ato produce a copperclad laminate11.

Referring toFIG. 1b, a via hole (b) is formed through the copperclad laminate11 to electrically connect the upper and lowercopper foil layers11bto each other.

InFIG. 1c, an electroless copper plating process is conducted to allow an electric current to flow through the via hole (b), thereby forming an electroless copper-platedlayer12 on the upper and lowercopper foil layers11band a wall of the via hole (b).

Subsequently, an electrolytic copper plating process is conducted to form an electrolytic copper-platedlayer13 on the electroless copper-platedlayer12 plated on the upper and lowercopper foil layers11band the wall of the via hole (b) as shown inFIG. 1d. At this time, the electrolytic copper-platedlayer13 has excellent physical properties.

Coated on the electrolytic copper-platedlayer13, adry film20 is exposed and developed using a first artwork film, having a predetermined pattern printed thereon, to be patterned as shown inFIG. 1e. The pattern of the first artwork film may be exemplified by a circuit pattern, a land of the via hole (b), a wire bonding terminal pattern, and an incoming line pattern.

InFIG. 1f, the resultingcopper clad laminate11 is dipped in an etching solution to remove a portion of the upper and lowercopper foil layers11b, electroless copper-platedlayer12, and electrolytic copper-platedlayer13, which is not coated with the patterneddry film20. At this time, the patterneddry film20 acts as an etching resist.

Thedry film20 coated on the patternedcopper clad laminate11 is then removed as shown inFIG. 1g.

Subsequently, asolder resist14 is coated on the patterned copperclad laminate11, and preliminarily dried as shown inFIG. 1h.

Referring toFIG. 1i, asecond artwork film30, having a solder resist pattern printed thereon, is mounted on the solder resist14 coated on the patterned copperclad laminate11, exposed, and developed to cure a portion of the solder resist14 corresponding in position to the solder resist pattern of thesecond artwork film30.

After thesecond artwork film30 is removed from the patterned copperclad laminate11, a uncured portion of thesolder resist14 is removed from the patternedcopper clad laminate11 to construct the solder resist pattern on the patternedcopper clad laminate11 as shown inFIG. 1j.

InFIG. 1k, a wire bonding terminal, that is, an opening (c) of the solder resist pattern on the patternedcopper clad laminate11 is subjected to an electrolytic gold plating process to form the electrolytic gold-platedlayer15 on the patternedcopper clad laminate11.

Subsequently, an outer structure of the patternedcopper clad laminate11 is formed using a router or a power press to accomplish thePCB10 as shown inFIG. 2.

Conventionally, regardless of the circuit pattern,incoming lines16 for plating use had to be formed on thePCB10 to form the electrolytic gold-platedlayer15 as shown in the dotted ellipse ofFIG. 2.

With respect to this, theincoming lines16 are mostly removed in the course of forming the outer structure of the copperclad laminate11 using the router or power press, but a small portion of theincoming lines16 remains on thePCB10. Sometimes, a large portion of theincoming lines16 may not be removed but remain on thePCB10 according to a method of designing thePCB10.

In accordance with the recent trend of a functional improvement and a miniaturization of electronic products, demand for highly fine and integrated circuit patterns of the PCB10 are increasing. However, theincoming lines16 remaining on thePCB10 have no relation to the circuit pattern, thus limiting the degree of freedom in designing thePCB10.

As well, theincoming lines16 remaining on thePCB10 act as a conductor in a relatively high frequency environment caused by an increased data communication speed. Accordingly, theincoming lines16 act as a sort of antenna to bring about a parasitic inductance.

The parasitic inductance interferes with the electric signals of the circuit pattern to cause an impedance mismatching, which reduces the performances of the electronic products.

Furthermore, a signal to noise ratio of each electronic product is reduced due to the parasitic inductance, leading to the misoperation of the electronic product to reduce the reliability of the electronic product.

SUMMARY OF THE INVENTION

Therefore, the present invention has been made keeping in mind the above disadvantages occurring in the prior arts, and an object of the present invention is to provide an electrolytic gold plating method of a PCB without using a separate incoming line for plating use.

The above object can be accomplished by providing an electrolytic gold plating method of a printed circuit board, which includes (A) forming an electrolytic copper-plated layer, corresponding to a predetermined copper plating resist pattern, on a substrate, (B) forming an electrolytic gold-plated layer, corresponding to a predetermined gold plating resist pattern, on the substrate using an outer layer of the substrate as a first incoming line for electrolytic gold plating use, and (C) removing a portion of the outer layer of the substrate, on which the electrolytic copper-plated layer is not coated.

The electrolytic gold plating method may also include (D) forming a via hole through the substrate, and (E) forming an electroless copper-plated layer on the outer layer of the substrate and on a wall of the via hole, prior to the step of (A). At this time, the electroless copper-plated layer is used as the first incoming line in the step of (B).

Additionally, the step of (A) includes (A-1) coating a copper plating resist on the electroless copper-plated layer of the substrate, and exposing and developing the copper plating resist to form a predetermined copper plating resist pattern on the electroless copper-plated layer, (A-2) conducting an electrolytic copper plating process, using the outer layer and electroless copper-plated layer of the substrate as a second incoming line for electrolytic copper plating use, to form an electrolytic copper-plated layer, corresponding to the copper plating resist pattern, on the electroless copper-plated layer of the substrate, and (A-3) removing the copper plating resist.

The electrolytic gold plating method may also include (D) processing the outer layer of the substrate to be thin, prior to the step of (A).

In this regard, the copper plating resist includes a photosensitive material.

Further, the step of (B) includes (B-1) coating a gold plating resist on the electroless copper-plated layer of the substrate, and exposing and developing the gold plating resist to form a predetermined gold plating resist pattern on the electroless copper-plated layer, (B-2) conducting an electrolytic gold plating process, using the outer layer and electroless copper-plated layer of the substrate as the first incoming line, to form an electrolytic gold-plated layer, corresponding to the gold plating resist pattern, on the electroless copper-plated layer of the substrate, and (B-3) removing the gold plating resist.

The electrolytic gold plating method may also include (B-4) conducting an electrolytic nickel plating process, using the electroless copper-plated layer as a third incoming line for electrolytic nickel plating use, to form an electrolytic nickel-plated layer, corresponding to the gold plating resist pattern, on the electroless copper-plated layer of the substrate after the step of (B-1).

In this respect, the gold plating resist includes a photosensitive material.

Furthermore, the substrate is dipped in an etching solution capable of etching copper, but not gold, to remove a portion of the electroless copper-plated layer and the outer layer of the substrate, which is not coated with the electrolytic copper-plated layer, in the step of (C). At this time, the outer layer of the substrate is in contact with the electroless copper-plated layer.

As well, the step of (C) includes (C-1) coating an etching resist on the electroless copper-plated layer of the substrate, and exposing and developing the etching resist to form a predetermined etching resist pattern, which is not coated with the electrolytic copper-plated layer, on the electroless copper-plated layer of the substrate, (C-2) etching a portion of the electroless copper-plated layer and outer layer of the substrate, which is not coated with the etching resist pattern, and (C-3) removing the etching resist. At this time, the outer layer is in contact with the electroless copper-plated layer.

Furthermore, the etching resist includes a photosensitive material.

In addition, the substrate is dipped in an etching solution to remove a portion of the electroless copper-plated layer and the outer layer of the substrate, which is not coated with the electrolytic copper-plated layer, in the step of (C-2). At this time, the outer layer of the substrate is in contact with the electroless copper-plated layer.

Furthermore, a portion of the electroless copper-plated layer and the outer layer of the substrate, which is not coated with the electrolytic copper-plated layer, is etched through a plasma etching process in the step of (C-2). At this time, the outer layer of the substrate is in contact with the electroless copper-plated layer.

The electrolytic gold plating method may also include (D) coating a solder resist on a patterned substrate to form a predetermined solder resist pattern on the patterned substrate after the step of (C).

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIGS. 1ato1kare sectional views illustrating the production of a conventional PCB;

FIG. 2 is a plan view of the conventional PCB produced according to a procedure ofFIGS. 1ato1K;

FIGS. 3ato3kare sectional views illustrating the production of a PCB according to the first embodiment of the present invention;

FIG. 4 is a plan view of the PCB produced according to a procedure ofFIGS. 3ato3k; and

FIG. 5 is a plan view of a PCB according to the second embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference now should be made to the drawings, in which the same reference numerals are used throughout the different drawings to designate the same or similar components.

FIGS. 3ato3kare sectional views illustrating the production of a PCB according to the first embodiment of the present invention, andFIG. 4 is a plan view of the PCB produced according to a procedure ofFIGS. 3ato3k. At this time,FIGS. 3ato3kare sectional views taken along the line A-A′ ofFIG. 4.

With reference toFIG. 3a, copper foil layers112 are coated on both sides of an insulatingresin layer111 to fabricate asubstrate110, that is, a copper clad laminate. At this time, it is preferable that the copper foil layers112 be thinly coated on the insulatingresin layer111 in consideration of the fact that the copper foil layers112 are etched and removed in subsequent processes.

Referring toFIG. 3b, a via hole (B) is formed through the copper clad laminate to electrically connect upper and lower copper foil layers112 to each other.

In this regard, the via hole (B) is formed at a predetermined position of the copper clad laminate using a computer numerical control drill (CNC drill) or a laser beam.

The CNC drill is useful to form the via hole (B) through the double-sided PCB or to form a through hole through the multilayer PCB. After the via hole (B) or through hole is formed using the CNC drill, a deburring process is conducted to remove burrs of a copper foil generated in the course of drilling the copper clad laminate, and dust attached to a wall of the via hole (B) and to surfaces of the copper foil layers112. At this time, the surfaces of the copper foil layers112 become rough, thus improving an attachment force of copper to the copper foil layers112 in a copper plating process.

The laser beam is useful to form a micro via hole through the multilayer PCB. For example, the copper foil layers112 and the insulatingresin layer111 may be simultaneously holed by a yttrium aluminum garnet (YAG) laser beam, or the insulatingresin layer111 may be holed by a carbon dioxide laser beam after a portion of eachcopper foil layer112 corresponding in position to the via hole is etched.

Meanwhile, a portion of the insulatingresin layer111 of thesubstrate110 may be molten due to heat generated in the course of forming the via hole (B) to form a smear on the wall of the via hole (B). Accordingly, it is preferable that a desmear process be conducted after the via hole (B) is formed through the copper clad laminate so as to remove the smear on the wall of the via hole (B).

InFIG. 3c, an electroless copper plating process is conducted to form an electroless copper-platedlayer120 on the upper and lower copper foil layers112 and wall of the via hole (B) of thesubstrate110.

In this respect, the wall of the via hole (B) of thesubstrate110 is comprised of the insulatingresin layer111, and thus, it is impossible to conduct an electrolytic copper plating process directly after the via hole (B) is formed through the copper clad laminate. Accordingly, the electroless copper plating process is conducted prior to conducting the electrolytic copper plating process to electrically connect the upper and lower copper foil layers112 to each other through the via hole (B). In the electroless copper plating process, the insulatingresin layer111 is plated by copper without the actions of ions with electricity. In other words, the electroless copper plating process is achieved by the deposition of copper on the copper foil layers112, and the deposition of copper is promoted by a catalyst. In detail, the catalyst is attached to the surface of eachcopper foil layer112 so as to separate copper from a plating solution to deposit copper on thecopper foil layer112. Hence, the electroless copper plating process requires some pre-treating processes.

For example, the electroless copper plating process may include a degreasing step, a soft etching step, a pre-catalyst treating step, a catalyst treating step, an accelerator step, an electroless copper plating step, and an anti-oxidizing step.

In the degreasing step, oxides, impurities, oils and fats are removed from the surfaces of the copper foil layers112 using a solution containing acid or alkaline surfactants, and the resulting copper foil layers112 are rinsed to remove the solution therefrom.

The soft etching step makes the surfaces of the copper foil layers112 slightly rough (for example, a roughness of about 1-2 μm) to uniformly deposit copper particles on the copper foil layers112 and to remove contaminants, which are not removed in the degreasing step, from the copper foil layers112.

In the pre-catalyst treating step, thesubstrate110 is dipped in a dilute first catalyst-containing chemical to prevent a second catalyst-containing chemical used in the catalyst treating step from being contaminated by the impurities attached to thesubstrate110 or to prevent a concentration of the second catalyst-containing chemical from being changed due to the contaminants attached to thesubstrate110. Moreover, because thesubstrate110 is preliminarily dipped in the first chemical, having the same components as the second chemical, prior to treat thesubstrate110 using the second chemical, the treating of thesubstrate110 using the catalyst is more preferably achieved. At this time, it is preferable that 1-3% chemical be used in the pre-catalyst treating step.

In the catalyst treating step, catalyst powder is coated on the copper foil layers112 and insulating resin layer111 (the wall of the via hole (B)) of thesubstrate110. In this respect, the catalyst powder may be exemplified by Pd—Sn compound powder, and Pd₂⁻ dissociated from the Pd—Sn compound powder contributes to promoting the plating of thesubstrate110 in conjunction with Cu₂⁺ plated on thesubstrate110.

During the electroless copper plating step, it is preferable that the plating solution contain CuSO₄, HCHO, NaOH, and a stabilizer. At this time, it is important to control a composition of the plating solution because chemical reactions constituting the plating process of thesubstrate110 must maintain an equilibrium state in order to desirably conduct the plating process. Accordingly, it is necessary to properly replenish each component constituting the plating solution, mechanically agitate the plating solution, and smoothly operate a cycling system of the plating solution so as to desirably maintain the composition of the plating solution. Furthermore, it is necessary to use a filtering device to remove by-products, and the removal of the byproducts using the filtering device contributes to extending a life of the plating solution.

An anti-oxidizing layer is coated on thesubstrate110 to prevent copper from being oxidized due to alkaline components remaining on the copper clad laminate after the electroless copper plating step in the anti-oxidizing step.

However, the electroless copper-platedlayer120 has poorer physical properties than an electrolytic copper-plated layer. Therefore, it is preferable to thinly form the electroless copper-platedlayer120 on thesubstrate110.

Referring toFIG. 3d, adry film200 is coated on the electroless copper-platedlayer120, exposed and developed using an artwork film, having a predetermined pattern printed thereon, to be patterned. The pattern of theartwork film200 may be exemplified by a circuit pattern, a land of the via hole (B), and a wire bonding terminal pattern.

Thedry film200 includes three films: a cover film, a photoresist film, and a Mylar film. Of the three films, the photoresist film substantially acts as a resist layer against ultraviolet light.

After the artwork film with the predetermined pattern is mounted on thedry film200, the ultraviolet light is irradiated to the artwork film to expose and develop thedry film200. At this time, the ultraviolet light is not transmitted through a black portion of the artwork film, which corresponds to the pattern, but through a remaining portion of the artwork film, on which the pattern is not printed, to cure thedry film200 under the artwork film. The copper clad laminate on which the cureddry film200 is mounted is dipped in a developing solution to remove an uncured portion of thedry film200. In this regard, a remaining cured portion of thedry film200 forms a resist pattern. With respect to this, examples of the developing solution include a sodium carbonate (Na₂CO₃) aqueous solution and a potassium carbonate (K₂CO₃) aqueous solution.

With reference toFIG. 3e, thesubstrate110 on which the patterneddry film200 is mounted is subjected to the electrolytic copper plating process to form the electrolytic copper-platedlayer130 on the electroless copper-platedlayer120 formed on the upper and lower copper foil layers112 and wall of the via hole (B). In this regard, the patterneddry film200 is used as a plating resist, and the upper and lower copper foil layers112 of thesubstrate110 are used as incoming lines for an electrolytic copper plating process.

At this time, thesubstrate110 having the patterneddry film200 mounted thereon is dipped in the plating solution in a vessel, and subjected to the electrolytic copper plating process using a DC rectifier (direct current rectifier). In this respect, a proper amount of electricity is applied by the DC rectifier to thesubstrate110 based on a calculated area of thesubstrate110, which is to be plated with copper, thereby depositing copper on thesubstrate110 having the patterneddry film200 mounted thereon.

The electrolytic copper-platedlayer130 has superior physical properties to the electroless copper-platedlayer120, and it is easy to form the relatively thick electrolytic copper-platedlayer130 on the electroless copper-platedlayer120.

After the completion of the electrolytic copper plating process, thedry film200 is removed from thesubstrate110 as shown inFIG. 3f.

In this respect, a delaminating solution, such as sodium hydroxide (NaOH) and potassium hydroxide (KOH), is used to remove thedry film200 from thesubstrate110.

InFIGS. 3dto3f, thedry film200 is used as the plating resist, but a photosensitive liquid may be alternatively used as the plating resist. In the case of using the photosensitive liquid as the plating resist, the photosensitive liquid, which is to be exposed to the ultraviolet light, is coated on the electroless copper plated-layer120 plated on thesubstrate110, and then dried to form a photosensitive layer on the electroless copper-platedlayer120. Subsequently, the photosensitive layer is exposed and developed by the ultraviolet light using the patternedartwork film300 to be patterned. In this respect, the patterned photosensitive layer acts as the plating resist. Thesubstrate110 having the patterned photosensitive layer mounted thereon is then dipped in the plating solution in the vessel, and subjected to the electrolytic copper plating process using the DC rectifier to form the electrolytic copper-platedlayer130 on the electroless copper-platedlayer120 plated on the upper and lower copper foil layers112 and the wall of the via hole (B) of thesubstrate110. After the completion of the electrolytic copper plating process, the photosensitive layer is removed from thesubstrate110. Examples of a process of coating the photosensitive liquid on thesubstrate110 include a dip coating process, a roll coating process, and an electro-depositing process.

Referring toFIG. 3g, after a gold plating resist300 is coated on the electrolytic copper-platedlayer130, the gold plating resist300 is exposed and developed using an artwork film, having an electrolytic gold plating pattern printed thereon, to be patterned.

Thesubstrate110 is then subjected to an electrolytic gold plating process using the patterned gold plating resist300 to form an electrolytic gold-platedlayer150 on the electrolytic copper-platedlayer130 of thesubstrate110 as shown inFIG. 3h. Like in the case of the electrolytic copper plating process inFIG. 3e, the electrolytic gold plating process is conducted using the copper foil layers112 as the incoming lines, and thus, it is not necessary to form a separate incoming line in the electrolytic gold plating process.

Subsequently, thesubstrate110 having the electrolytic gold-platedlayer150 mounted thereon is dipped in the plating solution in the vessel, and then subjected to the electrolytic gold plating process using the DC rectifier. At this time, a proper intensity of electricity is applied by the DC rectifier to thesubstrate110 based on a calculated area of thesubstrate110, which is to be plated with gold, thereby depositing gold on the electrolytic copper-platedlayer130 of thesubstrate110.

Additionally, the electrolytic gold plating process may be conducted after nickel is thinly coated on the electrolytic copper-platedlayer130 so as to increase an attachment force of gold to the electrolytic copper-platedlayer130.

Subsequently, the gold plating resist300 is removed from thesubstrate110 as shown inFIG. 3i.

The gold plating resist300 used inFIGS. 3gto3imay be thedry film200 or photosensitive liquid inFIGS. 3dto3f.

With reference toFIG. 3j, a portion of the electroless copper-platedlayer120 and copper foil layers112, which is not coated with the electrolytic copper-platedlayer130, is removed from thesubstrate110 to pattern the copper clad laminate. At this time, the pattern of the copper clad laminate includes the circuit pattern, the land of the via hole (B), and the wire bonding terminal pattern.

With respect to this, the removal of the electroless copper-platedlayer120 and copper foil layers112 from thesubstrate110 may be conducted according to various processes.

In detail, according to one process, thesubstrate110 is dipped in an etching solution capable of etching the electroless copper-platedlayer120 and copper foil layers112 but not the electrolytic gold-platedlayer150. At this time, a portion of the electroless copper-platedlayer120 and copper foil layers112 is easily removed from thesubstrate110 because pre-treating processes are conducted so as to make the copper foil layers112 thin inFIG. 3aand the electroless copper-platedlayer120 is thinly formed on thesubstrate110. However, the circuit pattern, the land and wall of the via hole (B), or wire bonding terminal pattern include the thick electrolytic copper-platedlayer130 with excellent physical properties as well as the copper foil layers112 and electroless copper-platedlayer120. Accordingly, the copper foil layers112 and electroless and electrolytic copper-plated

layers

120,130 are insufficiently etched.

According to another process, an etching resist, such as thedry film200, is coated on the electroless copper-platedlayer120 of thesubstrate110, and is patterned so as to protect the circuit pattern, the land of the via hole (B), or the wire bonding terminal pattern. The resultingsubstrate110 is then dipped in the etching solution to remove a useless portion of the electroless copper-platedlayer120 and copper foil layers112.

According to the third process, the etching resist, such as thedry film200, is coated on the electroless copper-platedlayer120 of thesubstrate110, and is patterned so as to protect the circuit pattern, the land of the via hole (B), or the wire bonding terminal pattern. Subsequently, a useless portion of the electroless copper-platedlayer120 and copper foil layers112 of thesubstrate110 is removed according to a plasma etching process. In this respect, a side wall of the circuit pattern is precisely processed due to an anisotropic etching considered as an advantage of the plasma etching process.

Referring toFIG. 3k, a solder resist140 is coated on the patternedsubstrate110, and then patterned to form a solder resist pattern on the patternedsubstrate110.

A detailed description will be given of the formation of the solder resist pattern, below. The solder resist140 is coated on the patternedsubstrate110 and then preliminarily dried. At this time, examples of a process of coating the solder resist140 on the patternedsubstrate110 include a screen printing process, a roller coating process, a curtain coating process, and a spray coating process.

Subsequently, an artwork film having the solder resist pattern printed thereon is mounted on the patternedsubstrate110, exposed, and developed to cure a portion of the solder resist140 corresponding in position to the solder resist pattern. The artwork film and an uncured portion of the solder resist140 are sequentially removed to form the solder resist pattern on the patternedsubstrate110. The primarily cured solder resist140 is completely cured by the ultraviolet light and a drier, and a residue of the solder resist140, which is to be removed, and impurities are removed by a plasma.

An exterior structure of the copper clad laminate is then constructed using the router or the power press to accomplish thePCB100 as shown inFIG. 4.

With reference toFIG. 4, thePCB100 according to the present invention has no incoming lines as shown in a dotted ellipse. The reason for this is that the electroless copper-platedlayer120 is used as the incoming line for the electrolytic gold plating process and removed from thesubstrate110 after the completion of the electrolytic gold plating process.

As described above,FIGS. 3 and 4 illustrate the double-sided PCB, which is fabricated using the copper clad laminate as thesubstrate110. However, a single-sided PCB or a multilayer PCB may be fabricated according to the electrolytic gold plating process without using the incoming line, if necessary.

In the case of fabricating the multilayer PCB, a pattern including a ground circuit and a signal process circuit is formed on an inner layer of the multilayer PCB. At this time, a copper foil is attached to the inner layer using an insulator adhesive resin, such as prepreg, or resin coated copper (RCC) is laminated on the inner layer to form an outer layer. The outer layer is then subjected to the electrolytic gold plating process as shown inFIGS. 3ato3kto accomplish the multilayer PCB.

As shown inFIG. 5, thePCB100 according to the present invention is advantageous in that the circuit pattern may be additionally formed instead of the incoming line on a portion of the PCB corresponding to a dotted ellipse ofFIG. 5 because it is not necessary to form the incoming line in the course of designing the PCB. Therefore, the degree of freedom is increased in the course of designing the PCB, thereby highly integrating the circuit pattern on thePCB100′.

The present invention has been described in an illustrative manner, and it is to be understood that the terminology used is intended to be in the nature of description rather than of limitation. Many modifications and variations of the present invention are possible in light of the above teachings. Therefore, it is to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.

As apparent from the above description, the present invention provides an electrolytic gold plating method of a PCB without using an incoming line for plating use.

Therefore, the electrolytic gold plating method according to the present invention is advantageous in that a circuit pattern is formed instead of the incoming line on a portion of the PCB, on which the incoming line was positioned conventionally, thereby improving the degree of freedom in the course of designing the PCB.

Another advantage of the electrolytic gold plating method according to the present invention is that a parasitic inductance caused by the incoming line does not occur because the PCB of the present invention has no incoming line.

Furthermore, the PCB according to the present invention has no incoming line, and thus, the parasitic inductance does not occur, a signal to noise ratio of an electronic product, fabricated using the PCB of the present invention, is improved in a relatively high frequency environment, an impedance matching is easily accomplished, a sudden misoperation of the electronic product is prevented, and electric performances and reliability of the PCB are improved.

Claims

1. An electrolytic gold plating method of a printed circuit board, comprising:

(A) forming an electrolytic copper-plated layer, corresponding to a predetermined copper plating resist pattern, on a substrate;

(B) forming an electrolytic gold-plated layer, corresponding to a predetermined gold plating resist pattern, on the substrate using an outer layer of the substrate as a first incoming line for electrolytic gold plating use; and

(C) removing a portion of the outer layer of the substrate, on which the electrolytic copper-plated layer is not coated.

2. The electrolytic gold plating method as set forth inclaim 1, further comprising:

(D) forming a via hole through the substrate; and

(E) forming an electroless copper-plated layer on the outer layer of the substrate and on a wall of the via hole, prior to the step of (A), the electroless copper-plated layer being used as the first incoming line in the step of (B).

3. The electrolytic gold plating method as set forth inclaim 2, wherein the step of (A) comprises:

(A-1) coating a copper plating resist on the electroless copper-plated layer of the substrate, and exposing and developing the copper plating resist to form a predetermined copper plating resist pattern on the electroless copper-plated layer;

(A-2) conducting an electrolytic copper plating process, using the outer layer and electroless copper-plated layer of the substrate as a second incoming line for electrolytic copper plating use, to form an electrolytic copper-plated layer, corresponding to the copper plating resist pattern, on the electroless copper-plated layer of the substrate; and

(A-3) removing the copper plating resist.

4. The electrolytic gold plating method as set forth inclaim 2, further comprising:

(D) processing the outer layer of the substrate to be thin, prior to the step of (A).

5. The electrolytic gold plating method as set forth inclaim 3, wherein the copper plating resist includes a photosensitive material.

6. The electrolytic gold plating method as set forth inclaim 2, wherein the step of (B) comprises:

(B-1) coating a gold plating resist on the electroless copper-plated layer of the substrate, and exposing and developing the gold plating resist to form a predetermined gold plating resist pattern on the electroless copper-plated layer;

(B-2) conducting an electrolytic gold plating process, using the outer layer and electroless copper-plated layer of the substrate as the first incoming line, to form an electrolytic gold-plated layer, corresponding to the gold plating resist pattern, on the electroless copper-plated layer of the substrate; and

(B-3) removing the gold plating resist.

7. The electrolytic gold plating method as set forth inclaim 6, further comprising (B-4) conducting an electrolytic nickel plating process, using the electroless copper-plated layer as a third incoming line for electrolytic nickel plating use, to form an electrolytic nickel-plated layer, corresponding to the gold plating resist pattern, on the electroless copper-plated layer of the substrate after the step of (B-1).

8. The electrolytic gold plating method as set forth inclaim 6, wherein the gold plating resist includes a photosensitive material.

9. The electrolytic gold plating method as set forth inclaim 2, wherein the substrate is dipped in an etching solution capable of etching copper, but not gold, to remove a portion of the electroless copper-plated layer and the outer layer of the substrate, which is not coated with the electrolytic copper-plated layer, in the step of (C), the outer layer of the substrate being in contact with the electroless copper-plated layer.

10. The electrolytic gold plating method as set forth inclaim 2, wherein the step of (C) comprises:

(C-1) coating an etching resist on the electroless copper-plated layer of the substrate, and exposing and developing the etching resist to form a predetermined etching resist pattern, which is not coated with the electrolytic copper-plated layer, on the electroless copper-plated layer of the substrate;

(C-2) etching a portion of the electroless copper-plated layer and outer layer of the substrate, which is not coated with the etching resist pattern, the outer layer being in contact with the electroless copper-plated layer; and

(C-3) removing the etching resist.

11. The electrolytic gold plating method as set forth inclaim 10, wherein the etching resist includes a photosensitive material.

12. The electrolytic gold plating method as set forth inclaim 10, wherein the substrate is dipped in an etching solution to remove a portion of the electroless copper-plated layer and the outer layer of the substrate, which is not coated with the electrolytic copper-plated layer, in the step of (C-2), the outer layer of the substrate being in contact with the electroless copper-plated layer.

13. The electrolytic gold plating method as set forth inclaim 10, wherein a portion of the electroless copper-plated layer and the outer layer of the substrate, which is not coated with the electrolytic copper-plated layer, is etched through a plasma etching process in the step of (C-2), the outer layer of the substrate being in contact with the electroless copper-plated layer.

14. The electrolytic gold plating method as set forth inclaim 2, further comprising (D) coating a solder resist on a patterned substrate to form a predetermined solder resist pattern on the patterned substrate after the step of (C).