US20050186742A1 - Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same - Google Patents

Abstract

A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

Description

CLAIM OF PRIORITY
• The present application claims priority from Korean Patent Application No. 10-2004-0012371 filed on Feb. 24, 2004, the disclosure of which is hereby incorporated by reference herein in its entirety.
FIELD OF THE INVENTION
• The present invention relates to semiconductor devices, and more particularly, to field-effect transistors and methods for fabricating the same.
BACKGROUND OF THE INVENTION
• As semiconductor devices are scaled-down, a variety of operational and structural problems may result. For example, in field-effect transistors (FETs) having a planar channel region, problems may occur when the length of the channel region is reduced to 100 nm and below. More particularly, planar channel FETs may include gate electrodes that are formed on a planar channel region. Since an electric field at upper and lower portions of the channel may be asymmetrical, the capacity of the gate to control the channel may become deteriorated as channel length is decreased. In order to improve the control capacity of the gate with respect to the channel, double-gate field effect transistors and/or triple-gate field effect transistors have been developed. In double- and triple-gate field effect transistors, the gate electrode may be formed to be in contact with multiple sides of the channel. As such, a more symmetrical electric field may be applied to the channel, which may thereby improve the control capacity of the gate with respect to the channel. As a result, it may be possible to better suppress short channel effects.
• Double-gate fin field-effect transistors (FinFETs) are disclosed in U.S. Pat. No. 6,396,108 entitled “SELF-ALIGNED DOUBLE GATE SILICON-ON-INSULATOR (SOI) DEVICE”. FinFET devices may include a fin-shaped active region vertically protruding from a semiconductor substrate. Since the height of the fin may be greater than the thickness thereof, a conductive layer may be formed on the fin so as to form a gate electrode on an upper portion and sidewalls of the fin. However, in some instances, the shape of the fin may be altered due to over-etching of the fin when the gate electrode is formed.
• Furthermore, FinFET devices may be capable of driving relatively high current through the channel at two and/or three sides of the fin. Therefore, in order to improve the control capacity of the gate with respect to the channel, the width/thickness of the fin may reduced, and wider source/drain regions may be formed in order to output the high current.
SUMMARY OF THE INVENTION
• According to some embodiments of the present invention, a FinFET device may include a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode may be formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts may be formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode.
• In some embodiments, the channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.
• In other embodiments, the device may further include a gate insulation layer on the upper surface and sidewalls of the channel region between the gate electrode and the channel region to form a triple-gate FinFET device.
• In still other embodiments, the device may further include a capping insulation layer on the upper surface of the channel region between the gate electrode and the channel region to form a double-gate FinFET device. The channel region may be narrower than the capping insulation layer.
• In some embodiments, the device may include sidewall spacers on the first and second source/drain regions adjacent opposing sidewalls of the gate electrode. The gate electrode may include a lower gate electrode on the upper surface and sidewalls of the channel region and an upper gate electrode on the lower gate electrode. The sidewall spacers may include an upper sidewall spacer adjacent sidewalls of the upper gate electrode and a lower sidewall spacer adjacent sidewalls of the lower gate electrode.
• In other embodiments, the substrate may be a silicon-on-insulator substrate having a base layer, a buried insulation layer on the base layer, and a semiconductor layer on the buried insulation layer. The fin-shaped active region may vertically protrudes from the semiconductor layer.
• According to other embodiments of the present invention, a Fin FET device may include a semiconductor substrate, a fin-shaped active region vertically extending from the semiconductor substrate, and a device isolation layer adjacent sidewalls of the fin-shaped active region. The device may further include a gate electrode on an upper surface and sidewalls of the fin-shaped active region, sidewall spacers on sidewalls of the gate electrode, and source/drain regions in the fin-shaped active region at opposite sides of the gate electrode. Upper surfaces and sidewalls of the fin-shaped active region may be exposed at the source/drain regions.
• According to further embodiments of the present invention a method of forming a fin field-effect transistor may include forming a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode may be formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts may be formed at opposite sides of the gate electrode on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region.
• In some embodiments, the method may further include recessing the sidewalls of the channel region prior to forming the gate electrode such that the channel region is narrower than the first and second source/drain regions of the fin-shaped active region. In some embodiments, recessing the sidewalls of the channel region may include isotropically etching the sidewalls of the channel region to narrow the channel region. In other embodiments, recessing the sidewalls of the channel region may include thermally oxidizing the channel region to form an oxide layer on the upper surface and sidewalls of the channel region and removing the oxide layer to narrow the channel region.
• According to some embodiments of the present invention, a method of forming a FinFET may include forming a fin-shaped active region vertically protruding from a semiconductor substrate, and forming a device isolation layer on the fin-shaped active region. The device isolation layer may include a trench therein exposing a first portion of the fin-shaped active region including an upper surface and sidewalls thereof. A gate electrode may be formed in the trench on the upper surface and sidewalls of the first portion of the fin-shaped active region, and first and second source/drain regions may be formed in second portions of the fin-shaped active region at opposite sides of the gate electrode. The device isolation layer may be recessed at opposite sides of the gate electrode to expose upper surfaces and sidewalls of the second portions of the fin-shaped active region.
• In some embodiments, the method may further include forming first and second source/drain contacts on the respective first and second source/drain regions at the exposed upper surface and sidewalls of the second portions of the fin-shaped active region.
• In other embodiments, forming the first and second source/drain regions may include implanting dopants into the upper surfaces and sidewalls of the second portions of the fin-shaped active region after recessing the device isolation layer.
• In further embodiments, the method may further include implanting dopants into the first portion of the fin-shaped active region prior to forming the gate electrode to form a channel region therein.
• In some embodiments, the method may include recessing the sidewalls of the first portion of the fin-shaped active region before forming the gate electrode such that the first portion is narrower than the second portions of the fin-shaped active region.
• In other embodiments, forming the device isolation layer may include forming an insulation layer on the substrate including the fin-shaped active region and recessing the insulation layer by chemical-mechanical polishing to expose the upper surface of the fin-shaped active region. A mask pattern may be formed on the insulation layer and the upper surface of the fin-shaped active region. The mask pattern may include an opening therein exposing the upper surface of the first portion of the fin-shaped active region and a portion of the insulation layer. The exposed portion of the insulation layer may be etched to define a trench in the insulation layer and to expose the sidewalls of the first portion of the fin-shaped active region.
• In some embodiments, the method may further include forming a gate insulation layer on the upper surface and sidewalls of the first portion of the fin-shaped active region. Forming the gate electrode may include forming the gate electrode on the gate insulation layer to define a triple-gate FinFET device.
• In other embodiments, the method may further include forming a capping insulation layer on the upper surface of the first portion of the fin-shaped active region. Forming the gate electrode may include forming the gate electrode on the capping insulation layer on the upper surface and on the gate insulation layer on the sidewalls of the first portion of the fin-shaped active region to define a double-gate FinFET device.
• In further embodiments, the method may include forming sidewall spacers on the first and second source/drain regions adjacent opposing sidewalls of the gate electrode. Forming the gate electrode may include forming a lower gate electrode on the upper surface and sidewalls of the first portion of the fin-shaped active region and forming an upper gate electrode on the lower gate electrode. Forming the sidewall spacers may include forming upper sidewall spacers adjacent sidewalls of the upper gate electrode and forming lower sidewall spacers adjacent sidewalls of the lower gate electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1A is a plan view illustrating fin field-effect transistors (FinFETs) according to some embodiments of the present invention.
• FIG. 1B is a cross-sectional view taken along line I-I′ ofFIG. 1A.
• FIG. 1C is a cross-sectional view taken along line II-II′ ofFIG. 1A.
• FIGS. 2A to8A are plan views illustrating exemplary operations for fabricating FinFETs according to some embodiments of the present invention.
• FIGS. 2B to8B are cross-sectional views taken along line I-I′ ofFIGS. 2A to8A, respectively.
• FIGS. 2C to8C are cross-sectional views taken along line II-II′ ofFIGS. 2A to8A, respectively.
• FIG. 9A is a plan view illustrating FinFETs according to other embodiments of the present invention.
• FIG. 9B is a cross-sectional view taken along line I-I′ ofFIG. 9A.
• FIG. 9C is a cross-sectional view taken along line II-II′ ofFIG. 9A.
• FIG. 10A is a plan view illustrating FinFETs according to further embodiments of the present invention.
• FIG. 10B is a cross-sectional view taken along line III-III′ ofFIG. 10A.
• FIG. 10C is a cross-sectional view taken along line IV-IV′ ofFIG. 10A.
• FIGS. 11A to16A are plan views illustrating exemplary operations for fabricating FinFETs according to further embodiments of the present invention.
• FIGS. 11B to16B are cross-sectional views taken along line III-III′ ofFIGS. 1A to16A, respectively.
• FIGS. 11C to16C are cross-sectional views taken along line IV-IV′ ofFIGS. 11A to16A.
• FIG. 17A is a plan view illustrating other embodiments according to the present invention.
• FIG. 17B is a cross-sectional view taken along line I-I′ ofFIG. 17A.
• FIG. 17C is a cross-sectional view taken along line II-II′ ofFIG. 17A.
• FIG. 18A is a plan view illustrating still other embodiments according to the present invention.
• FIG. 18B is a cross-sectional view taken along line I-I′ ofFIG. 18A.
• FIG. 18C is a cross-sectional view taken along line II-II′ ofFIG. 18A.
• FIG. 19A is a plan view illustrating FinFETs according to still further embodiments of the present invention.
• FIG. 19B is a cross-sectional view taken along line V-V′ ofFIG. 19A.
• FIG. 19C is a cross-sectional view taken along line VI-VI′ ofFIG. 19A.
• FIGS. 20A to25A are plan views illustrating exemplary operations for forming FinFETs according to still further embodiment of the present invention.
• FIGS. 20B to25B are cross-sectional views taken along line V-V′ ofFIGS. 20A to25A, respectively.
• FIGS. 20C to25C are cross-sectional views taken along line VI-VI′ ofFIGS. 20A to25A, respectively.
• FIG. 26A is a plan view illustrating FinFETs according to further embodiments of the present invention.
• FIG. 26B is a cross-sectional view taken along line V-V′ ofFIG. 26A.
• FIG. 26C is a cross-sectional view taken along line VI-VI′ ofFIG. 26A.
• FIG. 27A is a plan view illustrating FinFETs according to other embodiments of the present invention.
• FIG. 27B is a cross-sectional view taken along line VII-VII′ ofFIG. 27A.
• FIG. 27C is a cross-sectional view taken along line VIII-VIII′ ofFIG. 27A.
• FIGS. 28A to32A are plan views illustrating exemplary operations for fabricating FinFETs according to other embodiments of the present invention.
• FIGS. 28B to32B are cross-sectional views taken along line VII-VII′ ofFIGS. 28A to32A, respectively.
• FIGS. 28C to32C are cross-sectional views taken along line VIII-VIII′ ofFIGS. 28A to32A, respectively.
• FIG. 33A is a plan view illustrating FinFETs according to further embodiments of the present invention.
• FIG. 33B is a cross-sectional view taken along line VII-VII′ ofFIG. 33A.
• FIG. 33C is a cross-sectional view taken along line VIII-VIII′ ofFIG. 33A.
• FIG. 34C is a plan view illustrating FinFETs according to still further embodiments of the present invention.
• FIG. 34B is a cross-sectional view taken along line VII-VII′ ofFIG. 34A.
• FIG. 34C is a cross-sectional view taken along line VIII-VIII′ ofFIG. 34A.
• FIG. 35A is a plan view illustrating FinFETs according to still other embodiments of the present invention.
• FIG. 35B is a cross-sectional view taken along line IX-IX′ ofFIG. 35A.
• FIG. 35C is a cross-sectional view taken along line X-X′ ofFIG. 35A.
• FIGS. 36A to39A are plan views illustrating exemplary operations for fabricating FinFETs according to still other embodiments of the present invention.
• FIGS. 36B to39B are cross-sectional views taken along line XI-XI′ ofFIGS. 36A to39A, respectively.
• FIGS. 36C to39C are cross-sectional views taken along line XI-XI′ ofFIGS. 36A to39A, respectively.
• FIG. 40A is a plan view illustrating further embodiments of the present invention.
• FIG. 40B is a cross-sectional view taken along line IX-IX′ ofFIG. 40A.
• FIG. 40C is a cross-sectional view taken along line X-X′ ofFIG. 40A.
• FIG. 41A is a plan view illustrating FinFETs according to yet still other embodiments of the present invention.
• FIG. 411B is a cross-sectional view taken along line XI-XI′ ofFIG. 41A.
• FIG. 41C is a cross-sectional view taken along line XII-XII′ ofFIG. 41A.
• FIGS. 42A to45A are plan views illustrating exemplary operations for fabricating FinFETs according to yet still other embodiments of the present invention.
• FIGS. 42B to45B are cross-sectional views taken along line XI-XI′ ofFIGS. 42A to45A, respectively.
• FIGS. 42C to45C are cross-sectional views taken along line XII-XII′ ofFIGS. 42A to45A, respectively.
• FIG. 46A is a plan view illustrating FinFETs according to further embodiments of the present invention.
• FIG. 46B is a cross-sectional view taken along line XI-XI′ ofFIG. 46A.
• FIG. 46C is a cross-sectional view taken along line XII-XII′ ofFIG. 46A.
• FIG. 47A is a plan view illustrating FinFETs according to still further embodiments of the present invention.
• FIG. 47B is a cross-sectional view taken along line XI-XI′ ofFIG. 47A.
• FIG. 47C is a cross-sectional view taken along line XII-XII′ ofFIG. 47A.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
• The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.
• It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
• It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
• Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
• The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
• Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
• Unless otherwise defined, all terms used in disclosing embodiments of the invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and are not necessarily limited to the specific definitions known at the time of the present invention being described. Accordingly, these terms can include equivalent terms that are created after such time. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.
• FIG. 1A is a plan view illustrating a fin field-effect transistor (FinFET) according to some embodiments of the present invention.FIG. 1B is a cross-sectional view taken along line I-I′ ofFIG. 1A.FIG. 1C is a cross-sectional view taken along line II-II′ ofFIG. 1A.
• Referring now toFIGS. 1A, 1B and1C, a fin-shapedactive region20 is formed vertically protruding from asemiconductor substrate10. Adevice isolation layer18 including agate groove26gcovers sidewalls of thefin20. The bottom of thegate groove26gis formed by a recesseddevice isolation layer18r. Agate electrode30gfills thegate groove26gand covers an upper portion and both sidewalls of thefin20. Acapping layer12cis positioned between thegate electrode30gand the upper portion of thefin20. Agate insulation layer28 is positioned between thegate electrode30gand each sidewall of thefin20 to form a double-gate structure. Asidewall spacer34 is formed at both sidewalls of thegate electrode30g. Source/drain regions32sand32dare formed in thefin20 at opposite sides of thegate electrode30g. Thedevice isolation layer18 is aligned with thesidewall spacer34 and recessed to form a recessedportion18b. As such, the sidewalls of thefin20 is partially exposed, and the surface of the source/drain regions32sand32dare exposed at the exposed sidewalls. Accordingly, the exposed surface of the source/drain regions32sand32dmay be greater than the thickness of thefin20 in a direction parallel to thegate electrode30g. In other words, the surface area of the exposed upper surface and sidewalls of the source/drain regions32sand32dmay be greater than the surface area provided by the upper surface alone, which is limited by the width of thefin20. Although not shown, source/drain contacts may be respectively formed on the source/drain regions32sand32d. The source/drain contacts may be in contact with the upper portion and the exposed sidewalls of thefin20 where the source/drain regions32sand32dare formed. In other words, even as fin width/thickness is scaled-down, the exposed source/drain regions32sand32dprovide a greater contact area for the source/drain contacts, i.e. at both sidewalls of thefin20 as well as at the upper surface. Accordingly, contact resistance may be reduced due to the greater contact surface area. Resistance may be further reduced by forming a silicide layer on the exposed surface of the source/drain regions32sand32dand thegate electrode30g.
• FIGS. 2A to8A are plan views illustrating exemplary operations for fabricating FinFETs according to some embodiments of the present invention.FIGS. 2B to8B are cross-sectional views taken along line I-I′ ofFIGS. 2A to8A.FIGS. 2C to8C are cross-sectional views taken along line II-II′ ofFIGS. 2A to8A.
• Referring now toFIGS. 2A, 2B and2C, ahard mask layer12 is formed on asemiconductor substrate10. Aphotoresist pattern14 for forming a fin is formed on thehard mask layer12. Referring toFIGS. 3A, 3B and3C, thehard mask layer12 and thesemiconductor substrate10 are patterned using thephotoresist pattern14 as an etching mask to define a fin-shapedactive region20 vertically protruding from thesubstrate10 and a device isolation region surrounding thefin20. Ahard mask pattern12pis formed on the upper portion of thefin20. Thephotoresist pattern14 is removed, and thesemiconductor substrate10 is patterned using thehard mask pattern12pas an etching mask. An insulation layer is then formed on an entire surface of thesemiconductor substrate10, filling thedevice isolation region18. The insulation layer is polished, such as by chemical mechanical polishing (CMP), to expose thehard mask pattern12pand form thedevice isolation layer18 in the device isolation region.
• Referring now toFIGS. 4A, 4B and4C, asacrificial layer22 is formed on thesubstrate10 including thedevice isolation layer18. Aphotoresist pattern24 having agate opening26 is then formed on thesacrificial layer22. Thegate opening26 crosses over a middle portion of thefin20. Thesacrificial layer22 may be formed of the same material as thehard mask layer12. In addition, thesacrificial layer22 may be formed of a layer having an etch selectivity with respect to thedevice isolation layer18. For example, thesacrificial layer22 may be an amorphous silicon layer and/or a polysilicon layer.
• A gate electrode covering the upper portion and both sidewalls of thefin20 is then formed using a damascene process, as described below.
• Referring toFIGS. 5A, 5B and5C, asacrificial pattern22pand a gate trench/groove26gare formed by etching thesacrificial layer22 and thedevice isolation layer18 using thephotoresist pattern24 as an etching mask. Thegate groove26gexposes both sidewalls of thefin20. As shown inFIG. 5B, a part of thehard mask pattern12pmay also be etched. Thegate groove26gis formed such that a portion of thedevice isolation layer18rremains at the bottom of thegate groove26g. A channel region may be formed in thefin20 by implanting impurities into the sidewalls of thefin20 exposed by thegate groove26. Thephotoresist pattern24 is then removed. Alternatively, thephotoresist pattern24 may be etched after forming thesacrificial pattern22p. In this case, thegate groove26gmay be formed using thesacrificial pattern22pas an etching mask.
• Referring toFIGS. 6A, 6B and6C, agate insulation layer28 is formed on a the sidewalls of thefin20 exposed by thegate groove26g. Aconductive layer30 is formed on an entire surface of thesubstrate10 including thegate insulation layer28, filling thegate groove26g. Theconductive layer30 may be formed of various conductive materials, such as a polysilicon layer, a polycide layer, and/or a metal layer.
• Referring toFIGS. 7A, 7B and7C, theconductive layer30 is recessed to form thegate electrode30gin thegate groove26g. Theconducive layer30 may be recessed by an etch-back process. Alternatively, theconductive layer30 may be recessed using chemical mechanical polishing (CMP). Thesacrificial pattern22pat both sides of thegate electrode30gis also removed to expose sidewalls of thegate electrode30g. If thesacrificial pattern22pis formed of a material having similar polishing and etching rates as compared to thegate electrode30g, thesacrificial pattern22pmay also be etched-back at the same time as theconductive layer30.
• Referring now toFIGS. 8A, 8B and8C, thehard mask pattern12pis etched using thegate electrode30gas an etching mask. Thehard mask pattern12pis removed to expose the upper portion of thefin20 at both sides of thegate electrode30g, but a portion of hard mask pattern remains between thegate electrode30gand thefin20 to form acapping layer12c. Source/drain regions32sand32dare respectively formed in thefin20 at both sides of thegate electrode30gby implanting impurities into thefin20 using the gate electrode as an ion implantation mask.Sidewall spacers34 are formed at both sidewalls of thegate electrode30g. The sidewall spacers34 cover the sidewalls of thegate electrode30gand thecapping layer12con the upper portion of thefin20. Additionally, thesidewalls spacers34 extend to cover the sidewalls of thegate electrode30galong the upper portion of thedevice isolation layer18.
• Thedevice isolation layer18 is then etched using thesidewall spacers34 and thegate electrode30gas an etching mask to expose sidewalls of thefin20 on opposite sides of the gate electrode, as shown inFIGS. 1A, 1B, and IC. Thedevice isolation layer18 is aligned with thesidewall spacer34 and recessed so that the sidewalls of thefin20 are exposed, thereby exposing source/drain regions32sand32dat the sidewalls of thefin20. Accordingly, the exposed surface area of the source/drain regions32sand32dcan be increased, thereby allowing for reduced contact resistance.
• The source/drain regions32sand32dmay be formed before or after thesidewall spacers34 are formed, as well as after recessing thedevice isolation layer18. The source/drain regions32sand32dmay be formed using an oblique ion implantation method. In addition, the surface area of the source/drain regions32sand32dto be exposed at the sidewalls of thefin20 may be adjusted by controlling the implantation depth. The surface area of the source/drain regions32sand32dmay also be adjusted based on the recessed depth of thedevice isolation layer18. However, oblique ion implantation may not be applicable prior to forming thesidewall spacers34, because the upper portion of thefin20 is exposed. As such, where a projection range Rp is used, ions may be diffused under thegate30gin a thermal annealing process to form a uniform ion profile. Accordingly, it may be possible to prevent ions from being diffused under thegate30gby controlling implantation depth, implanting ions by swiping implantation energy and applying rapid thermal annealing.
• After forming thesidewall spacers34, the distance between the ion implantation region and thegate30gis covered by thesidewall spacers34. Accordingly, after implanting ions in a projection range Rp, they may be thermally diffused. In other words, thespacers34 may prevent ions from being diffused under thegate30g. However, the same ion implantation method used before forming thesidewall spacer34 may also be used.
• As a further alternative, after thedevice isolation layer18 is recessed, source/drain regions32sand32dmay be formed using any of the above-mentioned methods.
• As a result, as shown inFIGS. 1A, 1B and1C, the source/drain regions32sand32dare exposed at sidewalls and at an upper surface of thefin20, so that the exposed surface area of the source/drain regions32sand32dcan be increased regardless of the width of thefin20. Accordingly, when respective source/drain contacts are formed and connected to the source/drain regions32sand32din subsequent processes, contact resistance can be reduced despite scale-down of thefin20 by electrically connecting the source/drain contacts with the exposed upper surface and sidewalls of the source/drain regions32sand32din thefin20.
• In addition, although not shown, a silicide layer may be further formed on the surface of the source/drain regions32sand32d, that is, on the exposed upper surface and sidewalls of thefin20. Also, the silicide layer may be further formed on the upper surface of thegate electrode30g.
• A transistor according to some embodiments of the present invention may be formed on a bulk substrate, as well as on a SOI (Silicon-On-Insulator, or Semiconductor-On-Insulator) substrate.FIG. 9A is a plan view illustrating FinFETs according to some embodiments of the present invention formed on a SOI substrate.FIG. 9B is a cross-sectional view taken along line I-I′ ofFIG. 9A.FIG. 9C is a cross-sectional view taken along line II-II′ ofFIG. 9A.
• Referring now toFIGS. 9A, 9B and9C, the SOI substrate comprises abase substrate10, a buriedinsulation layer11 formed on thebase substrate10 and a semiconductor layer on the buriedinsulation layer11. The semiconductor layer may be formed of silicon, silicon-germanium, or a graded silicon, where the lattice distance of silicon is increased. The semiconductor layer is patterned to form a vertically protrudingfin20 on the buriedinsulation layer11. Adevice isolation layer18 encloses sidewalls of thefin20. Thedevice isolation layer18 includes agate groove26g, which exposes a portion of thefin20. Agate electrode30gfills thegate groove26gand covers the upper portion and both sidewalls of thefin20 exposed by thegate groove26g. The bottom of thegate groove26gis composed of a recesseddevice isolation layer18r. Acapping layer12cis positioned between thegate electrode30gand the upper portion of thefin20, and agate insulation layer28 is positioned between thegate electrode30gand both sidewalls of thefin20 to form a double-gate structure.Sidewall spacers34 are formed at both sidewalls of thegate electrode30g. Source/drain regions32sand32dare formed in thefin20 at opposite sides of thegate electrode30g. Thedevice isolation layer18 is aligned with thesidewall spacers34 and recessed to form a recessedportion18b, or alternatively, to be removed completely. Accordingly, at least a portion of the sidewalls of thefin20 is exposed, thereby exposing the source/drain regions32sand32dat the exposed sidewalls. Therefore, the exposed surface of the source/drain regions32sand32dmay be greater than the thickness of thefin20. In other words, the surface area of the exposed upper surface and sidewalls of the source/drain regions32sand32dmay be greater than the surface area provided by the upper surface alone, which is limited by the width of thefin20. Although not shown, source/drain contacts may be respectively formed on the source/drain regions32sand32d, and thus may be in contact with the upper surface and the exposed sidewalls of thefin20. In other words, even as fin width/thickness is scaled-down, the exposed source/drain regions32sand32dprovide a greater contact area for the source/drain contacts, i.e. at both sidewalls of thefin20 as well as at the upper surface, thereby reducing resistance. In addition, if a silicide layer is formed on the exposed surface of the source/drain regions32sand32dand thegate electrode30g, resistance may be further reduced. The bottom of thegate groove26gmay be the recesseddevice isolation layer18r, which may be recessed to a greater extent than a peripheral region. However, if thedevice isolation layer18ris completely removed, the bottom of thegate groove26gmay be the buriedinsulation layer11.
• FIG. 10A is a plan view illustrating FinFETs according to further embodiments of the present invention.FIG. 10B is a cross-sectional view taken along line III-III′ ofFIG. 10A.FIG. 10C is a cross-sectional view taken along line IV-IV′ ofFIG. 10A.
• Referring now toFIGS. 10A, 10B and10C, a vertically protruding fin-shapedactive region60 is formed on asemiconductor substrate50. Adevice isolation layer58 including agate groove66gcovers sidewalls of thefin60. Agate electrode70gfills thegate groove66gand covers an upper portion and both sidewalls of thefin60. Acapping layer52cis positioned between thegate electrode70gand the upper portion of thefin60. Agate insulation layer68 is positioned between thegate electrode70gand each sidewall of thefin60 to define a double-gate structure.Sidewall spacers74 are formed at both sidewalls of thegate electrode70g. Source/drain regions72sand72dare respectively formed in thefin60 at opposite sides of thegate electrode70g. Thefin60 may therefore include a first portion covered by and/or under thegate electrode70gand a second portion where the source/drain regions72sand72dare formed. The portion covered by thegate electrode70gmay be self-aligned with thegate electrode70g, and may have a narrower width than the portion where the source/drain regions72sand72dare formed. A channel region is formed in thefin60 between the source/drain regions72sand72d, i.e. in the portion of thefin60 covered by thegate electrode70g. Accordingly, the channel region may also be self-aligned with thegate electrode70g. As such, the width of the source/drain regions72sand72dmay be greater than the width of the channel region, i.e. greater than the width of the portion of thefin60 covered by thegate electrode70gin a direction parallel to the gate electrode. In other words, even if the channel region in thefin60 is scaled-down, the portion of thefin60 where the source/drain regions72sand72dare formed may be increased in width, thereby providing an increased contact surface area and reduced resistance. In addition, resistance may be further reduced by forming a silicide layer on the exposed source/drain regions72sand72dand thegate electrode70g.
• FIGS. 11A to16A are plan views illustrating exemplary operations for fabricating FinFETs according to further embodiments of the present invention.FIGS. 11B to16B are cross-sectional views taken along line III-III′ ofFIGS. 11A to16A, respectively.FIGS. 11C to16C are cross-sectional views taken along line IV-IV′ ofFIGS. 11A to16A.
• Referring toFIGS. 11A, 11B and11C, ahard mask layer52 is formed on asemiconductor substrate50. Aphotoresist pattern54 is formed so as to form a fin on thehard mask layer52.
• Referring toFIGS. 12A, 12B and12C, thehard mask layer52 and thesemiconductor substrate50 are patterned using thephotoresist pattern54 as an etching mask to define afin60 vertically protruding from thesubstrate50 and a device isolation region. Ahard mask pattern52pis formed on an upper portion of thefin60. Thephotoresist pattern54 is removed. Alternatively, thephotoresist pattern54 may be removed after patterning only thehard mask pattern52p. In this case, thesemiconductor substrate50 may be patterned using thehard mask pattern52pas an etching mask. An insulation layer is then formed on an entire surface of thesemiconductor substrate50, filling the device isolation region. Then, the insulation layer is polished by CMP to expose thehard mask pattern52pand to form adevice isolation layer58 in the device isolation region.
• Referring toFIGS. 13A, 13B and13C, asacrificial layer62 is formed on a substrate where thedevice isolation layer58 is formed. Aphotoresist pattern64 having agate opening66 is formed on thesacrificial layer62. Thegate opening66 crosses over thefin60. Thesacrificial layer62 has an etch selectivity with respect to thedevice isolation layer58 and may be formed of the same material as thehard mask layer52. For example, thesacrificial layer62 may be formed of polysilicon or amorphous silicon.
• A gate electrode covering the upper portion and both sidewalls of thefin20 is then formed using a damascene process, as described below.
• Referring now toFIGS. 14A, 14B and14C, thesacrificial layer62 is etched using thephotoresist pattern64 as an etching mask to form agate groove66gand asacrificial pattern62p. Thegate groove66gexposes both sidewalls and an upper surface of thefin60. As shown inFIG. 14B, thehard mask pattern52pmay be partially etched. Thegate groove66gis formed to provide a trench in order to form a gate electrode surrounded by thedevice isolation layer58. Thephotoresist pattern64 is then removed. Alternatively, thephotoresist pattern64 may be removed after forming thesacrificial pattern62p.
• The sidewalls of thefin60 exposed by thegate groove66gare then recessed, thereby reducing the thickness of the portion of thefin60 exposed by thegate groove66g, i.e. the portion of thefin60 to be covered by the gate electrode. Thefin60 may be recessed using an isotropic etch process or by removing an oxide layer formed by thermal oxidation. Where isotropic etching is used, the sidewalls of thefin60 may be recessed by controlling the concentration of etchant and the etching time. The fin may be recessed at one side by forming a polymer at sidewalls of an etched portion. Alternatively, if a thermal oxidation layer is grown on an exposed surface of thefin60 by a thermal oxidation process and then removed, the thickness of thefin60 may be reduced based on the reaction to the oxidation process. After the sidewalls of thefin60 have been recessed, a channel region may be formed by implanting impurities into the exposed sidewalls of thefin60.
• Referring toFIGS. 15A, 15B and15C, agate insulation layer68 is formed on sidewalls of thefin60 exposed by thegate groove66g. Aconductive layer70 is formed on an entire surface of thesubstrate50, filling thegate groove66gwhere thegate insulation layer68 is formed. Theconductive layer70 may be formed of a variety of materials, based on a desired conductivity for a particular application. For example, theconductive layer70 may be a polysilicon layer, a polycide layer or a metal layer.
• Referring toFIGS. 16A, 16B and16C, theconductive layer70 is recessed to form agate electrode70gin thegate groove66g. Theconductive layer70 may be recessed by an etch-back process or CMP. Thesacrificial pattern62pis removed to expose sidewalls of thegate electrode70g. If theconductive layer70 is formed of the same material as thesacrificial pattern62p, thesacrificial layer62pmay be recessed during the etch-back or CMP process used to form thegate electrode70g.
• Although not shown, thehard mask pattern52pis etched using thegate electrode70gas an etching mask to form acapping layer52c, and impurities are implanted into the fin using thegate electrode70gas an ion implantation mask, so that source/drain regions72sand72dare formed in the fin at opposite sides of thegate electrode70g. As shown inFIGS. 10A, 10B, and10C,sidewall spacers74 may be formed at both sidewalls of thegate electrode70g. The portion of thefin60 where the source/drain regions72sand72dare formed may be wider and may thereby provide a greater surface area than the portion of thefin60 where the channel region is formed, i.e. the portion of thefin60 that is self-aligned with thegate electrode70g. Accordingly, despite reducing the thickness of thefin60 at the channel region, source/drain regions72sand72dwith reduced contact resistance may be formed.
• The source/drain regions72sand72dmay be formed before or after forming thesidewall spacers34. However, before forming thesidewall spacers34, the upper portion of thefin60 is exposed. As a result, oblique ion implantation may not be suitable. In this case, if a projection range Rp is used, ions may be diffused under agate70gin the course of a thermal annealing process to form a uniform ion profile. Therefore, it may be possible to prevent ions from being diffused under thegate70gby controlling implantation depth, implanting ions by swiping implantation energy or applying rapid thermal annealing.
• After forming thesidewall spacers34, the area between the ion implantation region and thegate70gis covered by thesidewall spacers34. At this time, ions may be thermally diffused after implanting ions in a projection range Rp. In other words, the area protected by thespacers34 may prevent ions from being diffused under thegate70g. However, the same ion implantation method used before forming thesidewall spacer34 may also be used.
• Although not shown, a silicide layer may also be formed on the exposed surface of the source/drain regions72sand72d. As such, the silicide layer may be formed on the exposed upper portion and sidewalls of thefin60. The silicide layer may be further formed on an upper surface of thegate electrode70g.
• FIGS. 17A, 17B and17C illustrate alternate embodiments according to the present invention. As described above, the width of thefin60 where source/drain regions72sand72dare formed is greater than the width of thefin60 where the channel region is formed. However, the sidewalls of the fin where the source/drain regions72sand72dare formed may be exposed, as similarly described above with reference toFIGS. 1A, 1B, and1C.
• Referring toFIGS. 17A, 17B and17C, thehard mask pattern52pis removed to expose an upper surface of thefin60 at both sides of thegate electrode70g. A portion of thehard mask pattern52premains between thegate electrode70gand thefin60 to form acapping layer52c. The sidewall spacers74 cover the sidewalls of thegate electrode70gand thecapping layer52cadjacent the upper portion of thefin60. In addition, thesidewall spacers74 cover the sidewalls of thegate electrode70gadjacent thedevice isolation layer58. Thedevice isolation layer58 is then etched using thesidewall spacers74 and thegate electrode70gas an etching mask, to expose sidewalls of thefin60. As thedevice isolation layer58 is aligned with thesidewall spacers74 and then recessed to expose sidewalls of thefin60, sidewalls of the source/drain regions72sand72dare thereby exposed. Accordingly, the exposed surface area of the source/drain regions72sand72dmay be increased. In some embodiments, the source/drain regions72sand72dmay be formed after recessing thedevice isolation layer58. As such, the source/drain regions72sand72dmay also be formed using an oblique ion implantation process. Furthermore, the surface area of the source/drain regions72sand72dmay be controlled based on the recessed depth of thedevice isolation layer58.
• FIG. 18A is a plan view illustrating FinFETs according to still other embodiments of the present invention formed on a SOI substrate.FIG. 18B is a cross-sectional view taken along line I-I′ ofFIG. 18A.FIG. 18C is a cross-sectional view taken along line II-II′ ofFIG. 18A.
• Referring now toFIGS. 18A, 18B and18C, a SOI substrate comprises abase substrate50, a buriedinsulation layer51 formed on thebase substrate50, and a semiconductor layer on the buriedinsulation layer51. The semiconductor layer may be formed of silicon, silicon-germanium, and/or graded silicon, where the lattice distance of silicon is increased. Thesemiconductor layer50 is patterned to form a vertically protruding fin-shapedactive region60 on the buriedinsulation layer51. Adevice isolation layer58 including agate groove66gcovers sidewalls of thefin60. Agate electrode70gfills thegate groove66gand covers an upper portion and both sidewalls of thefin60. Acapping layer52cis positioned between the gate electrode and the upper portion of the fin. Agate insulation layer68 is positioned between thegate electrode70gand both sidewalls of thefin60.Sidewall spacers74 are formed at both sidewalls of thegate electrode70g. Source/drain regions72sand72dare formed in thefin60 at opposite sides of thegate electrode70g. Thefin60 may include a first portion covered by and/or under thegate electrode70g, and a second portion where the source/drain regions72sand72dare formed. The portion covered by thegate electrode70gmay be self-aligned with thegate electrode70g, and may have narrower width than the portion where the source/drain regions72sand72dare formed. A channel region is formed in the portion of thefin60 covered by thegate electrode70g. Accordingly, the channel region is self-aligned with thegate electrode70g.
• The portion of thefin60 where the source/drain regions72sand72dare formed may be wider than the portion of thefin60 covered by thegate electrode70gin a direction parallel to thegate electrode70g. In other words, even if the portion of thefin60 including the channel region and covered by thegate electrode70gis scaled-down and/or recessed, the portion of thefin60 including the source/drain regions72sand72dmay have a greater thickness, and thus, provide a greater contact area for source/drain contacts to be formed in a subsequent step. As a result, contact resistance at the source/drain regions72sand72dmay be reduced. Resistance may be further reduced by forming a silicide layer on the surface of the source/drain regions72sand72dand thegate electrode70g. The bottom of thegate groove66gmay formed of the recesseddevice isolation layer18rrather than peripheral regions. However, if thedevice isolation layer58 is completely removed so as to expose the buriedinsulation layer51, the bottom of thegate groove66gmay be formed of the buriedinsulation layer51. In addition, the base of the source/drain regions72sand72dmay be the same height or higher than thegate electrode70gat sidewalls of thefin60, to prevent punch-through. Therefore, the source/drain regions72sand72dmay be in contact with the buriedinsulation layer51.
• FIG. 19A is a plan view illustrating FinFETs according to still further embodiments of the present invention.FIG. 19B is a cross-sectional view taken along line V-V′ ofFIG. 19A.FIG. 19C is a cross-sectional view taken along line VI-VI′ ofFIG. 19A.
• Referring toFIGS. 19A, 19B and19C, a fin-shaped active region is formed vertically protruding from asemiconductor substrate110. A device isolation layer including agate groove126gcovers sidewalls of thefin120. The bottom of the gate groove126gis formed of a recessedisolation layer118r. Agate electrode130gfills the gate groove126gand covers an upper portion and both sidewalls of thefin120. Agate insulation layer128 is positioned between thegate electrode130gand the upper portion and both sidewalls of thefin120. Unlike the embodiments ofFIGS. 1A, 1B, and1C, a channel region is formed at three surfaces of the fin120: at both sidewalls of thefin120 and at the upper portion of thefin120. As such, a triple-gate structure is formed on thefin120. Accordingly, in comparison with the embodiments ofFIGS. 1A, 1B, and1C, higher drain current can be achieved with the same fin width/thickness.Sidewall spacers134 are formed at both sidewalls of thegate electrode130g. Source/drain regions132sand132dare formed in thefin120 at opposite sides of thegate electrode130g. Thedevice isolation layer118 is aligned with thesidewall spacers134 and recessed to form a recesseddevice isolation layer118b. Accordingly, sidewalls of thefin120 are partially exposed, and as such, the surfaces of the source/drain regions132sand132dare exposed at the exposed sidewalls. Therefore, the exposed surfaces of the source/drain regions132sand132dmay be greater than the thickness of thefin120 in a direction parallel to thegate electrode130g. Although not shown, source/drain contacts may be respectively formed on the source/drain regions132sand132d. The source/drain contacts may in contact with the upper portion and the exposed sidewalls of the fin where the source/drain regions132sand132dare formed. In other words, even as fin width/thickness is scaled-down, the exposed source/drain regions132sand132dprovide a greater contact area for the source/drain contacts, i.e. at both sidewalls of thefin120 as well as at the upper surface of thefin120. As a result, contact resistance may be reduced due to the greater contact surface area. Resistance may be further reduced by forming a silicide layer on the exposed surfaces of the source/drain regions132sand132dand thegate electrode130g.
• FIGS. 20A to25A are plan views illustrating exemplary operations for forming FinFETs according to still further embodiment of the present invention.FIGS. 20B to25B are cross-sectional views taken along line V-V′ ofFIGS. 20A to25A.FIGS. 20C to25C are cross-sectional views taken along line VI-VI′ ofFIGS. 20A to25A.
• Referring toFIGS. 20A, 20B and20C, ahard mask layer112 is formed on asemiconductor substrate110. Aphotoresist pattern114 for forming a fin is formed on thehard mask layer112.
• Referring toFIGS. 21A, 21B and21C, thehard mask layer112 and thesemiconductor substrate110 are patterned using thephotoresist pattern114 as an etching mask to define a vertically protruding fin-shapedactive region120 and a device isolation region. Ahard mask pattern112pis formed on thefin120. Thephotoresist pattern114 is then removed. An insulation layer is formed on an entire surface of thesemiconductor substrate110, filling the device isolation region. Then, the insulation layer is polished by CMP to expose thehard mask pattern112pand form adevice isolation layer118 in the device isolation region.
• Aphotoresist pattern124 having agate opening126 is formed on thesubstrate110 including thedevice isolation layer118. Thegate opening126 crosses over thefin120. In some embodiments, a sacrificial layer may be formed on thesubstrate110 prior to forming thephotoresist pattern124. The sacrificial layer may be formed of the same material as thehard mask layer112.
• A gate electrode is then formed covering the upper portion and both sidewalls of thefin120 using a damascene process, as described below.
• Referring now toFIGS. 22A, 22B and22C, thedevice isolation layer118 is etched using thephotoresist pattern124 as an etching mask to form agate groove126g. Thegate groove126gexposes both sidewalls of thefin120. The portion of thehard mask pattern112pexposed by the gate groove126gis also removed, so that only a residualhard mask pattern112aremains at both sides of the gate groove126g. Thegate groove126gis formed such that a recesseddevice isolation layer118rremains bottom of the gate groove126g. A channel region may be formed by implanting impurities into the exposed sidewalls of thefin120. The channel region may also be formed by ion implantation after forming thefin120. Thephotoresist pattern124 is then removed.
• Referring toFIGS. 23A, 23B and23C, agate insulation layer128 is formed on an upper surface and on sidewalls of the portion of thefin120 exposed by the gate groove126g. Aconductive layer130 is then formed on an entire surface of asubstrate110, filling the gate groove126gwhere thegate insulation layer128 is formed. Theconductive layer130 may be formed of a variety of materials depending on a desired conductivity for a particular application. For example, theconductive layer130 may be a polysilicon layer, a polycide layer and/or a metal layer.
• Referring toFIGS. 24A, 24B and24C, theconductive layer130 is recessed to form agate electrode130gin the gate groove126g. Theconductive layer130 may be recessed by an etch-back process or a CMP process. The residualhard mask pattern112ais exposed at both sides of thegate electrode130g.
• Referring toFIGS. 25A, 25B and25C, the residualhard mask pattern112ais removed to expose sidewalls of thegate electrode130g. Impurities are implanted into thefin120 using thegate electrode130gas an ion implantation mask to respectively form source/drain regions132sand132din thefin120 at opposite sides of thegate electrode130g.Sidewall spacers134 are formed at both sidewalls of thegate electrode130g. The sidewall spacers134 cover sidewalls of thegate electrode130gat the upper portions of thefin120. The sidewalls of thegate electrode130gmay or may not be exposed at the upper portion of thedevice isolation layer118. As a result, thesidewall spacer134 may or may not be on the upper portion of thedevice isolation layer118.
• Thedevice isolation layer118 is then etched using thesidewall spacers134 and thegate electrode130gas an etching mask to expose sidewalls of thefin120. Thedevice isolation layer118 is aligned with thesidewall spacers134 and is recessed to expose sidewalls of thefin120. As such, the source/drain regions132sand132dare exposed at the exposed sidewalls of thefin120. Accordingly, the exposed surface area of the source/drain regions132sand132dmay be increased, thereby reducing contact resistance when source/drain contacts are formed in a subsequent step. In addition, the surface area of the source/drain regions132sand132dto be exposed may be controlled based on the recessed depth of thedevice isolation layer118.
• The source/drain regions132sand132dmay be formed before or after forming thesidewall spacers134. More specifically, before forming thesidewall spacers134, the upper portion of thefin120 may be exposed. As such, oblique ion implantation may not be suitable. In this case, if a projection range Rp is used, ions may be diffused under thegate130gin a thermal annealing process to form a uniform ion profile. Therefore, it may be possible to prevent ions from being diffused under thegate130gby controlling implantation depth, implanting ions by swiping implantation energy and by applying rapid thermal annealing.
• After forming thesidewall spacers134, the area between the ion implantation region and thegate130gis covered by thesidewall spacers134. As such, ions may be thermally diffused after ion implantation using a projection range Rp. In other words, ions may be prevented from being diffused under thegate130gby thespacers134. Alternatively, ion implantation may be performed using the same method as described above before forming thesidewall spacers134.
• Resultantly, as shown inFIGS. 18A, 18B and18C, even though the fin width/thickness is scaled-down, the source/drain regions132sand132dare exposed at sidewalls of thefin120. As a result, the exposed surface area of the source/drain regions132sand132dmay be increased. Accordingly, when source/drain contacts are respectively formed on the source/drain regions132sand132din a subsequent process, contact resistance can be reduced despite the decreased fin width/thickness. In other words, by electrically connecting the source/drain contacts with source/drain regions132sand132dexposed at both sidewalls and the upper portion of thefin120, contact resistance may be reduced.
• Also, although not shown, a silicide layer may be formed at the exposed upper portion and sidewalls of thefin120, i.e. on the exposed source/drain regions132sand132d. The silicide layer may be further formed on an upper portion of thegate electrode130g.
• FIG. 26A is a plan view illustrating FinFETs according to further embodiments of the present invention.FIG. 26B is a cross-sectional view taken along line V-V′ ofFIG. 26A.FIG. 26C is a cross-sectional view taken along line VI-VI′ ofFIG. 26A.
• Transistors according to some embodiments of the present invention may be formed on a bulk substrate as well as on a SOI (Silicon-On-Insulator, or Semiconductor-On-Insulator) substrate.
• Referring now toFIGS. 26A, 26B and26C, a SOI substrate comprises abase substrate110, a buriedinsulation layer111 formed on thebase substrate110 and a semiconductor layer on the buriedinsulation layer111. The semiconductor layer may be formed of silicon, silicon-germanium, or graded silicon, where the lattice distance of silicon is increased. The semiconductor layer is patterned to form a vertically protruding fin-shapedactive region120 on the buriedinsulation layer111. Adevice isolation layer118 including agate groove126gcovers sidewalls of thefin120. The bottom of the gate groove126gmay be formed of a recesseddevice isolation layer118r, or alternatively, the buriedinsulation layer111 if thedevice isolation layer118 is completely removed. Agate electrode130gfills the gate groove126gand covers an upper portion and both sidewalls of thefin120. Agate insulation layer128 is formed between thegate electrode130gand the upper portion and both sidewalls of thefin120.Sidewall spacers134 are formed at both sidewalls of thegate electrode130g. Source/drain regions132sand132dare respectively formed in thefin120 at opposite sides of thegate electrode130g. Thedevice isolation layer118 is aligned with thesidewall spacers134, and may be removed until the buriedinsulation layer111 is exposed. Accordingly, the sidewalls of thefin120 are partially exposed, and surfaces of the source/drain regions132sand132dare exposed at the exposed sidewalls. Therefore, the exposed surface area of the source/drain regions132sand132dmay be greater than the surface area of the upper surface of thefin120, which is limited by the thickness of thefin120 in a direction parallel to thegate electrode130g. Although not shown, source/drain contacts may be respectively formed on the source/drain regions132sand132d. As such, the source/drain contacts may be in contact with the upper portion and the exposed sidewalls of thefin120. In other words, even though the fin width/thickness is scaled-down, the source/drain contacts are connected to source/drain regions132sand132dat both the exposed sidewalls of thefin120 and at the upper surface of thefin120, thereby reducing resistance. Resistance may be further reduced by forming a silicide layer on the exposed surface of the source/drain regions132sand132dand thegate electrode130g. The bottom of the gate groove126gmay be formed by the recesseddevice isolation layer118rrather than peripheral regions, or alternatively, may be formed by the buriedinsulation layer111. The source/drain regions132sand132dmay be formed after recessing thedevice isolation layer118, such as by using oblique ion implantation.
• FIG. 27A is a plan view illustrating FinFETs according to other embodiments of the present invention.FIG. 27B is a cross-sectional view taken along line VII-VII′ ofFIG. 27A.FIG. 27C is a cross-sectional view taken along line VIII-VIII′ ofFIG. 27A.
• Referring now toFIGS. 27A, 27B and27C, a fin-shapedactive region160 is formed vertically protruding from asemiconductor substrate150. Adevice isolation layer158 including agate grove166gcovers sidewalls of thefin160. The bottom of the gate groove166gis formed by a recesseddevice isolation layer158r. Agate electrode170gfills the gate groove166gand covers the upper portion and both sidewalls of thefin160. Agate insulation layer168 is positioned between thegate electrode170gand the upper portion and both sidewalls of thefin160 to define a triple-gate structure.Sidewall spacers174 are formed at both sidewalls of thegate electrode170g. Source/drain regions172sand172dare respectively formed in thefin160 at both sidewalls of thegate electrode170g. Thefin160 may include a first portion covered by and/or under thegate electrode170g, and a second portion where the source/drain regions172sand172dare formed. The portion covered by thegate electrode170gmay be self-aligned with thegate electrode170g, and may have a narrower width than the portion where the source/drain regions172sand172dare formed. A channel region is formed at the portion of thefin160 covered by thegate electrode170g. Accordingly, the channel region is self-aligned with thegate electrode170g. The channel region is formed at the upper portion and both sidewalls of thefin160.
• As shown inFIGS. 27A, 27B and27C, the portion of thefin160 including the source/drain regions172sand172dmay have a greater width/thickness than the portion of thefin160 covered by thegate electrode170gin a direction parallel to thegate electrode170g. In other words, even though the portion of thefin160 including the channel region is scaled-down, the portion of thefin160 where the source/drain regions172sand172dare formed may have a greater width/thickness. Accordingly, contact resistance at the source/drain regions172sand172dmay be reduced. Resistance may be further reduced by forming a silicide layer on the exposed surfaces of thegate electrode170gand the source/drain regions172sand172d.
• FIGS. 28A to32A are plan views illustrating exemplary operations for fabricating FinFETs according to other embodiments of the present invention.FIGS. 28B to32B are cross-sectional views taken along line VII-VII′ ofFIGS. 28A to32A.FIGS. 28C to32C are cross-sectional views taken along line VIII-VIII′ ofFIGS. 28A to32A.
• Referring now toFIGS. 28A, 28B and28C, ahard mask layer152 is formed on asemiconductor substrate150. Aphotoresist pattern154 for forming a fin is formed on thehard mask layer152.
• Referring toFIGS. 29A, 29B and29C, thehard mask layer152 and thesemiconductor substrate150 are patterned using thephotoresist pattern154 as an etching mask to define a vertically protruding fin-shapedactive region160 and a device isolation region. Ahard mask pattern152pis formed over thefin160. Thephotoresist pattern154 is removed. Alternatively, thephotoresist pattern154 may be removed after forming thehard mask pattern152p, and thehard mask pattern152pmay be used as an etching mask. An insulation layer is formed on an entire surface of thesemiconductor substrate150, filling the device isolation region. The insulation layer is polished by CMP to expose thehard mask pattern152pand to form adevice isolation layer158 in the device isolation region. Aphotoresist pattern164 including agate opening166 is formed on asubstrate150 where thedevice isolation layer158 is formed. Thegate opening166 crosses over thefin160.
• A gate electrode covering the upper portion and both sidewalls of thefin160 is then formed using a damascene process, as described below.
• Referring toFIGS. 30A, 30B and30C, thehard mask pattern152pand thedevice isolation layer158 are etched using thephotoresist pattern164 as an etching mask to form agate groove166g. Thegate groove166gexposes both sidewalls of thefin160. As shown inFIG. 30B, a portion of thehard mask pattern152pexposed by the gate groove166gis removed to expose an upper portion of thefin160, leaving a residualhard mask pattern152aat both sides of the gate groove166g. Thephotoresist pattern164 is removed.
• The thickness of thefin160 is then reduced by recessing sidewalls of thefin160 which are exposed by the gate groove166g. The fin may be recessed using an isotropic etching process, or alternatively, by removing an oxide layer formed on thefin160 by a thermal oxidation process. A channel region may be formed in thefin160 by implanting impurities into the exposed sidewalls of thefin160.
• Referring toFIGS. 31A, 31B and31C, agate insulation layer168 is formed on the upper surface and sidewalls of thefin160 exposed by the gate groove166g. Aconductive layer170 is formed on an entire surface of asubstrate150 to fill the gate groove166gwhere thegate insulation layer168 is formed. Theconductive layer170 may be formed of a variety of materials, depending on the conductivity desired for a particular application. For example, theconductive layer170 may be formed of a polysilicon layer, a polycide layer, or a metal layer.
• Referring toFIGS. 32A, 32B and32C, theconductive layer170 is recessed to form agate electrode170gin the gate groove166g. Theconductive layer170 may be recessed by an etch-back process and/or by CMP.
• The residualhard mask pattern152aat both sides of thegate electrode170gis removed, andsidewall spacers174 and source/drain regions172sand172dare formed. As a result, as shown inFIGS. 27A, 27B and27C, a FinFET may be formed.
• More particularly, an upper surface of thefin160, as well as sidewalls thereof, are covered by thegate electrode170gto form a triple-gate transistor. Impurities are implanted into thefin160 using thegate electrode170gas an ion implantation mask to respectively form source/drain regions172sand172din the fin at opposite sides of thegate electrode170g.Sidewall spacers174 are formed at both sidewalls of thegate electrode170g. The sidewall spacers174 cover sidewalls of thegate electrode170gat an upper portion of thefin160. Where thegate electrode170gis formed on the upper portion of thedevice isolation layer158, thesidewall spacers174 are formed at sidewalls of thegate electrode170g. However, thegate electrode170gmay not be formed on the upper portion of thedevice isolation layer158, and as such, thesidewall spacers174 may not be formed on thedevice isolation layer158. As a result, as shown inFIGS. 27A, 27B and27C, even though the portion of thefin160 where source/drain regions172sand172dare formed have a greater width/thickness, the portion of thefin160 including the channel region and self-aligned with thegate electrode170 may be scaled-down. Accordingly, the source/drain regions172sand172dmay have a lower contact resistance due to the greater area, despite the reduction in width/thickness of thefin160 at the channel region.
• The source/drain regions172sand172dmay be formed before or after forming thesidewall spacers174. More specifically, before forming thesidewall spacers174, an upper surface of thefin160 may be exposed, such that oblique ion implantation may not be suitable. In this case, if a projection range Rp is used, ions may be diffused under thegate170gin a thermal annealing process to form a uniform ion profile. Therefore, it may be possible to prevent ions from being diffused under thegate170gby controlling implantation depth, implanting ions by swiping ion energy, and applying rapid thermal annealing.
• After forming thesidewall spacers174, the area between the ion implantation region and thegate170gis covered by thesidewall spacers174. Accordingly, after implanting ions using the projection range Rp, ions may be thermally diffused. In other words, thespacers174 may prevent ions from being diffused under thegate170g. However, the same ion implantation method used before forming thesidewall spacers174 may also be used.
• Also, although not shown, a silicide layer may be formed on the source/drain regions172sand172d, that is, on the exposed upper portion and sidewalls of thefin160. In addition, the silicide layer may be formed on the upper portion of thegate electrode170g.
• FIGS. 33A, 33B and33C illustrate FinFETs according to further embodiments of the present invention.
• Referring now toFIGS. 33A, 33B and33C, thedevice isolation layer158 is etched using thesidewall spacers174 and thegate electrode170gas an etching mask to expose sidewalls of thefin160. Thedevice isolation layer158 is aligned with thesidewall spacers174, and is recessed to expose sidewalls of thefin160. The source/drain regions172sand172dare thereby exposed at the exposed sidewalls of thefin160. Accordingly, the exposed surface area of the source/drain regions172sand172dmay be increased, thereby decreasing contact resistance. In addition, the surface area of the source/drain regions172sand172dto be exposed may be controlled based on a recessed depth of thedevice isolation layer158. The source/drain regions172sand172dmay be formed after recessing thedevice isolation layer158, such as by ion implantation.
• FIG. 34C is a plan view illustrating FinFETs formed on an SOI substrate according to still further embodiments of the present invention.FIG. 34B is a cross-sectional view taken along line VII-VII′ ofFIG. 34A.FIG. 34C is a cross-sectional view taken along line VIII-VIII′ ofFIG. 34A.
• Referring toFIGS. 34A, 34B and34C, a SOI substrate comprises abase substrate150, a buriedinsulation layer151 formed on thebase substrate150 and a semiconductor layer on the buriedinsulation layer151. The semiconductor layer may be formed of silicon, silicon-germanium or graded silicon, where the lattice distance is increased. The semiconductor layer is patterned to form a vertically protruding fin-shapedactive region160 on the buriedinsulation layer151. Adevice isolation layer158 including agate groove166gcovers sidewalls of thefin160. The bottom of the gate groove166gmay be formed of a recesseddevice isolation layer158r, or alternatively, the buriedinsulation layer151. Agate electrode170gfills the gate groove166gand covers the upper portion and both sidewalls of thefin160. Agate insulation layer168 is formed between thegate electrode170gand the upper portion and both sidewalls of thefin160.Sidewall spacers174 are formed at both sidewalls of thegate electrode170g. Source/drain regions172sand172dare respectively formed in thefin160 at opposite sides of thegate electrode170g. Thefin160 may be include a first portion covered by and/or under thegate electrode170g, and a second portion where the source/drain regions172sand172dare formed. The portion covered by thegate electrode170gmay be self-aligned with thegate electrode170g, and may have a narrower width/thickness in comparison with the portion of thefin160 where the source/drain regions172sand172dare formed. A channel region is formed on thegate electrode170g. Accordingly, the channel region is self-aligned with thegate electrode170g. The width/thickness of the portion of thefin160 including the source/drain regions172sand172dmay be wider than the width/thickness of the portion of thefin160 covered by thegate electrode170gin a direction parallel to thegate electrode170g. In other words, even if the portion of thefin160 including the channel region is scaled-down and/or otherwise recessed, the portion of thefin160 where the source/drain regions172sand172dare formed may have a greater width/thickness. As a result, contact resistance at the source/drain regions172sand172dmay be reduced due to the greater contact surface area. In addition, resistance may be further reduced by forming a silicide layer on the source/drain regions172sand172dand thegate electrode170g. The bottom of the gate groove166gmay be formed by a recesseddevice isolation layer158rrather than by peripheral regions, or alternatively, may be formed by the buriedinsulation layer151. As described above, thedevice isolation layer158 is aligned with thesidewall spacers174 and is recessed to form the recesseddevice isolation layer158r. Alternatively, thedevice isolation layer118 may be aligned with thesidewall spacer134 and completely removed to expose the buriedinsulation layer111 at the bottom of the gate groove166g.
• FIG. 35A is a plan view illustrating FinFETs according to still other embodiments of the present invention.FIG. 35B is a cross-sectional view taken along line IX-IX′ ofFIG. 35A.FIG. 35C is a cross-sectional view taken along line X-X′ ofFIG. 35A.
• Referring now toFIGS. 35A, 35B and35C, a fin-shapedactive region220 is formed vertically protruding from asemiconductor substrate210. Adevice isolation layer218 including agate groove226gcovers sidewalls of thefin220. A gate electrode fills the gate groove226gand covers an upper portion and both sidewalls of thefin220. The bottom of the gate groove226gis formed by a recesseddevice isolation layer218r. The gate electrode includes alower gate pattern229 and anupper gate pattern230g. Thelower gate pattern229 is fills the gate groove226gto cover the sidewalls and the upper portion of thefin220. Theupper gate pattern230gis formed on thelower gate pattern229. Agate insulation layer228 is formed betweenlower gate pattern229 and the upper portion and both sidewalls of thefin220 to define a triple-gate structure. As such, a channel region may be formed at both sidewalls and the upper portion of thefin220. Sidewall spacers are formed at both sidewalls of the gate electrode. Source/drain regions232sand232dare respectively formed in thefin220 at opposite sides of the gate electrode. The sidewall spacers includelower sidewall spacers222bformed at sidewalls of thelower gate pattern229 andupper sidewall spacers234 formed at sidewalls of theupper gate pattern230g.
• Thedevice isolation layer118 is aligned with the upper andlower sidewall spacers222band234 and is recessed to partially expose the sidewalls of thefin220. As such, surfaces of the source/drain regions232sand232dare exposed at the exposed sidewalls of thefin220. Therefore, the exposed surface area of the source/drain regions232sand232d(including both sidewalls and the upper surface of the fin220) may be greater than the surface area of the upper surface of thefin220 alone, which is limited by the width/thickness of thefin220 in a direction parallel to the gate electrode. Although not shown, source/drain contacts may be respectively formed on the source/drain regions232sand232d. As such, the source/drain contacts may be in contact with both the upper portion and the exposed sidewalls of thefin220 at the source/drain regions232sand232d. In other words, even though thefin220 may be scaled-down, the exposed source/drain regions232sand232dprovide a greater contact area for the source/drain contacts, thereby reducing resistance. In addition, resistance may be further reduced by forming a silicide layer on the source/drain regions232sand232dand the gate electrode.
• FIGS. 36A to39A are plan views illustrating exemplary operations for fabricating FinFETs according to still other embodiments of the present invention.FIGS. 36B to39B are cross-sectional views taken along line XI-XI′ ofFIGS. 36A to39A.FIGS. 36C to39C are cross-sectional views taken along line XI-XI′ ofFIGS. 36A to39A.
• Referring now toFIGS. 36A, 36B and36C, a hard mask layer is formed on asemiconductor substrate210. The hard mask layer and the semiconductor substrate are patterned to define a vertically protruding fin-shapedactive region220 and a device isolation region. An insulation layer is formed on an entire surface of thesemiconductor substrate210, filling the device isolation region. The insulation layer is polished by CMP to form adevice isolation layer218 in the device isolation region. Aninsulation layer222 used as a gate mask is formed on an entire surface of a substrate including thedevice isolation layer218. Theinsulation layer222 can prevent thesemiconductor substrate220 and thedevice isolation layer218 from being etched. In addition, theinsulation layer222 may be formed of silicon nitride. Before forming theinsulation layer222, abuffer oxide layer228 may be further formed on a surface of thefin220.
• Referring toFIGS. 37A, 37B and37C, aphotoresist pattern224 including agate opening226 is formed on theinsulation layer222. Thegate opening226 crosses over thefin220. Theinsulation layer222 and thedevice isolation layer218 are etched using thephotoresist pattern224 as an etching mask to form aninsulation pattern222aand agate groove226g.
• Referring toFIGS. 38A, 38B and38C, after forming the gate groove226g, thephotoresist pattern224 is removed to expose aninsulation pattern222a. Alternatively, thephotoresist pattern224 may be used only to pattern theinsulation layer222a, and may then be removed, and theinsulation pattern222amay be used as an etching mask to etch thedevice isolation layer218 and form the gate groove226g. Thegate groove226gis formed such that a recesseddevice isolation layer218rremains at the bottom of the gate groove226g. A channel region may then be formed by implanting impurities into the upper surface and sidewalls of thefin220 exposed by the gate groove226g. Alternatively, the channel region may be formed by implanting impurities after forming thefin220.
• Agate insulation layer228 is then formed on the upper surface and sidewalls of thefin220 exposed by the gate groove226g. A first conductive layer is formed on an entire surface of a substrate, filling the gate groove226gwhere thegate insulation layer228 is formed. The first conductive layer is etched-back or recessed by CMP to form alower gate pattern229 covering the upper portion and both sidewalls of thefin220 in the gate groove226g. A secondconductive layer230 is formed on an entire surface of a substrate including thelower gate pattern229. The secondconductive layer230 may have excellent conductivity and may be formed of metal and/or metal silicide. The secondconductive layer230 may also be formed of polysilicon, and may be silicided in a subsequent process.
• Referring toFIGS. 39A, 39B and39C, the secondconductive layer230 is patterned to form anupper gate pattern230gon thelower gate pattern229. As such, theupper gate pattern230gcrosses over thefin220. Impurities are implanted into thefin220 using theupper gate electrode230gas an ion implantation mask to respectively form source/drain regions232sand232dat opposite sides of theupper gate electrode230g. The impurities may be transmitted through theinsulation pattern222ato be implanted into thefin220 and may be diffused into a portion of thefin220 adjacent to thelower gate pattern229.Upper sidewall spacers234 are formed at both sidewalls of theupper gate electrode230g. Theinsulation pattern222ais patterned using theupper sidewall spacers234 as an etching mask to formlower sidewall spacers222bunder theupper sidewall spacers234. Thelower sidewall spacers222bare formed at sidewalls of thelower gate pattern229.
• The source/drain regions232sand232dmay be formed before or after forming thesidewall spacers234. More specifically, before forming thesidewall spacers234, the upper portion of thefin220 is exposed, such that oblique ion implantation may not be suitable. As such, ions may be thermally diffused after implanting ions using a projection range Rp. In other words, thespacers234 may prevent ions from being diffused under the gate. Alternatively, ion implantation may be performed using the same method as described above before forming thesidewall spacers234.
• Thedevice isolation layer218 is then etched using theupper sidewall spacer234 and theupper gate electrode230gas an etching mask to expose sidewalls of thefin220. Thedevice isolation layer218 is aligned with thespacers234 and is recessed to expose the sidewalls of thefin220. As such, the source/drain regions232sand232dare exposed at the exposed sidewalls of thefin220. Accordingly, the exposed surface area of the source/drain regions232sand232dmay be increased, thereby providing reduced contact resistance when source/drain contacts are formed in a subsequent step. The source/drain regions232sand232dmay also be formed after recessing thedevice isolation layer218, such as by using oblique ion implantation. The exposed surface area of the source/drain regions232sand232dmay be controlled based on the recessed depth of thedevice isolation layer218.
• Resultantly, as shown inFIGS. 35A, 35B and35C, even though thefin220 is scaled-down, the sidewalls of the source/drain regions232sand232dare exposed, thereby increasing the exposed surface area of the source/drain regions232sand232d. Accordingly, when source/drain contacts are formed on the source/drain regions232sand232din a subsequent process, contact resistance can be reduced despite the reduced width/thickness of thefin220 by electrically connecting the source/drain contacts at both the upper surfaces and sidewalls of thefin220.
• Also, although not shown, a silicide layer may be formed on the source/drain regions232sand232d, that is, on the exposed upper portion and sidewalls of thefin220. In addition, the silicide layer may also be formed on an upper potion of the gate electrode.
• FIG. 40A is a plan view illustrating FinFETs formed on a SOI substrate according to further embodiments of the present invention.FIG. 40B is a cross-sectional view taken along line IX-IX′ ofFIG. 40A.FIG. 40C is a cross-sectional view taken along line X-X′ ofFIG. 40A.
• Referring toFIGS. 40A, 40B and40C, a SOI substrate comprises abase substrate210, a buriedinsulation layer211 formed on thebase substrate210 and a semiconductor layer on the buriedinsulation layer211. The semiconductor layer may be formed of silicon, silicon-germanium or graded silicon, where the lattice distance of silicon is increased.
• A vertically protruding fin-shapedactive region220 is formed on the buriedinsulation layer211. Adevice isolation layer218 including agate groove226gcovers sidewalls of thefin220. A gate electrode fills the gate groove226gand covers an upper portion and sidewalls of thefin220. The bottom of the gate groove226gmay be formed of a recesseddevice isolation layer218ror the buriedinsulation layer211. The gate electrode comprises alower gate pattern229 and anupper gate pattern230g. Thelower gate pattern229 fills the gate groove226gto cover sidewalls and the upper portion of thefin220. Theupper gate pattern230gis formed on thelower gate pattern229. Agate insulation layer228 is formed between the gate electrode and the upper portion and sidewalls of thefin220 to define a triple-gate structure. Accordingly, a channel region may be formed at both sidewalls and at the upper portion of thefin220. Sidewall spacers are formed at both sidewalls of the gate electrode. Source/drain regions232sand232dare respectively formed in thefin220 at opposite sides of the gate electrode. The sidewall spacers includelower sidewall spacers222bformed on sidewalls of thelower gate pattern229, andupper sidewall spacers234 formed at sidewalls of theupper gate pattern230g. Thedevice isolation layer218 is aligned with the lower andupper sidewall spacers222band234, and recessed to form a recesseddevice isolation layer218r. Therefore, the sidewalls of thefin220 are partially exposed, and thus the source/drain regions232sand232dare exposed at the exposed sidewalls of thefin220. The exposed surface area of the source/drain regions232sand232dmay be greater than surface area of the upper surface of thefin220 alone, which is limited by the width/thickness of thefin220 in a direction parallel to gate electrode. Although not shown, source/drain contacts may be respectively formed on the source/drain regions232sand232d. The source/drain contacts may be in contact with the upper portion and the exposed sidewalls of thefin220 where the source/drain regions232sand232dare formed. In other words, even as fin width/thickness is scaled-down, the exposed source/drain regions232sand232dprovide a greater contact area for the source/drain contacts, thereby reducing resistance. In addition, resistance may be further reduced by forming a silicide layer on the source/drain regions232sand232dand the gate electrode. The bottom of the gate groove226gmay be formed by the recesseddevice isolation layer218rrather than by peripheral regions, or alternatively, may be formed by the buriedinsulation layer211.
• FIG. 41A is a plan view illustrating FinFETs according to yet still other embodiments of the present invention.FIG. 41B is a cross-sectional view taken along line XI-XI′ ofFIG. 41A.FIG. 41C is a cross-sectional view taken along line XII-XII′ ofFIG. 41A.
• Referring now toFIGS. 41A, 411 and41C, a fin-shapedactive region260 is formed vertically protruding from asemiconductor substrate250. Adevice isolation layer258 including agate groove266gcovers sidewalls of thefin260. A gate electrode fills the gate groove266gand covers an upper portion and sidewalls of thefin260. The bottom of the gate groove266gmay be formed by a recesseddevice isolation layer258r. The gate electrode is fills the gate groove266gand includes alower gate pattern269 and anupper gate pattern270g. Thelower gate pattern269 covers the sidewalls and the upper portion of thefin260. Theupper gate pattern270gis formed on thelower gate pattern269. Agate insulation layer268 is formed between the gate electrode and the upper portion and both sidewalls of thefin260 to define a triple-gate structure. Accordingly, a channel region may be formed at both sidewalls the upper portion of thefin260. Sidewall spacers are formed at both sidewalls of the gate electrode. Source/drain regions272sand272dare respectively formed in thefin260 at opposite sides of the gate electrode. The sidewall spacers includelower sidewall spacesr262bformed at sidewalls of thelower gate pattern269, andupper sidewall spacers274 formed adjacent sidewalls of theupper gate pattern270g.
• Thefin260 may include a first portion covered by and/or under the lower gate pattern269g, and a second portion where the source/drain regions272sand272dare formed. The portion covered by thelower gate pattern269 may be self-aligned with thelower gate pattern269, and may have a narrower width than the portion where the source/drain regions272sand272dare formed. A channel region is formed in the portion of thefin260 covered by thelower gate pattern269. Accordingly, the channel region is self-aligned with thelower gate pattern269. The channel region is formed at the upper portion and both sidewalls of thefin260.
• As shown inFIGS. 41A, 41B and41C, the portion of thefin260 including the source/drain regions272sand272dmay be wider than the portion of thefin260 covered by the gate electrode in a direction parallel to the gate electrode. In other words, even though the portion of thefin260 including the channel region may be recessed, the portion of thefin260 where the source/drain regions272sand272dare formed may have a greater width/thickness, thereby reducing resistance at the source/drain regions272sand272ddue to the greater contact surface area. In addition, resistance may be further reduced by forming a silicide layer on the source/drain regions272sand272dand the gate electrode.
• FIGS. 42A to45A are plan views illustrating exemplary operations for fabricating FinFETs according to yet still other embodiments of the present invention.FIGS. 42B to45B are cross-sectional views taken along line XI-XI′ ofFIGS. 42A to45A.FIGS. 42C to45C are cross-sectional views taken along line XII-XII′ ofFIGS. 42A to45A.
• Referring toFIGS. 42A, 42B and42C, a hard mask layer is formed on asemiconductor substrate250. The hard mask layer and thesemiconductor substrate250 are patterned to define a vertically protruding fin-shapedactive region260 and a device isolation region. An insulation layer is formed on an entire surface of thesemiconductor substrate250, filling the device isolation region. The insulation layer is polished by CMP to form adevice isolation layer258 in the device isolation region. Aninsulation layer262 used as a gate mask is formed on an entire surface of asubstrate250 including thedevice isolation layer258. Theinsulation layer262 can prevent thesemiconductor substrate250 and thedevice isolation layer258 from being etched, and may be formed of silicon nitride. Before forming theinsulation layer262, abuffer oxide layer268 may be further formed on the surface of thefin260.
• Referring toFIGS. 43A, 43B and43C, aphotoresist pattern264 including agate opening266 is formed on theinsulation layer262. Thegate opening266 crosses over thefin260. Theinsulation layer262 is etched using thephotoresist pattern264 as an etching mask to form aninsulation pattern262ahaving an opening crossing over thefin260.
• Referring toFIGS. 44A, 44B and44C, a thedevice isolation layer258 is etched using thephotoresist pattern264 as an etching mask to form agate groove226g. After forming the gate groove266g, thephotoresist pattern264 is removed to expose aninsulation pattern262a. Alternatively, thephotoresist pattern264 may be removed after patterning only theinsulation layer262a, and theinsulation pattern262amay then be used as an etching mask to etch thedevice isolation layer258 and form the gate groove266g. Thegate groove266gis formed such that a recesseddevice isolation layer258rremains at the bottom of the gate groove266g. The width/thickness of thefin260 is then reduced by recessing the sidewalls of thefin260 exposed to thegate grove266g. Thefin260 may be recessed using an isotropic etching process, or by removing an oxide layer formed by a thermal oxidation process. A channel region may be formed by implanting impurities into the exposed sidewalls of thefin260. The channel region may also be formed by implanting impurities after forming thefin260.
• Referring toFIGS. 45A, 45B and45C, agate insulation layer268 is formed on the upper surface and sidewalls offin260 exposed by the gate groove266g. A first conductive layer is formed on an entire surface of a substrate, filling the gate groove266gwhere thegate insulation layer268 is formed. The first conductive layer is recessed by etch-back or CMP to form alower gate pattern269 covering the upper portion and both sidewalls of thefin260. A secondconductive layer270 is formed on an entire surface of a substrate where thelower gate pattern269 is formed. The secondconductive layer270 may have excellent conductivity and may be formed of metal or metal silicide. The secondconductive layer270 may also be formed of polysilicon, and may be silicided in a subsequent process.
• Although not shown, sidewall spacers and source/drain regions272sand272dare formed to form the transistor shown inFIGS. 41A, 41B and41C.
• More specifically, the secondconductive layer270 is patterned to form anupper gate pattern270gon thelower gate pattern269. Theupper gate pattern270gcrosses over thefin260. Impurities are implanted into thefin260 using theupper gate pattern270gas an ion implantation mask to form source/drain regions272sand272din thefin260 at opposite sides of the upper gate patttern270g. The impurities may be transmitted through theinsulation pattern262ato be implanted into thefin260, and may be diffused into a portion of thefin260 adjacent to thelower gate pattern229.Upper sidewall spacers274 are formed at both sidewalls of theupper gate electrode270g. Although not shown, a silicide layer may be further formed at the exposed upper surface of thefin260, that is, on the source/drain regions272sand272d. In addition, the silicide layer may also be formed on the upper surface of the gate electrode.
• The source/drain regions272sand272dmay be formed before or after forming thesidewall spacers274. More particularly, before forming thesidewall spacers274, the upper surface of thefin260 is exposed, such that oblique ion implantation may not be suitable. In this case, if projection range Rp is used, ions may be diffused under the gate in a thermal annealing process to form a uniform ion profile. Accordingly, it may be possible to prevent ions from being diffused under the gate by controlling implantation depth, implanting ions by swiping implantation energy, and by applying rapid thermal annealing.
• After forming thesidewall spacers274, the area between the ion implantation region and the gate is covered by thespacers274. Therefore, ions may be thermally diffused after implanting ions in projection range Rp. In other words, thespacers274 may prevent ions from being diffused under the gate. However, the same ion implantation method used before forming thesidewall spacer274 may also be used.
• FIG. 46A is a plan view illustrating FinFETs according to further embodiments of the present invention.FIG. 46B is a cross-sectional view taken along line XI-XI′ ofFIG. 46A.FIG. 46C is a cross-sectional view taken along line XII-XII′ ofFIG. 46A.
• Referring toFIGS. 46A, 46B and46C, thedevice isolation layer258 of a transistor according to the embodiments ofFIGS. 41A, 41B and41C is aligned withsidewall spacers274 and recessed to form a recessedportion258b. Accordingly, the exposed surface area of the source/drain regions272sand272dmay be increased, thereby decreasing contact resistance. In addition, the surface area of the source/drain regions272sand272dto be exposed may be controlled based on a recessed depth of thedevice isolation layer258. In this case, the source/drain regions272sand272dmay be formed after recessing thedevice isolation layer258. The source/drain regions272sand272dmay be formed using an oblique ion implantation method.
• FIG. 47A is a plan view illustrating FinFETs formed on a SOI substrate according to still further embodiments of the present invention.FIG. 47B is a cross-sectional view taken along line XI-XI′ ofFIG. 47A.FIG. 47C is a cross-sectional view taken along line XII-XII′ ofFIG. 47A.
• Referring now toFIGS. 47A, 47B and47C, a SOI substrate includes abase substrate250, a buriedinsulation layer251 formed on thebase substrate250 and a semiconductor layer on the buriedinsulation layer251. The semiconductor layer may be formed of silicon, silicon-germanium and/or graded silicon, where the lattice distance of silicon is increased. The semiconductor layer is patterned to form a vertically protruding fin-shapedactive region260 on the buriedinsulation layer251. Adevice isolation layer258 including agate groove266gcovers sidewalls of thefin260. The bottom of the gate groove266gmay be formed by a recesseddevice isolation layer258ror the buriedinsulation layer251. A gate electrode fills thegate grove266gand covers the upper portion and both sidewalls of thefin260. The gate electrode includes alower gate pattern269 and anupper gate pattern270g. Thelower gate pattern269 covers the upper portion and both sidewalls of thefin260. Theupper gate pattern270gis formed on thelower gate pattern269. Agate insulation layer268 is positioned between thelower gate electrode269 and the upper portion and both sidewalls of thefin260 to define a triple-gate structure. Sidewall spacers are formed at both sidewalls of the gate electrode. Source/drain regions272sand272dare respectively formed in thefin260 at opposite sides of the gate electrode. The sidewall spacers includelower sidewall spacers262bformed at sidewalls of thelower gate pattern269 andupper sidewall spacers274 formed at sidewalls of theupper gate pattern270g.
• Thefin260 may include a first portion covered by and/or under the lower gate pattern269g, and a second portion where the source/drain regions272sand272dare formed. The portion covered by thelower gate pattern269 is self-aligned with thelower gate pattern269 and may have a narrower width than the portion where the source/drain regions272sand272dare formed. A channel region is formed on the portion of thefin260 covered by thelower gate pattern269. Accordingly, the channel region is self-aligned with thelower gate pattern269. The channel region is formed at upper portion and at both sidewalls of thefin260. Thedevice isolation layer258 is aligned with the sidewall spacers and is recessed to form a recesseddevice isolation layer258r. Therefore, the source/drain regions272sand272dmay be exposed at sidewalls of thefin260, providing a greater contact surface area and thus reduced contact resistance. In addition, a silicide layer may be formed on source/drain regions272sand272dand on the gate electrode to further reduce resistance.
• In the embodiments described above, if the source/drain regions are formed under the gate electrode, punch-through may become a problem. Accordingly, a bottom depth of the source/drain regions may preferably be equal to or above the bottom of the gate electrode. Therefore, when the device isolation layer is recessed to expose sidewalls of the fin (and thereby expose the source/drain regions), it may be preferable that the device isolation layer is recessed to a depth equal to or above the depth of the recessed device isolation layer under the gate electrode.
• As discussed above, the source/drain regions are exposed at sidewalls of the fin so that it may be possible to increase the available contact area for source/drain contacts to be connected to the source/drain regions. Accordingly, contact resistance at the source/drain regions can be reduced without increasing the size of the source/drain regions. In addition, the width/thickness of the fin may be reduced by recessing only the portion of the fin exposed by the gate groove in the damascene process used to form the gate. As a result, the width of the fin where the source/drain regions are formed is not reduced, so it is not necessary to increase the thickness of the fin where the source/drain regions are formed to increase contact area.
• Thus, according to embodiments of the present invention, FinFETs may be formed with reduced contact resistance at the source/drain regions without increasing the occupied area of the transistors.
• While the present invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

Claims (25)

1. A FinFET device, comprising:

a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate;

a gate electrode on an upper surface and sidewalls of the channel region; and

first and second source/drain contacts on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode.

2. The device ofclaim 1, wherein the channel region is narrower than the first and second source/drain regions of the fin-shaped active region.

3. The device ofclaim 1, further comprising:

a gate insulation layer on the upper surface and sidewalls of the channel region between the gate electrode and the channel region to form a triple-gate FinFET device.

4. The device ofclaim 3, further comprising:

a capping insulation layer on the upper surface of the channel region between the gate electrode and the channel region to form a double-gate FinFET device.

5. The device ofclaim 4, wherein the channel region is narrower than the capping insulation layer.

6. The device ofclaim 1, further comprising:

sidewall spacers on the first and second source/drain regions adjacent opposing sidewalls of the gate electrode.

7. The device ofclaim 6, wherein the gate electrode comprises a lower gate electrode on the upper surface and sidewalls of the channel region and an upper gate electrode on the lower gate electrode.

8. The device ofclaim 7, wherein the sidewall spacers respectively comprise an upper sidewall spacer adjacent sidewalls of the upper gate electrode and a lower sidewall spacer adjacent sidewalls of the lower gate electrode.

9. The device ofclaim 1, wherein the substrate comprises a silicon-on-insulator substrate having a base layer, a buried insulation layer on the base layer, and a semiconductor layer on the buried insulation layer, wherein the fin-shaped active region vertically protrudes from the semiconductor layer.

10. A Fin FET device, comprising:

a semiconductor substrate;

a fin-shaped active region vertically extending from the semiconductor substrate;

a device isolation layer adjacent sidewalls of the fin-shaped active region;

a gate electrode on an upper surface and sidewalls of the fin-shaped active region;

sidewall spacers on sidewalls of the gate electrode; and

source/drain regions in the fin-shaped active region at opposite sides of the gate electrode, wherein upper surfaces and sidewalls of the fin-shaped active region are exposed at the source/drain regions.

11. A method of forming a fin field-effect transistor, comprising:

forming a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate;

forming a gate electrode on an upper surface and sidewalls of the channel region; and

forming first and second source/drain contacts at opposite sides of the gate electrode on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region.

12. The method ofclaim 11, further comprising:

recessing the sidewalls of the channel region prior to forming the gate electrode such that the channel region is narrower than the first and second source/drain regions of the fin-shaped active region.

13. The method ofclaim 12, wherein recessing the sidewalls of the channel region comprises isotropically etching the sidewalls of the channel region to narrow the channel region.

14. The method ofclaim 12, wherein recessing the sidewalls of the channel region comprises:

thermally oxidizing the channel region to form an oxide layer on the upper surface and sidewalls of the channel region; and

removing the oxide layer to narrow the channel region.

15. A method of forming a FinFET, comprising:

forming a fin-shaped active region vertically protruding from a semiconductor substrate;

forming a device isolation layer on the fin-shaped active region, the device isolation layer having a trench therein exposing a first portion of the fin-shaped active region including an upper surface and sidewalls thereof;

forming a gate electrode in the trench on the upper surface and sidewalls of the first portion of the fin-shaped active region;

forming first and second source/drain regions in second portions of the fin-shaped active region at opposite sides of the gate electrode; and

recessing the device isolation layer at opposite sides of the gate electrode to expose upper surfaces and sidewalls of the second portions of the fin-shaped active region.

16. The method ofclaim 15, further comprising:

forming first and second source/drain contacts on the respective first and second source/drain regions at the exposed upper surface and sidewalls of the second portions of the fin-shaped active region.

17. The method ofclaim 15, wherein forming the first and second source/drain regions comprises:

implanting dopants into the upper surfaces and sidewalls of the second portions of the fin-shaped active region after recessing the device isolation layer.

18. The method ofclaim 15, further comprising:

implanting dopants into the first portion of the fin-shaped active region prior to forming the gate electrode to form a channel region therein.

19. The method ofclaim 15, further comprising:

recessing the sidewalls of the first portion of the fin-shaped active region before forming the gate electrode such that the first portion is narrower than the second portions of the fin-shaped active region.

20. The method ofclaim 15, wherein forming the device isolation layer comprises:

forming an insulation layer on the substrate including the fin-shaped active region;

recessing the insulation layer by chemical-mechanical polishing to expose the upper surface of the fin-shaped active region;

forming a mask pattern on the insulation layer and the upper surface of the fin-shaped active region, the mask pattern having an opening therein exposing the upper surface of the first portion of the fin-shaped active region and a portion of the insulation layer; and

etching the exposed portion of the insulation layer to define a trench in the insulation layer and to expose the sidewalls of the first portion of the fin-shaped active region.

21. The method ofclaim 15, further comprising:

forming a gate insulation layer on the upper surface and sidewalls of the first portion of the fin-shaped active region,

wherein forming the gate electrode comprises forming the gate electrode on the gate insulation layer to define a triple-gate FinFET device.

22. The method ofclaim 21, further comprising:

forming a capping insulation layer on the upper surface of the first portion of the fin-shaped active region,

wherein forming the gate electrode comprises forming the gate electrode on the capping insulation layer on the upper surface and the gate insulation layer on the sidewalls of the first portion of the fin-shaped active region to define a double-gate FinFET device.

23. The method ofclaim 15, further comprising:

forming sidewall spacers on the first and second source/drain regions adjacent opposing sidewalls of the gate electrode.

24. The method ofclaim 23, wherein forming the gate electrode comprises:

forming a lower gate electrode on the upper surface and sidewalls of the first portion of the fin-shaped active region; and

forming an upper gate electrode on the lower gate electrode.

25. The method ofclaim 24, wherein forming the sidewall spacers comprises:

forming upper sidewall spacers adjacent sidewalls of the upper gate electrode; and

forming lower sidewall spacers adjacent sidewalls of the lower gate electrode.

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