US20050173744A1 - Recessed-type field effect transistor with reduced body effect - Google Patents
Recessed-type field effect transistor with reduced body effectDownload PDFInfo
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- US20050173744A1 US20050173744A1US11/051,834US5183405AUS2005173744A1US 20050173744 A1US20050173744 A1US 20050173744A1US 5183405 AUS5183405 AUS 5183405AUS 2005173744 A1US2005173744 A1US 2005173744A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
- H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
- H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Definitions
- the present inventionrelates generally to integrated circuit fabrication, and more particularly to fabrication of a recessed-type field effect transistor with an extra-doped channel region to reduce body effect.
- a field effect transistoris a common component of many integrated circuits.
- a field effect transistorincludes a source and a drain for defining a channel region, a gate insulator, and a gate electrode.
- the structure and operation of a field effect transistoris by now well known to one of ordinary skill in the art of electronics.
- the channel length of the field effect transistoris continually reduced.
- undesired short-channel effectsresult in the field effect transistor from such reduced channel length.
- a recessed-type field effect transistoris formed with the gate electrode filling a trench in a semiconductor substrate. Because the channel length is along the bottom wall and sidewalls of the trench, the channel length is increased for decreasing short channel effects.
- U.S. Pat. No. 5,817,558 to Shye Lin Wudiscloses such a recessed-type field effect transistor.
- the recessed-type field effect transistor of Wuincludes a gate electrode filling an opening formed within a semiconductor substrate.
- an anti-punch through layeris formed below such an opening in Wu for preventing leakage current between the source and the drain.
- the anti-punch through layer in Wuis formed well below the opening such that the field effect transistor of Wu is still susceptible to undesired body effect.
- the body effectrefers to variation of threshold voltage of the field effect transistor from bias on the semiconductor substrate.
- the anti-punch through layerdoes not abut the walls of the opening such that the anti-punch through layer does not prevent the undesired body effect.
- a field effect transistoris formed with an extra-doped channel region for preventing undesired body effect.
- an extra-doped channel regionis formed below a surface of a semiconductor substrate.
- An openingis formed in the semiconductor substrate into the extra-doped channel region.
- a gate insulatoris formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening.
- the openingis filled with a gate electrode.
- the extra-doped channel regionabuts the gate insulator at a bottom wall and sidewalls of the opening below a half-height of the opening.
- the openingis formed after the extra-doped channel region is formed.
- a drain and a sourceare formed in the semiconductor substrate to the sides of the opening with an overlap under the gate insulator and the gate electrode.
- the conductivity type of a dopant within the extra-doped channel regionis opposite to a respective conductivity type of a respective dopant in each of the drain, the source, and the gate electrode.
- a respective line padis formed on each of the drain and the source.
- the field effect transistoris formed as part of a DRAM (dynamic random access memory) cell.
- the respective line pad disposed on the sourceis coupled to a storage capacitor of the DRAM cell, and the gate electrode forms a word line for the DRAM cell.
- the field effect transistor of the present inventionmay be applied for other types of integrated circuits.
- the field effect transistorhas a more stable threshold voltage for more stable operation.
- FIG. 1shows a layout of field effect transistors with reduced body effect, according to an embodiment of the present invention
- FIG. 2shows a cross-sectional view along line I-I′ of FIG. 1 , according to an embodiment of the present invention
- FIGS. 3, 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , and 15show cross-sectional views during steps for fabricating the field effects transistors of FIGS. 1 and 2 , according to an embodiment of the present invention.
- FIG. 16shows a circuit diagram of a DRAM (dynamic random access memory) cell having a field effect transistor formed according to the present invention.
- FIGS. 1, 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , and 16refer to elements having similar structure and/or function.
- FIG. 1shows a layout of field effect transistors formed according to an embodiment of the present invention.
- FIG. 2shows a cross-sectional view of such field effect transistors along line I-I′ of FIG. 1 .
- a STI (shallow trench isolation) structure 10is formed within a semiconductor substrate 5 to define an active region 20 .
- the STI structure 10is comprised of an insulating material such as silicon dioxide (SiO 2 ), and the semiconductor substrate 5 is comprised of a semiconductor material such as silicon.
- At least one opening 70is formed into the semiconductor substrate 5 within the active region 20 .
- the openings 70each have a trench shape in one embodiment of the present invention.
- Each opening 70has a gate insulator 85 formed at walls including a bottom wall and side walls of the opening 70 .
- an extra-doped channel region 65is formed to surround a bottom portion of each opening 70 .
- the extra-doped channel region 65abuts the gate insulator 85 at the bottom wall and the sidewalls of the opening 70 .
- the extra-doped channel region 65abuts the gate insulator 85 only below a lower half of the height of the opening 70 , according to one embodiment of the present invention.
- a gate electrode 95fills each opening 70 , and a gate capping layer 105 is formed on each gate electrode 95 .
- Each gate electrode 95 and gate capping layer 105 formed within the active region 20forms a respective gate line pattern 110 for a respective field effect transistor.
- each gate electrode 95 and gate capping layer 105 formed on the STI structure 10forms an inactive gate line pattern 114 .
- the gate line patterns 110 and 114are formed as parallel lines as illustrated in FIG. 1 .
- the field effect transistors of FIG. 2are formed within a DRAM (dynamic random access memory) device.
- the gate electrodes 95 formed within the active region 20form word-lines of the DRAM device.
- Each gate electrode 95is comprised of polysilicon of N-type or P-type conductivity and a metal silicide stacked thereon.
- the polysilicon of the gate electrode 95has a conductivity that is opposite to the conductivity of the extra-doped channel region 65 .
- the gate capping layer 105is comprised of silicon nitride (Si 3 N 4 ) in an embodiment of the present invention.
- spacers 118are disposed on sidewalls of the gate electrode 95 and gate capping layer 105 .
- the gate insulator 85 formed on walls of the opening 70is also disposed under the spacers 118 .
- the spacers 118are comprised of an insulating material having the same etch selectivity as the gate capping layer 105 .
- the gate insulator 85is comprised of an insulating material having an etch selectivity different from the gate capping layer 105 .
- the gate insulatoris comprised of a silicon oxide (Si x O y ) or a silicon oxynitride (Si x O y N z ), in one embodiment of the present invention.
- a source/drain 125is formed within the semiconductor substrate 5 to the sides of the opening 70 .
- a pair of the source/drains 125 disposed to the two sides of the opening 70 within the active region 20form a source and a drain for a field effect transistor.
- such a source and drain pair 125 and the gate electrode 95 and the gate insulator 85 filling such an opening 70define a field effect transistor of the present invention.
- Each source/drain 125is formed under a portion of the gate electrode 95 and the gate insulator 85 .
- each source/drain 125is formed to overlap a portion of the gate electrode 95 and the gate insulator 85 .
- Each source/drain 125is doped with a dopant of a second conductivity type that is opposite of the first conductivity type of the dopant within the extra-doped channel region 65 , in one embodiment of the present invention.
- a respective landing pad 150is disposed on and contacts each source/drain 125 .
- the lower portion of the landing pad 150extends between the spacers 118 , and the upper portion of the landing pad 150 is surrounded by an interlayer insulating layer 130 .
- the present inventionmay be practiced with the conductivity of the dopant within the extra-doped channel region 65 being the same or opposite of the conductivity of the semiconductor substrate 5 .
- FIGS. 3, 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , and 15show cross-sectional views during steps for fabricating the field effect transistors of FIGS. 1 and 2 , according to an embodiment of the present invention.
- the STI (shallow trench isolation) structure 10is formed in the semiconductor substrate 5 to define the active region 20 .
- the STI structure 10is comprised of an insulating material such as silicon dioxide (SiO 2 ).
- an implantation masking layer 30a BARC (buried anti-reflective coating) layer 40 , and a photoresist layer 50 are sequentially deposited.
- the implantation masking layer 30is comprised of an insulating material having an etch selectivity different from the STI structure 10 .
- the BARC layer 40enhances pattern transfer to the photoresist layer 50 , and the present invention may be practiced with or without the BARC layer 40 .
- the photoresist layer 50 , the BARC layer 40 , and the implantation masking layer 30are patterned to form openings there-through.
- the photoresist layer 50is first patterned in a photolithography process. And the exposed portions of the BARC layer 40 and the implantation masking layer 30 are subsequently etched using the patterned photoresist layer 50 as an etch mask.
- portions of the semiconductor substrate 5are exposed through the openings formed in the photoresist layer 50 , the BARC layer 40 , and the implantation masking layer 30 .
- the remaining portions of the photoresist layer 50 , the BARC layer 40 , and the implantation masking layer 30form a photoresist pattern 55 , a BARC pattern 45 , and an implantation masking pattern 35 , respectively.
- ion implantation 60is performed with the photoresist pattern 55 , the BARC pattern 45 , and the implantation masking pattern 35 acting as an implantation mask to form extra-doped channel regions 65 .
- the extra-doped channel regions 65are formed at a predetermined depth from the top surface of the semiconductor substrate 5 .
- the ion implantation 60is for doping the extra-doped channel regions 65 with a dopant of a first conductivity type that is same or opposite of the conductivity type of the semiconductor substrate 5 .
- the photoresist pattern 55is removed, and subsequently, exposed portions of the semiconductor substrate 5 are etched using the BARC pattern 45 and the implantation masking pattern 35 as an etch mask.
- openings 70are formed within the active region 20 of the semiconductor substrate 5 .
- the openings 70are each formed as a trench in an example embodiment of the present invention.
- each opening 70is etched into a respective extra-doped channel region 65 such that the extra-doped channel region 65 surrounds a lower portion of the opening 70 .
- the bottom wall of the opening 70abuts the extra-doped channel region 65 .
- a portion of the sidewalls of the opening 70 below half the height of the opening 70abuts the extra-doped channel region 65 , in an example embodiment of the present invention.
- a first oxidation processis performed to form a sacrificial insulating layer 75 at exposed walls of the openings 70 .
- the openings 70further extend into the extra-doped channel regions 65 from the oxidation process.
- the openings 70may be initially formed without extending into the extra-doped channel regions 65 .
- the openings 70extend into the extra-doped channel regions 65 .
- the sacrificial insulating layer 75is comprised of silicon dioxide (SiO 2 ) in one embodiment of the present invention.
- the sacrificial insulating layer 75stabilizes the interface state of the semiconductor material at the walls of the openings 70 .
- the gate insulator material 80is comprised of a silicon oxide (Si x O y ) or a silicon oxynitride (Si x O y N z ), in one embodiment of the present invention.
- a gate electrode material 90 and a gate capping material 100are deposited sequentially.
- the gate electrode material 90fills the openings 70 , and the gate capping material 100 is formed to cover the gate electrode material 90 .
- the gate electrode material 90is comprised of polysilicon with N or P type conductivity with a metal silicide stacked thereon.
- the conductivity type of the polysilicon forming the gate electrode material 90is opposite to the conductivity type of the extra-doped channel region 65 , in one embodiment of the present invention.
- the gate capping material 100is comprised of an insulating material, such as silicon nitride (Si 3 N 4 ) for example, having an etch selectivity different from the gate insulator material 80 .
- the gate electrode material 90 and the gate capping material 100are patterned to form gate electrodes 95 and gate capping layers 105 .
- Each gate electrode 95 formed within the active region 20fills one of the openings 70 .
- the gate insulator material 80acts as an etch stop during such patterning for the gate electrodes 95 and the gate capping layers 105 .
- Each gate electrode 95 and gate capping layer 105 formed within the active region 20forms a line pattern 110 for the field effect transistor, and each gate electrode 95 and gate capping layer 105 formed on the STI structure 10 forms an inactive line pattern 114 .
- the spacers 118are formed on sidewalls of the gate electrodes 95 and the gate capping layers 105 . Thereafter, exposed portions of the gate insulator material 80 are etched away to expose the portions of the semiconductor substrate 5 between the spacers 118 . In this manner, remaining portions of the gate insulator material 80 forms a gate insulator 85 disposed at walls of the openings 70 and under the spacers 118 .
- the spacers 118are comprised of an insulating material having the same etch selectivity as the gate capping layer 105 .
- an ion implantation process 120is performed with the gate capping layers 105 , the gate electrodes 95 , and the spacers 118 acting as implantation masks.
- a dopantis implanted into exposed portions of the semiconductor substrate 5 to form source/drain regions 125 . After thermal diffusion, the source/drain regions 125 spread out to be disposed under portions of the gate insulator 85 and the gate electrode 95 .
- the dopant within the source/drain regions 125have a second conductivity type that is opposite to the first conductivity type of the dopant within the extra-doped channel region 65 .
- the dose of the dopant within the source/drain regions 125is higher than that of the dopant within the extra-doped channel region 65 .
- a source and drain pair 125 and the gate electrode 95 and the gate insulator 85 filling such an opening 70define a field effect transistor of the present invention.
- an interlayer insulating material 130is blanket-deposited to cover the structures on the semiconductor substrate 5 .
- the interlayer insulating material 130is patterned to form landing pad openings 135 over the source/drain regions 125 .
- the upper portions of the landing pad openings 135have a larger diameter than that of the lower portions.
- the upper portions of the landing pad openings 135are surrounded by the remaining interlayer insulating material 130 , and the lower portions of the landing pad openings 135 are surrounded by the spacers 118 .
- landing pads 150are formed to fill the landing pad openings 135 . Each landing pad 150 contacts a respective source/drain 125 .
- an additional ion implantation process 140may be performed prior to the formation of the landing pads 150 in FIG. 15 for reducing contact resistance of the landing pads 150 .
- the landing pads 150are comprised of polysilicon having the same conductivity type as the source/drain regions 125 , in one embodiment of the present invention.
- the extra-doped channel region 65abuts the gate insulator 85 at the bottom portion of the opening 70 containing the gate electrode 95 .
- the field effect transistor formed with such structureshas reduced body effect for more stable operation.
- such a field effect transistor 202is advantageously formed as part of a DRAM (dynamic random access memory) cell 200 .
- the field effect transistor 202is fabricated according to the process as illustrated in FIGS. 3 - 15 within the active region 20 of the semiconductor substrate 5 .
- the drain 125 of the field effect transistor 202forms a bit line 204 of the DRAM cell 200 with such a bit line 204 being coupled to a sense amplifier 210 .
- the gate electrode 95forms a word line 206 of the DRAM cell 200 .
- the source 125is coupled to a charge storage node of a capacitor 208 .
- the charge storage node of the capacitor 208is formed onto the landing pad 150 for the source 125 .
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Abstract
Description
- This patent application claims priority to Korean Patent Application No. 2004-0009122, filed on Feb. 11, 2004 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.
- The present invention relates generally to integrated circuit fabrication, and more particularly to fabrication of a recessed-type field effect transistor with an extra-doped channel region to reduce body effect.
- Field effect transistors are a common component of many integrated circuits. A field effect transistor includes a source and a drain for defining a channel region, a gate insulator, and a gate electrode. The structure and operation of a field effect transistor is by now well known to one of ordinary skill in the art of electronics.
- As device dimensions are constantly scaled down, the channel length of the field effect transistor is continually reduced. However, undesired short-channel effects result in the field effect transistor from such reduced channel length.
- For preventing such undesired short-channel effects, a recessed-type field effect transistor is formed with the gate electrode filling a trench in a semiconductor substrate. Because the channel length is along the bottom wall and sidewalls of the trench, the channel length is increased for decreasing short channel effects.
- For example, U.S. Pat. No. 5,817,558 to Shye Lin Wu (hereafter referred to as “Wu”) discloses such a recessed-type field effect transistor. The recessed-type field effect transistor of Wu includes a gate electrode filling an opening formed within a semiconductor substrate. In addition, an anti-punch through layer is formed below such an opening in Wu for preventing leakage current between the source and the drain.
- However, the anti-punch through layer in Wu is formed well below the opening such that the field effect transistor of Wu is still susceptible to undesired body effect. Generally, the body effect refers to variation of threshold voltage of the field effect transistor from bias on the semiconductor substrate. In Wu, the anti-punch through layer does not abut the walls of the opening such that the anti-punch through layer does not prevent the undesired body effect.
- Accordingly, a field effect transistor is formed with an extra-doped channel region for preventing undesired body effect.
- For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode.
- In one embodiment of the present invention, the extra-doped channel region abuts the gate insulator at a bottom wall and sidewalls of the opening below a half-height of the opening. In another embodiment of the present invention, the opening is formed after the extra-doped channel region is formed. In addition, a drain and a source are formed in the semiconductor substrate to the sides of the opening with an overlap under the gate insulator and the gate electrode.
- In a further embodiment of the present invention, the conductivity type of a dopant within the extra-doped channel region is opposite to a respective conductivity type of a respective dopant in each of the drain, the source, and the gate electrode. In another embodiment of the present invention, a respective line pad is formed on each of the drain and the source.
- In an example application, the field effect transistor is formed as part of a DRAM (dynamic random access memory) cell. In that case, the respective line pad disposed on the source is coupled to a storage capacitor of the DRAM cell, and the gate electrode forms a word line for the DRAM cell. However, the field effect transistor of the present invention may be applied for other types of integrated circuits.
- In this manner, because the extra-doped channel region abuts the gate insulator at walls of the opening of the recessed type field effect transistor, body effect is prevented. Thus, the field effect transistor has a more stable threshold voltage for more stable operation.
- The above and other features and advantages of the present invention will become more apparent when described in detailed exemplary embodiments thereof with reference to the attached drawings in which:
FIG. 1 shows a layout of field effect transistors with reduced body effect, according to an embodiment of the present invention;FIG. 2 shows a cross-sectional view along line I-I′ ofFIG. 1 , according to an embodiment of the present invention;FIGS. 3, 4 ,5,6,7,8,9,10,11,12,13,14, and15 show cross-sectional views during steps for fabricating the field effects transistors ofFIGS. 1 and 2 , according to an embodiment of the present invention; andFIG. 16 shows a circuit diagram of a DRAM (dynamic random access memory) cell having a field effect transistor formed according to the present invention.- The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number in
FIGS. 1, 2 ,3,4,5,6,7,8,9,10,11,12,13,14,15, and16 refer to elements having similar structure and/or function. FIG. 1 shows a layout of field effect transistors formed according to an embodiment of the present invention.FIG. 2 shows a cross-sectional view of such field effect transistors along line I-I′ ofFIG. 1 .- Referring to
FIGS. 1 and 2 , a STI (shallow trench isolation)structure 10 is formed within asemiconductor substrate 5 to define anactive region 20. TheSTI structure 10 is comprised of an insulating material such as silicon dioxide (SiO2), and thesemiconductor substrate 5 is comprised of a semiconductor material such as silicon. At least one opening70 is formed into thesemiconductor substrate 5 within theactive region 20. Theopenings 70 each have a trench shape in one embodiment of the present invention. - Each opening70 has a
gate insulator 85 formed at walls including a bottom wall and side walls of the opening70. In addition, anextra-doped channel region 65 is formed to surround a bottom portion of each opening70. For example, theextra-doped channel region 65 abuts thegate insulator 85 at the bottom wall and the sidewalls of the opening70. Theextra-doped channel region 65 abuts thegate insulator 85 only below a lower half of the height of the opening70, according to one embodiment of the present invention. - In addition, a
gate electrode 95 fills each opening70, and agate capping layer 105 is formed on eachgate electrode 95. Eachgate electrode 95 andgate capping layer 105 formed within theactive region 20 forms a respectivegate line pattern 110 for a respective field effect transistor. In addition, eachgate electrode 95 andgate capping layer 105 formed on theSTI structure 10 forms an inactivegate line pattern 114. - In one embodiment of the present invention, the
gate line patterns FIG. 1 . In an example application of the present invention, the field effect transistors ofFIG. 2 are formed within a DRAM (dynamic random access memory) device. In that case, thegate electrodes 95 formed within theactive region 20 form word-lines of the DRAM device. - Each
gate electrode 95 is comprised of polysilicon of N-type or P-type conductivity and a metal silicide stacked thereon. In addition, the polysilicon of thegate electrode 95 has a conductivity that is opposite to the conductivity of theextra-doped channel region 65. Thegate capping layer 105 is comprised of silicon nitride (Si3N4) in an embodiment of the present invention. - Further referring to
FIG. 2 ,spacers 118 are disposed on sidewalls of thegate electrode 95 andgate capping layer 105. Thegate insulator 85 formed on walls of theopening 70 is also disposed under thespacers 118. Thespacers 118 are comprised of an insulating material having the same etch selectivity as thegate capping layer 105. Thegate insulator 85 is comprised of an insulating material having an etch selectivity different from thegate capping layer 105. The gate insulator is comprised of a silicon oxide (SixOy) or a silicon oxynitride (SixOyNz), in one embodiment of the present invention. - A source/
drain 125 is formed within thesemiconductor substrate 5 to the sides of theopening 70. A pair of the source/drains125 disposed to the two sides of theopening 70 within theactive region 20 form a source and a drain for a field effect transistor. In addition, such a source anddrain pair 125 and thegate electrode 95 and thegate insulator 85 filling such anopening 70 define a field effect transistor of the present invention. Each source/drain 125 is formed under a portion of thegate electrode 95 and thegate insulator 85. Thus, each source/drain 125 is formed to overlap a portion of thegate electrode 95 and thegate insulator 85. - Each source/
drain 125 is doped with a dopant of a second conductivity type that is opposite of the first conductivity type of the dopant within theextra-doped channel region 65, in one embodiment of the present invention. Arespective landing pad 150 is disposed on and contacts each source/drain 125. The lower portion of thelanding pad 150 extends between thespacers 118, and the upper portion of thelanding pad 150 is surrounded by aninterlayer insulating layer 130. In addition, the present invention may be practiced with the conductivity of the dopant within theextra-doped channel region 65 being the same or opposite of the conductivity of thesemiconductor substrate 5. FIGS. 3, 4 ,5,6,7,8,9,10,11,12,13,14, and15 show cross-sectional views during steps for fabricating the field effect transistors ofFIGS. 1 and 2 , according to an embodiment of the present invention. Referring toFIG. 3 , the STI (shallow trench isolation)structure 10 is formed in thesemiconductor substrate 5 to define theactive region 20. TheSTI structure 10 is comprised of an insulating material such as silicon dioxide (SiO2).- Referring to
FIG. 4 , animplantation masking layer 30, a BARC (buried anti-reflective coating)layer 40, and aphotoresist layer 50 are sequentially deposited. Theimplantation masking layer 30 is comprised of an insulating material having an etch selectivity different from theSTI structure 10. TheBARC layer 40 enhances pattern transfer to thephotoresist layer 50, and the present invention may be practiced with or without theBARC layer 40. - Referring to
FIG. 5 , thephotoresist layer 50, theBARC layer 40, and theimplantation masking layer 30 are patterned to form openings there-through. For example, thephotoresist layer 50 is first patterned in a photolithography process. And the exposed portions of theBARC layer 40 and theimplantation masking layer 30 are subsequently etched using the patternedphotoresist layer 50 as an etch mask. - Further referring to
FIG. 5 , portions of thesemiconductor substrate 5 are exposed through the openings formed in thephotoresist layer 50, theBARC layer 40, and theimplantation masking layer 30. In addition, the remaining portions of thephotoresist layer 50, theBARC layer 40, and theimplantation masking layer 30 form aphotoresist pattern 55, aBARC pattern 45, and animplantation masking pattern 35, respectively. - Thereafter referring to
FIG. 6 ,ion implantation 60 is performed with thephotoresist pattern 55, theBARC pattern 45, and theimplantation masking pattern 35 acting as an implantation mask to formextra-doped channel regions 65. Theextra-doped channel regions 65 are formed at a predetermined depth from the top surface of thesemiconductor substrate 5. Theion implantation 60 is for doping theextra-doped channel regions 65 with a dopant of a first conductivity type that is same or opposite of the conductivity type of thesemiconductor substrate 5. - Referring to
FIG. 7 , thephotoresist pattern 55 is removed, and subsequently, exposed portions of thesemiconductor substrate 5 are etched using theBARC pattern 45 and theimplantation masking pattern 35 as an etch mask. Thus,openings 70 are formed within theactive region 20 of thesemiconductor substrate 5. Theopenings 70 are each formed as a trench in an example embodiment of the present invention. - In addition, each opening70 is etched into a respective
extra-doped channel region 65 such that theextra-doped channel region 65 surrounds a lower portion of theopening 70. In an example embodiment of the present invention, the bottom wall of theopening 70 abuts theextra-doped channel region 65. In addition, a portion of the sidewalls of theopening 70 below half the height of theopening 70 abuts theextra-doped channel region 65, in an example embodiment of the present invention. - Further referring to
FIG. 7 , a first oxidation process is performed to form a sacrificial insulatinglayer 75 at exposed walls of theopenings 70. In one embodiment of the present invention, theopenings 70 further extend into theextra-doped channel regions 65 from the oxidation process. In that case, theopenings 70 may be initially formed without extending into theextra-doped channel regions 65. Then, after the oxidation process for forming the sacrificial insulatinglayer 75, theopenings 70 extend into theextra-doped channel regions 65. - The sacrificial insulating
layer 75 is comprised of silicon dioxide (SiO2) in one embodiment of the present invention. The sacrificial insulatinglayer 75 stabilizes the interface state of the semiconductor material at the walls of theopenings 70. - Thereafter referring to
FIG. 8 , theBARC pattern 45, theimplantation masking pattern 35, and the sacrificial insulatinglayer 75 are removed. In addition, a second oxidation process is performed to form agate insulator material 80 on exposed surfaces of thesemiconductor substrate 5 including on the walls of theopenings 70. Thegate insulator material 80 is comprised of a silicon oxide (SixOy) or a silicon oxynitride (SixOyNz), in one embodiment of the present invention. - Subsequently, referring to
FIG. 9 , agate electrode material 90 and agate capping material 100 are deposited sequentially. Thegate electrode material 90 fills theopenings 70, and thegate capping material 100 is formed to cover thegate electrode material 90. - The
gate electrode material 90 is comprised of polysilicon with N or P type conductivity with a metal silicide stacked thereon. In addition, the conductivity type of the polysilicon forming thegate electrode material 90 is opposite to the conductivity type of theextra-doped channel region 65, in one embodiment of the present invention. Thegate capping material 100 is comprised of an insulating material, such as silicon nitride (Si3N4) for example, having an etch selectivity different from thegate insulator material 80. - The
gate electrode material 90 and thegate capping material 100 are patterned to formgate electrodes 95 and gate capping layers105. Eachgate electrode 95 formed within theactive region 20 fills one of theopenings 70. Thegate insulator material 80 acts as an etch stop during such patterning for thegate electrodes 95 and the gate capping layers105. Eachgate electrode 95 andgate capping layer 105 formed within theactive region 20 forms aline pattern 110 for the field effect transistor, and eachgate electrode 95 andgate capping layer 105 formed on theSTI structure 10 forms aninactive line pattern 114. - Referring to
FIG. 11 , thespacers 118 are formed on sidewalls of thegate electrodes 95 and the gate capping layers105. Thereafter, exposed portions of thegate insulator material 80 are etched away to expose the portions of thesemiconductor substrate 5 between thespacers 118. In this manner, remaining portions of thegate insulator material 80 forms agate insulator 85 disposed at walls of theopenings 70 and under thespacers 118. Thespacers 118 are comprised of an insulating material having the same etch selectivity as thegate capping layer 105. - Referring to
FIG. 12 , anion implantation process 120 is performed with thegate capping layers 105, thegate electrodes 95, and thespacers 118 acting as implantation masks. A dopant is implanted into exposed portions of thesemiconductor substrate 5 to form source/drain regions 125. After thermal diffusion, the source/drain regions 125 spread out to be disposed under portions of thegate insulator 85 and thegate electrode 95. - In addition, the dopant within the source/
drain regions 125 have a second conductivity type that is opposite to the first conductivity type of the dopant within theextra-doped channel region 65. In addition, the dose of the dopant within the source/drain regions 125 is higher than that of the dopant within theextra-doped channel region 65. - A pair of the source/
drain regions 125 disposed to the two sides of theopening 70 within theactive region 20 form a source and a drain for a field effect transistor of the present invention. In addition, such a source anddrain pair 125 and thegate electrode 95 and thegate insulator 85 filling such anopening 70 define a field effect transistor of the present invention. - Thereafter referring to
FIG. 13 , aninterlayer insulating material 130 is blanket-deposited to cover the structures on thesemiconductor substrate 5. Referring toFIG. 14 , theinterlayer insulating material 130 is patterned to formlanding pad openings 135 over the source/drain regions 125. In one embodiment of the present invention, the upper portions of thelanding pad openings 135 have a larger diameter than that of the lower portions. The upper portions of thelanding pad openings 135 are surrounded by the remaininginterlayer insulating material 130, and the lower portions of thelanding pad openings 135 are surrounded by thespacers 118. - Referring to
FIG. 15 ,landing pads 150 are formed to fill thelanding pad openings 135. Eachlanding pad 150 contacts a respective source/drain 125. In addition referring toFIG. 14 , an additionalion implantation process 140 may be performed prior to the formation of thelanding pads 150 inFIG. 15 for reducing contact resistance of thelanding pads 150. Thelanding pads 150 are comprised of polysilicon having the same conductivity type as the source/drain regions 125, in one embodiment of the present invention. - In this manner, the
extra-doped channel region 65 abuts thegate insulator 85 at the bottom portion of theopening 70 containing thegate electrode 95. Thus, the field effect transistor formed with such structures has reduced body effect for more stable operation. - Referring to
FIG. 16 , such afield effect transistor 202 is advantageously formed as part of a DRAM (dynamic random access memory)cell 200. Thefield effect transistor 202 is fabricated according to the process as illustrated in FIGS.3-15 within theactive region 20 of thesemiconductor substrate 5. In that case, thedrain 125 of thefield effect transistor 202 forms abit line 204 of theDRAM cell 200 with such abit line 204 being coupled to asense amplifier 210. In addition, thegate electrode 95 forms aword line 206 of theDRAM cell 200. Furthermore, thesource 125 is coupled to a charge storage node of acapacitor 208. For example, the charge storage node of thecapacitor 208 is formed onto thelanding pad 150 for thesource 125. - While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
- Thus, the foregoing is by way of example only and is not intended to be limiting. For example, although a field effect transistor formed according to the present invention is described for application within a DRAM cell, the field effect transistor formed according to the present invention may also be used in other integrated circuits. In addition, any materials or numbers of elements illustrated and described herein are by way of example only.
- The present invention is limited only as defined in the following claims and equivalents thereof.
Claims (20)
1. A field effect transistor, comprising:
a gate electrode filling an opening formed within a semiconductor substrate;
a gate insulator formed at walls of the opening; and
an extra-doped channel region abutting the gate insulator at a bottom portion of the opening.
2. The field effect transistor ofclaim 1 , further comprising:
a drain and a source formed in the semiconductor substrate to the sides of the opening with an overlap under the gate insulator and the gate electrode.
3. The field effect transistor ofclaim 2 , wherein a conductivity type of a dopant within the extra-doped channel region is opposite to a respective conductivity type of a respective dopant in each of the drain, the source, and the gate electrode.
4. The field effect transistor ofclaim 2 , further comprising:
a respective line pad disposed on each of the drain and the source.
5. The field effect transistor ofclaim 4 , wherein the field effect transistor is part of a DRAM (dynamic random access memory) cell.
6. The field effect transistor ofclaim 5 , wherein the respective line pad disposed on the source is coupled to a storage capacitor of the DRAM cell.
7. The field effect transistor ofclaim 5 , wherein the gate electrode forms a word line for the DRAM cell.
8. The field effect transistor ofclaim 1 , further comprising:
a gate capping layer disposed on the gate electrode; and
spacers disposed on sidewalls of the gate electrode and the gate capping layer.
9. The field effect transistor ofclaim 1 , further comprising:
a STI (shallow trench isolation) structure for defining an active region having the opening formed therein.
10. The field effect transistor ofclaim 1 , wherein the extra-doped channel region abuts the gate insulator at a bottom wall and sidewalls of the opening below a half-height of the opening.
11. A method for fabricating a field effect transistor, comprising:
forming an extra-doped channel region below a surface of a semiconductor substrate;
forming an opening in the semiconductor substrate into the extra-doped channel region;
forming a gate insulator at walls of the opening such that the extra-doped channel region abuts the gate insulator at the bottom portion of the opening; and
filling the opening with a gate electrode.
12. The method ofclaim 11 , wherein the extra-doped channel region abuts the gate insulator at a bottom wall and sidewalls of the opening below a half-height of the opening.
13. The method ofclaim 11 , wherein the opening is formed after the extra-doped channel region is formed.
14. The method ofclaim 11 , further comprising:
forming a drain and a source in the semiconductor substrate to the sides of the opening with an overlap under the gate insulator and the gate electrode.
15. The method ofclaim 14 , wherein a conductivity type of a dopant within the extra-doped channel region is opposite to a respective conductivity type of a respective dopant in each of the drain, the source, and the gate electrode.
16. The method ofclaim 14 , further comprising:
forming a respective line pad on each of the drain and the source.
17. The method ofclaim 16 , further comprising:
forming the field effect transistor as part of a DRAM (dynamic random access memory) cell.
18. The method ofclaim 17 , wherein the respective line pad disposed on the source is coupled to a storage capacitor of the DRAM cell, and wherein the gate electrode forms a word line for the DRAM cell.
19. The method ofclaim 11 , further comprising:
forming a gate capping layer on the gate electrode; and
forming spacers on sidewalls of the gate electrode and the gate capping layer.
20. The method ofclaim 11 , further comprising:
forming a STI (shallow trench isolation) structure for defining an active region having the opening formed therein.
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| US11/452,867US7534708B2 (en) | 2004-02-11 | 2006-06-14 | Recessed-type field effect transistor with reduced body effect |
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| KR2004-0009122 | 2004-02-11 | ||
| KR1020040009122AKR100593443B1 (en) | 2004-02-11 | 2004-02-11 | Transistors and Manufacturing Methods |
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| US11/452,867DivisionUS7534708B2 (en) | 2004-02-11 | 2006-06-14 | Recessed-type field effect transistor with reduced body effect |
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| US11/051,834AbandonedUS20050173744A1 (en) | 2004-02-11 | 2005-02-04 | Recessed-type field effect transistor with reduced body effect |
| US11/452,867Expired - LifetimeUS7534708B2 (en) | 2004-02-11 | 2006-06-14 | Recessed-type field effect transistor with reduced body effect |
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| US11/452,867Expired - LifetimeUS7534708B2 (en) | 2004-02-11 | 2006-06-14 | Recessed-type field effect transistor with reduced body effect |
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Also Published As
| Publication number | Publication date |
|---|---|
| US7534708B2 (en) | 2009-05-19 |
| KR100593443B1 (en) | 2006-06-28 |
| US20060234437A1 (en) | 2006-10-19 |
| KR20050080940A (en) | 2005-08-18 |
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