US20050116290A1 - Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers - Google Patents

Abstract

A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

Description

FIELD OF THE INVENTION
• The present invention relates to high-performance complementary metal oxide semiconductor (CMOS) circuits in which carrier mobility is enhanced by utilizing different semiconductor surface orientations for p-type field effect transistors (FETs) and n-type FETs. More particularly, the present invention relates to methods for fabricating planar substrate structures with different surface crystal orientations, and to the hybrid-orientation substrate structures produced by such methods.
BACKGROUND OF THE INVENTION
• The CMOS circuits of current semiconductor technology comprise n-type FETs (nFETs), which utilize electron carriers for their operation, and p-type FETs (pFETs), which utilize hole carriers for their operation. CMOS circuits are typically fabricated on semiconductor wafers having a single crystal orientation. In particular, most of today's semiconductor devices are built on Si having a (100) surface orientation.
• It is known that electrons have a high mobility in Si with a (100) surface orientation and that holes have high mobility in Si with a (110) surface orientation. In fact, hole mobility can be about 2 to 4 times higher on a110-oriented Si wafer than on a standard100-oriented Si wafer. It would therefore be desirable to create a hybrid-orientation substrate comprising100-oriented Si (where nFETs would be formed) and110-oriented Si (where pFETs would be formed).
• Planar hybrid substrate structures with different surface orientations have been described previously (see, for example, co-assigned U.S. application Ser. No. 10/696,634, filed Oct. 29, 2003, and co-assigned U.S. application Ser. No. 10/250,241, filed Jun. 17, 2003).
• FIGS. 1A-1E show, in cross section view, some prior art examples of planar hybrid-orientation semiconductor substrate structures comprisingbulk semiconductor substrate10, dielectrictrench isolation regions20,semiconductor regions30 with a first surface orientation (e.g., j′k′l′), andsemiconductor region40 with a second surface orientation (e.g., jkl). In the structure ofFIG. 1A,semiconductor regions30 and40 are both directly onbulk substrate10, withsemiconductor region40 andbulk substrate10 having the same orientation. The structure ofFIG. 1B differs from that ofFIG. 1A only in thatsemiconductor regions30 are on buried oxide (BOX)layer50 instead of directly onbulk substrate10. The structures ofFIGS. 1C-1E differ from those ofFIGS. 1A-1B by the thickness ofBOX layers50 and50′ and by the depth oftrench isolation structures20 and20′.
• FIGS. 2A-2B show, in cross section view, previous examples of how integrated CMOS circuits comprising at least one pFET on a (110) crystallographic plane of Si and at least one nFET on a (100) crystallographic plane of Si may be advantageously disposed on the hybrid-orientation substrate structure ofFIG. 1B. InFIG. 2A, abulk Si substrate120 with100 orientation hasregions130 of110-oriented Si onBOX layer140, andregions150 of regrown100-oriented Si onbulk substrate120.pFET devices170 are disposed on110-orientedregions130 andnFET devices180 are disposed on100-orientedregions150. InFIG. 2B, abulk Si substrate180 with110 orientation hasregions190 of100-oriented Si on aBOX layer140 andregions200 of regrown110-oriented Si onbulk substrate180.pFET devices210 are disposed on110-orientedregions180 andnFET devices220 are disposed on100-orientedregions190.
• FIGS. 3A-3I show, in cross section view, the steps of a prior art method used to form the structure of FIG1B. Specifically,FIG. 3A shows the startingSi substrate250, andFIG. 3B showssubstrate250 after formation ofBOX layer260 and silicon-on-insulator (SiOI)device layer270.Si substrate250 may be110- (or100-) oriented, andSiOI device layer270 would be100- (or110-) oriented. SiOIlayer270 may be formed by bonding or other methods. After depositing protective dielectric (preferably SiN_x)layer280 to form the structure ofFIG. 3C,SiOI device layer270 andBOX layer260 are removed in selected areas to formopenings290 extending toSi substrate250, as shown inFIG. 3D.Openings290 are lined with a dielectric (preferably SiN_x) which is then etched to formsidewall spacers300, as shown inFIG. 3E. Next,epitaxial Si310 is selectively grown inopenings290 to produce the structure ofFIG. 3F, which is planarized back to form the structure ofFIG. 3G. Protective dielectric280 is then removed by a process such as polishing to form the structure ofFIG. 3H with coplanar, differently oriented Si device layers310 (on bulk Si substrate250) and320 (on BOX layer260).FIG. 3I shows the completed substrate structure after shallowtrench isolation areas330 have been formed in the structure ofFIG. 3H.
• However, for many applications, it would be desirable to have both of the differently oriented Si regions on a BOX. Such structures are possible, but not easy, to produce by variations of the method ofFIGS. 3A-3I. For example, the structure ofFIG. 4 may be produced by replacingSi substrate250 inFIG. 3A with aSiOI substrate400 comprisingsubstrate410,BOX layer420, andSi layer430 to produce differently orientedsingle crystal regions320 with a first orientation and440 with a second orientation matching that ofsemiconductor layer430. However, the use of two BOX layers adds extra complexity to the process and produces structures where one of the hybrid orientations is significantly thicker than the other (a disadvantage when both layers need to be thin). In addition, selective epitaxial Si growth can be tricky; defects are likely to nucleate on the sides of sidewall spacers300 (shown inFIGS. 3E-3F), especially whenopenings290 are small (e.g., less than 500 nm in diameter).
• In view of the above, it would be desirable to have simpler and better methods (i.e., those that do not require epitaxial regrowth) to form planar hybrid-orientation semiconductor substrate structures, especially planar hybrid-orientation semiconductor-on-insulator (SOI) substrate structures wherein the differently oriented semiconductors are disposed on a common BOX layer.
• In addition, it would be desirable to have integrated electrical circuits on such planar hybrid-orientation SOI substrates wherein the electrical circuits comprise pFETs on a (110) crystallographic plane and nFETs on a (100) crystallographic plane.
SUMMARY OF THE INVENTION
• It is therefore an object of the present invention to provide a planar hybrid-orientation SOI substrate structure with a surface comprising at least two clearly defined single-crystal semiconductor regions with different surface orientations, wherein the differently oriented semiconductor regions are disposed on a common BOX layer. The term “clearly defined” is used herein to denote that the surface regions of a given surface orientation are macroscopic and not merely single grains of polycrystalline Si.
• It is a related object of the present invention to provide methods for fabricating such a planar hybrid-orientation semiconductor substrate structure.
• It is a further object of the present invention to provide methods for fabricating similar hybrid-orientation semiconductor substrate structures on a variety of support layers.
• It is yet another object of the present invention to provide integrated circuits (ICs) on the hybrid-orientation substrates of the present invention, wherein the ICs comprise pFETs on a (110) crystallographic plane and nFETs on a (100) crystallographic plane.
• In accordance with the above listed and other objects, new methods are provided for forming a variety of planar hybrid-orientation semiconductor substrate structures. Common to all methods are three basic steps, by which the orientation of selected semiconductor regions may be changed from an original orientation to a desired orientation:
• • forming a bilayer template layer stack comprising a first, lower single crystal semiconductor layer (or substrate) having a first orientation and a second, upper (typically bonded) single crystal semiconductor layer having a second orientation different from the first;
  • amorphizing one of the layers of the bilayer template stack in selected areas (by ion implantation through a mask, for example) to form localized amorphized regions; and
  • recrystallizing the localized amorphized regions using the non-amorphized layer of the stack as a template, thereby changing the orientation in the localized amorphized regions from an original orientation to a desired orientation.
• To minimize the possibility of lateral templating, the sides of the regions selected for amorphization and templated recrystallization would typically be isolated from adjacent crystalline regions, for example, by trenches. The trenches may be formed and filled before amorphization, formed and filled between amorphization and recrystallization, or formed after amorphization and filled after recrystallization.
• In one embodiment of the present invention, the basic steps above are incorporated into a method for forming a planar hybrid-orientation SiOI substrate structure. A100-oriented Si substrate is used for the first, lower layer of the bilayer template stack and a110-oriented Si layer for the second, upper layer of the bilayer template stack. The uppermost portion of the template stack is amorphized in selected areas to a depth that ends in the underlying100-oriented Si substrate. The amorphized Si regions are then recrystallized into100-oriented Si, using the underlying100-oriented Si as a template. Following these steps of patterned amorphization and recrystallization, which leave surface regions of100-oriented Si in the treated areas and surface regions of110-oriented Si in the untreated areas, a buried oxide (BOX) layer is formed by oxygen implantation and annealing (e.g., a “Separation by Implantation of Oxygen” or SIMOX process).
• In another embodiment of the present invention, the basic steps above are incorporated into a another method to form a planar hybrid-orientation SiOI substrate structure. In this method, a110-oriented SiOI layer on a BOX layer is used for the first, lower layer of a bilayer template stack, and a100-oriented Si layer is used for the second, upper layer of a bilayer template stack. The lowermost portion of the bilayer template stack is then amorphized in selected areas from the BOX layer up to a depth ending in the upper template layer. The amorphized Si regions are then recrystallized into100-orientated Si, using the upper100-oriented Si layer as a template. The uppermost portion of the bilayer template is then removed by a process such as polishing to leave coplanar surface regions of110-oriented Si (in the untreated areas) and100-oriented Si (in the treated areas).
• The basic steps of the present invention can be easily adapted in whole or in part to form planar hybrid-orientation semiconductor structures on different substrates (e.g., bulk, thin or thick BOX, insulating or high resistivity substrates), or to form planar hybrid-orientation semiconductor substrate structures having three or more surface orientations.
• Yet another aspect of the present invention provides integrated circuits on the planar hybrid-orientation semiconductor substrates of this invention, wherein the integrated circuits comprise pFETs on a (110) crystallographic plane and nFETs on a (100) crystallographic plane.
BRIEF DESCRIPTION OF THE DRAWINGS
• These and other features, aspects, and advantages will be more readily apparent and better understood from the following detailed description of the invention, in which:
• FIGS. 1A-1E show, in cross section view, some examples of prior art planar hybrid-orientation semiconductor substrate structures, wherein the first of two semiconductor orientations is disposed directly on a bulk semiconductor substrate and the second of two semiconductor orientations is disposed either on the substrate (FIGS. 1A and 1C), partially insulated from the substrate by a thin BOX layer (FIG. 1E), or fully insulated from the substrate by a thick BOX layer (FIGS.1B and1D);
• FIGS. 2A-2B show, in cross section view, prior art examples of how the hybrid-orientation substrate structure ofFIG. 1B might form the basis of integrated circuits comprising at least one pFET on a110-oriented single crystal Si region and at least one nFET on a100-oriented single crystal Si region;
• FIGS. 3A-3I show, in cross section view, the steps of the basic prior art method used to form the structures ofFIGS. 1A-1E, illustrated for the case ofFIG. 1B;
• FIG. 4 shows, in cross section view, a prior art example of a planar hybrid-orientation semiconductor substrate structure wherein both of two differently oriented single crystal Si regions are disposed on buried insulator layers;
• FIGS. 5A-5B show, in cross section view, two preferred SOI embodiments of the hybrid-orientation substrates of the present invention;
• FIG. 6 shows, in cross section view, how a hybrid-orientation substrate structure of the present invention can be used to form the basis of an integrated circuit comprising at least one pFET on a (110) Si crystallographic plane and at least one nFET on a (100) Si crystallographic plane.
• FIGS. 7A-7G show, in cross section view, the basic steps underlying the methods of the present invention, illustrated for the case of upper layer amorphization and lower layer templating;
• FIGS. 8A-8G show, in cross section view, a first preferred method to produce the structure ofFIG. 5A of the present invention;
• FIG. 9A-9F show, in cross section view, a second preferred method to produce the structure ofFIG. 5B of the present invention; and
• FIGS. 10A-10I show, in cross section view, different embodiments of the hybrid-orientation substrates that may be produced by the methods of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
• The present invention, which provides planar hybrid-orientation SOI substrate structures and methods of fabricating the same, will now be described in greater detail by referring to the drawings that accompany the present application.
• FIGS. 5A-5B show, in cross section view, two preferred embodiments of hybrid-orientation substrates that can be fabricated by the methods of the present invention. Hybrid-orientation substrate450 ofFIG. 5A and hybrid-orientation substrate460 ofFIG. 5B both comprise first singlecrystal semiconductor regions470 with a first orientation, and second singlecrystal semiconductor regions480 with a second orientation different from the first orientation.Semiconductor regions470 and480 have approximately the same thickness and are disposed on thesame BOX layer490. The term “BOX” denotes a buried oxide region. Although this terminology is specifically used here, the present invention is not limited to merely buried oxides. Instead, various insulating layers can be used; the various insulating layers are described in greater detail hereinbelow.
• Semiconductor regions470 and480 are separated by dielectrictrench isolation regions500, which are shown as having the same depth and stopping onBOX layer490. However, in some embodiments of the present invention,trench isolation regions500 may be shallower (so as not to reach BOX layer490), deeper (so as to extend past BOX layer490), or of non-equal depths, as desired. The structures ofFIGS. 5A and 5B differ from each other only in the particulars ofsubstrates510 and520.Substrate510 inFIG. 5A is a semiconductor having an epitaxial relationship to singlecrystal semiconductor region480, whereassubstrate520 inFIG. 5B has no particular restrictions other than being compatible with whatever subsequent processing it will be subjected to.
• The hybrid-orientation substrate structures ofFIGS. 5A-5B may be incorporated as the substrates for integrated circuits comprising at least one pFET on a (110) crystallographic plane and at least one nFET on a (100) crystallographic plane.FIG. 6 illustrates an exemplary integrated circuit on a Si version of the hybrid-orientation substrate structure ofFIG. 5B, in cross section view.Substrate520 has single crystal110-orientedSi regions530 and single crystal100-orientedSi regions540, separated byisolation regions500 onBOX layer490.pFET devices170 are disposed on110-orientedregions530 andnFET devices180 are disposed on100-orientedregions540. For clarity, dopings are not shown.
• The FETs shown inFIG. 6 can be fabricated on the structure shown inFIG. 5A using techniques that are well known to those skilled in the art. In some embodiments, the110 and100 crystal orientations oflayers540 and530 are reversed. In that embodiment, thepFET devices170 would still be fabricated atop the110-oriented regions and thenFET devices180 would be fabricated atop the100-oriented surface.
• The present invention also provides new methods for forming planar hybrid-orientation semiconductor substrate structures. Common to all methods are three basic steps, by which the orientation of selected semiconductor regions may be changed from an original orientation to a desired orientation:
• • forming a bilayer template layer stack comprising a first, lower single crystal semiconductor layer (or substrate) having a first orientation and a second, upper (typically bonded) single crystal semiconductor layer having a second orientation different from the first;
  • amorphizing one of the layers of the bilayer template stack in selected areas (by ion implantation through a mask, for example) to form localized amorphized regions; and
  • recrystallizing the localized amorphized regions using the non-amorphized layer of the stack as a template, thereby changing the orientation in the localized amorphized regions from an original orientation to a desired orientation.
• These steps are illustrated inFIGS. 7A-7D for the case of upper layer amorphization and bottom layer templating. Although this embodiment is shown, the present invention also contemplates methods in which the bottom layer is amorphized and recrystallization is templated from the top layer.
• FIG. 7A showsinitial SOI substrate580 comprisingbase substrate520,BOX layer490, and singlecrystal SOI layer590 with a first orientation.SOI layer590 may be formed by bonding or by any other method known to the art.FIG. 7B showsbilayer template stack600 comprisingSOI layer590 as a lower template layer with a first orientation and singlecrystal semiconductor layer610 as an upper template layer with a second orientation different from the first orientation.Layer610 would typically be formed by bonding.FIG. 7C shows the structure ofFIG. 7B afterion bombardment620 in selected areas creates localizedamorphized regions630. Localizedamorphized regions630 extend from the top surface ofupper template layer610 down tointerface640, located withinlower template layer590. Selectedarea ion bombardment620 would typically be effected by blanket ion bombardment in combination with a patterned mask.FIG. 7D shows the structure ofFIG. 7C after localizedamorphized regions630 have been recrystallized (starting atinterface640, usinglower layer590 as a template) to form singlecrystal semiconductor region650. Non-amorphized uppertemplate layer regions610′ (with the second crystal orientation) and recrystallized region650 (with the first crystal orientation) now comprise planar hybrid-orientation substrate650 with surface A-B comprising at least two clearly defined single-crystal semiconductor regions with different surface orientations.
• To minimize the possibility of lateral templating, the sides of the region(s)630 selected for amorphization and templated recrystallization would typically be at least partially isolated from adjacent crystalline regions, for example, by trenches. The trenches may be formed and filled before amorphization, formed and filled between amorphization and recrystallization, or formed after amorphization and filled after recrystallization. Trench formation would typically be effected by a process such as reactive ion etching (RIE) through a mask.
• FIGS. 7E-7G show examples of three geometries for isolation trenches. InFIG. 7E,isolation trenches660 extend through the upper template layer, but do not extend past the amorphization depth. In this case, some templating fromside interfaces670 may occur. InFIG. 7F,isolation trenches680 extend past the amorphization depth, but not all the way to BOXlayer490, and inFIG. 7G,isolation trenches690 extend all the way to BOXlayer490. However, isolation trenches may not be necessary if the recrystallization rate of the desired crystal orientation is much faster than recrystallization templated from competing undesired crystal orientations. For example, the recrystallization rates of Si-implant-amorphized single crystal Si samples has been reported to be three times faster for100-oriented Si than for110-oriented Si [see, for example, L. Csepregi et al., J. Appl. Phys. 49 3096 (1978)].
• The fact that different semiconductor orientations can differ in their recrystallization rates should also be considered when designing the template layer stacks and process flows. The layer of a bilayer template stack having the slower-growing orientation would preferably be the one that is amorphized, whereas the layer with the faster-growing orientation would preferably be the one from which the recyrstallization is templated.
• In one embodiment of the invention, shown inFIGS. 8A-8G, the basic steps ofFIGS. 7A-7D are incorporated into a method for forming a planar hybrid-orientation SiOI substrate structure similar to structure450 ofFIG. 5A. For simplicity, isolation trenches are not shown.FIG. 8A shows100-orientedSi substrate700 comprising the first, lower layer of the template stack;FIG. 8B shows thesubstrate700 after addition of110-orientedSi layer710 comprising the second, upper layer of the template stack.Layer710 would typically be formed by bonding.
• FIG. 8C shows the structure ofFIG. 8B being subjected toion bombardment720 in selected areas to create the structure ofFIG. 8D with localizedamorphized regions730 extending from the top surface oftemplate layer710 to a depth ending insubstrate700.FIG. 8E shows the structure ofFIG. 8D after localizedamorphized regions730 have been recrystallized (using100-orientedSi substrate700 as a template) to form single crystal100-oriented Si region(s)740. Non-amorphized110-orientedSi regions710′ and recrystallized100-oriented Si region(s)740 now comprise bulk planar hybrid-orientation substrate750 with surface A-B comprising at least two clearly defined single-crystal semiconductor regions with different surface orientations.
• A SIMOX process is then used to create a BOX layer, as shown inFIGS. 8F-8G.FIG. 8F shows the structure ofFIG. 8E being exposed to blanketoxygen ion implantation760 used to create buried O-rich layer770. O-rich layer770 preferably contains the original interface betweenlayers700 and710, and is converted intoBOX layer780 ofFIG. 8G by the appropriate annealing steps.
• In another embodiment of the present invention, shown inFIGS. 9A-9F, the basic steps ofFIGS. 7A-7D are incorporated into yet another method to form a planar hybrid-orientation SiOI substrate structure similar to structure460 ofFIG. 5B. Specifically,FIG. 9A showsinitial SiOI substrate800 comprisingbase substrate520,BOX layer490, and110-oriented singlecrystal Si layer810.Si layer810 may be formed by bonding or by any other method known to the art.FIG. 9B showsbilayer template stack820 comprising110-orientedSi layer810 as a lower template layer and single crystal100-orientedSi layer830 as an upper template layer.Layer830 would typically be formed by bonding.FIG. 9C shows the structure ofFIG. 9B being subjected toion bombardment840 in selected areas to create the structure ofFIG. 9D with buried localizedamorphized regions850. Localizedamorphized regions850 extend fromBOX layer490 throughlower template layer810 and partially intoupper template layer830. As mentioned above, the areas selected for amorphization and templated recrystallization would typically be isolated from adjacent crystalline regions by trenches (not shown) to minimize the possibility of lateral templating.FIG. 9E shows the structure ofFIG. 9D after localizedamorphized regions850 have been recrystallized, usingupper template layer810 as a template, to form100-oriented singlecrystal Si regions860.Upper template layer810 is then removed by a process such as polishing (or oxidation followed by wet etchback) to leave coplanar110-oriented single-crystal Si regions810′ and100-oriented single-crystal Si regions860 disposed oncommon BOX layer490.
• It should be noted that the method ofFIGS. 8A-8G may equally well be employed with the orientations ofsubstrate700 andupper template layer710 reversed, i.e., withsubstrate700 comprising a110-oriented Si wafer instead of a100-oriented Si wafer, andupper template layer710 comprising a single crystal layer of100-oriented Si instead of a single crystal layer of110-oriented Si. Likewise, the method ofFIGS. 9A-9F may be employed with the orientations oflower template layer810 andupper template layer830 reversed, i.e., withlower template layer810 being100-oriented Si instead of110-oriented Si andupper template layer830 being110-oriented Si instead of100-oriented Si. More generally, the structures and methods of the present invention may be employed using semiconductors other than Si, as will be described in more detail below.
• FIGS. 10A-10I show, in cross section view, different embodiments of the hybrid-orientation substrates that may be produced by the methods of the present invention.FIG. 10A shows “bulk” planar hybrid-orientationsemiconductor substrate structure900 comprising first singlecrystal semiconductor regions910 with a first orientation, and second singlecrystal semiconductor regions920 with a second orientation different from the first orientation, but identical to the orientation ofsubstrate930. Planar hybrid-orientationsemiconductor substrate structure940 ofFIG. 10B is similar to structure900 ofFIG. 10A, but hastrench isolation regions950 separating singlecrystal semiconductor regions910 and920.
• Planar hybrid-orientationsemiconductor substrate structure960 ofFIG. 10C is similar to structure900 ofFIG. 10A. However,substrate930 has been replaced withsubstrate980, which may or not be epitaxially related tosemiconductor region920.Structure960 also comprisesBOX layer970 undersemiconductor regions910 and920, andresiduals990 of second semiconductor material with the second orientation remaining underfirst semiconductor regions910. Planar hybrid-orientationsemiconductor substrate structure1000 ofFIG. 10D is similar to structure960 ofFIG. 10C, except thatsemiconductor region920 is epitaxially related tosemiconductor substrate930, andBOX layer970 is located aboveinterface1010 between first singlecrystal semiconductor regions910 andsubstrate930.
• Planar hybrid-orientationsemiconductor substrate structures1020 and1030 ofFIGS. 10E-10F are identical tostructures1000 and940 ofFIGS. 10A-10B, except thatsemiconductor substrate930 has been replaced by insulatingsubstrate1040.
• Planar hybrid-orientationsemiconductor substrate structures1050 and1060 ofFIGS. 10G-10H are similar to structure960 ofFIG. 10C, but havetrench isolation regions950. Instructure1050 ofFIG. 10G,trench isolation regions950 extend belowinterface1070 between first singlecrystal semiconductor regions910 andresiduals990, but do not reachBOX layer970. Instructure1060 ofFIG. 10H,trench isolation regions950 extend to BOXlayer970.
• Planar hybrid-orientationsemiconductor substrate structure1080 ofFIG. 10I comprises three differently oriented singlecrystal semiconductor regions910,920, and1090, separated bytrench isolation regions950 extending toBOX layer970. Planar hybrid-orientation semiconductor substrate structures with three or more surface orientations may be produced by the localized amorphization and recrystallization methods of this invention by using a multilayer template stack instead of a bilayer template stack.
• Structures like those ofFIGS. 5A-5B andFIGS. 10A-10I may be produced by using various permutations of the basic steps of the invention with or without additional steps. For example, a planar hybrid-orientation structure resembling460 ofFIG. 5B may be produced from the structure ofFIG. 10H by the additional steps ofamorphizing residuals990 ofsecond semiconductor material920 and recrystallizing the amorphized regions usingsingle crystal region910 as a template.
• The semiconductor substrates and single crystal semiconductor regions of the present invention may be selected from a wide range of semiconductor materials. For example,substrates510,520,700,930 and980, and differently oriented first andsecond semiconductor regions470,610′,910, and480,650, and920 may be selected from the group including Si, SiC, SiGe, SiGeC, Ge alloys, Ge, C, GaAs, InAs, InP as well as other III-V or II-VI compound semiconductors. Layered combinations or alloys of the aforementioned semiconductor materials (for example, Si layers on SiGe), with or without one or more dopants, are also contemplated herein. First and second semiconductor regions may be strained, unstrained, or a combination of strained and unstrained layers can be used. The crystallographic orientations would typically be selected from the group including (110), (111), and (100).
• The thickness of first and second singlecrystal semiconductor regions470,610′,910, and480,650, and920 is typically from about 1 to about 500 nm, with a thickness from about 10 to about 100 nm being more typical. The thickness ofsubstrates510,520,700,930, and980 would typically be between 5 and 1000 μm, and most typically be about 600 μm.
• BOX layers and insulatingsubstrates1040 may be selected from a wide range of dielectric materials, including, but not limited to the group including SiO₂, crystalline SiO₂, SiO₂containing nitrogen or other elements, silicon nitrides, metal oxides (e.g., Al₂O₃), insulating metal nitrides (e.g., AlN), highly thermally conductive materials such as crystalline diamond. BOX thicknesses may range from about 2 nm to about 500 nm, with preferable thicknesses typically being in the range from about 50 to about 150 nm.
• Bonding methods for forming the template stack may include any methods known to those skilled in the art (see, for example, Q. Y. Tong et al. [inSemiconductor Wafer Bonding: Science and Technology(John Wiley, 1998)] and co-pending and co-assigned U.S. application Ser. No. 10/696,634, filed Oct. 29, 2003, and co-pending and co-assigned U.S. application Ser. No. 10/250,241, filed Jun. 17, 2003). The contents of each of the above mentioned co-assigned U.S. applications are incorporated herein by reference.
• Differently oriented semiconductor surfaces to be bonded are preferably hydrophobic (rather than hydrophilic) for the cleanest possible interfaces, since impurities in the amorphized regions will typically impede the progress of the recrystallization. However, very thin oxides at the bonded interface may be tolerable if the oxide can be made to assume a discontinuous, islanded morphology by suitable annealing (see, for example, P. McCann et al. [“An investigation into interfacial oxide in direct silicon bonding,” 6th Int. Symp. on Semiconductor Wafer Bonding, San Francisco, Sep. 2-7, 2001]). Wafer separation/removal after bonding may be accomplished by grinding or etching the wafer away (preferably making use of an etch stop layer), or by making use of a mechanically weak interface layer created at earlier steps in processing. Examples of mechanically weak interface layers include porous Si (see, for example, Epitaxial Layer Transfer (ELTRAN) described by K. Sakaguchi et al. in Solid State Technology, June 2000] and ion-implanted H-containing bubbles (see, for example, Smart Cut process, described in U.S. Pat. No. 5,374,564 by M. Bruel, which issued Dec. 20, 1994, and U.S. Pat. No. 5,882,987 by K. V. Srikrishnan, which issued Mar. 16, 1999).
• Amorphization would typically be effected by ion implantation. The optimum ion implantation conditions will depend on the materials of the template layers, the thickness of the template layers, and position (upper or lower) of the stack layer being amorphized. Any ion species known to those skilled in the art may be used, including but not limited to: Si, Ge, Ar, C, O, N, H, He, Kr, Xe, P, B, As, etc. Ions for the amorphization are preferably Si or Ge. Lighter ions such as H and He are typically less effective at amorphization. Ion implantation may be performed at temperatures ranging from cryogenic to several hundred ° C. above nominal room temperature. By “nominal room temperature” it is meant a temperature from about 20° to about 40° C. Regions not being amorphized would typically be protected from ion implantation by a patterned mask (for example, patterned photoresist for a room temperature implantation process). Implants may be performed with or without “screen oxide” layers and may be performed with multiple implants at different energies if a sufficiently uniformly amorphized region cannot be easily achieved with a single implant. The required implant dose depends on the implanting species, the semiconductor being implanted, and the thickness of the layer needing to be amorphized. Si implanted at cryogenic temperatures at 50, 100, 150, and 200 keV with a total dose of 6E15/cm²was found to be sufficient to amorphize the top 400 nm of100-oriented and110-oriented Si (see, for example, L. Csepregi et al.). However, much lower doses (for example, 5E14/cm²at 40 keV) can amorphize Si when the implanted ion is Ge and surface region to be amorphized is thinner than 50-100 nm.
• Recrystallization of localizedamorphous regions630,730, and850 is typically effected by annealing at temperatures from about 200° to about 1300° C., preferably from about 400° to about 900° C., and more preferably from about 400° and 600° C., for a time period sufficient to bring about the desired recrystallization. This time period will depend on the orientation of the template layer, on the thickness of the amorphized region to be recrystallized, on the presence of implanted and other impurities in the amorphized layer, and possibly on the sharpness of the interface between the implanted and unimplanted regions. Annealing may be performed in a furnace or by rapid thermal annealing. In other embodiments, annealing may be performed using a laser anneal or a spike anneal. The annealing ambient would typically be selected from the group of gases including N₂, Ar, He, H₂and mixtures of these gases.
• When a buried insulating is created in the structure following the recrystallizing step, any conventional ion implant step and annealing step that can be used in forming a buried insulating layer can be employed. For example, any conventional SIMOX process can be used in producing a buried oxide layer in the structures shown inFIGS. 8F-8G.
• Several embodiments of the present invention, together with modifications thereof, have been described in detail herein and illustrated in the accompanying drawings, it will be evident that various further modifications are possible without departing from the scope of the invention. In particular, it should be emphasized that while most of the substrate structures, circuits, and methods of this invention have been illustrated for the case of a small number of single crystal regions having two different orientations, the invention applies equally well to methods for providing and structures comprising large pluralities of such single crystal regions. Furthermore, the hybrid-orientation substrates of the invention may incorporate additional overlayers (such as epitaxially grown semiconductors or additional bonded layers), removal or etchback of certain surface features (for example, recessing one or more of the single crystal semiconductor regions or trench isolations), and/or specialized doping profiles, if such substrate features are desired for the subsequently fabricated devices. Nothing in the above specification is intended to limit the invention more narrowly than the appended claims. The examples given are intended only to be illustrative rather than exclusive.

Claims (55)

1. A planar hybrid-orientation semiconductor-on-insulator (SOI) substrate structure comprising:

at least two clearly defined single crystal semiconductor regions with different surface orientations, said at least two clearly defined single crystal semiconductor regions disposed on a common buried insulating layer, said common buried insulating layer disposed on a substrate.

2. The planar hybrid-orientation SOI substrate structure ofclaim 1 further comprising at least one isolation region separating said at least two clearly defined single crystal semiconductor regions from each other.

3. The planar hybrid-orientation SOI substrate structure ofclaim 2 wherein said at least one isolation region is a trench isolation region.

4. The planar hybrid-orientation SOI substrate structure ofclaim 2 wherein said at least one isolation region extends down to at least an upper surface of the common buried insulating layer.

5. The planar hybrid-orientation SOI substrate structure ofclaim 2 wherein said at least one isolation region does not extend down to said common buried insulating layer.

6. The planar hybrid-orientation SOI substrate structure ofclaim 1 wherein said at least two clearly defined single crystal semiconductor regions comprise the same or different semiconductor materials.

7. The planar hybrid-orientation SOI substrate structure ofclaim 6 wherein said semiconductor materials are selected from the group consisting of Si, SiC, SiGe, SiGeC, Ge alloys, Ge, C, GaAs, InAs, InP, layered combinations or alloys thereof, and other III-V or II-VI compound semiconductors.

8. The planar hybrid-orientation SOI substrate structure ofclaim 1 wherein said at least two clearly defined single crystal semiconductor regions with different surface orientations both comprise a Si-containing semiconductor material.

9. The planar hybrid-orientation SOI substrate structure ofclaim 1 wherein said at least two clearly defined single crystal semiconductor regions are each comprised of strained, unstrained or a combination of strained and unstrained semiconductor materials.

10. The planar hybrid-orientation SOI substrate structure ofclaim 1 wherein said different surface orientations are selected from the group consisting of (110), (111) and (100).

11. The planar hybrid-orientation SOI substrate structure ofclaim 8 wherein said different surface orientations are selected from the group consisting of (110), (111) and (100).

12. The planar hybrid-orientation SOI substrate structure ofclaim 11 wherein said first Si-containing semiconductor region has a (100) crystal orientation and said second Si-containing semiconductor region has a (110) crystal orientation.

13. The planar hybrid-orientation SOI substrate structure ofclaim 12 further comprising at least one nFET device and at least one pFET device, wherein said at least one nFET device is located on said (100) crystal orientation and said at least pFET device is located on said (110) crystal orientation.

14. The planar hybrid-orientation SOI substrate structure ofclaim 1 further comprising at least one nFET device and at least one pFET device, wherein said at least one nFET device is located on a crystal orientation that is optimal for said device said at least pFET device is located on a crystal orientation that is optimal for said device.

15. The planar hybrid-orientation SOI substrate structure ofclaim 1 wherein said buried insulating layer is a dielectric material selected from the group consisting of SiO₂, crystalline SiO₂, SiO₂containing nitrogen, silicon nitride, metal oxides, metal nitrides, and highly thermally conductive materials.

16. The planar hybrid-orientation SOI substrate structure ofclaim 15 wherein said dielectric material is SiO₂or crystalline SiO₂.

17. The planar hybrid-orientation SOI substrate structure ofclaim 1 wherein said substrate is a semiconductor material selected from the group consisting of Si, SiC, SiGe, SiGeC, Ge alloys, Ge, C, GaAs, InAs, InP, layered combinations or alloys thereof, and other III-V or II-VI compound semiconductors.

18. The planar hybrid-orientation SOI substrate structure ofclaim 1 wherein said substrate has an epitiaxial relationship to at least one of said single crystal semiconductor regions.

19. The planar hybrid-orientation SOI substrate structure ofclaim 1 wherein said at least two clearly defined single crystal semiconductor regions comprise three single crystal semiconductor regions of different crystal orientation that are separated by isolation regions.

20. The planar-hybrid-orientation SOI substrate structure ofclaim 19 further comprising at least one nFET device and at least one pFET device, wherein said at least one nFET device is located on a crystal orientation that is optimal for said device said at least pFET device is located on a crystal orientation that is optimal for said device.

21. The planar-hybrid-orientation SOI substrate structure ofclaim 1 wherein at least one of said at least two clearly defined single crystal regions comprises an upper semiconductor disposed on a lower, residual semiconductor, said upper and lower semiconductors having different surface orientations, said residual semiconductor in direct contact with said common buried insulating layer.

22. The planar-hybrid-orientation SOI substrate structure ofclaim 21 further comprising at least one nFET device and at least one pFET device, wherein said at least one nFET device is located on a crystal orientation that is optimal for said device said at least pFET device is located on a crystal orientation that is optimal for said device.

23. The planar hybrid-orientation SOI substrate structure ofclaim 21 further comprising at least one isolation region separating said at least two clearly defined single crystal semiconductor regions from each other, wherein said at least one isolation region extends down at least to said common buried insulating layer.

24. The planar hybrid-orientation SOI substrate structure ofclaim 21 further comprising at least one isolation region separating said at least two clearly defined single crystal semiconductor regions from each other, wherein said at least one isolation region does not extend down to said common buried insulating layer.

25. The planar hybrid-orientation SOI substrate structure ofclaim 1 wherein said substrate is an insulator.

26. The planar hybrid-orientation SOI substrate structure ofclaim 8 wherein at least one of said at least two clearly defined single crystal Si-containing semiconductor regions comprises an upper Si-containing semiconductor disposed on a lower, residual Si-containing semiconductor, said upper and lower semiconductors having different surface orientations, said residual semiconductor in direct contact with said common buried oxide layer.

27. The planar hybrid-orientation SOI substrate structure ofclaim 26 wherein said different surface orientations are selected from the group consisting of (110), (111) and (100).

28. The planar hybrid-orientation SOI substrate structure ofclaim 27 wherein first Si-containing semiconductor region has a (100) crystal orientation and said second Si-containing semiconductor region has a (110) crystal orientation.

29. The planar hybrid-orientation SOI substrate structure ofclaim 28 further comprising at least one nFET device and at least one pFET device, wherein said at least one nFET device is located on said (100) crystal orientation and said at least pFET device is located on said (110) crystal orientation.

30. The planar hybrid-orientation SOI substrate structure ofclaim 26 further comprising at least one nFET device and at least one pFET device, wherein said at least one nFET device is located on a crystal orientation that is optimal for said device said at least pFET device is located on a crystal orientation that is optimal for said device.

31. The planar hybrid-orientation SOI substrate structure ofclaim 26 further comprising at least one isolation region separating said at least two clearly defined single crystal Si-containing semiconductor regions from each other.

32. The planar hybrid-orientation SOI substrate structure ofclaim 31 wherein said at least one isolation region is a trench isolation region.

33. The planar hybrid-orientation SOI substrate structure ofclaim 31 wherein said at least one isolation region extends down to at least an upper surface of the common buried insulating layer.

34. The planar hybrid-orientation SOI substrate structure ofclaim 31 wherein said at least one isolation region does not extend to said common buried oxide layer.

35. A method of forming a planar hybrid-orientation substrate comprising the steps of

forming a bilayer template layer stack comprising a first, lower single crystal semiconductor layer having a first orientation and a second, upper single crystal semiconductor layer having a second orientation different from the first;

amorphizing one of the semiconductor layers of the bilayer template stack in selected areas to form localized amorphized regions; and

recrystallizing the localized amorphized regions using a non-amorphized semiconductor layer of the stack as a template, thereby changing the orientation in the localized amorphized regions from an original orientation to a desired orientation.

36. The method ofclaim 35 wherein said first, lower single crystal semiconductor layer is disposed on the insulating layer of an SOI substrate.

37. The method ofclaim 35 wherein said first, lower single crystal semiconductor layer comprises a single crystal semiconductor substrate.

38. The method ofclaim 35 wherein said second, upper single crystal semiconductor layer is formed atop the first, lower single crystal semiconductor by bonding.

39. The method ofclaim 35 wherein said localized amorphized region is formed predominately within the second, upper single crystal semiconductor layer.

40. The method ofclaim 35 wherein said localized amorphized region is formed predominately within the first, lower single crystal semiconductor layer.

41. The method ofclaim 36 wherein said localized amorphized region is formed predominately within the first, lower single crystal semiconductor layer, and further including the step of removing said top layer after recrystallization, by a process such as chemical mechanical polishing.

42. The method ofclaim 35 further comprising forming at least one trench isolation region to separate said areas selected for amorphization from those not selected for amorphization, said at least one trench isolation being formed prior to amorphizing, between amorphizing and recrystallizing, or partially after amorphizing and partially after recrystallizing.

43. The method ofclaim 35 wherein said first, lower single crystal semiconductor and layer said second, upper single crystal semiconductor layer are composed of the same or different semiconductor material selected from the group consisting of Si, SiC, SiGe, SiGeC, Ge alloys, Ge, C, GaAs, InAs, InP, layered combinations or alloys thereof, and other III-V or II-VI compound semiconductors.

44. The method ofclaim 35 wherein said first, lower single crystal semiconductor layer and said second, upper single crystal semiconductor layer are both composed of a Si-containing semiconductor material.

45. The method ofclaim 35 wherein said first, lower single crystal semiconductor layer and said second, upper single crystal semiconductor layer are composed of strained, unstrained or a combination of strained and unstrained semiconductor materials.

46. The method ofclaim 35 wherein said first, lower single crystal semiconductor layer and said second, upper single crystal semiconductor layer have different surface orientations selected from (110), (111) and (100).

47. The method ofclaim 35 further comprising forming at least one nFET device and at least one pFET device, wherein said at least one nFET device is located on a crystal orientation that is optimal for said device said at least pFET device is located on a crystal orientation that is optimal for said device.

48. The method ofclaim 37 further comprising forming a buried insulating layer after said recrystallizing step.

49. The method ofclaim 48 wherein said buried insulating layer is formed by a separation-by-ion implantation of oxygen (SIMOX) process.

50. The method ofclaim 35 wherein said amorphizing is accomplished by ion implantation.

51. The method ofclaim 50 wherein said ion implantation comprises an ion selected from the group consisting of Si, Ge, Ar, C, O, N, H, He, Kr, Xe, P, B and As.

52. The method ofclaim 50 wherein said ion implantation comprising an ion selected from the group consisting of Si and Ge.

53. The method ofclaim 50 wherein said ion implantation is performed using a patterned mask.

54. The method ofclaim 35 wherein said recrystallizing is performed at a temperature from about 200° C. to about 1300° C.

55. The method ofclaim 35 wherein said recrystallizing is performed in a gas selected from the groups consisting of N₂, Ar, He, H₂and mixtures thereof.

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