US20050087855A1 - Microelectronic component and assembly having leads with offset portions - Google Patents

Abstract

A microelectronic component comprising a dielectric layer having an opening and leads extending across the opening is disclosed. The leads have an offset portion. A method of making a microelectronic assembly comprises connecting each of the leads to a contact on a microelectronic element. A semiconductor chip assembly has a microelectronic component with an opening and leads extending across the opening. The leads are connected to contacts on a semiconductor chip and have at least one twisted portion.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 10/301,188, filed Nov. 21, 2002, which application is a continuation of U.S. patent application Ser. No. 10/164,116, filed Jun. 5, 2002, which is in turn a continuation of U.S. application Ser. No. 09/656,690, filed Sep. 7, 2000, which is in turn a continuation of U.S. patent application Ser. No. 09/488,268, filed Jan. 20, 2000, which is in turn a continuation of U.S. patent application Ser. No. 08/984,615, filed Dec. 3, 1997, which in turn is a divisional of U.S. patent application Ser. No. 08/861,280 filed May 21, 1997 which is in turn a continuation of U.S. patent application Ser. No. 08/319,966, filed on Oct. 7, 1994, now U.S. Pat. No. 5,685,885, which is in turn a continuation of U.S. patent application Ser. No. 08/030,194, filed Apr. 28, 1993 as the national phase of International Application PCTUS/91/06920 filed Sep. 24, 1991 and now U.S. Pat. No. 5,679,977. Said application Ser. No. 08/030,194 in turn is a continuation of U.S. patent application Ser. No. 07/765,928, filed Sep. 24, 1991 now U.S. Pat. No. 5,347,159. Said application Ser. No. 07/765,928 in turn was a continuation-in-part of U.S. patent application Ser. No. 07/673,020, filed Mar. 21, 1991, now U.S. Pat. No. 5,148,265 and said application Ser. No. 07/765,928 was a continuation-in-part of U.S. patent application Ser. No. 07/586,758, filed Sep. 24, 1990, now U.S. Pat. No. 5,148,266. Said application Ser. No. 08/030,194 is also a continuation-in-part of said application Ser. Nos. 07/586,758 and 07/673,020.
BACKGROUND OF THE INVENTION
• The present invention relates to the art of electronic packaging, and more specifically to assemblies incorporating semiconductor chips and to methods and components useful in making such assemblies.
• Modern electronic devices utilize semiconductor chips, commonly referred to as “integrated circuits” which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements. Such substrates may be secured to an external circuit board or chassis. Alternatively, in a so-called “hybrid circuit” one or more chips are mounted directly to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The interconnection between the chip itself and its supporting substrate is commonly referred to as “first level” assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as a “second level” interconnection.
• The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial numbers of I/O connections.
• The size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. More compact assemblies, with smaller distances between chips provide smaller signal transmission delays and hence permit faster operation of the devise.
• First level interconnection structures connecting a chip to a substrate ordinarily are subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperatures of the chip and substrate rise each time the device is turned on and fall each time the device is turned off. As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion, the chip and substrate ordinarily expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause breakage of the electrical interconnections. Thermal cycling stresses may occur even where the chip and substrate are formed from like materials having similar coefficients of thermal expansion, because the temperature of the chip may increase more rapidly than the temperature of the substrate when power is first applied to the chip.
• The cost of the chip and substrate assembly is also a major concern. All these concerns, taken together, present a formidable engineering challenge. Various attempts have been made heretofore to provide primary interconnection structures and methods to meet these concerns, but none of these is truly satisfactory in every respect. At present, the most widely utilized primary interconnection methods are wire bonding, tape automated bonding or “TAB” and flip-chip bonding.
• In wire bonding, the substrate has a top surface with a plurality of electrically conductive contact pads or lands disposed in a ring-like pattern. The chip is secured to the top surface of the substrate at the center of the ring-like pattern, so that the chip is surrounded by the contact pads on the substrate. The chip is mounted in a face-up disposition, with the back surface of the chip confronting the top surface of the substrate and with the front surface of the chip facing upwardly, away from the substrate, so that electrical contacts on the front surface are exposed. Fine wires are connected between the contacts on the front face of the chip and the contact pads on the top surface of the substrate. These wires extend outwardly from the chip to the surrounding contact pads on the substrate. In the wire-bonded assemblies, the area of the substrate occupied by the chip, the wires and the contact pads of the substrate is substantially greater than the surface area of the chip itself.
• In tape automated bonding, a polymer tape is provided with thin layers of metallic material forming conductors on a first surface of the tape. These conductors are arranged generally in a ring-like pattern and extend generally radially, towards and away from the center of the ring-like pattern. The chip is placed on the tape in a face down arrangement, with contacts on the front surface of the chip confronting the conductors on the first surface of the tape. The contacts on the chip are bonded to the conductors on the tape. Ordinarily, numerous patterns of conductors are arranged along the length of the tape and one chip is bonded to each of these individual patterns, so that the chips, once bonded to the tape, can be advanced through successive work stations by advancing the tape. After each chip is bonded to the metallic conductors constituting one pattern, the chip and the immediately adjacent portions of the pattern are encapsulated and the outermost portions of the metallic conductors are secured to additional leads and to the ultimate substrate. Tape automated bonding can provide the assembly with good resistance to thermal stresses, because the thin metallic leads on the tape surface are quite flexible, and will bend readily upon expansion of the chip without imposing significant stresses at the juncture between the lead and the contact on the chip. However, because the leads utilized in tape automated bonding extend outwardly in a radial, “fan out” pattern from the chip, the assembly is much larger than the chio itself.
• In flip-chip bonding, contacts on the front surface of the chip are provided with bumps of solder. The substrate has contact pads arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces toward the top surface of the substrate, with each contact and solder bump on the chip being positioned on the appropriate contact pad of the substrate. The assembly is then heated so as to liquify the solder and bond each contact on the chip to the confronting contact pad of the substrate. Because the flip-chip arrangement does not require leads arranged in a fan-out pattern, it provides a compact assembly. The area of the substrate occupied by the contact pads is approximately the same size as the chip itself. Moreover, the flip-chip bonding approach is not limited to contacts on the periphery of the chip. Rather, the contacts on the chip may be arranged in a so-called “area array” covering substantially the entire front face of the chip. Flip-chip bonding therefore is well suited to use with chips having large numbers of I/O contacts. However, assemblies made by flip-chip bonding are quite susceptible to thermal stresses. The solder interconnections are relatively inflexible, and may be subjected to very high stress upon differential expansion of the chip and substrate. These difficulties are particularly pronounced with relatively large chips. Moreover, it is difficult to test and operate or “burn-in” chips having an area array of contacts before attaching the chip to the substrate. Additionally, flip-chip bonding ordinarily requires that the contacts on the chip be arranged in an area array to provide adequate spacing for the solder bumps. Flip-chip bonding normally cannot be applied to chips originally designed for wire bonding or tape automated bonding, and having rows of closely spaced contacts on the periphery of the chip.
SUMMARY OF THE INVENTION
• One aspect of the present invention provides a semiconductor chip assembly. An assembly according to this aspect of the invention typically includes a semiconductor chip having a plurality of surfaces and having contacts on at least one of said surfaces. The assembly further includes a sheetlike, preferably flexible, element having terminals thereon, the terminals being electrically connected to the contacts on the chip. Assemblies according to this aspect of the invention are characterized in that the sheetlike element and at least some of said terminals overly one surface of said chip, said terminals are movable with respect to said chip and in that resilient means for permitting displacement of the terminals toward the chip, but resisting such displacement are provided. Most preferably, a compliant layer is disposed between said terminals and said chip so that said compliant layer will be compressed upon movement of said terminals toward said chip.
• The compliant layer may be incorporated in the sheetlike element, or formed separately therefrom. The contacts typically are disposed on the front or top surface of the chip. The sheetlike element and terminals may overlie said front surface of the chip. Alternatively, the sheetlike element and said terminals may overlie the rear, or bottom surface of said chip. The terminals on the sheetlike element can be connected to contact pads on a substrate, as by solder bonding. Because the terminals, and hence the contact pads on the substrate overlie the chip front or back surface, the assembly is compact. The ability of the terminals to move with respect to the chip in directions parallel to the chip surfaces provides compensation for differential thermal expansion of the chip and substrate.
• The ability to accumulate movement of the terminals towards the face of the chip greatly facilitates temporary engagement of the terminals by test equipment and hence facilitates testing and “burn-in” of the assembly before the same is mounted to a substrate. According to a further aspect of the present invention the compliant layer includes masses of compliant material interspersed with holes. Desirably, each such mass is aligned with one of the terminals.
• A further aspect of the invention provides method of making a semiconductor chip assembly including the step of assembling a flexible, sheetlike element having terminals thereon to a semiconductor chip and connecting terminals on said sheetlike element to contacts on said chip. Methods according to this aspect of the invention desirably are characterized in that the assembling step is conducted so that said terminals on said sheetlike element overlie a surface of the chip and in that a compliant layer is disposed between said chip and said terminals. Most preferably, these methods are further characterized by the step of testing the chip by establishing temporary electrical contact between a plurality of test probes and said terminals and utilizing said temporary electrical contact to actuate said chip. The compliant layer permits displacement of at least some of said central terminals toward said chip during the step of establishing temporary electrical contact. The step of establishing temporary electrical contact preferably includes the step of simultaneously establishing temporary contact between a plurality of terminals and a plurality of test probes rigidly connected to a test fixture.
• Further aspects of the invention provide components for assembly to a semiconductor chip including a flexible sheetlike element having terminals thereon, characterized by a compliant layer underlying said terminals. The compliant layer preferably includes masses of a low modulus material and holes interspersed with said masses of low modulus material, said masses of said low modulus material being aligned with said terminals, said holes in said compliant layer being out of alignment with said terminals.
• A chip assembly according to a further aspect of the invention includes a semiconductor chip having a front surface with a plurality of contacts disposed in a pattern on the front surface. The pattern of contacts on the front surface encompasses an area, referred to herein as the “contact pattern area” on the front surface. The chip assembly according to this aspect of the invention also includes a sheetlike dielectric element, referred to herein as “interposer,” overlying the front surface of the chip. The interposer has a first surface facing toward the chip and a second surface facing away from the chip. An area of the interposer overlies the contact pattern area of the chip. The interposer has apertures extending through it, from the first surface to the second surface. The interposer also has a plurality of electrically conductive terminals disposed in a pattern on the second surface of the interposer. At least some of these terminals, and preferably most or all of these terminals, are disposed within the area of the interposer overlying the contact pattern area on the chip. Each such terminal is associated with one contact on the chip.
• The assembly also includes flexible, electrically conductive leads. The leads preferably extend through the apertures in the interposer. Each such lead has a contact end connected to the associated contact of the chip and a terminal end connected to the associated terminal on the second surface of the interposer. The leads and the interposer are constructed and arranged so that the contact ends of the leads are moveable relative to the terminals at least to the extent required to compensate for differential thermal expansion of components. The leads desirably are flexible to permit such movement. Most preferably, the interposer itself is flexible so as to facilitate such movement. The assembly according to this aspect of the invention optionally may include a compliant layer as discussed above.
• The assembly incorporating the chip, interposer, terminals and leads may be incorporated in a larger assembly including a substrate having a top surface facing toward the second surface of the interposer.
• Preferred chip assemblies according to this aspect of the present invention are compact and may be utilized with chips having large numbers of input-output connections. The terminals on the interposer, and the corresponding contact pads on the substrate, desirably are disposed in areas substantially the same size as the contact pattern area on the chip itself.
• The flexible leads may be formed integrally with the terminals on the interposer, or else may be separately formed fine wires. The leads desirably are curved to provide increased flexibility. The interposer desirably is a thin, flexible sheet of a polymeric material such as polyimide, a fluoropolymer, a thermoplastic polymer or an elastomer. In this arrangement, flexing of the interposer facilitates movement of the contact ends of the leads relative to the terminals and thus contributes to the ability of the assembly to withstand thermal cycling. The assembly may also include a compliant dielectric encapsulant having a low elastic modulus, such as an elastomeric encapsulant, covering the flexible leads in whole or in part. The encapsulant may be provided in the form of a layer, with holes in the encapsulant layer aligned with the terminals on the second surface of the interposer. The bonds between the terminals and the contact pads of the substrate extend through these holes. The encapsulant protects the relatively delicate leads during handling and during service, but does not prevent flexing of the leads or the absorption by the leads of relative motion of the chip and substrate during thermal expansion.
• A chip assembly according to yet another aspect of the present invention incorporates a chip having a front surface including a central region and a peripheral region surrounding the central region, the chip having a plurality of peripheral contacts disposed in the peripheral region of the front surface. The assembly preferably further includes a sheet-like dielectric interposer overlying the central region of the chip front surface. The interposer has a first surface facing downwardly toward the chip and a second surface facing upwardly, away from the chip. The interposer also has edges disposed inwardly of the peripheral contacts. For example, the interposer may overly only the central portion of the chip front surface. A plurality of central terminals are disposed on the interposer and overly the central region of the chip front surface. The assembly preferably also includes a plurality of peripheral contact leads connecting at least some of the peripheral contacts on the chip with at least some of the central terminals on the interposer. Each such peripheral contact lead thus has a central terminal end overlying the interposer and connected to one of the central terminals and a contact end projecting outwardly beyond one of the edges of the interposer and connected to one of the peripheral contacts. Each peripheral contact lead extends inwardly from one of the peripheral contacts to one of the central terminals on the interposer. The peripheral contact leads and preferably the interposer as well are at least partially flexible so that the central terminals are movable with respect to peripheral contacts to accommodate movement caused by differential thermal expansion. Here again, the assembly may optionally include a compliant layer as discussed above. Desirably, the peripheral contact leads include bent portions.
• The peripheral contact leads and central terminals provide a “fan-in” arrangement in which the terminals on the interposer are disposed inside the region bounded by the peripheral contacts on the chip. Typically, the peripheral contacts on the chip are disposed in one or two rows along each edge of the chip, in a generally rectangular pattern, so that the contacts on the chip are close to one another. By contrast, the terminals on the interposer may be substantially evenly disposed over the second surface of the interposer. The central terminals may be disposed in a so-called “area array.” Accordingly, the distance between adjacent terminals may be substantially greater than the distance between adjacent contacts on the chip. The distances between adjacent terminals on the interposer may be large enough to accommodate solder bonding and similar processes which require substantial distances between adjacent bonds.
• Some or all of the peripheral contact leads may have outward extensions projecting outwardly beyond the peripheral contacts of the chip. The assembly may include securement means for holding these outward extensions. For example, one or more securement elements may be disposed outwardly of the peripheral contacts, and each such securement element may be physically connected to a plurality of the outward extensions on the peripheral contact leads. Each such securement element may be a generally planar strip of dielectric material having an inboard edge extending generally parallel to one of the edges of the interposer so that each pair of parallel edges define an elongated slot between each such securement element and the interposer, and each peripheral contact lead may extend across one of these slots. In this arrangement, the peripheral contacts of the chip may be disposed in alignment with the slots between the securement elements and the interposer. The securement element may be physically connected to the interposer, as by bridge elements extending between the securement elements and the interposer at spaced-apart locations around the periphery of the chip front surface. The securement elements, bridge elements and interposer may be formed integrally with one another as a single, sheet-like unit. The securement elements provide physical reinforcement to the peripheral contact leads during the manufacturing operations and in service. Additional terminals, referred to herein as “outside” terminals, may be disposed on the securement elements, and may be connected to some of the peripheral contacts on the chip by outside terminal leads extending across the slots, the inboard ends of the outside terminal leads being secured to the interposer so that the slot and interposer cooperatively provide reinforcement to the outside terminal leads as well.
• These assemblies may be made by methods which include the step of assembling a sheet-like dielectric interposer to the chip so that the interposer overlies the central region of the chip front surface, the outboard edges of the interposer being disposed inwardly of the peripheral contacts on the chip. When the dielectric interposer is disposed on the chip, a first surface of the interposer faces downwardly toward the chip and a second surface of the interposer faces upwardly away from the chip, and a plurality of central terminals on the interposer overly the central region of the chip front surface. The method further includes the step of connecting a plurality of peripheral contact leads between at least some of the peripheral contacts of the chip and at least some of the central terminals on the interposer, so that each such peripheral contact lead extends inwardly from one of the peripheral contacts on the chip to one of the central terminals on the interposer. The method may further include the step of assembling a substrate having a plurality of contact pads to be assembled interposer and chip and connecting each of the central terminals on the interposer to one of the contact pads on the substrate.
• The interposer may have prefabricated leads mounted thereon and connected to the central terminals before the interposer is assembled to the chip. In this case, the prefabricated contact leads are positioned on the chip when the interposer is assembled to the chip. Such prefabricated contact leads may be electrically connected to the contacts of the chip by thermocompression bonding or similar processes. Alternatively, the peripheral contact leads may be formed after the interposer is applied to the chip, as in a wire-bonding step in which a fine wire is dispensed and formed into a lead connecting the contact and terminal. Preferably, securement elements are provided as discussed above with reference to the chip assembly, and the securement elements are connected to the interposer before the interposer is placed on the chip. In this case, the securement elements may support the prefabricated leads during the step of placing the interposer on the chip.
• A semiconductor chip assembly in accordance with yet another aspect of the invention includes a semiconductor chip having oppositely facing front and rear surfaces with edges extending between these surfaces, the chip having contacts on the front surface. The assembly further includes a generally sheet-like element referred to herein as “backing element” underlying the chip, the backing element having a top surface facing toward the chip and a bottom surface facing away from the chip. A central region of the backing element is aligned with the chip. The backing element is provided with terminals. At least some, and preferably all of the terminals on the backing element are disposed in the central region, so that the terminals underlie the bottom surface of the chip. The assembly in accordance with this aspect of the present invention further includes electrically conductive leads interconnecting the contacts on the chip front surface with the terminals on the backing element, these leads extending alongside the edges of the chip. Preferably, the backing element and the leads are flexible so that the terminals on the backing element are moveable with respect to the chip. Thus, the terminals desirably are moveable with respect to the contacts on the front surface of the chip in directions parallel to the plane of the chip top and bottom surfaces. The backing element and leads provide for connection to the chip at the back surface, so that the chip can be mounted in face-up disposition on a substrate. However, because the terminals on the backing element are disposed in the central region and aligned with the chip itself, the connections to the substrate can be made in the area beneath the chip. Therefore, the assembly need not be substantially larger than the chip itself.
• The ability to accommodate relative movement between the chip and the terminals on the backing element allows the assembly to accommodate differential thermal expansion between the chip and substrate. Desirably, the terminals on the backing elements are also moveable relative to the chip in directions towards the bottom surface of the chip as discussed above, and the assembly may include resilient means for permitting movement of the terminals towards the bottom surface but resisting such movement. For example, the assembly may incorporate a layer of a compliant material disposed between the chip rear surface and the terminals.
• Most desirably, the assembly includes at least one generally sheet-like flap connected to the backing element. Each such flap extends upwardly, towards the front surface of the chip and away from the backing element alongside one edge of the chip. Each of the aforementioned leads desirably includes a flap portion extending along one of these flaps. The flaps may be formed integrally with the backing element. Desirably, both of the flaps and the backing element include electrically conductive layers and a dielectric layer disposed between the electrically conductive layers and the leads so as to provide a controlled impedance in the leads. Assemblies of this type are especially well suited to use with chips having contacts arranged in rows adjacent the periphery of the chip front surface peripherate. Desirably, each flap extends to the vicinity of at least one row of contacts. The flap portions of the leads on each such flap are connected to the adjacent row of contacts. Such connection may be made for instance by wire bonding or by direct connections between the flap portions of the leads and the contacts on the chip. Even where wire bonding is employed, however, the wires extending between the chip contacts and the flap portions of the leads are short. Such short wire bonds can be readily applied and have relatively low inductance.
• Most preferably, the chip assembly includes one or more support elements disposed between the flaps and the edges of the chip. The support elements may cooperatively constitute a ring or box surrounding the chip. The box may also incorporate a floor element disposed beneath the rear surface of the chip, between the rear surface and the backing element. Where the assembly includes a floor element underlying the chip rear surface, the compliant layer may be disposed between the floor element and the terminals, as, for example, between the floor element and the backing element. These arrangements provide for mechanical support of the flaps and protection of the interconnections. Further protection may be afforded by encapsulating the assembly.
• Further aspects of the invention provide components incorporating subassemblies of the backing element, leads and support element. Preferably, these components include support elements defining a box, and include flaps integral with the backing element extending upwardly along the sides of the box. The conductors extending along the flaps are prepositioned adjacent the top edges of the box walls. In manufacture of the assembly, the chip may be placed within the box and the conductors may be joined to the chip terminals.
• Assemblies as discussed above may be incorporated in a larger assembly with a substrate having contact pads, the contact pads of the substrate being aligned with the terminals on the backing element and connected thereto. Such connection may be made for example by masses of electrically conductive bonding material disposed between the terminals and the contact pads of the substrate.
• A further aspect of the present invention provides a circuit assembly including a plurality of chip assemblies, each including an interposer and a backing element as discussed above. According to this aspect of the invention, the chip assemblies may be arranged in a stack, one on top of the other, such that each chip assembly other than the bottom-most chip assembly overlies another, immediately subjacent chip assembly. The bottom surface of the backing element in each such overlying chip assembly faces the second surface of the interposer of the immediate subjacent chip assembly. Most preferably, at least some of the inside terminals on the backing element of each such overlying chip assembly are connected to the central terminals on the interposer of the immediately subjacent chip assembly, so that the chips of the various chip assemblies are electrically connected to one another.
• Further aspects, features and advantages of the present invention will be more readily apparent from the detailed description of the preferred embodiments set forth below, taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
• FIG. 1 is a diagrammatic perspective view of a chip assembly in accordance with one embodiment of the invention.
• FIG. 2 is a fragmentary sectional view taken along line2-2 inFIG. 1.
• FIG. 3 is a fragmentary view, on an enlarged scale, of the area indicated inFIG. 2.
• FIG. 4 is a layout diagram depicting the spatial relationship of certain components in the assembly ofFIG. 1.
• FIGS. 5A and 5B are fragmentary diagrammatic perspective views depicting certain operations, in manufacture of a component utilized in the assembly ofFIG. 1.
• Each ofFIGS. 6, 7 and8 is a fragmentary diagrammatic perspective view depicting certain operations in the process of manufacture of the assembly ofFIG. 1.
• FIG. 9 is a fragmentary diagrammatic perspective view similar toFIG. 7 but depicting components and process steps in accordance with a further embodiment of the invention.
• Each ofFIGS. 10A through 10E is a fragmentary diagrammatic perspective view depicting a stage in a further component fabrication process according to the invention.
• FIG. 11 is a diagrammatic plan view of a semiconductor chip incorporated in one embodiment of the present invention.
• FIG. 12 is a view similar toFIG. 11 but showing the chip in conjunction with additional components.
• FIG. 13 is a fragmentary, partially sectional perspective view on an enlarged scale depicting portions of the components illustrated inFIG. 12.
• FIG. 14 is a fragmentary, diagrammatic sectional view depicting the components shown inFIG. 13 together with additional components and process equipment.
• FIG. 15 is a fragmentary, diagrammatic sectional view depicting an assembly operation according to a further embodiment of the invention.
• FIG. 16 is a fragmentary, partially sectional diagrammatic perspective view depicting an assembly according to a further embodiment of the invention.
• FIG. 17 is a diagrammatic plane view depicting the assembly ofFIG. 16.
• FIG. 18 is a diagrammatic plan view depicting an assembly according to yet another embodiment of the invention.
• FIG. 19 is a fragmentary plan view depicting certain components used in the assembly according toFIGS. 16 and 17.
• FIG. 20 is a fragmentary perspective view similar toFIG. 16 but depicting portions of any assembly in accordance with a further embodiment of the invention.
• FIG. 21 is a diagrammatic plan view of a component.
• FIG. 22 is a fragmentary sectional view on an enlarged scale taken along lines22-23 inFIG. 21.
• FIG. 23 is a diagrammatic perspective view of a further component used with the components ofFIGS. 21-22.
• FIG. 24 is a fragmentary sectional view taken along lines24-24 inFIG. 23.
• FIG. 25 is a diagrammatic perspective view showing the components ofFIGS. 21-24 at an intermediate stage of an assembly process.
• FIG. 26 is a fragmentary, partially sectional perspective view depicting a final assembly incorporating the components ofFIGS. 21-25.
• FIGS. 27 and 28 are fragmentary, partially sectional perspective views depicting components in accordance with additional embodiments of the invention.
• FIGS. 29 and 30 are diagrammatic sectional views depicting still further embodiments.
• Each ofFIGS. 31, 32 and33 is a diagrammatic, perspective view depicting further processes according to the invention.
DETAILED DESCRIPTION
• Each chip assembly in accordance with one embodiment of the present invention includes arigid substrate20 having atop surface22 and havingcontact pads24 disposed on the top surface.Substrate20 is also provided withconductors26 interconnecting certain ones of thecontact pads24. Thecontact pads24 are arranged in a pattern on the top surface of the substrate generally corresponding to the pattern of connections to devices, such assemiconductor chips28 and30 anddiscrete components32 mounted on the substrate.Substrate20 also has external connections such as pins34. Theconductors26 are arranged to interconnect thevarious contact pads24 in the desired patterns so as to interconnectchips28 and30 when the same are mounted to the substrate and also to connect these chips to thediscrete components32 and to theexternal connectors34 in the appropriate manner for functioning of the particular circuit. Although only afew contact pads24,conductors26 andexternal connections34 are illustrated inFIG. 1, thesubstrate20 may have an unlimited number ofcontact pads24,conductors26 andexternal connections34. Hundreds or thousands of these elements typically are provided in each substrate.
• Chip28 has a generally planarrear face36 and a generally planarfront face38 with electrical contacts40 (FIG. 2) disposed thereon. Theelectrical contacts40 are electrically connected to the internal electronic components (not shown) ofchip28.Chip28 is mounted onsubstrate20 in a front-face-down orientation, with thefront face38 of the chip facing toward the top offace22 of the substrate. A flexible, sheetlikedielectric interposer42 is disposed between the chip and the substrate.Interposer42 has a first generallyplanar face44 facing towardchip28 and a second generally planarface46 facing in the opposite direction, away fromchip28.Interposer42 may incorporate one or more layers. Preferably, the interposer includes a compliant, compressible layer as further discussed below.Interposer42 has a plurality ofterminals48 on itssecond face46. Each such terminal is associated with one of thecontacts40 onchip28 and connected to such contact by aflexible lead50. Each terminal48 is also associated with onecontact pad24 onsubstrate20, and each terminal is bonded to the associated contact pad by amass52 of electrically conductive bonding material such as solder or a conductive polymer. Thus, the contacts onchip40 are interconnected, via leads50,terminals48 andmasses52 with thecontact pads24 on the substrate.
• Interposer42 hasapertures54 extending through it, from itsfirst surface44 to its second face of46. Each aperture is aligned with onecontact40 onchip28. Each terminal48 is disposed adjacent one of theapertures54. Thelead50 associated with each terminal has acontact end56 disposed within the associatedaperture54 and connected to the associatedcontact40 on the chip. Each lead50 also has aterminal end58 connected to the associatedterminal48. In the structure ofFIG. 2, theleads50 are formed integrally with theterminals48 so that theterminal end58 of each lead merges with the associatedterminal48. As best seen inFIG. 2, each lead50 is curved between itscontact end56 and itsterminal end58. The curvature is in the direction perpendicular to thefaces46 and48 of the interposer. An elastomeric,dielectric encapsulant60 is disposed inapertures54 so that the encapsulant covers the contact ends56 ofleads50 and hence covers the junctures of the leads with thecontacts40.
• Thecontact end56 of each lead50 is moveable relative to the associatedterminal48. As best seen inFIG. 3, the contact end56aof lead50acan be displaced from its normal, undeformed position (shown in solid lines) in the directions parallel to thefaces44 and46 ofinterposer42 and parallel to thefront face38 ofchip28. For example, the contact end56amay be displaced to the position indicated in broken lines at56a′. This displacement is permitted by the flexibility of thelead50 and by buckling and wrinkling ofinterposer42.Encapsulant60 is compliant, and does not substantially resist flexing ofleads50 and buckling and wrinkling ofinterposer42. The displacement illustrated inFIG. 3, from the normal undisplaced position56ato the displaced position56a′ places thelead50 in compression. That is, the terminal end56amoves generally toward the associated terminal48 in moving from position56ato position56a′. Movement in this direction is particularly well accommodated by buckling of thelead50. The contact end of each lead can also move in other directions, such as in the opposite direction from position56aaway from the associatedterminal48, and in directions perpendicular to these directions, into and out of the plane of the drawing as seen inFIG. 3. Prefabricated leads formed on the interposer may curved in directions parallel to the face of the interposer and parallel to the plane of the front face of the chip. This provides increased flexibility in the leads. Desirably, the curved portion of each lead overlies an aperture in the interposer. Thus, the curved portion of the lead is not bonded to the interposer. This portion of the lead therefore can flex to accommodate relative movement of the contact and terminal without deformation of the interposer.
• As best seen inFIG. 4, thecontacts40 on chip28 (each symbolized by a dot inFIG. 4) are disposed in a pattern on the front surface ofchip28.Contacts40 cooperatively encompass a contact pattern area62 on the front face ofchip28. The boundary of the contact pattern area is illustrated by a broken line B inFIG. 4. The boundary of the contact pattern area may be taken as the shortest combination of imaginary line segments along the front face of the chip which cooperatively enclose all of thecontacts40. In the particular example illustrated inFIG. 4, this boundary is generally in the form of a rectangle.Contacts40 are disposed throughout contact pattern area62, in locations determined by the interior structure ofchip28. Contact pattern area62 includes a peripheral region, adjacent the boundary B, and a central region, adjacent thegeometric center64 of the contact pattern area.Contacts40 are disposed both in the peripheral region and in the central region. Typically, although not necessarily, thecontacts40 are disposed at substantially equal spacings throughout the entirety of contact pattern area62. Theterminals48, each symbolized by an X inFIG. 4, are disposed in a similar pattern on thesecond surface46 ofinterposer42. At least some ofterminals40 are disposed in the area ofinterposer surface46 overlying contact pattern area62.Terminals64 encompass aterminal pattern area66 on thesecond face46 of the interposer. The boundary ofterminal pattern area66 is illustrated inFIG. 4 by the broken line T. The boundary of the terminal pattern area may be taken as the shortest combination of imaginary line segments which would cooperatively enclose all of the terminals on the second surface of the interposer. The geometric center ofterminal array area66 desirably is coincident, or approximately coincident, with thegeometric center64 of the contact array area. Desirably,terminal pattern area66 is not substantially larger than contact pattern area62. That is, the perimeter of the terminal area preferably is less than about 1.2 times, and most preferably about 1.0 times the perimeter of contact pattern area62. Stated another way, theoutermost terminals48 desirably lie within or close to the boundary B of contact array area62. The total area encompassed withinterminal pattern area66 desirably is less than about 1.4 times, and most desirably about 1.0 times the total area encompassed within contact pattern area62. Thus theleads50 connectingcontacts48 toterminals40 do not “fan out,” away from thegeometric center64 the contact pattern area. Typically, the mean distance of theterminals48 fromgeometric center64 of the contact pattern area, measured in the direction parallel to the surfaces of the chip and interposer, is less than about 1.1, and typically about 1.0, times the mean distance of thechip contacts40 fromcenter64.
• The interposer and leads utilized in the structure ofFIGS. 1-4 may be fabricated by a process as schematically illustrated inFIGS. 5A-5B. In this procedure, theterminals48 and leads50 may be deposited on thesecond surface46 of the sheetlike interposer by conventional printed circuit manufacturing techniques before formation ofapertures54. Thus, the leads and terminals may be formed either by an additive process, wherein the metal is deposited in the desired pattern by plating, or else in a subtractive process which begins with a laminate including both thesheetlike interposer42 and a full layer of metal and removes the metal except in the areas where the terminals and leads are desired, so as to yield a sheet having the terminals and leads in position (FIG. 5A). After formation of the terminals and leads,apertures54 are formed in registration with the contact ends56 of the leads50 (FIG. 5B) by etching through the interposer from thefirst surface44, or by applying radiant energy such as laser beam focused at the appropriate spots on thefirst surface44.
• A further method of making a component incorporating the interposer, terminals and leads is shown inFIGS. 10A-10E. In this method, theapertures54 are formed ininterposer42, and the aperture interposer is provided with alayer302 of adhesive on thesecond surface46 of the interposer. A conductive sheet, such as a sheet ofcopper304 is applied on the first surface of the interposer, so thatsheet304 overlies adhesive302 and so thatsheet304 overlies theapertures54. Afirst surface306 ofsheet304 faces towardsinterposer42 and confronts thesecond surface46 of the interposer, with theadhesive layer302 disposed there between. Asecond surface308 of the conductive sheet faces away from the interposer. Alayer310 of a photosensitive resist composition is applied on thesecond surface308 ofconductive layer304. A second resistcomposition312 is placed withinapertures54 so that resist312 covers thefirst surface306 ofconductive layer304 withinapertures54. Desirably, resist312 is applied by applying a layer of the second resist composition to thefirst surface44 ofinterposer42 as illustrated inFIG. 10B. Both resistcompositions310 and312 may be provided as so-called “dry resist” i.e., as a film of resist composition which can be laminated to the other structures. Resistcomposition312 is laminated to thefirst surface44 of theinterposer42 under pressure so that the resist composition flows intoapertures54 and substantially fills these apertures.
• In the next stage of the process, depicted inFIG. 10C, the first resistlayer310 is selectively cured and uncured portions are removed so as to leave the cured resist in a pattern corresponding to the desired pattern of conductive materials in the finished product. Such selective curing and removal of a resist layer may be accomplished by known photographic techniques. The remaining resist pattern on thesecond surface308 of theconductive layer304 includeselongated lead areas314 andterminal areas316 contiguous with the lead areas. At least a part of eachlead area314 overlies one of theapertures54 in the interposer, whereas theterminal areas316 do not overly the apertures. The portion of eachlead area314 overlying an aperture is smaller than the aperture, so that each lead area overlies only a portion of the associatedaperture54. Desirably, eachlead area54 protrudes lengthwise across theaperture54, as illustrated inFIG. 10C. The second resistmaterial312 withinapertures54 desirably also is cured. As the second resist material may be cured in its entirety, and need not be cured selectively in a predetermined pattern, the second resist material may be of a type which can be cured by exposure to heat or other nonselective curing method. Alternatively, the second resistmaterial312 may be photographically cured.
• In the next stage of the process, illustrated inFIG. 10D, the assembly is immersed in an etchant capable of dissolving the conductive material inlayer304 so that the etchant contacts this layer. During the etching procedure, the first resist inlead area314 andterminal areas316 protects thesecond surface308 ofconductive layer304. Theinterposer42 protects thefirst surface306 oflayer304 in theterminal areas316 and in those portions oflead areas314 which do not overly apertures54. The second resist312 protects thefirst surface306 in those portions oflead areas314 which overlieapertures54. The etchant therefore does not attack those portions ofconductive layer304 covered bylead portions314 andterminal portions316 of the first resistlayer310. The first resistlayer310 and the second resist312 are then removed by conventional resist decomposition processes such as exposure to solvents which attack the resist. This leaves the unattached portions ofconductive layer304 as leads50 andterminals48 on thesecond surface46 ofinterposer42, with acontact end56 of each lead50 protruding over the associatedaperture54 and with aterminal end58 of each lead connected to the associatedterminal48.
• This process can be modified. For example, theadhesive layer302 may be omitted where the conductive layer forms a satisfactory bond to the material of the interposer. Also, the pattern first resist310 need not be provided by a subtractive process as discussed above but instead may be provided by an additive process, wherein the resist is applied only in the areas to form the pattern, as by silk screening. Formation of theleads50 and terminal48 by this type of etching process is particularly useful in forming fine leads in good registration withapertures54. Also, as theapertures54 are pre-formed, there is no possibility of damaging the leads during formation of the apertures.
• The assembly of the interposer and terminals and contacts is fabricated in a substantially continuous sheet or strip. As illustrated inFIG. 6, the interposers may be provided in the form of acontinuous tape70, withplural interposers42 spaced lengthwise along the tape, each suchinterposer having terminals48 and leads50 thereon.Tape70 may be in the form of a single sheet of the material employed for theinterposers42, or else may include separate pieces of such material, each constituting one or more interposers, secured to a backing or the like.Tape70 may have sprocket holes (not shown) or other features such as those commonly utilized on the tapes for tape automated bonding of semiconductor chips.
• In an assembly method according to the invention,tape70 is advanced in a downstream direction (to the right as seen inFIG. 6) andchips28 are connected to the tape upon assembly of each chip with oneinterposer42 and with the associated terminals and leads. The chips are subsequently carried downstream with the tape, through further operations as discussed below.
• As best seen inFIG. 7, each interposer, with theterminals48 and leads50 thereon, is brought into juxtaposition with achip28, and the chip is aligned with the interposer so that eachaperture54 is aligned with onecontact40 of the chip. Theinterposer42 andchip28 are brought together, so that thefirst face44 of the interposer bears on thefront face38 of the chip, and the contacts are received in theapertures54 of the interposer. Thecontact end56 of each lead50 initially lies substantially in the plane of thesecond surface46 of the interposer. A tool74 is advanced into engagement with thecontact end56 of each lead so as to deform thecontact end56 downwardly, into the underlyingaperture54 and towards the associatedcontact40. Tool74 may be a substantially conventional thermal bonding tool, thermosonic bonding tool, ultrasonic bonding tool, compression bonding tool, or the like of the types commonly used in tape automated bonding or wire bonding. By advancing the tool74 into eachaperture54, the contact ends of leads are manipulated within the apertures and bonded to thecontacts40 on the chip. Although only a single tool74 is depicted inFIG. 7, the bonding operation may be performed in a multiple operation, with many or all of theleads50 being bonded to the associated contacts at once.
• After the contacts and leads have been bonded to one another, the interposer and the chip are advanced to a further station, where theencapsulant60 is applied within eachaperture54. Theencapsulant60 may be applied dropwise, by conventional drop application equipment. As best seen inFIG. 8, each drop ofencapsulant60 covers thecontact end56 of the associated lead, but leaves the associatedcontact48 uncovered. The encapsulant protects the relatively delicate contact ends56 of the leads and the relatively delicate junctures with theterminals40. Once the encapsulant has been applied, the assembly of the interposer, leads, terminals and chips is advanced to a testing station. As illustrated inFIG. 8, the assembly, including thechip28, may be tested. The test may involve connection of the chip, through theterminals48, to an external electronic test device (not shown). The test device may be arranged to operate the chip under power for an appreciable period so as to “burn-in” the chip and detect any latent defects. Typically, numerous connections should be established to the chip simultaneously. As illustrated inFIG. 8, this may be accomplished by applyingprobes76 toterminals48.Probes76 may be so called “noncompliant” probes. That is, probes may be arranged to move in unison, in the directions towards and away from the chip28 (upwardly and downwardly as seen inFIG. 8). Theprobes76 are mounted to a common fixture (not shown) so that the vertical position of the probes relative to one another are fixed. This type of “noncompliant” probe array is particularly convenient where the required spacings between probes (the spacings of the terminals48) are relatively small. However, non-uniformities in the dimensions of theprobes76 and/or in the dimensions of theterminals48 orchip28 may cause one or more of theprobes76 to engage the associatedterminal48 before the other probes have engaged their terminals. Desirably,interposer42 is compliant, so that each terminal48 can be displaced slightly by the associatedprobe76 in the direction towardchip28. The region ofinterposer42 beneath each terminal48 compresses slightly to accommodate such displacement. This allows all of theprobes76 to engage their associatedcontacts48 without imposing excessive loading on any one probe. Theterminals48 may be larger than the contacts on the chip, so as to provide a relatively large area for engagement by eachcontact76 and thus accommodate a reasonable amount of misalignment of the contacts in the directions parallel to the faces of the interposer. Because each chip can be tested in this fashion, prior to assembly with the substrate, defects in the chips, in the terminals and leads associated with the interposer and in the bonds between the leads and the chip contacts can be detected before the chip is united with the substrate.
• After the testing operation, the chip and interposer are united with the substrate. The chip and interposer assembly is oriented so that the second face of the interposer, and theterminals48, face the top surface of the substrate, and each terminal48 confronts onecontact pad24 on substrate. Masses of solder are applied between the confrontingterminals48 andcontact pads24 and melted in a “solder reflow” operation so that the solder forms a solid joint between the contact pad and terminal, and so that the solder masses support the chip and interposer assembly above thesubstrate20, in the orientation illustrated inFIG. 2. The solder application and reflow operation may be performed in substantially the same way as the solder application and reflow operation of conventional flip-chip bonding. Thus, the masses of solder may initially be applied to thecontact pads24 of the substrate, before the chip and interposer assembly is united with the substrate. Alternatively, the solder may be applied to theterminals48 and bonded to thecontact pads24 in the reflow operation. A flux typically is employed in the solder reflow operation. Because the solder masses support the chip and interposer surface assembly above the substrate, there is a gap80 between the interposer and the substrate. Flux residues may be rinsed out of the assembly by passing a rinsing fluid through this gap.
• In an assembly method according to a further embodiment of the invention, theinterposer42 is not provided with leads before the interposer is united with thechip28. Instead, leads50′ are applied by bonding separately formed pieces of fine wire to theterminals48 and to thecontacts40 after the interposer is assembled with the chip. Leads50′ are flexible and curved, and arranged to deform as discussed above so that eachcontact40, and the associated contact end of the lead50′ can move relative to the associated terminal48 so as to accommodate thermal expansion. In the embodiment illustrated inFIG. 9, a layer of an adhesive81 is disposed between the first surface of the interposer and the front surface of the chip.
• The subassembly illustrated inFIG. 9 may be further provided with an encapsulant (not shown) in the form of a layer covering substantially the entiresecond face46 ofinterposer42 and hence filling theapertures54 and covering theleads50′. The layer is provided with holes in alignment with theterminals48. These holes may be formed by etching the encapsulant layer by applying this layer in a selective coating process such as silk screening or the like or by applying the encapsulant layer in a selective curing process. Thus, the encapsulant which may be curable by ultraviolet or other radiant energy. The encapsulant may be deposited over the entire interposer, and overterminals48. After application of the encapsulant, radiant energy may be applied selectively, so that the areas of the layeroverlying terminals48 remain uncured. These layers are then removed by washing or by a relatively mild etching operation, leaving holes in alignment withterminals48. Alternatively, the encapsulant layer may be cured non-selectively and then portions may be removed by applying radiant energy such as laser light in alignment withterminals48. Masses of electrically conductive bonding material are deposited within these holes in the encapsulant layer. These masses are then engaged with the contact pads (not shown) of the substrate and heated so that bonding material forms a bond between each terminal48 and the associated contact pad on the substrate, in a manner similar to the solder bonds of the assembly depicted inFIG. 2.
• A chip may have contacts disposed in a peripheral arrangement, i.e., where all of the contacts are disposed adjacent the periphery of the chip and hence adjacent the periphery of the contact pattern area. The central zone of the contact pattern area, adjacent the geometric center of the contact array, may be devoid of contacts. With such a chip, the terminals on the interposer may be arranged in a “fan in” pattern, i.e., where the mean distance from the geometric center of the contact array to the terminals on the interposer is less than the mean distance from this geometric center to the contacts on the chip. Some of the terminals are disposed on the area of the interposer overlying the central, contact-free zone of the contact pattern area. This arrangement can provide a substantially uniform distribution of terminals over an area equal to the contact pattern area. This provides a spacing between adjacent terminals larger than the spacing between adjacent contacts. Such an arrangement allows connection of chips with peripheral contact arrays to area arrays of contact pads on the substrate. Thus chips originally intended for conventional bonding processes such as tape automated bonding can be adapted readily and economically to substrates having compact contact pad arrays similar to those used in flip-chip bonding.
• As illustrated inFIG. 31,chips928 may be provided in the form of awafer930 incorporating a plurality of chips, all of the same design or of differing designs. Individual, separate, interposers924 may be positioned on the individualchips constituting wafer930 and the interposers may be assembled to the chips as discussed above. In this operation, the contacts on eachchip928 are secured to the leads and terminals of each interposer. After the interposers are secured to the chips, and desirably after the junctures between the leads of each interposer and the contacts of each chip are encapsulated, the individual chips are separated from the wafer and from one another, as by cutting the wafer using conventional wafer severing or “dicing” equipment commonly utilized to sever individual chips without interposers. This procedure yields a plurality of chip and interposer subassemblies, each of which may be secured to an individual substrate.
• Alternatively, as illustrated inFIG. 32, awafer950 incorporating a plurality of chips may be assembled to asheet952 incorporating a plurality ofinterposers954. Again, the contacts on each chip are secured to the terminals and leads of one individual interposer overlying the particular chip. Thewafer950 and thesheet952 are severed after this operation, and desirably after encapsulating the leads, so as to provide individual subassemblies each including a chip and an interposer.
• Interposers also may be provided in the form of asheet960 incorporating plural interposers such asinterposer962 and964 at predetermined relative positions corresponding to the positions of chips on a completed assembly including a substrate.Chips966 and968 may be secured to the individual interposers and the entire assembly of plural chips and the sheet of plural interposers may be secured to asubstrate970. Each interposer in such an assembly desirably incorporates a pattern of terminals and leads as discussed above. This variant of the assembly procedures provides for consolidation of plural chips into a larger subassembly before bonding to the substrate.
• Asemiconductor chip820 used in a further embodiment of the invention has a generally planar front face822 (the face visible inFIG. 11) having acentral region824 adjacent the geometric center of the face and aperipheral region826 adjacent theedges828 boundingface822. The front or contact-bearingface822 of the chip is regarded as defining the top of the chip. Thus, in specifying directions, the direction pointing out offront face822, and away from the chip, i.e., the direction pointing out of the plane of the drawing towards the viewer inFIG. 11, is the upwardly direction. The downward direction is the opposite direction. As used in the present disclosure with respect to a semiconductor chip assembly, such terms should be understood as based on this convention, and should not be understood as implying any particular directions with respect to the ordinary gravitational frame of reference. Thechip820 also has a plurality ofperipheral contacts830 arranged inrows832, there being one such row adjacent eachedge828 of the chip. Therows832 do not intersect one another but instead terminate at appreciable distances from the corners of the chip so that thecorners834 are devoid ofperipheral contacts830. Thecentral region824 of the chipfront surface822 is also devoid of contacts. Thecontacts830 in eachrow832 are spaced at very close intervals, typically about 100 to about 250 micrometers center-to-center. This center-to-center spacing is adequate for wire bonding or tape automated bonding. This chip configuration is typical of high I/O count chips originally intended for use with wire bonding or tape automated bonding systems.
• In an assembly method according to one embodiment of the invention, a sheet-likedielectric interposer836 is assembled tochip820.Interposer836 includes a flexible top layer838 (FIG. 13) formed by a thin sheet of material having a relatively high elastic modulus and a compliantbottom layer840 formed from a material having a relatively low elastic modulus. The high-modulus material oftop layer838 may be a polymer such as a polyimide or other thermoset polymer, a fluoropolymer or a thermoplastic polymer. The compliant, low-modulus material ofbottom layer840 may be an elastomer. Desirably, the low-modulus material has elastic properties (including modulus of elasticity) comparable to those of soft rubber, about 20 to 70 Shore A durometer hardness.Interposer836 has a first orbottom surface842 defined bybottom layer840 and a second ortop surface844 defined bytop layer838. Bottom,compliant layer840 includes holes or voids841 interspersed withmasses843 of the low-modulus material.
• Interposer836 hasedges846 boundingsurfaces842 and844 and extending therebetween. The interposer also has a plurality ofcentral terminals848 distributed over the second ortop surface844.Terminals848 are disposed at substantially even spaces onsurface844 so thatterminals848 constitute a “area array.” The dimensions ofinterposer836 in the plane oftop surface844 are smaller than the corresponding dimensions ofchip820 in the plane offront surface822. The number ofcentral terminals848 may be approximately equal to the number ofperipheral contacts830 on the semiconductor chip. Nonetheless, the center-to-center linear distance between adjacent ones ofcentral terminals848 is substantially greater than the center-to-center distance between adjacentperipheral contacts830 on the chip, because thecentral contacts848 are substantially evenly distributed rather than concentrated in only a few rows. Eachcentral terminal848 is aligned with one of themasses843 of low-modulus material incompliant layer840, whereas theholes841 in the complaint layer are out of alignment with thecentral terminals848. In a variation of this embodiment, the holes may be aligned withterminals848. In a further variation, the holes may be continuous with one another whereas the masses of low-modulus material may be separate posts or pillars entirely surrounded by such continuous holes.
• As best seen inFIG. 13, eachcentral terminal848 is connected with apartial lead50 and abonding terminal852 which are formed integrally with the central terminal.Central terminals848, partial leads50 andbonding terminals852 may be formed from substantially any electrically conductive material, but preferably are formed from metallic material such as copper and copper alloys, noble metals and noble metal alloys. These components typically are fabricated on the top orsecond surface844 ofinterposer836 by conventional photolithographic end etching or deposition techniques.Bonding terminals852 are arranged inrows54 adjacent theedges846 of the interposer. As best seen inFIG. 12, there are foursuch rows54 of bonding terminals, one adjacent each edge of the interposer.
• In the assembly method according to this embodiment of the invention, theinterposer836 with the preformedterminals848, partial leads50 andbonding terminals852 thereon is positioned onchip820 so that thefirst surface842 of the interposer faces thefront surface822 of the chip, and so that theedges846 of the interposer are disposed inwardly of therows832 ofperipheral contacts830 on the chip.Bonding terminals852 are electrically connected tocontacts830 on the chip by a conventional wire bonding operation. The arrangement of thebonding terminals852 in rows parallel to and adjacent to the rows ofperipheral contacts830 on the chip substantially facilitates the wire bonding process. The fine,flexible bonding wires856 applied in the wire bonding operation merge with thebonding terminals852 andpartial leads50 on the interposer to form composite leads extending from the peripheral contacts of the chip to the central terminals on the interposer. As best appreciated with reference toFIG. 13, each such composite lead extends inwardly from oneperipheral contact830 to an associatedcentral terminal848 in the central way. Each such composite lead extends across theedge846 of the interposer.
• In the next stage of the process, a low elastic modulus dielectric encapsulant or solder masking material such as a silicone rubber or other castable elastomer858 (FIG. 14) is applied over the interposer and chip and overbonding wires856. The encapsulant is applied so as to leaveholes860 in alignment with each of thecentral terminals848 on the interposer. This may be accomplished as discussed above with reference to the assembly ofFIG. 9. At this stage, the assembly is relatively rugged and can be handled readily. Thus, thewires856 are fully protected by the encapsulant.
• Either before or after theencapsulant858 is applied, the chip and all of the connections made within the assembly can be tested by making temporary electrical connections to thecentral terminals848. Because thecentral terminals848 are at substantial center-to-center distances, they may be readily contacted with probes such as the plural probe set862 schematically illustrated inFIG. 14. Moreover, because thebottom layer840 of the interposer is compliant, eachcentral terminal848 is displaceable towards and away from thefront surface822 of thechip820. Thus, the bottom layer can be compressed by thetips864 of the probe set862. This greatly facilitates making good electrical contact between a plurality of probes and a plurality of central terminals at once, and hence greatly facilitates electrical testing of the chip and the other components of the assembly. The configuration ofcompliant layer840 contributes to this action. Eachmass843 of low-modulus material provides backing and support for the alignedterminal848. As thetips864 of the test probe set862 engage the terminals, each mass843 is compressed in the vertical direction and therefore tends to bulge in horizontal directions, parallel to the plane of the chip.Holes841 provide space for such bulging. Each terminal848 can move downwardly toward the chip substantially independently of the other terminals.Compliant layer840 need only provide for sufficient downward movement ofterminals848 to accommodate tolerances in the components and test equipment by accommodating differences in vertical position between adjacent terminals and/or test probes. Typically, about 0.125 mm or less compliance is sufficient. For example,complaint layer840 may be about 0.2 mm thick.
• Although test probe set862 is schematically illustrated as including only afew tips864, the test probe set in fact may include a full complement oftips864, equal in number to the number ofterminals848, so that all ofterminals848 can be engaged simultaneously. The tips of probe set862 may be rigidly mounted to acommon support865. Therefore, the test probe set may be rugged, reliable and durable. The particular shape oftips864 is not critical. However,tips864 may desirably be formed as small metallic spheres solder-bonded to support865.Support865 in turn may be a ceramic body with appropriate internal leads, similar to a conventional semiconductor substrate. Because the test probe set may make simultaneous connections with all terminals in the subassembly, and because the test probe set may have dimensions and configuration similar to a real substrate, the temporary electrical connection made using the test probe can provide a realistic test of the chip and interposer subassembly. In particular, the test probe set need not involve long leads which may introduce unwanted inductance and/or capitance. Accordingly, the test probe set can be employed to test and operate the chip at full speed. Because the test probe set may be a simple, economical device, many such probe sets can be provided in a manufacturing plant, so that each chip can be tested for a prolonged period.
• In the next stage of the assembly operation after testing, the chip and interposer subassembly is juxtaposed with a substrate having electrical contact pads thereon. The assembly is placed on the substrate so that thecentral terminals848 face toward the electrical contact pads on the substrate, and so that eachcentral terminal848 is aligned with one contact pad. Masses of an electrically conductive bonding material such as a solder or an electrically conducted adhesive may be disposed between the central terminals and the contact pads of the substrate. These masses may then be caused to flow and to bond with thecentral terminals848 and the contact pads thereby forming mechanical and electrical connections between the central terminals and the contact pads. This stage of the process may utilize essentially the same techniques as are employed in surface mount technology for assembly of components on printed circuit boards. Because thecentral terminals848 are disposed at substantial center-to-center distances, the standard surface mount techniques can be used without difficulty. For example, a high I/O count can be achieved with 10-25 mil (250-625 micrometer) center-to-center distances. In an alternate embodiment, each contact pad on the substrate may be a microminiature separable connector such as a socket, and a mating separable connector may be provided on each terminal. For example, each terminal848 may incorporate a miniature pin adapted to engage such a socket. In this case, the pins would serve as the means for connectingterminals848 to the contact pads of the substrate. The encapsulant or solder mask layer can be provided with metal rings surrounding eachhole860 and hence surrounding each terminal848. Each such ring defines a preselected area which can be wetted by solder and thus confines the solder of each joint to a preselected area. Also, small studs, balls, or pins may be positioned in the holes of the solder mask layer in electrical contact with theterminals848, and these studs may be soldered to a substrate.
• Inasmuch as eachperipheral contact830 on the chip is connected to one of thecentral terminals848 on the interposer, and each such central terminal is connected to one of the contact pads on the substrate, eachperipheral contact830 is connected to one of the contact pads of the substrate. The substrate contact pad of course may be connected to other elements of an electrical circuit through conventional connections (not shown) incorporated in the substrate. For example, substrate may be a circuit board, circuit panel or hybrid circuit substrate incorporating various electronic elements in addition tochip820.
• The interconnections between the chip and the substrate (betweenperipheral contacts830 and contact pads) are accommodated within the area of the chip itself, i.e., within the area on the substrate occupied bychip820. Thus, no space on the surface of the substrate is wasted by a conventional “fan-out” pattern of interconnections. Moreover, the assembly is substantially resistant to thermal cycling. Each of the composite leads connecting one of the chip peripheral contacts and one of thecentral terminals848 on the interposer is flexible. Thus, the partial leads50 (FIG. 13) on the interposer surface itself preferably are flexible, and thefine bonding wires856 are also flexible. The interposer itself, and particularly thetop layer838 and bottomcompliant layer840 may be flexible. Accordingly, there can be substantial movement ofterminals848 on the interposer relative tocontacts830 on the chip in directions parallel to the chip front surface. Such movement can be accommodated without applying substantial forces to the junctions between the leads and the chip contacts. During use of the assembly, differential thermal expansion ofchip820 and substrate may cause appreciable displacement of the contact pads on the substrate relative toperipheral contacts830 on the chip. Inasmuch as thecentral terminals848 of the interposer are bonded to the contact pads of the substrate by relatively stiff noncompliant conductive masses, the central terminals will tend to move with the contact pads. However, such movement is readily accommodated and does not result in substantial stresses at the bonds between the central terminals and contact pads.
• The assembly shown inFIG. 15 has aninterposer836′ similar to the interposer discussed above with reference toFIGS. 11-14. However, the prefabricated leads850′ associated withterminals848′ have outer orcontact portions854′ projecting outwardly beyond theedge846′ of the interposer. As prefabricated leads850′ are disposed ontop layer838′ of the interposer, the prefabricated leads cross theedge846′ of the interposer at an appreciable height above the first orbottom surface842′ of the interposer. The projectingouter portions854′ are curved downwardly, toward thefirst surface842′ of the interposer. This curvature desirably is provided during fabrication of the interposer and leads, before the interposer is assembled to the chip. In the assembly operation, theinterposer836′, with theleads850′ andterminals848′ already mounted thereon is placed ontochip820′ so that theouter portions854′ are in alignment withcontacts830′ of the chip. The curvature of the leads places the outer orcontact portions854′ in close proximity to chipcontacts830′. Atool855 is then applied to theouter portions854′ so as to force the outer portions thus forcing leads854′ into engagement with thechip contacts830′ so as to bond theouter portions854 ofleads850′ directly to the chip contacts. Typically, pressure is applied throughtool855 along with heat and/or ultrasonic energy. This stage of the process may employ conventional thermocompression or ultrasonic bonding techniques commonly used to bond inner leads in a tape automated bonding or “TAB” operation. This bonding establishes a connection between eachchip contact850′ and one of theterminals848′ on the interposer, without the need for any intermediate wire bonding operation. Once the contacts and terminals are connected in this manner, the resulting subassembly can be encapsulated and bonded to a substrate in substantially the same fashion as discussed above. As leads850′ are flexible,terminals848′ are movable with respect tocontacts830′ to compensate for thermal expansion.
• Theterminals848′ and leads850′ used in this structure can be fabricated by photolithographic techniques. For example, the interposer may initially be fabricated with a solid sheet of copper or other metal covering thesecond surface844′ and extending beyondedges846′. These portions of the metal sheet extending beyond the edges of the interposer may be embossed to impact a downward curvature. The surface of the metallic layer facing upwardly away from the interposer (facing toward the top of the drawing inFIG. 15) may be covered with a conventional photoresist pattern such that the photoresist covers the areas corresponding to theterminals848′ and leads850′. The opposite surface of the sheet may be covered with a further photo resist in the areas extending beyond theedges846′ of the interposer. The sheet may then be exposed to an etching solution so as to remove those areas not covered by the photo resist on the top surface, i.e., to remove all areas of the metal sheet other than theterminals848′ and leads850′. The photo resist may be removed, leaving interposer with the terminals and leads thereon. The curvature imparted to the metal sheet by embossing provides the desired downward curvature in theouter portions854′ of the leads. Alternatively, the leads may be bent after etching, using a forming die. In yet another lead-forming method, the dielectric interposer, or one of the generally planar dielectric layers constituting the interposer may be provided with features projecting out of the plane of the layers, such as bumps or elongated ridges. The leads may be formed by depositing metal or other conductive material so that it forms leads extending over the projecting features and then removing those portions of the dielectric layer or interposer constituting the projecting features, as by selectively etching the dielectric layer, leaving behind leads which are curved out of the plane. The step of depositing the conductive material to form the leads may be performed by selectively depositing the conductive material using conventional techniques, or by depositing conductive material and selectively etching or otherwise removing conductive material before etching the dielectric layer.
• An alternate, generally similar arrangement, includes an interposer incorporates a flexible top layer similar to thetop layer838 of the interposer discussed above with reference toFIGS. 11-14. Terminals and leads are positioned on the first or bottom surface of this layer, so that the terminals face towards the chip when the layer is in position on the chip. The interposer may also include a separate compliant underlayer disposed between the top layer and the chip front surface, and also disposed beneath terminals i.e., between the terminals and the chip. The compliant layer may be positioned on the chip surface, before the top layer, and terminals are positioned on the compliant layer. In this case, the compliant layer may incorporate adhesives at its top and bottom surfaces so as to bind the top layer to the chip. Because the compliant layer is soft, the top layer will remain flexible even when bound to the chip through the compliant layer, and the terminals will still be movable with respect to the contacts in directional parallel to the face of the chip. Alternatively, the compliant layer may be formed from a partially cured elastomer such as a so-called “B-stage” silicone elastomer. After assembly of the top layer, this partially cured material may be more fully cured, as by heating it, which causes the elastomer to bond with the top layer and with the chip surface. In this arrangement, the terminals are disposed beneath the top layer. To provide access to the terminals from the second or top surface of the interposer, the interposer top layer is punctured as applying radiant energy from a radiant energy source such as a laser in registration with the terminals to thereby form holes in alignment with the terminals. Once the holes have been formed, the resulting subassembly can be bonded to a substrate in the same manner as discussed above. These holes may be formed before the interposer is connected to the chip, and indeed may be formed before the terminals are positioned on the interposer. In a further alternative arrangement, the terminals and leads can be provided on the compliant layer itself.
• The assembly illustrated inFIG. 16 is similar to the assembly ofFIG. 15. However, theoutboard portions8354 ofleads8350 have outward extensions projecting outwardly beyond chipperipheral contacts8330. These outward extensions are secured to asecurement element8361. Although only onesecurement element8361 is visible inFIG. 16, it should be clearly appreciated that asimilar securement element8361 is provided at each edge ofinterposer8336 as seen inFIG. 17. Each securement element serves to reinforce and support the outboard portions of the leads, and to prevent undesired bending of the leads in directions parallel to the surfaces of the interposer and chip during assembly. Thecentral terminals8348 and peripheral contact leads8350 associated withinterposer8336 are disposed on the first or chip-facing surface8342 of theinterposer top layer8338. As best seen inFIG. 17, thesecurement elements8361 are connected to interposer8336 bybridge elements8363. The bridge elements are disposed at spaced-apart locations around the periphery of the interposer. Preferably, the interposer, securement elements and bridge elements are formed as an integral unit. All of these components may be portions of a unitary sheet of dielectric material. Thus, theinterposer8336,bridge elements8363 andsecurement elements8361 may all be formed as part of an elongated tape8381 (FIG. 17), which may includeseveral interposers8336, each with its associated securement elements and bridge elements. The tape may also include waste or trimareas8383. During the various assembly and handling operations, the interposers and chips may be advanced through the process by advancing the tape.
• Bridge elements8363 are disposed at the corners of the interposer. Thechip8320 used in this assembly includes fourrows8332 ofperipheral contacts8330, the rows forming a generally rectangular pattern. However, the rows of peripheral contacts stop short of the corners of this rectangular pattern, so that the corner regions of the pattern are substantially devoid ofcontacts8330.Bridge elements8363 overlie these corner regions, and hence do not cover any of thecontacts8330.
• Eachsecurement element8361 includes a top layer8301 (FIG. 16). Each securement element has aninboard edge8365 extending generally parallel to anedge8346 of interposer so that these parallel edges define anelongated slot8367 between the securement element and the interposer.Slots8367 are aligned with therows8332 of chipperipheral contacts8330. The peripheral contact leads8350 extend acrossslots8367, theoutward extensions8354 of these leads being attached to thesecurement elements8361, so that eachperipheral contact lead8350 is supported both by the interposer and by the securement element.
• Eachsecurement element8361 has a single row ofoutside terminals8372 extending generally parallel to theadjacent slot8367.Outside terminals8372 are disposed on the first or chip-facingsurface8369 of thetop layer8301 of eachsecurement element8361. Outside terminal leads8374 (FIG. 16) extend inwardly fromoutside terminals8372 acrossslots8367. Each such outside terminal lead has aninboard end8376 secured to theinterposer8336. Thus, both the outside terminal leads8372 and peripheral contact leads8350 extend acrossslot8367. These leads are interspersed with one another along the length of eachslot8367.
• Holes8360 are provided in the interposer and in each securement element top layer in alignment with thecentral terminals8348 andoutside terminals8372 so that the central terminals and outside terminals are accessible from the second surfaces of the interposer and securement elements, i.e., from the surface facing away from the chip.
• Interposer8336 includes acompliant bottom layer8340, and eachsecurement element8361 may include a compliant bottom layer8303 (FIG. 16). All of these compliant layers may be similar to the compliant layers discussed above, and may include holes (not shown) to increase their compliance. The compliant layers of the interposer and securement elements may be formed and assembled separately from these components, or may be incorporated intape8381.
• The leads and terminals may be formed in place on the interposer and on the securement elements by an etching process similar to those described above. A copper or other metallic sheet may be laminated to the dielectric sheet which will ultimately form theinterposer top layer8338 and the securement elementtop layers8301, and then covered with a photoresist pattern and etched to form the various terminals and leads.Holes8360 andslots8367 may be formed after the terminals and leads, by selectively applying radiant energy such as laser radiation to the sheet to selectively remove portions of the sheet. Alternatively, the slots and holes may be formed before the leads and terminals, as by etching or mechanically punching the dielectric sheet. The leads and terminals may then be formed by applying and selectively etching a metallic layer. In this case, the holes and slots in the dielectric sheet should be temporarily filled with a resist to prevent unwanted etching of the leads and terminals by etchant entering through the holes and slots. Peripheral contact leads8350 and outside terminal leads8374 are bent downwardly, toward the bottom of the interposer, withinslots8367. The downward curvature of these leads may be formed by embossing the sheet used to fabricate these leads. Thus, although each lead8350 and8374 extends into aslot8367 from above thebottom layers8303 and8340 of the securement elements and interposer, each such lead extends to the bottom of the interposer. Before the interposer is assembled to the chip, a set ofsupport elements8307 is juxtaposed withchip8320 so that one such support element lies alongside eachedge8309 of the chip. As best seen inFIG. 19,support elements8307 may be provided as a unitary rectangular ring orbox8311 which may closely surround the edges of the chip. Each support element has a top surface8313 (FIG. 16) arranged to lie substantially coplanar with the front ortop surface8322 of the chip. Thus,chip8320 andsupport elements8307 may be disposed on aplanar carrier8315, and the thickness of the support elements may be substantially equal to the thickness of the chip.
• In assembling the interposer to the chip, the interposer with the various terminals and leads thereon is positioned on the chip so that the slots, and hence the leads, are aligned with the peripheral contacts on the chip. Eachsecurement element8361 overlies onesupport element8307, and is at least partially supported by such element. A bonding tool is then advanced into eachslot8367 and engaged with the peripheral contact leads8350 and with the outside terminal leads8372, so as to force each such lead into engagement with one of theperipheral contacts8330 on the chip. Heat, pressure and ultrasonic energy may be applied through the tool to promote bonding. The arrangement of the leads within the slots greatly facilitates the bonding operation.Bonding tool8355 may be advanced into one of theslots8367 and moved along the length of the slot so as to bond all of the leads to all of theperipheral contacts8330 aligned with that slot. This process may be repeated for eachslot8367. The tool may engage and bond many leads simultaneously.
• After the leads have been bonded to the contacts, a low modulus dielectric encapsulant (not shown) is applied. In an alternative assembly process, thecompliant layers8340 and8303 may be formed by the encapsulant. Thus, the encapsulant may be applied so as to penetrate between the interposer (not shown) and the chip to formcompliant layer8340 between the interposer and the chip. The encapsulant may also penetrate betweensecurement elements8361 andsupport elements8307 to formcompliant layers8303 and penetrate intoslots8367 to coverleads8374 and8350. The encapsulant may be introduced under pressure in a liquid or flowable state and then cured. The interposer, chip and associated elements may be disposed in a mold during this process, and the mold may clamp thewaste areas8383 of the sheet or tape (FIG. 17) so as to limit the flow of the encapsulant. The encapsulant may be injected under pressure using standard injection molding technique. After encapsulation, the assembly illustrated inFIGS. 16 and 17 may be separated from the tape and mounted to a substrate in substantially the same way as the assemblies discussed above. Thus, both theoutside terminals8372 and thecentral terminals8348 may be bonded to contact pads on the substrate.
• The assembly illustrated inFIGS. 16 and 17 provides good reinforcement of the leads during manufacture. Also, the outside terminals provide increased connection capacity. Although the securement elements and outside terminals extend outwardly beyond the peripheral contacts on the chip, this outward extension or “fan-out” is minimal. Preferably, the assembly with securement elements and outside terminals occupies an area in the plane parallel to the chip surface no more than about 1.5 times, and desirably no more than about 1.2 times, the area occupied by the chip itself.
• As shown inFIG. 18, aninterposer8436 according to a further embodiment of the invention is provided withsecurement elements8461,slots8467 andoutside terminals8472 similar to the corresponding components discussed above with reference toFIGS. 16 and 17.Outside terminals8472 are disposed on the second surface of each securement element, i.e., on the surface directed away from thesemiconductor chip8420.Interposer8436 also hascentral terminals8448 on the second surface of the interposer. Eachcentral terminal8448 is connected to apartial lead8450 andbonding terminal8452. Likewise, eachoutside terminal8472 is connected to a similarpartial lead8475 andbonding terminal8477. There are rows ofbonding terminals8452 and8477 on both sides of eachslot8467. The bonding terminals are connected to theperipheral contacts8430 onchip8420 by a wire-bonding operation similar to that discussed above with reference toFIG. 13. Here again, disposition of the bonding terminals in rows facilitates the wire-bonding operation.
• Chip8420 also hascentral contacts8431 disposed in the central region of the chip front surface.Interposer8436 has ahole8480 encompassing these central contacts. Some of thebonding terminals8452 associated with certaincentral terminals8448 are disposed adjacent the edges ofhole8480. These bonding terminals are connected by wire bonds to thecentral contacts8431 of the chip, so that the central contacts as well as theperipheral contacts8430 will be connected to the substrate through thecentral terminals8448 of the interposer.
• Assemblies according to the invention may include additional elements for mechanical and electrical protection. Thus, a thin electrically conductive grounding layer such as a metallic layer may be incorporated in the interposer to electrically isolate the terminals from the chip, and to provide better control of impedances in leads extending along the interposer. Such a conductive layer must be separated from the terminals by a dielectric layer. The interposer itself may include multiple layers of terminals and leads separated from one another by intermediate dielectric layers. Such an arrangement allows the leads on the interposer to cross over one another without contacting one another, and allows for more leads and/or wider leads in a given area. The topmost layers of such a multilayer interposer may have holes aligned with the terminals of the lower layers, to provide access to these lower-layer terminals and permit connection to a substrate.
• The components illustrated inFIG. 20 are similar to those depicted inFIGS. 16 and 17. Thus, the structure includes aninterposer8736 andsecurement elements8761 definingslots8767 therebetween, only one such securement element and slot being visible inFIG. 20. The outside terminal leads and peripheral leads includeportions8754 extending across the slots. Each such lead portion extends into the slot from above thecompliant layer8703 of the associated securement element and above thecompliant layer8740 of the interposer. In the condition illustrated inFIG. 16, before bonding oflead portions8754 toterminals8730 of the chip, these lead portions are substantially planar. That is, they extend substantially in a plane parallel to the plane ofinterposer8736 and hence parallel to the plane ofchip front surface8722 when the interposer overlies the chip. Each such lead is curved in this horizontal plane, in the direction of elongation of the slot. Thus, each such lead includesend portions8780 and8782 at the edges of the slot,adjacent securement element8761 andinterposer8736 respectively. Eachlead portion8754 further includes amiddle portion8784 adjacent the center of the slot and overlying one of theperipheral contacts8730 onchip8720. Each suchmiddle portion8784 is offset from the imaginary axis connecting ends8780 and8782. As shown inFIG. 20, the offset is in the direction of elongation ofslot8767. During the assembly process, atool8786 is advanced intoslot8767 tobond lead portion8754 to chipperipheral contact8730. The tool engages themiddle portion8784 of each lead portion, and forces the middle portion downwardly into engagement withchip contact8730. Because the middle portion is offset from the axis connecting ends8780 and8782, this downward motion of the middle portion can be accommodated by a controlled twisting motion of the ends. Themiddle portion8784 may also bend downwardly to some degree. This structure provides a controlled downward motion ofmiddle portion8784. As eachlead portion8754 is retained atends8780 and8782 during this operation, the portions will remain in the desired positions and hence will be properly aligned withchip contact8730. As all of themiddle portions8784 are offset in the same direction, the offsets in the lead portions do not appreciably increase the required spacings betweenlead portions8754 along the length ofslot8767. Moreover, these offsets, lying in the plane of the interposer, can be formed without any separate embossing or bending operation, in the same etching operation used to form the leads. The bonding tool may engage and bond the middle portions of several leads simultaneously.
• As illustrated inFIGS. 21 and 22, aconnection component930 for use in providing terminals on the rear or bottom surface of a chip includes a generally cruciform, unitary sheet comprising a generallyrectangular backing element932 and flaps934 projecting from the edges of the backing element. The sheet has a layered structure including aconductive layer936, an insulatinglayer938 and a further insulatinglayer940 on the opposite side ofconductive layer936.Layer938 defines afirst surface942 of the connection component, whereaslayer940 defines asecond surface944. A set ofterminals946 are disposed on thefirst surface942 of the connection component in a central region of thebacking element932. These terminals may be disposed in a rectilinear, grid-like array. Although only a few terminals are shown inFIG. 21 for clarity of illustration, several hundred terminals may be provided on a typical component.
• Leads948 are also formed on thefirst surface942 ofconnection component930, each such lead being formed integrally with oneterminal946 and electrically connected thereto.Leads948 extend outwardly, away from backingelement932 onflaps934, and project to the extremities of the flaps. Thus, eachsuch lead948 includes a flap portion extending along the associated flap, and a central portion extending from the inner margin of the flap to the associatedterminal946. The thickness of the various layers constitutingconnection component930 is greatly exaggerated inFIG. 22 for clarity of illustration. In practice, each of these layers has the minimum thickness required to meet electrical requirements. Desirably, insulatinglayers938 and940 have the minimum thickness required to provide freedom from pinholes and breaks in the insulation, whereasconductive layer936 and leads948 have the minimum thickness required for electrical continuity and to provide a relatively low resistance current path. Preferably, each of the insulating layers is less than about 0.5 mm thick, and more preferably, less than about 0.25 mm thick, whereasconductive layer936 preferably is less than about 0.1 mm thick and each of leads948 preferably is less than about 0.1 mm thick.Connection component930 may be formed from substantially the same materials, and in substantially the same manner, as the tape used for tape automated bonding processes. Thus, insulatinglayers938 and940 may incorporate conventional polymeric dielectric materials such as polyimide, whereaslayer936,conductors948 andterminals946 may be formed from copper or other metals. The pattern of terminals and conductors may be formed by photochemical etching or deposition techniques similar to those used in the manufacture of tape automated bonding tapes and flexible printed circuits.
• Component930 may be used with a box-like element950 shown inFIGS. 23 and 24.Box element950 includes four support elements orwalls952 arranged to form a generally rectangular ring and afloor element954 extending across the interior of this ring so thatwalls952 andfloor element954 cooperatively define a rectilinear closed-bottom box having aninterior space956 open at the top (the side visible inFIG. 23). The box has length l and width w slightly larger than the corresponding dimensions ofchip920, whereas the depth d of the box desirably is slightly greater than the thickness ofchip920, i.e., slightly greater than the distance betweensurfaces922 and924 of the chip. Each support member orwall952 has aprojection958 extending downwardly, beneathfloor element954, so thatprojections958 andfloor element954 cooperatively define a further openinterior space960 on the bottom side offloor element954. The floor element has several holes orapertures962 extending through it, betweenspaces956 and960.Space960 is shallower thanspace956.Box element950 may be formed from substantially rigid materials such as thermoplastics or thermosetting polymers, glass, ceramics glass-ceramic materials, polymer-matrix composites and metal-matrix composites, and metals, metals and polymers being preferred.
• In a fabrication process according to one aspect of the invention, a resilient, compliant layer964 (FIG. 25) formed from a relatively low elastic modulus material is provided in the lower or downwardly facingspace960 ofbox element950. Preferably, this low-modulus material has elastic properties (including modulus of elasticity) comparable to those of soft rubber, about 20 to about 70 Shore A durometer.Compliant layer964 hasholes966 interspersed withmasses968 of the low modulus material.Layer964 may be formed from a sheet of solid elastomer by punching or perforating to formholes966, and then inserted into thelower space960 ofbox element950 and fastened in place byadhesive material970 extending throughholes962 in thefloor element954 ofbox element950. A portion of this adhesive material may partially or fully coat the top surface offloor element954 so as to provide some degree of surface adhesion or tack on the top surface of the floor element. Alternatively,compliant layer964 may be formed by molding in place within the lower space of the box element. Thus, the elastomeric material may be introduced in a fluid condition and chemically or heat cured to a resilient state. Where thecompliant layer964 is formed in this fashion, some portion of the elastomeric material may protrude throughholes962 in much the same way asadhesive material970. This serves to fasten the compliant layer to the undersurface of the floor element. The compliant layer may also be applied by silk-screening. In yet another alternative procedure, the compliant layer can simply be placed within the lower space of the box element without fastening it to the box element.
• In the next stage of the assembly process,connection component930 is juxtaposed withbox element950 so that thesecond surface44 of the connection component confronts the exposed or bottom surface ofcompliant layer964, and so that thebacking element932, is aligned withfloor element954 andcompliant layer964. At this stage of the process, eachflap934 ofconnection component930 projects outwardly beyondwalls952 and extends across the lower extremity of oneprojection958. Thus, the central region of the backingelement bearing terminals946 is aligned withcompliant layer964, the terminals facing downwardly, away from the compliant layer andfloor element954. The arrangement ofmasses968 incompliant layer964 is selected to match the arrangement ofterminals946. As best illustrated inFIG. 26 (showing a later stage of the process) each terminal946 is aligned with amass968 of the low modulus material whereas theholes966 inlayer964 are aligned with spaces betweenterminals946.
• In the next stage of the manufacturing process, flaps934 are bent upwardly alongside the walls or supportelements952 ofbox element950. Thus, eachflap934 and theflap portions48 of the conductors on such flap extends upwardly alongside the associatedwall952. The extremity of each flap is bent inwardly over the uppermost margin of the associatedwall952. Thus, as seen inFIG. 25, the extremity offlap934ais bent inwardly at the upper extremity ofwall952a.Likewise,flap934bextends upwardly alongside wall952bas illustrated inFIG. 26 and is bent inwardly over the upper most extremity ofwall952b.Thus, the extremities ofconductors948 adjacent the edges of the flaps are disposed along the top edges ofwalls952, remote fromfloor element954 around the top opening ofspace956.Conductors948 extend downwardly alongside the walls of the box element toterminals946, which are disposed beneath the box element. As connectingelement930 and hence flaps934 are flexible, the bending operation can be performed readily. The extremities of the flaps overlying the top edges ofwalls950 are bonded to the tops of the walls.
• A layer of a preferably flexible dielectric material is applied as asolder mask layer972 covering the downwardly facing first surface ofbacking element932.Solder mask layer972 is provided withapertures974 aligned withterminals946 of the backing element. This solder mask layer may be formed by molding or by selective curing of an elastomeric material. For example, the material may be applied in a flowable, uncured state and then cured by radiant energy. The radiant energy may be applied selectively so as to cure all portions of the layer except those portions overlying theterminals946. Subsequent to this selective curing, the uncured portions may be removed. Alternatively, the solder mask may be applied as a solid layer and punctured to exposeterminals946. As discussed further hereinbelow,solder mask layer972 may be omitted in certain cases.
• The assembly at this stage constitutes a receptacle adapted to receive a semiconductor chip. These receptacles can be prefabricated in mass production and distributed to semiconductor chip manufacturers and users. Alternatively, the receptacle can be fabricated immediately before it is united with the semiconductor chip.
• The receptacle is united with asemiconductor chip920 by first placing chip920 (FIG. 26) into the top orupper space956 ofbox element950, so that thefront face922 of the chip faces upwardly, away fromfloor element954 andbacking element932. Thechip920 may be temporarily retained in position within the receptacle by the adhesive970 on the top surface offloor element954. In this position, theedges926 of the chip confront the support elements orwalls952 of the box element.Chip920 is of substantially the same type as illustrated inFIG. 11. This,chip920 hascontacts928 disposed on itsfront surface922, the contacts being arranged in rows adjacent theedges926 of the chip.Flaps934, and hence leadportions948 on the flaps, extend upwardly alongsideedges926 of the chip, so that the leads on each such flap extend to the vicinity of one row ofcontacts928 on the chip. Each row ofcontacts928 is positioned immediately adjacent to the extremities ofleads948 on one offlaps934. Thefront surface922 of the chip, and hencecontacts928, are disposed at approximately the same height abovefloor element954 as are the extremities ofleads948, although the extremities of the leads may be elevated slightly abovesurface922.
• While the chip is in this position, thecontacts928 are electrically connected to leads948 by wire bonding the contacts to the adjacent extremities of the leads. In the wire bonding operation,fine wires974 are connected betweencontacts928 andlead portions948, thereby electrically connecting eachlead portion948 to onecontact928 in the adjacent row of contacts. In effect,wires974 merge withlead portions948 to form a composite lead extending fromterminal928, around onewall element952 and downwardly alongside theedge926 of the chip to oneterminal946 on thebacking element932. The process of wire bonding per se is well known in the electronics art and need not be described in detail herein. Briefly, this process utilizes a movable wire dispensing and bonding head. The head is brought into engagement with one of the elements to be connected and an end of a fine wire is bonded to such element. The head is then moved while paying out the wire until it reaches the other element to be connected, whereupon the wire is bonded to such other element and cut, leaving the wire in place. Wire bonding processes typically are controlled by detecting the relative position and orientation of the components to be connected and then controlling the wiring bonding head accordingly so as to bring the wires into contact with the desired elements. This allows the desired interconnections to be made even where the relative positions of the components to be connected differ from the nominal positions. Typically, the relative positions and orientations of the components are detected by robot vision systems, such as television-based pattern recognition systems. These techniques desirably are used in the wire-bonding step of the present method. Where such techniques are employed, it is not essential to provide great precision in the positioning ofchip920 or in the positioning oflead portions948. This minimizes the need for close control of the bending operation discussed above.
• After thebonding wires974 have been attached, apad975 of a soft, thermally conductive material, such as silicone with a thermally conductive filler, is placed atop thefront surface922 of the chip. The pad covers the central portion of the chip front surface, remote from contacts918 andwires974. A layer of anencapsulant976 is applied over thefront face922 of the chip. The encapsulant, which desirably is a soft, dielectric material covers thebonding wires974, thecontacts928 and the extremities of thelead portions948 disposed atop thewalls952. The encapsulant desirably also penetrates into and at least partially fills spaces between theedges926 of the chip and the confrontingwalls952 of the box element. Acover978 is then placed over the top of the assembly. Cover978 may be a box-like metallic elemrient, commonly referred to as a “chip can,” or else may be molded in a place on the assembly from a polymeric material such as an epoxy. Cover978 may be united with the periphery of thesolder mass layer972 so as to seal the assembly against subsequent contamination.Encapsulant976 contacts thefront surface922 of the chip and also contacts cover978, thus providing a path for heat transmission from the chip to the cover. This facilitates heat transfer from the chip to the surroundings, outside the assembly, during operation of the chip. Cover978 alsocontacts layer975, further facilitating heat transfer.
• The assembly desirably is tested before being used as part of a larger assembly. The assembly desirably is tested in substantially the same way as discussed above using an electrical testing fixture having numerous pins or probes connected to an appropriate test circuit and rigidly mounted to a common fixture or support. To provide a reliable test, the numerous pins or probes on the test fixture must be held in contact with therespective terminals946 at the same time. In this arrangement as wellterminals946 can be independently displaced towardschip922. Such displacement permits continued movement of the test fixture and assembly towards one another, until all of the pins are engaged with theirrespective terminals946. Each terminal946 will be biased against the associated pin of the test fixture by the resilience of the compliant layer. This assures reliable contact and a reliable test. As discussed above, the configuration ofcompliant layer964 contributes to this action. Eachmass968 of low modulus material provides backing and support for the terminal946 aligned therewith. As the pins of the test fixture engage the terminals, each mass968 is compressed in the vertical direction and therefore tends to bulge in horizontal directions, parallel to the plane of the chip.Holes966 provide space for such bulging.Compliant layer964 need only provide for sufficient movement ofterminals946 to accommodate tolerances in the test equipment and in the assembly itself. Typically, about 0.0005 inch (0.125 mm) or less compliance is sufficient. For example,compliant layer964 may be about 0.008 inch (0.2 mm) thick.
• After testing, the assembly is mounted to a substrate988 (FIG. 26) havingelectrical contact pads990, using techniques similar to those used for mounting the assemblies discussed above. For example, the assembly may be placed on the substrate so that theapertures974 insolder mass layer972 andterminals946 are aligned with thecontact pads990 of the substrate. Masses of an electricallyconductive bonding material991 such as a solder or an electrically conductive adhesive may be disposed between theterminals946 and thecontact pads990 of the substrate. These masses may be caused to flow and to bond with the terminals and contact pads, in the same manner as discussed above.
• Becauseterminals946 are disposed at substantial center-to-center distances, standard surface mount techniques can be used without difficulty. In this regard, it should be appreciated thatterminals946 are distributed over an area approximately equal to the entire area of the chip bottom surface924. By contrast,contacts928 of the chip itself are concentrated in rows around the periphery. Thus, the center-to-center distances between theterminals946 may be substantially greater than the center-to-center distances betweencontacts928. In typical applications, electrical connections for a chip having a substantial number of input and output terminals, commonly referred to as a “I/O count” can be achieved with 10-25 mil (250-625 micrometer) center-to-center distances.
• The composite leads includinglead portions948 andbond wire974 provide reliable interconnections betweencontacts928 andterminals946. Because the electricallyconductive layer936 of connectingelement930 extends upwardly, alongside the chip withlead portions948,lead portions948 have predictable, controlled impedance. This reliable electrical performance is also enhanced by the predictable geometric configuration oflead portions948. Eachlead portion948 has a predetermined width and is located in a predetermined position relative to the adjacent lead portions. These relative positions and widths are fixed when the connectingelement930 is made. Although the composite leads do includebonding wires974, these bonding wires are so short that they do not introduce appreciable unpredictable capacitance or inducence.
• The assembly thus provides a compact, rugged and economical chip mounting. The entire assembly occupies little more area (in the plane of the chip) than the chip itself. As the leads and flaps extend alongside the chip, in close proximity to the edges of the chip, they do not substantially increase the area occupied by the assembly. Also, because the assembly can be pretested before mounting to the substrate, high quality can be assured. The methods and structure discussed above can be varied in numerous ways. Also,solder mask layer972 may be applied at any stage in the process. If desired, this layer could be formed as part ofconnection element930 or applied after the remaining components of the assembly, as by molding in place so thatsolder mass layer932 contacts cover978.
• The configuration ofbox element950 can be varied from that illustrated. Thefloor element954 can be omitted entirely, or else the floor element may include only small tabs projecting inwardly from thewalls952 so as to support the chip only at its edges or corners. In either casecompliant layer964 will be in direct engagement with the bottom surface of the chip and with the backing element. Alternatively, theholes962 in thefloor element954 may be omitted. Thedownward projections958 of thewalls952 may be omitted, so that the walls terminate flush with the floor element or flush with the bottom surface of the chip if the floor element is omitted. The bottom edges of the walls may be provided with chamfers or radii to prevent damage to theconnection component930 when the flaps are bent upwardly. The box element may be provided with supports, such as legs at the corners of the box element, projecting downwardly for engagement with the substrate. In this case, the box element will serve to support the chip above the substrate, thereby preventing crushing of the solder joints during manufacturing procedures or in use. This arrangement is particularly useful where a heat sink is forcibly held in engagement with the front surface of the chip. Also, the box element can be employed as part of a hermetic sealing arrangement around the chip.
• Thecompliant layer964 disposed adjacent the backing element can extend outwardly to the outer surfaces of the walls or supportelements952, so that a portion of the compliant layer is interposed between the lower edge of each such wall or support element and the backing element. This arrangement is particularly useful when some of theterminals946 are disposed on that portion of the backing element aligned with the bottom edges of the walls.
• Where the coefficient of thermal expansion of the box element differs substantially from the coefficient of thermal expansion of the chip, thebonding wires974 can flex to compensate for relative movement of the chip and the lead portions at the extremities of the flaps, overlying the top edges of the walls. In those cases where the flap portions ofleads948 are bonded directly to the contacts on the chip as discussed below, those flap portions of the leads may be flexible to provide similar compensation. Where the coefficient of thermal expansion of the box element differs substantially from that of the substrate, the backing element preferably is not bonded to the bottom of the box element except through the compliant layer. This permits the flaps to flex and the backing element to move relative to the box element and absorb differential thermal expansion.
• The configuration of the heat transfer elements can be varied considerably. Thus, the thermally conductive pad orlayer975 may include a metallic slab bonded to the front or top surface of the chip. Such a metallic heat sink may include fins, plates or projections to further facilitate heat transfer. A plurality of chips can be engaged with the same heat sink. Essentially any heat sink which can be used with conventional face-up chip assemblies can be employed.
• The backing element and flaps may include more than one layer of leads, so as to accommodate particularly complex interconnection requirements. Also, more than one flap may be provided at each edge of the backing element, and these multiple flaps may extend in superposed relation along the edge of the chip or along the wall of the box element.
• As illustrated inFIG. 27, the box element may be omitted. Thus, theflaps9134 of connectingelement9130 may be folded upwardly, alongside theedges9126 ofchip9120, without intervening wall members. Also,compliant layer9164 may be disposed directly betweenbacking element9132 and the bottom or rear surface9124 of thechip9120, without any intervening floor element. In the arrangement shown inFIG. 27, eachflap9134 not only extends upwardly along theedge9126 of the chip but also extends inwardly, over a marginal portion of thechip front surface9122 adjacent theedge9126. Each flap has aslot9137 overlying a row ofcontacts9128 on the chip. Theextremities9149 oflead portions9148 extend across this slot and hence overlie thechip contacts9128. In the assembly process,extremities9149 can be bonded directly toterminals9128 by techniques similar to those discussed above with reference toFIGS. 16 and 20. To facilitate the bonding operation,extremities9149 may be curved in directions parallel to the length ofslot9137 so as to permit them to deflect downwardly and engagecontacts9128 more readily under the influence ofbonding tool9151. In the manufacturing process, the connectingelement9130 andcompliant layer9164 are assembled tochip9120, and theflaps9134 of the connecting element are folded directly upwardly, alongside theedges9126 of the chip. The extremities of flaps are then folded inwardly over the front surface of the chip. The assembly illustrated inFIG. 27 may also be provided with a solder mask layer, housing and encapsulant as discussed above.
• The arrangement ofFIG. 28 is similar to that discussed above with reference toFIG. 27, in that the extremities offlaps9234 are folded over thefront surface9222 of the chip, thereby positioning theextremities9249 oflead portions9248 over contacts228 on the chip. Here, however, the connecting element includesvias9251 extending through it from beneath eachlead extremity9249 to thesecond surface9244 of the flap, i.e., the surface opposite from the first or lead-bearing surface9242. Each such via is filled with an electrically conductive bonding material such as athermocompression bonding alloy9253.Bonding material9253 is activated by heat or pressure, using conventional bonding techniques, to bond eachlead extremity9249 to onecontact9228 on the chip. The electricallyconductive layer9236 of the connecting element terminates remote fromvias9251, so that the electrically conductive layer does not make an electrical connection with theconductive material9253. If desired, theconductive layer9236 may be extended to one or a few ofvias9251 so as to provide a ground connection tolayer9236. That is, one ofleads9248 may be connected to a terminal (not shown) which in turn is connected to a ground on the substrate, andlayer9236 may be grounded through that lead.
• As an alternative to thermocompression or other conventional bonding techniques, the leads can be connected to the contacts on the chip by using a so-called “Z-conducting” adhesive. Such materials ordinarily include electrically conductive particles selected so that when the material is applied in a thin layer, it will have appreciable electrical conductivity in the direction through the layer but only insignificant conductivity in directions parallel to the layer. Z-conducting adhesives may also be used to connect the leads of the interposers discussed above to the contacts of the chips.
• As illustrated inFIG. 29, a sub-assembly in accordance with the present invention may be mounted on another chip. For example, as illustrated inFIG. 29contacts9328 on thefront surface9322 ofchip9320 are connected, throughterminals9346, tocontacts9391 of asemiconductor chip9393. Thus,chip9393 itself serves as the substrate for mounting theassembly incorporating chip9320.Chip9393 in turn is connected via conventional wire bond leads9395 to a further substrate and hence to other electronic elements. Conversely, afurther chip9377 is mounted so as to overlie the front surface ofchip9320. Aninterposer9379 is disposed onchip front surface9322. This interposer hasterminals9381 connected to some of thecontacts9328 on the chip front surface via flexible leads. The interposer itself is flexible and includes acompliant layer9383 disposed betweenterminals9381. Those terminals in turn are connected toterminals9356 of a further sub-assembly, which in turn are connected tocontacts9338 ofchip9377. Thus,chips9320 and9377 are interconnected in a stacked circuit assembly which in turn is mounted onchip9393. Any number of chips can be interconnected in such a stacked assembly.
• In an assembly according to a further embodiment of the invention, illustrated inFIG. 30, the orientation of the sheet-like connection component is reversed. That is, the lead-bearing orfirst surface9442 faces towardchip9420.Terminals9446 are exposed through holes9473 extending through the insulatinglayers9440 and9438. Theconductive layer9436 disposed between these insulating layers terminates remote from holes9473, so that the two insulating layers merge with one another at the boundaries of the holes and insulate the holes fromlayer9436. Thus, bonding material can be introduced inholes9437 so as to connectterminals9446 to a substrate. Also in this arrangement, theextremities9435 offlaps9434 are bent outwardly, away from the chip, and the walls orsupport elements9452 are disposed outside of the flaps. That is, the flaps lie betweensupport elements9452 and the chip.Compliant layer9464 immediately underliesterminals9446.
• In a further variant (not shown) the support elements or walls can be integral with the connecting element, and particularly can be integral with the flaps. Thus, the connecting element can have relatively stiff regions constituting the flaps and a flexible region constituting the central or backing element. The stiff regions constituting the flaps can be bent upwardly so as to form a self-supporting structure. As in the arrangement discussed above, this provides a generally box-like or cup-like structure having an open top with lead portions disposed around the periphery of the opening for receiving a chip and connecting thereto.
• As will be readily appreciated, numerous further variations and combinations of the features discussed above can be utilized without departing from the present invention as defined by the claims. In one such variant (not shown) the backing element is provided substantially as discussed above, but the flaps and the lead portions on the flaps are omitted. In this arrangement, the bonding wires constitute the principal portion of each lead. The bonding wires extend downwardly, alongside the edges of the chip, to the backing element and join the backing element adjacent to the rear or bottom face of the chip. In this arrangement, the bonding wires constitute the leads extending alongside the edges of the chip. This arrangement is distinctly less preferred because it does not offer the same degree of control over lead impedance as the other arrangements discussed above. Thus, the foregoing descriptions of the preferred embodiments should be taken by way of illustration rather than by way of limitation of the invention defined by the claims.

Claims (44)

1. (canceled)

2. A unit comprising:

(a) a semiconductor chip having a front surface with contacts thereon and a rear surface;

(b) a plurality of terminals, at least some of said terminals being electrically connected to at least some of said contacts and overlying a surface of said chip;

(c) a dielectric material overlying said chip and having holes extending through it such that said terminals are exposed through said holes; and

(d) masses of electrically conductive bonding material disposed in said holes in contact with said terminals.

3. A unit as claimed inclaim 2 wherein said holes in said dielectric material are devoid of electrically conductive material other than said bonding material.

4. A unit as claimed inclaim 2 wherein said dielectric material is polymeric material.

5. A unit as claimed inclaim 2 wherein said holes are formed by selectively applying radiant energy to said dielectric material so as to remove portions of said dielectric material.

6. A unit as claimed inclaim 2 wherein said holes are formed by selectively applying radiant energy to said dielectric material so as to selectively cure the dielectric material, and then removing uncured dielectric material.

7. A unit as claimed inclaim 2 wherein said holes are formed by mechanically punching said dielectric material.

8. A unit as claimed inclaim 2 wherein said terminals are flat.

9. A unit as claimed inclaim 2 further comprising electrically conductive lead portions, said at least some of said terminals being electrically connected to said contacts through said lead portions.

10. A unit as claimed inclaim 9. wherein said lead portions are formed integrally with said terminals.

11. A unit as claimed inclaim 10 wherein said at least some of said terminals overlie said front surface of said chip.

12. A unit as claimed inclaim 9 wherein said lead portions are attached to said contacts.

13. A unit as claimed inclaim 9 further comprising wire bonds connecting said lead portions to said contacts.

14. A unit as claimed inclaim 2 wherein said bonding material is a solder.

15. A unit as claimed inclaim 2 wherein said bonding material abuts said dielectric material.

16. An assembly comprising a unit as claimed inclaim 2 and a circuit panel having contact pads thereon, said bonding material connecting said terminals to said contact pads.

17. An assembly as claimed inclaim 16 wherein said bonding material projects beyond said dielectric material to said contact pads.

18. A unit comprising:

(a) a semiconductor chip having a front surface with contacts thereon and a rear surface;

(b) a first dielectric layer having a plurality of electrically conductive terminals, at least some of said terminals being electrically connected to at least some of said contacts and overlying a surface of said chip;

(c) a dielectric material overlying said terminals and having holes extending through it in alignment with said terminals; and

(d) masses of electrically conductive bonding material disposed in said holes in contact with said terminals.

19. A unit as claimed inclaim 18 wherein said holes in said dielectric material are devoid of electrically conductive material other than said bonding material.

20. A unit as claimed inclaim 19 wherein said dielectric material is in the form of a second dielectric layer.

21. A unit as claimed inclaim 18 wherein said first dielectric layer has a first surface facing toward said chip and a second surface facing away from said chip and said terminals are disposed on said second surface of said first dielectric layer.

22. A unit as claimed inclaim 21 wherein said terminals are formed by etching a metallic sheet disposed on said second surface of said first dielectric layer.

23. A unit as claimed inclaim 18 wherein said dielectric material is polymeric material.

24. A unit as claimed inclaim 18 wherein said holes are formed by selectively applying radiant energy to said dielectric material so as to remove portions of said dielectric material.

25. A unit as claimed inclaim 18 wherein said holes are formed by selectively applying radiant energy to said dielectric material so as to selectively cure the dielectric material, and then removing uncured dielectric material.

26. A unit as claimed inclaim 18 wherein said holes are formed by mechanically punching said dielectric material.

27. A unit as claimed inclaim 18 wherein said terminals are flat.

28. A unit as claimed inclaim 18 further comprising electrically conductive lead portions extending along said first dielectric layer, said at least some of said terminals being electrically connected to said contacts through said lead portions.

29. A unit as claimed inclaim 28 wherein said lead portions are formed integrally with said terminals.

30. A unit as claimed inclaim 28, wherein said first dielectric layer overlies said front surface of said chip.

31. A unit as claimed inclaim 30, wherein said lead portions are attached to said contacts.

32. A unit as claimed inclaim 28 wherein said first dielectric layer overlies said rear surface of said chip.

33. A unit as claimed inclaim 32 further comprising wire bonds connecting said lead portions to said contacts.

34. A unit as claimed inclaim 18 wherein said bonding material is a solder.

35. A unit as claimed inclaim 18 wherein said bonding material abuts said dielectric material.

36. An assembly comprising a unit as claimed inclaim 18 and a circuit panel having contact pads thereon, said bonding material connecting said terminals to said contact pads.

37. An assembly as claimed inclaim 36 wherein said bonding material projects beyond said dielectric material to said contact pads.

38. A unit comprising:

(a) a semiconductor chip having a front surface with contacts thereon and a rear surface;

(b) a first dielectric material overlying said chip;

(c) a plurality of terminals, at least some of said terminals being electrically connected to at least some of said chip contacts and overlying the first dielectric material;

(d) a second dielectric material overlying said chip and having holes extending through it such that said terminals are exposed through said holes; and

(e) masses of electrically conductive bonding material in electrical contact with said terminals and disposed in and protruding out of said holes.

39. A unit as claimed inclaim 38 wherein said first dielectric material is in the form of a first dielectric layer.

40. A unit as claimed inclaim 39 further comprising electrically conductive lead portions extending along a surface of said first dielectric layer, said at least some of said terminals being electrically connected to said at least some of said contacts through said lead portions.

41. A unit as claimed inclaim 39 wherein said second dielectric material is in the form of a second dielectric layer overlying said first dielectric layer.

42. A unit as claimed inclaim 38 further comprising electrically conductive lead portions, said at least some of said terminals being electrically connected to said contacts through said lead portions.

43. A unit as claimed inclaim 42 wherein said lead portions are formed integrally with said terminals.

44. An assembly comprising a unit as claimed inclaim 38 and a circuit panel having contact pads thereon, said bonding material connecting said terminals to said contact pads.

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