US20050077613A1 - Integrated circuit package - Google Patents
Integrated circuit packageDownload PDFInfo
- Publication number
- US20050077613A1 US20050077613A1US10/635,839US63583903AUS2005077613A1US 20050077613 A1US20050077613 A1US 20050077613A1US 63583903 AUS63583903 AUS 63583903AUS 2005077613 A1US2005077613 A1US 2005077613A1
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- United States
- Prior art keywords
- integrated circuit
- substrate
- circuit package
- semiconductor die
- package
- Prior art date
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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Definitions
- the present inventionrelates to integrated circuit packaging and manufacturing thereof, and more particularly, to integrated circuit packaging for improved dissipation of thermal energy.
- a heat sinkis one type of device used to help dissipate heat from some integrated circuit packages.
- Various shapes and sizes of heat sink deviceshave been incorporated onto, into or around integrated circuit packages for improving heat dissipation from the particular integrated circuit package.
- U.S. Pat. No. 5,596,231 to Combsentitled “High Power Dissipation Plastic Encapsulated Package For Integrated Circuit Die,” discloses a selectively coated heat sink attached directly on to the integrated circuit die and to a lead frame for external electrical connections.
- the inventionfeatures a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate.
- the inventionfeatures a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a plurality of cavities, each said cavity through the substrate between the first and second surfaces, and a plurality of conductive vias, each said via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of said substrate, mounting a plurality of semiconductor dies on the strip, at least a portion of each semiconductor die being disposed inside each cavity, encapsulating in a molding material at least a portion of the first surface of said substrate, and removing the strip from the substrate to expose a surface of each semiconductor die.
- the inventionfeatures an integrated circuit package including a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, a semiconductor die electrically coupled with the conductive via, at least a portion of the semiconductor die being disposed inside the cavity of the substrate, an encapsulant material encapsulating a portion of the semiconductor die such that at least a portion of a surface of the semiconductor die is exposed.
- FIG. 2is a simplified cross-sectional view of an integrated circuit package according to a second embodiment of the present invention.
- FIG. 3is a simplified bottom view of an integrated circuit package according to embodiments of the present invention.
- FIGS. 4A-4Hshow one example of steps performed in assembly of embodiments of an integrated circuit package of the present invention.
- FIGS. 5A-5Ishow another example of steps performed in assembly of embodiments of an integrated circuit package of the present invention.
- FIG. 6is a simplified cross-sectional view of an integrated circuit package assembly including an integrated circuit package as shown in FIG. 2 and another integrated circuit package.
- FIGS. 1 and 2show certain components of integrated circuit packages according to embodiments of the present invention.
- the integrated circuit packages depicted in FIGS. 1 and 2each generally include a substrate 101 , a semiconductor die 103 and an encapsulant 105 .
- the substrate 101may be made of either a rigid material (e.g., BT, FR4, FR5 or ceramic) or a flexible material (e.g., polyimide), and may have circuit traces 112 onto which a semiconductor die 103 may be interconnected using, for example, wire bonding techniques or tape automated bonding.
- the packagemeasures about 1.0 mm thick (shown as dimension “a” in FIG. 1 ) and about 35 mm wide (shown as dimension “b” in FIG. 3 ).
- the width dimension of certain other embodimentsmay vary from 7 mm to 50 mm. However, such dimensions are provided only as non-limiting examples of certain embodiments of the present invention.
- external terminals of one embodiment of the present inventionmay include an array of solder balls 106 .
- the solder balls 106may function as leads capable of providing power, signal inputs and signal outputs to the semiconductor die 103 .
- Such a configurationmay be referred to as a type of ball grid array. Absent the solder balls 106 , such a configuration may be referred to as a type of land grid array, as shown in FIG. 1 .
- traces 112may be embedded photolithographically into the substrate 101 , and are electrically conductive to provide a circuit connection between the semiconductor die 103 and the substrate 101 . Such traces 112 may also provide an interconnection between input and output terminals of the semiconductor die 103 and external terminals provided on the package.
- the substrate 101 of the embodiment shown in FIG. 1may have a multi-layer circuit trace 112 made of copper.
- the substrate 101 shown in FIG. 1has vias 110 which may be drilled into it to connect the top and bottom portions of each circuit trace 112 .
- Such vias 110may be plated with copper to electrically connect the top and bottom portions of each trace 112 .
- the substrate 101 shown in FIG. 1may also have a solder mask on its surface. The solder mask of one embodiment electrically insulates the substrate and reduces wetting (i.e., reduces unwanted flow of solder into the substrate 101 ).
- One embodimentmay include a conductive trace 112 in the form of a ring around the cavity 120 in the substrate 101 .
- a ring-shaped conductive trace 112may be connected to the top surface of the substrate 101 by means of electrically conductive vias 110 .
- Such an arrangementmay allow a heat slug 108 to be electrically connected to the semiconductor die 103 by the way of wire bonding 104 , thereby resulting in a ground plane surface beneath the semiconductor die 103 , which may enhance the electrical characteristics of the package.
- FIG. 4Ashows a step in the manufacture of one type of the integrated circuit package showing a substrate 101 with a cavity 120 .
- the substrate 101may be produced in a form to accommodate standard semiconductor manufacturing equipment and process flows, and may also be configured in a matrix format to accommodate high-density package manufacturing.
- FIG. 5Adepicts a step in another process for manufacturing integrated circuit packages, and shows a substrate 501 with a number of cavities 520 - 1 , 520 - 2 .
- a tape 102 with adhesive material on at least one sideis applied to the bottom side of the substrate 101 , and may be applied in strip form to accommodate a number of substrates.
- the tape 102may be, for example, a high temperature stable polyimide with an adhesive material on at least one surface.
- FIG. 5Bdepicts a tape 502 having its adhesive material on the surface which interfaces with the bottom of the substrate 501 .
- the adhesive materialhas a contact sticking characteristic such that a semiconductor die 103 placed into contact with the adhesive material will stick to the tape 502 . In this embodiment, however, the adhesive material is such that no adhesive residue is left on the substrate 101 when the tape 502 is removed.
- FIG. 4Ca semiconductor die 103 may then be mounted or otherwise attached to the tape 102 through the cavity 120 in the substrate 101 .
- FIG. 5Cdepicts a number of semiconductor dies 503 - 1 , 503 - 2 mounted or otherwise attached to the tape 502 through each of the cavities 520 - 1 , 520 - 2 of the substrate 501 .
- the semiconductor die 103may then be interconnected to routing traces 112 of the substrate 101 by a gold thermo-sonic wire bonding technique.
- gold wires 104may interconnect the semiconductor die 103 to traces 112 of the substrate 101 .
- FIG. 5Ddepicts the semiconductor dies 503 - 1 , 503 - 2 being interconnected to routing traces by, e.g., a gold thermo-sonic wire bonding technique.
- the substrate 101 , 501may be encapsulated.
- the encapsulant material 105 , 505may be an epoxy based material applied by, for example, either a liquid molding encapsulation process or a transfer molding technique.
- the substrate 101is fully encapsulated on one side.
- the substrate 101is encapsulated only in the semiconductor die 130 and wire bond area, leaving much of the surface of the substrate 101 opposite to the solder ball area free of encapsulant material 105 .
- the tape 102 , 502may then be removed from the package subassembly as shown in FIGS. 4F and 5F .
- solder balls 106may then be attached to traces 112 of the substrate 101 using, for example, a reflow soldering process.
- FIG. 5Gdepicts solder balls 506 being attached to traces 512 of the substrate 501 .
- the solder balls 106 , 506may be made of a variety of materials including lead (Pb) free solder.
- a heat slug 108may be attached to the exposed surface of the semiconductor die 103 and the area surrounding the cavity 120 in the substrate 101 using a thermally conductive adhesive material 107 such as epoxy.
- the adhesive material 107may also be electrically conductive, such as silver-filled epoxy.
- FIG. 5Hdepicts attachment of a heat slug 508 to each semiconductor die 503 only.
- an alternative heat slugsuch as the one depicted in FIG. 4H , may also be attached to one or more semiconductor dies 503 .
- the integrated circuit packagesmay be singulated into individual units using, e.g., a saw singulation or punching technique.
- FIG. 6shows an integrated circuit package assembly according to an embodiment of the present invention.
- such an embodimentincludes two integrated circuit packages stacked one on top of the other and attached to one another by solder balls 106 .
- the integrated circuit package assembly shown in FIG. 6includes two packages of the embodiment shown in FIG. 2 and a heat slug 108 .
- Another embodiment of an integrated circuit package assembly according to the present inventionmay include two or more integrated circuit packages without a heat slug 108 .
- Other embodiments of integrated circuit package assemblies according to the present inventionmay include integrated circuit packages other than the embodiments specifically shown in FIG. 6 .
- the substrate 101 of certain embodiments of integrated circuit packages and assembliesmay contain electrically conductive traces 112 on an upper surface of the substrate 101 to facilitate electrical coupling with a second integrated circuit package.
- the heat slug 108 shown in FIG. 6may provide a thermal path between a semiconductor die 103 and the environment.
- the heat slug 108may be aligned with and positioned below the bottom surface of the semiconductor die 103 such that the heat slug 108 may contact or thermally couple with an external device such as, e.g., a printed circuit board 200 .
- the heat slug 108is preferably made of a thermally conductive material such as copper or copper alloy.
- the heat slug 108may be sized and configured for use in a specific package arrangement such that, in certain embodiments, the heat slug 108 contacts another type of external device (e.g., an integrated circuit package) to which a package is attached.
- the heat slug 108may be plated with solder or some other appropriate metal to enhance the reflow of solder to the surface of the heat slug 108 .
- the opposite side of the heat slug 108may also be oxide coated to enhance the adhesion to the encapsulant material 105 .
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Abstract
Description
- The present invention relates to integrated circuit packaging and manufacturing thereof, and more particularly, to integrated circuit packaging for improved dissipation of thermal energy.
- A semiconductor device generates a great deal of heat during normal operation. As the speed of semiconductors has increased, so too has the amount of heat generated by them. It is desirable to dissipate this heat from an integrated circuit package in an efficient manner.
- A heat sink is one type of device used to help dissipate heat from some integrated circuit packages. Various shapes and sizes of heat sink devices have been incorporated onto, into or around integrated circuit packages for improving heat dissipation from the particular integrated circuit package. For example, U.S. Pat. No. 5,596,231 to Combs, entitled “High Power Dissipation Plastic Encapsulated Package For Integrated Circuit Die,” discloses a selectively coated heat sink attached directly on to the integrated circuit die and to a lead frame for external electrical connections.
- In one aspect, the invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate.
- In another aspect, the invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a plurality of cavities, each said cavity through the substrate between the first and second surfaces, and a plurality of conductive vias, each said via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of said substrate, mounting a plurality of semiconductor dies on the strip, at least a portion of each semiconductor die being disposed inside each cavity, encapsulating in a molding material at least a portion of the first surface of said substrate, and removing the strip from the substrate to expose a surface of each semiconductor die.
- In a further aspect, the invention features an integrated circuit package including a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, a semiconductor die electrically coupled with the conductive via, at least a portion of the semiconductor die being disposed inside the cavity of the substrate, an encapsulant material encapsulating a portion of the semiconductor die such that at least a portion of a surface of the semiconductor die is exposed.
- The foregoing features and other aspects of the invention are explained in the following description taken in connection with the accompanying drawings, wherein:
FIG. 1 is a simplified cross-sectional view of an integrated circuit package according to one embodiment of the present invention;FIG. 2 is a simplified cross-sectional view of an integrated circuit package according to a second embodiment of the present invention;FIG. 3 is a simplified bottom view of an integrated circuit package according to embodiments of the present invention;FIGS. 4A-4H show one example of steps performed in assembly of embodiments of an integrated circuit package of the present invention.FIGS. 5A-5I show another example of steps performed in assembly of embodiments of an integrated circuit package of the present invention.FIG. 6 is a simplified cross-sectional view of an integrated circuit package assembly including an integrated circuit package as shown inFIG. 2 and another integrated circuit package.- Various embodiments of the integrated circuit package and various examples of methods for manufacturing integrated circuit packages according to the present invention will now be described with reference to the drawings.
FIGS. 1 and 2 show certain components of integrated circuit packages according to embodiments of the present invention. The integrated circuit packages depicted inFIGS. 1 and 2 each generally include asubstrate 101, asemiconductor die 103 and anencapsulant 105. Thesubstrate 101 may be made of either a rigid material (e.g., BT, FR4, FR5 or ceramic) or a flexible material (e.g., polyimide), and may havecircuit traces 112 onto which asemiconductor die 103 may be interconnected using, for example, wire bonding techniques or tape automated bonding. In the embodiment shown inFIG. 1 , the package measures about 1.0 mm thick (shown as dimension “a” inFIG. 1 ) and about 35 mm wide (shown as dimension “b” inFIG. 3 ). The width dimension of certain other embodiments may vary from 7 mm to 50 mm. However, such dimensions are provided only as non-limiting examples of certain embodiments of the present invention.- As shown in
FIG. 2 , external terminals of one embodiment of the present invention may include an array ofsolder balls 106. In such an embodiment, thesolder balls 106 may function as leads capable of providing power, signal inputs and signal outputs to thesemiconductor die 103. Such a configuration may be referred to as a type of ball grid array. Absent thesolder balls 106, such a configuration may be referred to as a type of land grid array, as shown inFIG. 1 . - In one embodiment,
traces 112 may be embedded photolithographically into thesubstrate 101, and are electrically conductive to provide a circuit connection between thesemiconductor die 103 and thesubstrate 101.Such traces 112 may also provide an interconnection between input and output terminals of the semiconductor die103 and external terminals provided on the package. In particular, thesubstrate 101 of the embodiment shown inFIG. 1 may have amulti-layer circuit trace 112 made of copper. Thesubstrate 101 shown inFIG. 1 hasvias 110 which may be drilled into it to connect the top and bottom portions of eachcircuit trace 112.Such vias 110 may be plated with copper to electrically connect the top and bottom portions of eachtrace 112. Thesubstrate 101 shown inFIG. 1 may also have a solder mask on its surface. The solder mask of one embodiment electrically insulates the substrate and reduces wetting (i.e., reduces unwanted flow of solder into the substrate101). - As shown in
FIGS. 1-3 , thesubstrate 101 is designed with acavity 120 made through the base material with sufficient clearance to accommodate the specific size ofsemiconductor die 103 used in the package. - One embodiment may include a
conductive trace 112 in the form of a ring around thecavity 120 in thesubstrate 101. Such a ring-shapedconductive trace 112 may be connected to the top surface of thesubstrate 101 by means of electricallyconductive vias 110. Such an arrangement may allow aheat slug 108 to be electrically connected to thesemiconductor die 103 by the way ofwire bonding 104, thereby resulting in a ground plane surface beneath thesemiconductor die 103, which may enhance the electrical characteristics of the package. - In a preferred embodiment shown in
FIG. 2 , theencapsulant material 105 does not extend to the package edge. In such an embodiment, electricallyconductive vias 110 connecttraces 112 from the top surface of the package tocorresponding pads 113 on the side of the package opposite to the solder ball attachment. - Example methods of manufacturing embodiments of the integrated circuit packages will now be described with reference to the drawings, in particular,
FIGS. 4A-4H andFIGS. 5A-5I .FIG. 4A shows a step in the manufacture of one type of the integrated circuit package showing asubstrate 101 with acavity 120. Thesubstrate 101 may be produced in a form to accommodate standard semiconductor manufacturing equipment and process flows, and may also be configured in a matrix format to accommodate high-density package manufacturing.FIG. 5A depicts a step in another process for manufacturing integrated circuit packages, and shows asubstrate 501 with a number of cavities520-1,520-2. - As shown in
FIG. 4B , atape 102 with adhesive material on at least one side is applied to the bottom side of thesubstrate 101, and may be applied in strip form to accommodate a number of substrates. Thetape 102 may be, for example, a high temperature stable polyimide with an adhesive material on at least one surface.FIG. 5B depicts a tape502 having its adhesive material on the surface which interfaces with the bottom of thesubstrate 501. In one embodiment, the adhesive material has a contact sticking characteristic such that asemiconductor die 103 placed into contact with the adhesive material will stick to the tape502. In this embodiment, however, the adhesive material is such that no adhesive residue is left on thesubstrate 101 when the tape502 is removed. - As shown in
FIG. 4C , asemiconductor die 103 may then be mounted or otherwise attached to thetape 102 through thecavity 120 in thesubstrate 101.FIG. 5C depicts a number of semiconductor dies503-1,503-2 mounted or otherwise attached to the tape502 through each of the cavities520-1,520-2 of thesubstrate 501. - As shown in
FIG. 4D , the semiconductor die103 may then be interconnected to routing traces112 of thesubstrate 101 by a gold thermo-sonic wire bonding technique. In such an embodiment,gold wires 104 may interconnect the semiconductor die103 totraces 112 of thesubstrate 101.FIG. 5D depicts the semiconductor dies503-1,503-2 being interconnected to routing traces by, e.g., a gold thermo-sonic wire bonding technique. - As shown in
FIGS. 4E and 5E , after wire bonding, thesubstrate encapsulant material FIG. 1 , thesubstrate 101 is fully encapsulated on one side. To manufacture another embodiment of an integrated circuit package (shown inFIG. 2 ), thesubstrate 101 is encapsulated only in the semiconductor die130 and wire bond area, leaving much of the surface of thesubstrate 101 opposite to the solder ball area free ofencapsulant material 105. After an encapsulation process, thetape 102,502 may then be removed from the package subassembly as shown inFIGS. 4F and 5F . - As shown in
FIG. 4G ,solder balls 106 may then be attached totraces 112 of thesubstrate 101 using, for example, a reflow soldering process. In another example method of manufacture,FIG. 5G depictssolder balls 506 being attached totraces 512 of thesubstrate 501. Thesolder balls - As shown in
FIG. 4H , after solder ball attachment, aheat slug 108 may be attached to the exposed surface of the semiconductor die103 and the area surrounding thecavity 120 in thesubstrate 101 using a thermally conductive adhesive material107 such as epoxy. The adhesive material107, may also be electrically conductive, such as silver-filled epoxy.FIG. 5H depicts attachment of aheat slug 508 to each semiconductor die503 only. However, an alternative heat slug, such as the one depicted inFIG. 4H , may also be attached to one or more semiconductor dies503. - As shown in
FIG. 5I , after such heat slug attachment, the integrated circuit packages may be singulated into individual units using, e.g., a saw singulation or punching technique. FIG. 6 shows an integrated circuit package assembly according to an embodiment of the present invention. As depicted inFIG. 6 , such an embodiment includes two integrated circuit packages stacked one on top of the other and attached to one another bysolder balls 106. The integrated circuit package assembly shown inFIG. 6 includes two packages of the embodiment shown inFIG. 2 and aheat slug 108. Another embodiment of an integrated circuit package assembly according to the present invention may include two or more integrated circuit packages without aheat slug 108. Other embodiments of integrated circuit package assemblies according to the present invention may include integrated circuit packages other than the embodiments specifically shown inFIG. 6 . As shown inFIGS. 1, 2 , and6, thesubstrate 101 of certain embodiments of integrated circuit packages and assemblies may contain electricallyconductive traces 112 on an upper surface of thesubstrate 101 to facilitate electrical coupling with a second integrated circuit package.- The
heat slug 108 shown inFIG. 6 may provide a thermal path between asemiconductor die 103 and the environment. In the embodiment shown inFIG. 6 , theheat slug 108 may be aligned with and positioned below the bottom surface of the semiconductor die103 such that theheat slug 108 may contact or thermally couple with an external device such as, e.g., a printedcircuit board 200. Theheat slug 108 is preferably made of a thermally conductive material such as copper or copper alloy. Theheat slug 108 may be sized and configured for use in a specific package arrangement such that, in certain embodiments, theheat slug 108 contacts another type of external device (e.g., an integrated circuit package) to which a package is attached. Theheat slug 108 may be plated with solder or some other appropriate metal to enhance the reflow of solder to the surface of theheat slug 108. The opposite side of theheat slug 108 may also be oxide coated to enhance the adhesion to theencapsulant material 105. - Although specific embodiments of integrated circuit packages, integrated circuit package assemblies, and methods of manufacturing integrated circuit packages have been shown and described, it is to be understood that there are other embodiments which are equivalent to the described embodiments. Moreover, although a particular order of certain manufacturing steps has been discussed, it is to be understood that aspects of the invention are not limited to the particular order disclosed. The scope of the invention is not to be limited by the specific embodiments and examples depicted and described herein, but only by the claims.
Claims (21)
1-22. (canceled)
23. An integrated circuit package, comprising:
a substrate comprising:
a first surface,
a second surface opposite said first surface,
a cavity through said substrate between said first and second surfaces, and
a conductive via extending through said substrate and electrically connecting said first surface of said substrate with said second surface of said substrate;
a semiconductor die electrically coupled with said conductive via at said first surface of said substrate, at least a portion of said semiconductor die being disposed inside said cavity of said substrate;
an encapsulant material encapsulating a portion of said semiconductor die such that at least a portion of a surface of said semiconductor die is exposed; and
a heat slug thermally and electrically coupled with said semiconductor die, wherein said conductive via is further electrically coupled with said heat slug to provide a ground connection for said semiconductor die at said first surface of said substrate.
24. The integrated circuit package ofclaim 23 , further comprising a conductive member adapted for attachment of said integrated circuit package to an external device.
25. The integrated circuit package ofclaim 24 , said conductive member attached to said first surface of said substrate.
26. The integrated circuit package ofclaim 23 , further comprising at least one wire electrically coupling said semiconductor die with said conductive via.
27. The integrated circuit package ofclaim 23 , at least a portion of said first surface of said substrate being adapted for coupling said integrated circuit package with a second integrated circuit package.
28. The integrated circuit package ofclaim 23 , said substrate further comprising a multi-layer trace embedded therein.
29. An integrated circuit package assembly comprising the integrated circuit package ofclaim 23 attached to at least one other integrated circuit package.
30. The integrated circuit package assembly ofclaim 29 , wherein one of said integrated circuit packages is stacked on top of at least one of the other of said integrated circuit packages.
31. The integrated circuit package ofclaim 25 , further comprising a second conductive member attached to said second surface of said substrate.
32. The integrated circuit package ofclaim 23 , said package having a thickness dimension of about one millimeter.
33. The integrated circuit package ofclaim 39 , said package having a width dimension of about seven millimeters.
34. The integrated circuit package ofclaim 23 , said substrate being substantially planar and said semiconductor die being aligned in a plane with said substrate.
35. The integrated circuit package ofclaim 23 , said integrated circuit package being a land grid array.
36. The integrated circuit package ofclaim 23 said integrated circuit package being a ball grid array.
37. The integrated circuit package ofclaim 23 , said encapsulant material comprising an epoxy.
38. The integrated circuit package ofclaim 23 , further comprising a ring-like trace embedded in said substrate.
39. The integrated circuit package ofclaim 33 , said package having a width dimension of about 7 mm to 50 mm inclusively.
40. An integrated circuit package, comprising:
a substrate comprising:
a first surface,
a second surface opposite said first surface,
a cavity through said substrate between said first and second surfaces, and
means for electrically connecting said first surface of said substrate with said second surface of said substrate;
a semiconductor die, at least a portion of which is disposed inside said cavity of said substrate;
an encapsulant material encapsulating a portion of said semiconductor die such that at least a portion of a surface of said semiconductor die is exposed; and
means for thermally coupling said semiconductor die to a printed circuit board, wherein said means for thermally coupling is electrically coupled with said means for electrically connecting said first surface of said substrate with said second surface of said substrate to provide a ground connection for said semiconductor die at said first surface of said substrate.
41. An integrated circuit package assembly comprising the integrated circuit package ofclaim 40 attached to at least one other integrated circuit package.
42. The integrated circuit package assembly ofclaim 41 , wherein one of said integrated circuit packages is stacked on top of at least one of the other of said integrated circuit packages.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| US10/635,839US20050077613A1 (en) | 2002-01-31 | 2003-08-06 | Integrated circuit package |
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| Application Number | Priority Date | Filing Date | Title |
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| US10/062,650US6790710B2 (en) | 2002-01-31 | 2002-01-31 | Method of manufacturing an integrated circuit package |
| US10/635,839US20050077613A1 (en) | 2002-01-31 | 2003-08-06 | Integrated circuit package |
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| Application Number | Title | Priority Date | Filing Date |
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| US10/062,650DivisionUS6790710B2 (en) | 2001-08-15 | 2002-01-31 | Method of manufacturing an integrated circuit package |
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| US20050077613A1true US20050077613A1 (en) | 2005-04-14 |
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| US10/635,839AbandonedUS20050077613A1 (en) | 2002-01-31 | 2003-08-06 | Integrated circuit package |
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| US10/062,650Expired - LifetimeUS6790710B2 (en) | 2001-08-15 | 2002-01-31 | Method of manufacturing an integrated circuit package |
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| US20030143781A1 (en) | 2003-07-31 |
| US6790710B2 (en) | 2004-09-14 |
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