US20050067683A1 - Memory expansion and chip scale stacking system and method - Google Patents

Abstract

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

Description

TECHNICAL FIELD
• The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages and providing such stacked integrated circuits on boards.
BACKGROUND OF THE INVENTION
• A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits.
• The predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
• Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages known as chip scale packaging or “CSP” have recently gained market share.
• CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package.
• The goal of CSP is to occupy as little area as possible and, preferably, approximately the area of the encapsulated IC. Therefore, CSP leads or contacts do not typically extend beyond the outline perimeter of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
• The previous known methods for stacking CSPs typically present complex structural arrangements and thermal or high frequency performance issues. For example, thermal performance is a characteristic of importance in CSP stacks. To increase dissipation of heat generated by constituent CSPs and the module, the thermal gradient between the lower CSP and upper CSP in a CSP stack or module should be minimized.
• Memory expansion is one of the many fields in which stacked module solutions provide advantages. For example, the well-known DIMM board is frequently populated with stacked modules from those such as the assignee of the present invention. This adds capacity to the board without adding sockets.
• A memory expansion board such as a DIMM, for example, provides plural sites for memory IC placement (i.e., sockets) arranged along both major surfaces of a board having an array of contacts dispersed along at least one board edge. Although stacking reduces interconnect length per unit of memory, and thus takes advantage of the general rule that interconnects that are less than half the spatial extent of the leading edge of a signal operate as a lumped element more than a transmission line, it does increase the raw number of devices on a DIMM board. Consequently, despite the reduction in interconnect length per unit of memory, signals accessing data stored in memory circuits physically placed on the DIMM board are typically presented with relatively high impedance as the number of devices on the bus is increased by stacking.
• What is needed, therefore, is a technique and system for stacking CSPs that provides a thermally efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows production at reasonable cost with readily understood and managed materials and methods and allows significant reductions in interconnect lengths and/or loading when employed in memory expansion boards and design.
SUMMARY OF THE INVENTION
• The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. Although the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die.
• Multiple numbers of CSPs may be stacked in accordance with the present invention. A four-high CSP stacked module is preferred for use with the disclosed high performance memory access system while, for many applications, a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention is preferred. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers with preferred embodiments having two conductive layers.
• The flex circuitry is partially wrapped above a form standard. A form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent ICs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material, a metal for example, such as copper would be preferred, to improve thermal performance.
• In a preferred embodiment of the present invention, four-high stacked CSP modules are disposed on a memory expansion boards in accordance with the memory expansion system and methods of the present invention which may be employed with CSP or other IC stacked modules. A high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by the board loading. The high speed DQ selection switch may be implemented, in a preferred embodiment, for example, with a high speed FET switch. FET multiplexers for example, under logic control select particular data lines associated with particular levels of the DIMM-populated stacked modules for connection to a controlling chip set in a memory expansion system in accordance with a preferred embodiment.
SUMMARY OF THE DRAWINGS
• FIG. 1 is an elevation view of a high-density circuit module devised in accordance with a preferred four-high embodiment of the present invention.
• FIG. 2 is an elevation view of a stacked high-density circuit module devised in accordance with a preferred two-high embodiment of the present invention.
• FIG. 3 depicts, in enlarged view, the area marked “A” inFIG. 2.
• FIG. 4 depicts in enlarged view, the area marked “B” inFIG. 2.
• FIG. 5 is an enlarged depiction of an exemplar connection in stacked module devised in accordance with a preferred embodiment.
• FIG. 6 depicts a flexible circuit connective set of flex circuits that has a single conductive layer.
• FIG. 7 depicts a four-high stacked module mounted on a memory expansion board in accordance with a preferred embodiment of the present invention.
• FIG. 8 depicts a memory expansion board or DIMM mounted with four-high modules.
• FIG. 9 depicts a memory system devised in accordance with the present invention.
DESCRIPTION OF PREFERRED EMBODIMENTS
• FIG. 1 is an elevation view ofmodule10 devised in accordance with a preferred embodiment of the present invention.Module10 is comprised of four CSPs: level four CSP12, level three CSP14, level two CSP16, and level one CSP18. Each of the CSPs has anupper surface20 and alower surface22 and oppositelateral edges24 and26 and typically include at least one integrated circuit surrounded by aplastic body27. The body need not be plastic, but a large majority of packages in CSP technologies are plastic. Those of skill will realize that the present invention may be devised to create modules with different size CSPs and that the constituent CSPs may be of different types within thesame module10. For example, one of the constituent CSPs may be a typical CSP havinglateral edges24 and26 that have an appreciable height to present a “side” while other constituent CSPs of thesame module10 may be devised in packages that havelateral edges24 and26 that are more in the character of an edge rather than a side having appreciable height.
• The invention is used with CSP packages of a variety of types and configurations such as, for example, those that are die-sized, as well those that are near chip-scale as well as the variety of ball grid array packages known in the art. It may also be used with those CSP-like packages that exhibit bare die connectives on one major surface. Thus, the term CSP should be broadly considered in the context of this application. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the elevation views ofFIGS. 1 and 2 are depicted with CSPs of a particular profile known to those in the art, but it should be understood that the figures are exemplary only. The invention may be employed to advantage in the wide range of CSP configurations available in the art where an array of connective elements is available from at least one major surface. The invention is advantageously employed with CSPs that contain memory circuits, but may be employed to advantage with logic and computing circuits where added capacity without commensurate PWB or other board surface area consumption is desired.
• Typical CSPs, such as, for example, ball-grid-array (“BGA”), micro-ball-grid array, and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, or balls that extend fromlower surface22 of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Shown inFIG. 1 arecontacts28 alonglower surfaces22 of the illustratedconstituent CSPs12,14,16, and18.Contacts28 provide connection to the integrated circuit or circuits within the respective packages. In embodiments of the present invention,module10 may be devised to present a lower profile by stripping from the respective CSPs, the balls depicted inFIG. 1 ascontacts28 and providing a connection facility atcontact28 that results from solder paste that is applied either to the pad contact of the CSP that is typically present under or within the typical ball contacts provided on CSP devices or to the contact sites on the flex circuitry to be connected to contact28.
• InFIG. 1, iterations of flex circuits (“flex”, “flex circuits” or “flexible circuit structures”)30 and32 are shown connecting various constituent CSPs. Any flexible or conformable substrate with an internal layer connectivity capability may be used as a flex circuit in the invention. The entire flex circuit may be flexible or, as those of skill in the art will recognize, a PCB structure made flexible in certain areas to allow conformability around CSPs and rigid in other areas for planarity along CSP surfaces may be employed as an alternative flex circuit in the present invention. For example, structures known as rigid-flex may be employed.
• Form standard34 is shown disposed adjacent toupper surface20 of each of the CSPs below level fourCSP12. Form standard34 may be fixed to upper surface of the respective CSP with an adhesive36 which preferably is thermally conductive. Form standard34 may also, in alternative embodiments, merely lay onupper surface20 or be separated fromupper surface20 by an air gap or medium such as a thermal slug or non-thermal layer. However, where form standard34 is a thermally conductive material such as the copper that is employed in a preferred embodiment, layers or gaps interposed between form standard34 and the respective CSP (other than thermally conductive layers such as adhesive) are not highly preferred.
• Form standard34 is, in a preferred embodiment, devised from copper to create, as shown in the depicted preferred embodiment ofFIG. 1, a mandrel that mitigates thermal accumulation while providing a standard sized form about which flex circuitry is disposed. Form standard34 may take other shapes and forms such as for example, an angular “cap” that rests upon the respective CSP body. It also need not be thermally enhancing although such attributes are preferable. Theform standard34 allows the invention to be employed with CSPs of varying sizes, while articulating a single set of connective structures useable with the varying sizes of CSPs. Thus, a single set of connective structures such asflex circuits30 and32 (or a single flexible circuit in the mode where a single flex is used in place of theflex circuit pair30 and32) may be devised and used with the form standard34 method and/or systems disclosed herein to create stacked modules with CSPs having different sized packages. This will allow the same flexible circuitry set design to be employed to create iterations of a stackedmodule10 from constituent CSPs having a first arbitrary dimension X across attribute Y (where Y may be, for example, package width), as well asmodules10 from constituent CSPs having a second arbitrary dimension X prime across that same attribute Y. Thus, CSPs of different sizes may be stacked intomodules10 with the same set of connective structures (i.e. flex circuitry). Further, as those of skill will recognize, mixed sizes of CSPs may be implemented into thesame module10, such as would be useful to implement embodiments of a system-on-a-stack such as those disclosed in co-pending application U.S. patent application Ser. No. 10/136,890, filed May 2, 2002, which is hereby incorporated by reference and commonly owned by the assignee of the present application.
• Preferably, portions offlex circuits30 and32 are fixed to form standard34 by adhesive35 which is preferably a tape adhesive, but may be a liquid adhesive or may be placed in discrete locations across the package. Preferably, adhesive35 is thermally conductive.
• In a preferred embodiment,flex circuits30 and32 are multi-layer flexible circuit structures that have at least two conductive layers examples of which are those described in U.S. application Ser. No. 10/005,581 which has been incorporated by reference herein. Other embodiments may, however, employ flex circuitry, either as one circuit or two flex circuits to connect a pair of CSPs, that have only a single conductive layer.
• Preferably, the conductive layers are metal such as alloy110. The use of plural conductive layers provides advantages and the creation of a distributed capacitance acrossmodule10 intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize.Module10 ofFIG. 1 hasplural module contacts38 collectively identified asmodule array40. Connections between flex circuits are shown as being implemented withinter-flex contacts42 which are shown as balls but may be low profile contacts constructed with pads and/or rings that are connected with solder paste applications to appropriate connections. Appropriate fills such as those indicated byconformal media reference41 can provide added structural stability and coplanarity where desired.Media41 is shown only as toCSPs14 and16 and only on one side to preserve clarity of view.
• FIG. 2 shows a two-high module10 devised in accordance with a preferred embodiment of the invention.FIG. 2 has an area marked “A” that is subsequently shown in enlarged depiction inFIG. 3 and an enlarged area marked “B” that is shown subsequently in enlarged depiction inFIG. 4.
• FIG. 3 depicts in enlarged view, the area marked “A” inFIG. 2.FIG. 3 illustrates in a preferred embodiment, one arrangement of aform standard34 and its relation to flexcircuitry32 in a two-high module10. The internal layer constructions offlex circuitry32 are not shown in this figure. Also shown areadhesives35 betweenflex circuit32 and form standard34. Those of skill will note that adhesive35 is not required but is preferred and the site of its application may be determined as being best in the area between CSPs with a smaller amount near the terminal point of form standard34 as shown inFIG. 3. Also shown inFIG. 3 is an application of adhesive36 between form standard34 andCSP18.
• FIG. 4 illustrates the connection betweenexample contact28 andmodule contact38 through alower flex contact44 to illustrate a preferred solid metal path from level oneCSP18 tomodule contact38 and, therefore, to an application PWB or memory expansion board to which the module is connectable. As those of skill in the art will understand, heat transference frommodule10 is thereby encouraged.
• Flex30 is shown inFIG. 4 to be comprised of multiple layers. This is merely an exemplar flexible circuitry that may be employed with the present invention. Single conductive layer and other variations on the described flexible circuitry may, as those of skill will recognize, be employed to advantage in the present invention.Flex30 has a firstouter surface50 and a secondouter surface52.Flex circuit30 has at least two conductive layers interior to first and secondouter surfaces50 and52. There may be more than two conductive layers inflex30 andflex32. In the depicted preferred embodiment, firstconductive layer54 and secondconductive layer58 are interior to first and secondouter surfaces50 and52.Intermediate layer56 lies between firstconductive layer54 and secondconductive layer58. There may be more than one intermediate layer, but one intermediate layer of polyimide is preferred.
• As depicted inFIG. 4 and seen in more detail in figures found in U.S. application Ser. No. 10/005,581 which has been incorporated by reference,lower flex contact44 is preferably comprised from metal at the level of secondconductive layer58 interior to secondouter surface52.
• FIG. 5 is an enlarged depiction of an exemplar area around alower flex contact44 in a preferred embodiment.Windows60 and62 are opened in first and second outer surface layers50 and52 respectively, to provide access to particularlower flex contacts44 residing at the level of secondconductive layer58 in the flex. In a two-high embodiment ofmodule10, theupper flex contacts42 are contacted bycontacts28 ofsecond level CSP16.Lower flex contacts44 andupper flex contacts42 are particular areas of conductive material (preferably metal such as alloy110) at the level of secondconductive layer58 in the flex.Upper flex contacts42 andlower flex contacts44 are demarked in secondconductive layer58 and, as will be shown in subsequent Figs., may be connected to or isolated from the conductive plane of secondconductive layer58. Demarking alower flex contact44 from secondconductive layer58 is represented inFIG. 5 by demarcation gap63 shown at secondconductive layer58. Where an upper orlower flex contact42 or44 is not completely isolated from secondconductive layer58, demarcation gaps do not extend completely around the flex contact.Contacts28 offirst level CSP18 pass through awindow60 opened through firstouter surface layer50, firstconductive layer54, andintermediate layer56, to contact an appropriatelower flex contact44.Window62 is opened through secondouter surface layer52 through whichmodule contacts36 pass to contact the appropriatelower flex contact44.
• Respective ones ofcontacts28 ofsecond level CSP16 andfirst level CSP18 are connected at the secondconductive layer58 level inflex circuits30 and32 to interconnect appropriate signal and voltage contacts of the two CSPs. In a preferred embodiment,respective contacts28 ofsecond level CSP16 andfirst level CSP18 that convey ground (VSS) signals are connected at the firstconductive layer54 level inflex circuits30 and32 by vias that pass throughintermediate layer56 to connect the levels as will subsequently be described in further detail. Thereby,CSPs16 and18 are connected. Consequently, whenflex circuits30 and32 are in place aboutfirst level CSP18,respective contacts28 of each ofCSPs16 and18 are in contact with upper andlower flex contacts42 and44, respectively. Selected ones ofupper flex contacts42 andlower flex contacts44 are connected. Consequently, by being in contact withlower flex contacts44,module contacts38 are in contact with bothCSPs16 and18.
• In a preferred embodiment,module contacts38 pass throughwindows62 opened in secondouter layer52 to contactlower CSP contacts44. In some embodiments, as is shown in incorporated U.S. application Ser. No. 10/005,581,module10 will exhibit a module contact array that has a greater number of contacts than do the constituent CSPs ofmodule10. In such embodiments, some ofmodule contacts38 may contactlower flex contacts44 that do not contact one of thecontacts28 offirst level CSP18 but are connected tocontacts28 ofsecond level CSP16. This allowsmodule10 to express a wider datapath than that expressed by theconstituent CSPs16 or18. Amodule contact38 may also be in contact with alower flex contact44 to provide a location through which different levels of CSPs in the module may be enabled when no unused CSP contacts are available or convenient for that purpose.
• In a preferred embodiment, firstconductive layer54 is employed as a ground plane, while secondconductive layer58 provides the functions of being a signal conduction layer and a voltage conduction layer. Those of skill will note that roles of the first and second conductive layers may be reversed with attendant changes in windowing and use of commensurate interconnections.
• FIG. 6 depicts a flexible circuit connective set offlex circuits30 and32 that has a singleconductive layer64. It should be understood with reference toFIG. 6 thatflex circuits30 and32 extend further than shown and have portions which are, in the construction ofmodule10 brought about thecurvature areas66 of form standard34 that mark the lateral extent of this example of a preferred form standard and are then disposed above the body ofCSP18 or the respective CSP of the module and therefore, the form standard. In this single conductive layer flex embodiment ofmodule10, there are shown first and secondouter layers50 and52 andintermediate layer56. Also shown inFIG. 6 are a set of single layerlower flex contacts68 demarked at the level ofconductive layer64.
• Form standard34 is shown attached to thebody27 offirst level CSP18 through an adhesive. In some embodiments, it may also be positioned to directly contactbody27 of the respective CSP. Form standard34 may take many different configurations to allow a connective flex circuitry to be prepared exhibiting a single set of dimensions which may, when used in conjunction with form standard34, be employed to createstacked modules10 from CSPs of a variety of different dimensions. In a preferred embodiment, form standard34 will present a lateral extent broader than the upper major surface of the CSP over which it is disposed. Thus, the CSPs from one manufacturer may be aggregated into astacked module10 with the same flex circuitry used to aggregate CSPs from another manufacturer into a differentstacked module10 despite the CSPs from the two different manufacturers having different dimensions.
• Further, heat transference can be improved with use of a form standard34 comprised of heat transference material such as a metal or preferably, copper or a copper compound or alloy to provide a significant sink for thermal energy. Such thermal enhancement ofmodule10 particularly presents opportunities for improvement of thermal performance where larger numbers of CSPs are aggregated in a single stackedmodule10.
• FIG. 7 depicts a four-highstacked module10 mounted on amemory expansion board70 in accordance with a preferred embodiment of the present invention. As do typical DIMM boards,expansion board70 shown inFIG. 7 has a set of contacts along one edge that as depicted are set insocket connector72. Those contacts connectmodule10 to a logic system on or connected to board74 on whichexpansion board70 is mounted. It should be understood that in a preferred embodiment of the memory expansion system and method provided herein,expansion board70 will be populated with ninesuch modules10 per side for a total of 72 devices if the stacked modules are each comprised from four devices.
• FIG. 8 depictsmemory expansion board70 mounted with four-high modules10. As those of skill will recognize, using four-high stacked modules onexpansion board70 reduces the interconnect length for the number of devices accessed but increase the total number of devices and, therefore, the impedance and particularly, the capacitive loading presented by a densely populated DIMM board.
• FIG. 9 depicts amemory system80 devised in accordance with the present invention. In a preferred mode,system80 is employed with stackedmodules10 devised in accordance with the present invention. The preferred embodiment is for a DDRII registered DIMM populated with 4 highstacked modules10 although it may be employed with an equivalent number of DRAMs, i.e., 72 devices of either leaded or CSP packaging aggregated in stacks of any number of levels.
• Chipset82 depicted inFIG. 9 typically includes a microprocessor or memory controller that controls the memory access withsystem80.Clock84 is provided to decodelogic86 on each of depictedmemory expansion boards70₍₁₎,70₍₂₎,70₍₃₎, and70₍₄₎. Those of skill will understand thatsystem80 and its methods may be employed with one or more DIMMs or othermemory expansion boards70. It may also be employed off a memory expansion board to access separately, the integrated circuits from which stacked circuit modules are comprised.Decode logic86 on each ofmemory expansion boards70₍₁₎,70₍₂₎,70₍₃₎, and70₍₄₎provides a decoding of the respective CS signals provided to the respectivememory expansion boards70 as shown inFIG. 9. As those of skill will understand, the particular interconnection employed in the system should preferably be devised to minimize and balance power consumption across the circuit modules employed in the system.
• As shown in the example depicted inFIG. 9, CS0, CS1, CS2, and CS3 are provided tomemory expansion board70₍₁₎fromchipset82 while CS4, CS5, CS6, and CS7 are provided tomemory expansion board70₍₂₎as are CS8, CS9, CS10, and CS11 provided tomemory expansion board70₍₃₎and CS12, CS13, CS14, and CS15 are provided tomemory expansion board70₍₄₎.
• In a preferred embodiment,memory expansion boards70 are populated with nine fourhigh CSP modules10 per side. The depiction ofFIG. 9 shows, however, only onemodule10 permemory expansion board70 to preserve clarity of the view. The shownmodule10 is exploded to depict the four levels ofmodule10 which, in a preferred construction ofmodule10 includeCSPs18,16,14, and12 with theform standard34. However, those of skill will recognize that modules employed withsystem80 need not have four levels and need not be CSP devices although that is preferred.
• Thus, decodelogic86 may, on the appropriate signal fromclock84, generate a level select signal which, in a preferred embodiment, is a multi-bit signal that controls amultiplexing switch90 associated with several data lines.Switch90 is in a preferred embodiment, a high speed switch and a FET muliplexer would provide apreferred multiplexing switch90 in the practice of a preferred mode of the invention. The fan out of multiplexingswitch90 may be any that provides a selection capability to a variety of device data lines from a DQ line fromchipset82. The DQ lines betweenchipset82 and switches90 are depicted by double-headed arrows94(1),94(2),94(3) and94(4). As with the depiction of stackedmodules10, only onemultiplexing switch90 is shown permemory expansion board70, but those of skill will understand that multiple multiplexing switches90 are employed in practice of the depicted preferred embodiment of the invention. The number of multiplexing switches90 will depend upon the fan out ratios. For example, use of nine 8:32 multiplexingswitches90 would be preferred (if available) or 4:8 or 1:4 multiplexing switches90 will also provide advantages as an example. It should be understood that there are merely examples and that a variety of multiplexing switches and ratios may be employed for multiplexingswitches90 although the type of switch and the ratios will affect the loading figures. Consequently, a FET mux is preferred for multiplexingswitch90 and a ratio of 1:4 is one of the preferred ratios to employ.
• The depiction inFIG. 9 is illustrative only and not meant to be limiting. For example, a single DIMM board orexpansion board70 may be employed in asystem80 in accordance with the present invention as well as larger numbers ofexpansion boards70. The number ofexpansion boards70 that may function insystem80 is partially a function of the access speeds required and the signal conformity.
• Anexemplar multiplexing switch90 has multiple inputs92(a),92(b),92(c), and92(d) to provide independent data lines for each level of anexemplar module10 populated upon the respectivememory expansion board70. Thus, with a 1:4switch90, there will be 18 iterations of multiplexingswitch90, one for each of the 18 four-high module10's populating memory expansion board70(1). Thus, thesystem80 shown inFIG. 9 presents a total of 288 memory devices. It should be noted thatsystem80 may be employed with ICs of any package type and need not be limited to DDR or DDRII or even CSP.
• The data line of each level of the constituent CSPs of eachmodule10 is connected to oneinput92 of a correspondingexemplar multiplexing switch90. In response to theCS signal88 fromdecode logic86 on aDIMM expansion board70, multiplexingswitch90 connects the appropriate one of the DQ signals94 to one of the four levels of amodule10 on thatmemory expansion board70. This switching of the data bus through multiplexingswitch90 may, in some systems, required further control signal connections as those of skill in the art will recognize to accomodate the data latency of one or more clocks cycles, CAS latency, and burst length, for example. In a preferred mode,expansion board70 may keep all the constituent devices of themodules10 as if each constituent device of themodules10 were the target, instead of having to switch terminations each time a different CS is chosen. In some applications it may be preferred to terminate the end of the data line past the lastDIMM expansion board70. Other features may enable improvements to the efficiency ofsystem80 such as creating more CS banks by decoding the chip select lines.
• In thesystem80, the capacitive load presented tochipset82 would be approximately the combination of the input capacitance of switchingmultiplexer90 times the number of DIMM slots plus one DRAM device load plus one times the output capacitance of themultiplexing switch90. In large systems, this will reduce capacitive loading by a notable amount, thus allowing more DIMM slots at higher speeds and/or more densely populated DIMMs.Memory access system80 provides an opportunity to improve high speed memory performance and allows use of memory expansion configurations that might not otherwise be available due to capacitive loading in conventional DIMM systems.
• Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.

Claims (25)

1. A memory access system comprising:

a memory expansion board;

a high-density circuit module comprised of first and second integrated circuits, the high-density circuit module being mounted on the memory expansion board;

a switching multiplexer mounted on the memory expansion board, the switching multiplexer for switching data lines between the first and second integrated circuits; and

a decode logic circuit for decoding chip selection signals from a control circuit and providing a switching multiplexer control signal.

2. A memory access system comprising:

a high-density circuit module comprised of plural integrated circuits;

a switch for connecting a datapath to one of the plural integrated circuits of the high-density circuit module;

a decode logic for generating a control signal that causes the switch to connect the datapath to one of the plural integrated circuits in response to a combination signal comprised of a clock signal and a chip select signal.

3. The memory access system ofclaim 2 in which the plural integrated circuits of the high-density circuit module number four.

4. The memory access system ofclaim 2 in which the plural integrated circuit of the high-density circuit module number two.

5. A memory access system comprising:

plural memory expansion boards each populated with plural high-density circuit modules, each of which plural high-density circuit modules being comprised of plural integrated circuits;

plural multiplexers mounted upon each of the plural memory expansion boards, the plural multiplexers for making connections between a datapath and single ones of the plural integrated circuits comprising the high-density circuit modules;

decode logic on each of the plural memory expansion boards, the decode logic for generating a control signal in response to a combination signal comprised of a clock signal and a chip select signal, the control signal causing at least one of the plural multiplexers to connect a particular datapath to a particular one of the plural integrated circuits.

6. The memory access system ofclaim 5 in which the multiplexers are FET multiplexers.

7. The memory access system ofclaim 5 in which the plural high-density circuit modules are comprised of four integrated circuits.

8. The memory access system ofclaim 5 in which the plural high-density circuit modules are comprised from two integrated circuits.

9. The memory access system ofclaim 7 in which the four integrated circuits are CSPs.

10. The memory access system ofclaim 8 in which the two integrated circuits are CSPs.

11. A memory access system comprising:

a memory board having a board memory signal data connection that provides a connection for memory signals between a plurality of integrated circuits mounted on the memory board and memory control circuitry;

a high-density circuit module comprised of first, second, third, and fourth individual integrated circuits, the high-density circuit module being mounted on the memory board;

a switching multiplexer mounted on the memory board, the switching multiplexer having a set of plural input data connections, individual ones of the plural input data connections connected to provide individual data connections between each of the first, second, third, and fourth individual integrated circuits and the switching multiplexer; and

a decode logic circuit for decoding chip selection signals from a control circuit and providing a switching multiplexer control signal.

12. The memory access system ofclaim 11 in which the switching multiplexer further comprises an output data connection connected to the board signal memory data connection.

13. The memory access system ofclaim 12 in which the switching multiplexer provides selective individual connection between the board signal memory data connection and the first, second, third, and fourth individual integrated circuits.

14. The memory access system ofclaim 13 in which the individual connection between the board signal memory data connection and the first, second, third, and fourth individual integrated circuits occurs in response to the switching multiplexer control signal from the decode logic circuit.

15. The memory access system ofclaim 11 in which the decode logic circuit is mounted on the memory board.

16. A memory access system comprising:

a high-density circuit module comprised of stacked plural individual integrated circuits;

a switch for individually connecting a datapath to one of the plural individual integrated circuits of the high-density circuit module at a time; and

a decode logic for generating a control signal that causes the switch to connect the datapath to one of the plural individual integrated circuits at a time.

17. The memory access system ofclaim 16 in which the control signal is generated from a clock signal and a chip select signal.

18. The memory access system ofclaim 16 in which the stacked plural integrated circuits of the high-density circuit module number four.

19. The memory access system ofclaim 16 in which the stacked plural integrated circuit of the high-density circuit module number two.

20. A memory access system comprising:

X memory expansion boards each populated with Y high-density circuit modules, each of which Y high-density circuit modules being comprised of Z individual integrated circuits;

plural multiplexers mounted upon each of the X memory expansion boards, the plural multiplexers each for selectively making connections between a datapath and single ones of the Z integrated circuits comprising each of the Y high-density circuit modules;

decode logic on each of the plural memory expansion boards, the decode logic for generating a control signal in response to a combination signal comprised of a clock signal and a chip select signal, the control signal causing at least one of the plural multiplexers to connect a particular datapath to a particular one of the Z integrated circuits.

21. The memory access system ofclaim 20 in which the multiplexers are FET multiplexers.

22. The memory access system ofclaim 20 in which Z equals 4.

23. The memory access system ofclaim 20 in which Z equals 2.

24. The memory access system ofclaim 22 in which the four integrated circuits are CSPs.

25. The memory access system ofclaim 23 in which the two integrated circuits are CSPs.

Images