US20050013163A1 - Semiconductor memory cell, array, architecture and device, and method of operating same - Google Patents

Abstract

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application claims priority to: U.S. Provisional Application Ser. No. 60/470,385, entitled “Two Transistor Gain Cell”, filed May 13, 2003 (hereinafter “the Provisional Application”). The contents of the Provisional Application are incorporated by reference herein in their entirety.
BACKGROUND
• This invention relates to a semiconductor memory cell, array, architecture and device, and techniques for controlling and/or operating such cell and device; and more particularly, in one aspect, to a semiconductor dynamic random access memory (“DRAM”) cell, array, architecture and/or device wherein the memory cell includes an electrically floating body in which an electrical charge is stored.
• There are many different types and/or forms of DRAM cells, including, for example, a semiconductor memory cell consisting of an access transistor and a capacitor, which stores an electric charge representing a bi-stable memory state. The access transistor serves as a switch for controlling the charging and discharging of the capacitor as well as reading and writing of the logic states into the capacitor (i.e., charging or discharging the capacitor).
• Although significant integration densities can be achieved with DRAM devices employing one transistor—one capacitor memory cells, such devices tend to be limited or restricted with respect to the size of the memory cell. In this regard, conventional techniques employ stacked and/or trench capacitor approaches, whereby the capacitor is partially disposed above and/or below an access transistor.
• In addition, DRAM devices employing one transistor—one capacitor memory cells tend to be fabricated using manufacturing processes that are different from and/or incompatible with manufacturing processes for logic devices (for example, microprocessors). As a result, integration of one transistor—one capacitor memory cells into logic devices is often complicated and expensive.
• Another type of dynamic random access memory cell is described and illustrated in non-provisional patent application entitled “Semiconductor Memory Device”, which was filed on Jun. 10, 2003 and assigned Ser. No. 10/450,238 (hereinafter “Semiconductor Memory Device Patent Application”). With reference toFIGS. 1A and 1B, the Semiconductor Memory Device Patent Application discloses, among other things,semiconductor DRAM device10 in which eachmemory cell12 consists oftransistor14 havinggate16,body region18, which is electrically floating,source region20 anddrain region22. Thebody region18 is disposed between and adjacent tosource region20 and drainregion22. Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s)24, a selected source line(s)26 and/or a selected bit line(s)28. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floatingbody region18 wherein the data states are defined by the amount of carriers within electrically floatingbody region18. Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
• In particular, in one embodiment, the memory cell of the Semiconductor Memory Device Patent Application operates by accumulating in or emitting/ejecting majority carriers (electrons or holes)30 frombody region18 of, for example, N-channel transistors. (See,FIGS. 2A and 2B). In this regard, accumulating majority carriers (in this example, “holes”)30 inbody region18 ofmemory cells12 via, for example, impact ionization nearsource region20 and/ordrain region22, is representative of a logic high or “1” data state. (See,FIG. 2A). Emitting or ejectingmajority carriers30 frombody region18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or “0”. (See,FIG. 2B).
• Several techniques may be implemented to read the data stored in (or write the data into) a memory device of the Semiconductor Memory Device Patent Application. For example, a current sense amplifier (not illustrated) may be employed to read the data stored inmemory cells12. In this regard, a current sense amplifier may compare the cell current to a reference current, for example, the current of a reference cell (not illustrated). From that comparison, it may be determined whethermemory cell12 contained a logic high (relatively more majority carries30 contained within body region18) or logic low data state (relatively less majority carries28 contained within body region18).
• Notably,transistor14 may be a symmetrical or non-symmetrical device. Wheretransistor14 is symmetrical, the source and drain regions are essentially interchangeable. However, wheretransistor14 is a non-symmetrical device, the source or drain regions oftransistor14 have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of a non-symmetrical device are typically not interchangeable.
SUMMARY OF THE INVENTION
• There are many inventions described and illustrated herein. In a first principal aspect, the present invention is a semiconductor dynamic random access memory cell for storing a first data state and a second data state. The memory cell includes first and second transistors, wherein each transistor includes a source region, a drain region, an electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. In addition, each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further the memory cell is in: (1) the first data state when the first transistor is in the first state and the second transistor is in the second state and (2) the second data state when the first transistor is in the second state and the second transistor is in the first state.
• In one embodiment, the semiconductor dynamic random access memory cell includes two outputs including a first output connected to the drain region of the first transistor and a second output connected to the drain region of the second transistor. In this embodiment, the gate of the first transistor is connected to the gate of the second transistor, and the source region of the first transistor and the source region of the second transistor are the same region.
• In another embodiment, the semiconductor dynamic random access memory cell includes two outputs including a first output connected to the source region of the first transistor and a second output connected to the source region of the second transistor. In this embodiment, the drain region of the first transistor and the drain region of the second transistor are the same region.
• Notably, the memory cell may be programmed to a first data state by applying a first control signal to the gate of the first transistor and a second control signal to the gate of the second transistor and wherein the first and second control signals include different voltage amplitudes.
• In another principal aspect, the present invention is a semiconductor memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes first and second transistors. Each transistor includes a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. The transistors include a first state representative of a first charge in the body region; and a second data state representative of a second charge in the body region. Further each memory cell is in: (1) the first data state when its first transistor is in the first state and its second transistor is in the second state and (2) the second data state when its first transistor is in the second state and its second transistor is in the first state.
• The semiconductor memory array may also include a comparator having a plurality of inputs to sense the states of the first and second transistors of a semiconductor dynamic random access memory cell of the plurality of semiconductor dynamic random access memory cell. A first input of the comparator is selectively coupled to a first transistor of the semiconductor dynamic random access memory cell and the second input of the comparator is selectively coupled to the second transistor of a semiconductor dynamic random access memory cell.
• In one embodiment, at least one of the rows of semiconductor dynamic random access memory cells includes a source line that is connected to each of the semiconductor dynamic random access memory cells of the row. Indeed, in another embodiment, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
• In another embodiment, a first input of a comparator is selectively coupled to the drain region of the first transistor of the semiconductor dynamic random access memory cell and a second input of the comparator is selectively coupled to the drain of second first transistor of a semiconductor dynamic random access memory cell. In this embodiment, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the row.
• The semiconductor dynamic random access memory cell may be programmed in a first data state by performing a clear operation of the first and second transistors of the semiconductor dynamic random access memory cell and then performing a write operation. In response, the first transistor of the semiconductor dynamic random access memory cell is in a first state and the second transistor of the semiconductor dynamic random access memory cell is in a second state.
• Moreover, the semiconductor dynamic random access memory cell may be programmed in a first data state by first placing the first and second transistors of the semiconductor dynamic random access memory cell in a first state and thereafter placing the second transistor of the semiconductor dynamic random access memory cell is in a second state. In this embodiment, an unselected portion of the semiconductor memory array is maintained in a fixed state when programming the at least one semiconductor dynamic random access memory cell by applying a write inhibit signal to the transistors of the semiconductor dynamic random access memory cells comprising the unselected portion of the semiconductor memory array.
• In one embodiment, each semiconductor dynamic random access memory cell includes two outputs including a first output connected to the drain region of the first transistor and a second output connected to the drain region of the second transistor.
• In another embodiment, the gate of the first transistor and the gate of the second transistor of each semiconductor dynamic random access memory cell are each connected to an associated common gate line.
• In yet another embodiment, the source region of the first transistor and the source region of the second transistor of each semiconductor dynamic random access memory cell are the same region. However, in another embodiment, the source region of the first transistor and the source region of the second transistor of each semiconductor dynamic random access memory cell are connected to different source lines.
• Indeed, a first output of each semiconductor dynamic random access memory cell may be connected to the source region of the first transistor and a second output of the semiconductor dynamic random access memory cell may be connected to the source region of the second transistor. In this embodiment, the drain region of the first transistor and the drain region of the second transistor of each semiconductor dynamic random access memory cell are the same region.
• Again, there are many inventions described and illustrated herein. This Summary of the Invention is not exhaustive of the scope of the present invention. Moreover, this Summary is not intended to be limiting of the invention and should not be interpreted in that manner. While certain embodiments, features, attributes and advantages of the inventions have been described in this Summary, it should be understood that many others, as well as different and/or similar embodiments, features, attributes and/or advantages of the present inventions, which are apparent from the description, illustrations and claims, which follow.
BRIEF DESCRIPTION OF THE DRAWINGS
• In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present invention and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated and are within the scope of the present invention.
• FIG. 1A is a schematic representation of a semiconductor DRAM array as illustrated (and described) in the Semiconductor Memory Device Patent Application;
• FIG. 1B illustrates a memory cell according to the Semiconductor Memory Device Patent Application;
• FIGS. 2A and 2B are exemplary schematic illustrations of the charge relationship, for a particular memory state, of the floating body, source and drain regions of a memory cell according to the Semiconductor Memory Device Patent Application;
• FIGS. 3A and 3B illustrate a memory cell, according to certain embodiments of certain aspects of the present inventions;
• FIG. 4 illustrates a memory cell, in conjunction with a read amplifier, according to one embodiment of the present invention;
• FIG. 5 illustrates a memory cell including two transistors that are configured to have a common drain region, according to one embodiment of the present invention;
• FIG. 6 illustrates an exemplary layout of the memory cell ofFIG. 5;
• FIGS. 7A, 7B,8A and8B illustrate writing and/or programming techniques including exemplary programming voltage values, according to two embodiments of the present invention, for the memory cell including two transistors that are configured to have a common drain region;
• FIG. 9 illustrates a memory cell of this embodiment, in conjunction with a read amplifier and read operation including exemplary voltage values, according to an embodiment of the present invention, for the memory cell including two transistors that are configured to have a common drain region;
• FIGS. 10A and 10B illustrate writing and/or programming techniques including exemplary programming voltage values, according to two embodiments of the present invention, for a memory array including a plurality of memory cells each having two transistors that are configured to have a common drain region;
• FIG. 10C illustrates exemplary read operation voltage values, according to an embodiment of the present invention, for a memory array including a plurality of memory cells each having two transistors that are configured to have a common drain region;
• FIG. 11 illustrates a memory cell including two transistors that are configured to have a common source region and connected gates, according to one embodiment of the present invention;
• FIG. 12 illustrates an exemplary layout of the memory cell ofFIG. 11;
• FIGS. 13A and 13B illustrate writing and/or programming techniques including exemplary programming voltage values, for the memory cell ofFIG. 11;
• FIG. 14 illustrates a memory cell ofFIG. 11, in conjunction with a read amplifier and read operation including exemplary voltage values, according to an embodiment of the present invention;
• FIGS. 15A and 15B illustrate writing and/or programming techniques including exemplary programming voltage values, for a memory array including a plurality of memory cells ofFIG. 11;
• FIG. 15C illustrates exemplary read operation voltage values, according to an embodiment of the present invention, for a memory array including a plurality of memory cells ofFIG. 11;
• FIGS. 16A-16C illustrate writing and/or programming techniques (including exemplary programming voltage values), according to another aspect of the present invention, for a memory cell ofFIG. 11;
• FIGS. 17 and 18 illustrate a memory array including a plurality of memory cells having a separate source line array that define a particular row of memory cells, and exemplary writing and/or programming techniques (including exemplary programming voltage values), according to another aspect of the present invention;
• FIGS. 19A and 19B illustrate exemplary and alternative read operation voltage values, according to an embodiment of the present invention, for a memory array ofFIGS. 17 and 18;
• FIG. 20 illustrates an exemplary layout of the memory array ofFIGS. 17 and 18;
• FIGS. 21 and 22 illustrate a memory array including a plurality of memory cells having a common source line array that define a particular row of memory cells, and exemplary writing and/or programming techniques (including exemplary programming voltage values), according to another aspect of the present invention;
• FIG. 23 illustrates exemplary read operation voltage values, according to an embodiment of the present invention, for a memory array ofFIGS. 21 and 22;
• FIG. 24 illustrates an exemplary layout of the memory array ofFIGS. 21 and 22;
• FIGS. 25 and 26 illustrate another memory array architecture including a plurality of memory cells having a common source line array, and exemplary writing and/or programming techniques (including exemplary programming voltage values), according to another aspect of the present invention;
• FIG. 27 illustrates exemplary read operation voltage values, according to an embodiment of the present invention, for a memory array ofFIGS. 25 and 26;
• FIG. 28 illustrates an exemplary layout of the memory array ofFIGS. 25 and 26; and
• FIGS. 29 and 30 illustrate a refresh architecture and technique for the memory cell and memory cell array according to one embodiment of the present invention.
DETAILED DESCRIPTION
• There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”).
• The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing, measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.
• With reference toFIGS. 3A and 3B, in one embodiment,memory cell100 is a bi-stable memory cell which includestransistor102aandtransistor102b. In a first logic state ofmemory cell100,transistor102astores a logic low andtransistor102bstores a logic high. (See, for example,FIG. 3A). In contrast, in a second logic state ofmemory cell100,transistor102astores a logic high andtransistor102bstores a logic low. (See, for example,FIG. 3B).
• With reference toFIG. 4, the state ofmemory cell100 may be read and/or determined bycomparator104, which may be a voltage or current type comparator (for example, a cross-coupled sense amplifier). In this regard,comparator104 may compare the different logic states stored intransistor102aandtransistor102b. Thus, wheretransistor102aandtransistor102bstore either logic “1” or logic “0”, the difference is either 1−0=1 or 0−1=−1. As such, the read window may be described as the absolute difference between the logic high state and logic low state (i.e., 1−(−1)=2), which may be 2× the read window of the conventional memory cell. Notably, pass gates and/or column switch circuitry (not illustrated) may be employed to selectively connecttransistors102aand102btocomparator104 to facilitate the read operation of the data state ofmemory cell100.
• Thus,memory cell100 of the present invention may include several advantages relative to conventional dynamic random access memory cells, including, for example: (i) the read operation is less sensitive to variation in the values of the binary states because a logic state is determined by the difference in states of the individual transistors, (ii) no reference circuit is necessary, (iii) thememory cell100 includes a larger read window (as compared to conventional dynamic random access memory cells), which results in faster access time, and (iv) a less complicated and/or complex sense amplifier may be employed.
• Thetransistor102aand/ortransistor102bmay be symmetrical or non-symmetrical devices. Wheretransistors102aand/ortransistor102bare symmetrical, the source and drain regions are essentially interchangeable. However, wheretransistors102aand/ortransistor102bare non-symmetrical devices, the source or drain regions oftransistor102aand/ortransistor102bmay have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of the non-symmetrical device are typically not interchangeable.
• In one embodiment,memory cell100 includestransistors102aand102bthat have the same or similar characteristics. Indeed,transistors102aand/or102bmay have the same or similar characteristics as the transistors described and illustrated in the Semiconductor Memory Device Patent Application. Notably,transistors102aand102bmay employ any type of design and/or control technique, whether now known or later developed, including, for example, those discussed above in the Semiconductor Memory Device Patent Application. All such designs of and/or control techniques fortransistors102aand102b, whether now known or later developed, are intended to be within the present invention.
• In those instances wheretransistors102aand102bare designed to have the same or similar characteristics, it may be advantageous to physically locatetransistors102aand102bnearby each other. In this way, during manufacturing,transistors102aand102bare likely to be fabricated with little to no process variations or differences and, as such,transistors102aand102bare likely to have the same or similar electrical, physical, doping concentration and/or profile characteristics.
• A memory device may include a plurality ofmemory cells100 arranged in repeating patterns. Thememory cell100 may be arranged in an array in many different ways. All layout configurations fortransistors102aand102b, whether now known or later developed, are intended to be within the present invention. For example, in one layout,transistors102aand102bare configured to have a common drain region. With reference toFIGS. 5 and 6, in one embodiment,transistors102aand102binclude acommon drain regions110aand110b. Data is written into or read fromtransistors102aand102bby applying suitable control signals to sourceregions108aand108b,drain regions110aand110band/orgates112aand112b, respectively. In response, charge carriers are accumulated in or emitted from electrically floatingbody regions106aand106bwherein the data state of eachtransistors102aand102bis defined by the amount of carriers within electrically floatingbody regions106aand106b, respectively.
• In particular, with reference toFIGS. 7A and 7B, in one embodiment, a logic low (binary “0” state) is written intotransistor102aand a logic high (binary “1” state) is written intotransistor102busing the indicated (exemplary) voltage levels. Notably, the voltage levels indicated inFIGS. 7A and 7B may be relative or absolute. In this regard, a logic low may be written intotransistor102a(FIG. 7A) ortransistor102b(FIG. 7B) using the voltages indicated. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage (for example, 0.5 volts).
• With reference toFIGS. 8A and 8B, the logic levels may be programmed intotransistors102aand102busing a low power consumption technique. The low power consumption technique employs positive and negative control signals/voltages in order to program the complementary states. For example, a logic high is written intotransistor102a(FIG. 8B) and a logic high is written intotransistor102b(FIG. 8A) using a negative gate voltage.
• Thesource regions108aand108boftransistors102aand102b, respectively, are employed to read, sense and/or determine the data state ofcell100. In this regard,source regions108aand108bare selectively connected to comparator104 (for example, a voltage or current sense amplifier) to permit the logic value of memory cell110 to be read, sensed and/or determined. As indicated above,transistors102aand102bmay store the respective data state via majority carriers within the electrically floatingbody regions106aand106b, respectively. In response to read control signals, the logic state of eachtransistor102aand102bis read bycomparator104 in a differential manner. Exemplary read voltage signals are indicated inFIG. 9.
• Notably, pass gates and/or column switch circuitry (not illustrated) may be employed to selectively connectsource regions108aand108boftransistors102aand102b, respectively, to comparator104 to facilitate the read operation of the data state ofcell100. Moreover, as is apparent fromFIG. 6, a memory device may include a plurality ofmemory cells100, arranged in repeating patterns. In this regard, with reference toFIGS. 10A and 10B, the exemplary write techniques, described above, are illustrated in a schematic representation of a memory matrix. Further, with reference toFIG. 10C, the exemplary read technique, described above, is illustrated in a schematic representation of a memory matrix. Notably, the exemplary read and write techniques ofFIGS. 10A-10C, including the exemplary levels of the read and write voltages, may reduce, minimize and/or eliminate any disturbance issues (for example, issues of stored charge loss or gain within memory cells) caused to memory cells having common gate lines, drain lines and/or source lines with memory cells that are accessed via read and write operations.
• In another embodiment, with reference toFIGS. 11 and 12,memory cell100 may include a layout wherebytransistors102aand102binclude (1)common source regions108aand108b, respectively, and (2)gates112aand112b, respectively, that are connected to the same gate line118. Exemplary write techniques are indicated inFIG. 13A (write logic low) andFIG. 13B (write logic high). An exemplary read technique is illustrated inFIG. 14. Notably, the voltage levels indicated inFIGS. 13A, 13B and14 may be relative or absolute. In this regard, a logic low may be written intotransistor102a(FIG. 13A) ortransistor102b(FIG. 13B) using the voltages indicated. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage (for example, 0.25 volts).
• A memory array having a plurality ofmemory cells100 wherein the source regions and gates (gate lines) oftransistors102aand102bare in common may include a layout as illustrated inFIGS. 15A-15C. In this regard, with reference toFIGS. 15A and 15B, exemplary write techniques of the memory array of this embodiment are illustrated in a schematic representation of a memory matrix. With reference toFIG. 15C, an exemplary read technique is illustrated in a schematic representation of a memory matrix including a plurality ofmemory cells100 configured with common source regions and gates (gate line). Notably, the exemplary read and write techniques ofFIGS. 15A-15C, including the exemplary levels of the read and write voltages, may reduce, minimize and/or eliminate any disturbance issues (to neighboring cells) that may result using other read and write voltage levels.
• In certain embodiments, it may be advantageous to further reduce, minimize and/or eliminate any issues of disturbance (for example, issues of stored charge loss or gain within memory cells) of the data states of memory cells having common gate lines, drain lines and/or source lines with those memory cells that are being accessed (i.e., being read from or written to). In one embodiment, a two-step write operation may be employed toprogram memory cell100awith little to no disturbance to adjacent and/or neighboring cells (i.e., cells that share source lines, drain lines and/or gate lines). In this regard, an entire row of memory cells may first be written to the same logic state and thereafter, individual bits are written to the opposite state in accordance with a desired data state (i.e., the individual bits are written to another state to reflect a desired data state).
• In particular, with reference toFIG. 16A, in one embodiment, the memory cells having a common source line are first written to the same logic state (for example, logic high or binary “1”). In this way, the state ofmemory cell100 is “cleared”. Thereafter, individual transistors102 ofmemory cells100 are written to a particular, desired and/or predetermined logic state (see, for example,FIG. 16B (write “0”) andFIG. 16C (write “1”)) according to the particular, desired and/or predetermined logic state ofmemory cell100. That is, one of the transistors ofmemory cell100 is written to logic low (binary “0”) to write either a logic high or logic low into memory cell100 (i.e.,transistor102aofFIG. 16B to store logic low inmemory cell100; andtransistor102bofFIG. 16C to store logic high in memory cell100). Notably, writing logic low to the other transistor ofmemory cell100 is inhibited by applying a suitable bitline voltage.
• Thus, in this embodiment, the first step of the write operation clears the memory cells having a common source line and the second step writes or stores new data or the previous data (in the event that the data did not change). Array architectures employing this write operation technique may have an advantage that the memory cells of the array are not “disturbed” (or experience little and/or negligible disturbance) because “high” voltages are applied in the row direction (i.e., on source lines114) but not in the column direction (i.e., on the drain lines116). Notably, this write technique may be performed as a page mode write where the page is first “cleared” and then individual bytes (or bits) in a page are written to a new state.
• Such a write technique may also be suitable for other memory array architectures or configurations. For example, the write technique may be implemented wherememory cells100 of each row of transistors102 has a dedicated source line to minimize, reduce and/or eliminate disturbance on adjacent rows. With reference toFIGS. 17, 18,19A and19B, and20, in one embodiment, a given row may be written to by applying a clear operation followed by a selective write operation. In this regard, a plurality ofmemory cells100, having gates that are connected to a common gate line, are arranged to formrow120. Exemplary voltages that implement a clear operation forrow120 and maintain the remaining portion of the array in a fixed state (i.e., unchanged in response to the clear operation) are indicated inFIG. 17. In response, the same logic state (for example, logic high or binary “1”) is stored in bothtransistors102aand102bofmemory cells100 ofrow120. In this way, the state ofmemory cell100 is “cleared”.
• Thereafter,individual transistors102aand102bof thememory cells100 ofrow120 are written to a particular, desired and/or predetermined logic state (see, for example,FIG. 18 (write “1”) inmemory cell100a) in order to store a particular, desired and/or predetermined logic state inmemory cell100. That is, as described above, one of the transistors ofmemory cell100 is written to logic low (binary “0”) to write either a logic high or logic low intomemory cell100. Notably, writing logic low to the other transistor of thememory cell100 is inhibited by applying a suitable bitline voltage.
• With reference toFIGS. 19A and 19B, the data may be read frommemory cells100 ofrow120 by applying the exemplary voltages indicated. Notably, the exemplary read voltages ofFIG. 19B may avoid, reduce and/or minimize the need for charge pumping to eliminate minority carriers from the floating body—gate interface.
• Another memory array architectures that may employ the two-step write technique that eliminates, minimizes and/or reduces disturbance to memory cells when reading from and/or writing to adjacent memory cells is illustrated inFIGS. 21-24. In this architecture, the source lines are shared but bit lines are separated. Thetransistors102aand102bofmemory cell100aare located on separate rows. The gates oftransistors102aand102bare connected together at the array boundary.
• Notably,transistors102aand102bofmemory cell100aare located on separate rows with the gates of eachtransistor102aand102bconnected at, for example, the array boundary. In this embodiment, there is a separate bit line (here,drain lines116aand116b) for eachtransistor102aand102bofmemory cell100aso that eachtransistor102aand102bmay be read separately using, for example, comparator104 (not illustrated inFIG. 23).
• FIGS. 25-28 illustrate another memory array architecture in which a plurality of memory cells “share” a source line and employ the two-step write technique that may eliminate, minimize and/or reduce disturbance to memory cells when reading from and/or writing to adjacent memory cells. In this regard, with reference toFIGS. 25 and 26, in one embodiment, a given row may be written to by applying suitable voltages to implement a clear operation followed by a selective write operation. In conjunction with applying suitable voltages to implement the clear operation, a write inhibit signal is applied to the gates of memory cells that share a source line114 (for example, a write inhibit signal may be applied to the gates of transistors that comprisememory cell100xandmemory cell100y).
• In particular, exemplary voltages that implement a clear operation forrow120 and maintain the neighboring memory cells (for example,memory cells100xand100y) remaining portion of the array in a fixed state (i.e., unchanged in response to the clear operation) are indicated inFIG. 25. The individual transistors102 of thememory cells100 ofrow120 are written to a particular, desired and/or predetermined logic state (see, for example,FIG. 26 (write “1”) inmemory cell100a) in order to store a particular, desired and/or predetermined logic state of thememory cell100. That is, as described above, one of the transistors ofmemory cell100 is written to logic low (binary “0”) to write either a logic high or logic low into thememory cell100.
• With reference toFIG. 27, the data may be read frommemory cells100 ofrow120 by applying the exemplary voltages indicated. Notably, an exemplary read inhibit voltage for the remaining portion of the array (including the neighboring memory cells) is also indicated. The read inhibit voltage/signal maintains the unselected portion of the array in a fixed state (i.e., unchanged in response to the read operation).
• Thememory cell100 is a dynamic storage device. As such,memory cell100 must be periodically or intermittently refreshed to maintain its data state.FIGS. 29 and 30 illustrate an exemplary (and inventive) refresh configuration and technique for refreshing and/or re-storing the data state ofmemory cell100. In one embodiment,gates112aand112bandsource regions108aand108boftransistors102aand102b(respectively) ofmemory cell100 are connected and thereafter a current (I) is applied on the electrically shorted gates and sources. Thedrain regions110aand110boftransistors102aand102b(respectively) are maintained at a predetermined voltage (for example, 0V).
• With reference toFIG. 29, in operation, becausetransistors102aand102bofmemory cell100 have different thresholds depending on which transistor is storing logic low and which transistor is storing a logic high, the forced current (I) will pass mainly through the transistor having the lower threshold (i.e., the transistor storing a logic high (binary “1”)). With a small forced current, the transistor currents will differ by orders of magnitude. The higher current through the low threshold transistor will inject holes into the body of that transistor and, as such, will reinforce the logic high (binary “1”). The high threshold transistor may have some hole injection but not enough to overcome the natural tendency to return to the neutral state.
• Notably, the current (I) may also be applied to the electrically shorted gates and drains with the sources maintained at a predetermined voltage (for example, 0V).
• FIG. 30 illustrates the refresh technique in the context of a memory array whereinrow120 ofmemory cells100 are refreshed. When refreshing an entire row, the forced current flows almost exclusively through all the transistors storing a logic high (binary “1”). It should be noted that this refresh technique is well suited to the memory cells and memory array architecture of the present inventions because the optimum range of forced current is independent of the data stored in the refreshed row (that is, half the transistors contain a logic high and the other half contain a logic low).
• Notably, althoughFIG. 30 illustrates a “separated source” array architecture, the technique is also applicable to the other array architectures described herein. For the sake of brevity, the discussion regarding refresh will not be repeated for such other array architectures.
• There are many inventions described and illustrated herein. While certain embodiments, features, materials, configurations, attributes and advantages of the inventions have been described and illustrated, it should be understood that many other, as well as different and/or similar embodiments, features, materials, configurations, attributes, structures and advantages of the present inventions that are apparent from the description, illustration and claims. As such, the embodiments, features, materials, configurations, attributes, structures and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different, embodiments, features, materials, configurations, attributes, structures and advantages of the present inventions are within the scope of the present invention.
• For example, as mentioned above, the illustrated voltage levels to implement the write and read operations are exemplary. The indicated voltage levels may be relative or absolute. That is, for example, a logic low may be written intotransistor102a(see, for example,FIG. 7A) ortransistor102b(see, for example,FIG. 7B) using the voltages indicated therein. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased by 0.5 volts).
• As mentioned above, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
• While a significant portion of this description includes details (for example, clear, write, read and inhibit voltages) directed to N-channel transistors, the inventions (and embodiments thereof described herein are entirely applicable to P-channel transistors. In such embodiments, majority carriers inbody region18 are electrons and minority carriers are holes. Indeed, the memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Moreover, the circuitry that is peripheral to the memory array (for example, row and column address decoders, not illustrated herein) may include P-channel and/or N-channel type transistors, including transistors liketransistor14.
• Notably, where P-channel type transistors are employed asmemory cells12 in the memory array(s), suitable clear, write, read and inhibit voltages are well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, these discussions will not be repeated.
• Further, memory cell(s)102 (as well as memory array and matrices40a-n) may also employ the structure, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated in non-provisional patent application entitled “Semiconductor Device”, which was filed on Feb. 18, 2004, by Fazan and Okhonin, and assigned Ser. No. 10/487,157 (hereinafter “Semiconductor Device Patent Application”). The entire contents of the Semiconductor Device Patent Application, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.

Claims (21)

1. A semiconductor dynamic random access memory cell for storing a first data state and a second data state, the memory cell comprising:

first and second transistors, wherein each transistor includes:

a source region;

a drain region;

a body region disposed between and adjacent to the source region and the drain region, wherein the body region is electrically floating; and

a gate spaced apart from, and capacitively coupled to, the body region;

wherein each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region, and

wherein the memory cell is in: (1) the first data state when the first transistor is in the first state and the second transistor is in the second state and (2) the second data state when the first transistor is in the second state and the second transistor is in the first state.

2. The semiconductor dynamic random access memory cell ofclaim 1 wherein the memory cell includes two outputs including a first output connected to the drain region of the first transistor and a second output connected to the drain region of the second transistor.

3. The semiconductor dynamic random access memory cell ofclaim 2 wherein the gate of the first transistor is connected to the gate of the second transistor.

4. The semiconductor dynamic random access memory cell ofclaim 3 wherein the source region of the first transistor and the source region of the second transistor are the same region.

5. The semiconductor dynamic random access memory cell ofclaim 1 wherein the memory cell is programmed to a first data state by applying a first control signal to the gate of the first transistor and a second control signal to the gate of the second transistor and wherein the first and second control signals include different voltage amplitudes.

6. The semiconductor dynamic random access memory cell ofclaim 1 wherein the memory cell includes two outputs including a first output connected to the source region of the first transistor and a second output connected to the source region of the second transistor.

7. The semiconductor dynamic random access memory cell ofclaim 6 wherein the drain region of the first transistor and the drain region of the second transistor are the same region.

8. A semiconductor memory array, comprising:

a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes:

first and second transistors, wherein each transistor includes:

a source region;

a drain region;

a body region disposed between and adjacent to the source region and the drain region, wherein the body region is electrically floating; and

a gate spaced apart from, and capacitively coupled to, the body region;

wherein each transistor includes a first state representative of a first charge in the body region; and a second data state representative of a second charge in the body region; and

wherein each memory cell is in: (1) the first data state when its first transistor is in the first state and its second transistor is in the second state and (2) the second data state when its first transistor is in the second state and its second transistor is in the first state.

9. The semiconductor memory array ofclaim 8 further including a comparator having a plurality of inputs to sense the states of the first and second transistors of a semiconductor dynamic random access memory cell of the plurality of semiconductor dynamic random access memory cell, wherein a first input of the comparator is selectively coupled to a first transistor of the semiconductor dynamic random access memory cell and a second input of the comparator is selectively coupled to the second transistor of a semiconductor dynamic random access memory cell.

10. The semiconductor memory array ofclaim 8 wherein at least one of the rows of semiconductor dynamic random access memory cells includes a source line that is connected to each of the semiconductor dynamic random access memory cells of the row.

11. The semiconductor memory array ofclaim 8 wherein each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

12. The semiconductor memory array ofclaim 8 further including:

a comparator having a plurality of inputs to sense the data state of a semiconductor dynamic random access memory cell of the plurality of semiconductor dynamic random access memory cell, wherein a first input of the comparator is selectively coupled to the drain region of the first transistor of the semiconductor dynamic random access memory cell and a second input of the comparator is selectively coupled to the drain of second first transistor of a semiconductor dynamic random access memory cell; and

wherein each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the row.

13. The semiconductor memory array ofclaim 8 wherein at least one semiconductor dynamic random access memory cell is programmed in a first data state by performing a clear operation of the first and second transistors of the semiconductor dynamic random access memory cell and then performing a write operation wherein, in response, the first transistor of the semiconductor dynamic random access memory cell is in a first state and the second transistor of the semiconductor dynamic random access memory cell is in a second state.

14. The semiconductor memory array ofclaim 8 wherein at least one semiconductor dynamic random access memory cell is programmed in a first data state by first placing the first and second transistors of the semiconductor dynamic random access memory cell in a first state and thereafter placing the second transistor of the semiconductor dynamic random access memory cell is in a second state.

15. The semiconductor memory array ofclaim 14 wherein an unselected portion of the semiconductor memory array is maintained in a fixed state when programming the at least one semiconductor dynamic random access memory cell by applying a write inhibit signal to the transistors of the semiconductor dynamic random access memory cells comprising the unselected portion of the semiconductor memory array.

16. The semiconductor memory array ofclaim 8 wherein each semiconductor dynamic random access memory cell includes two outputs including a first output connected to the drain region of the first transistor and a second output connected to the drain region of the second transistor.

17. The semiconductor memory array ofclaim 8 wherein gate of the first transistor and the gate of the second transistor of each semiconductor dynamic random access memory cell are each connected to an associated common gate line.

18. The semiconductor memory array ofclaim 8 wherein the source region of the first transistor and the source region of the second transistor of each semiconductor dynamic random access memory cell are the same region.

19. The semiconductor memory array ofclaim 8 wherein the source region of the first transistor and the source region of the second transistor of each semiconductor dynamic random access memory cell are connected to different source lines.

20. The semiconductor memory array ofclaim 8 wherein each semiconductor dynamic random access memory cell includes two outputs including a first output connected to the source region of the first transistor and a second output connected to the source region of the second transistor.

21. The semiconductor memory array ofclaim 20 wherein the drain region of the first transistor and the drain region of the second transistor of each semiconductor dynamic random access memory cell are the same region.

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