US20040253803A1 - Packaging assembly and method of assembling the same - Google Patents

Abstract

A packaging assembly includes a substrate; chip-site lands disposed on the first surface; first solder balls connected to the chip-site lands; second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2003-170905, filed on Jun. 16, 2003; the entire contents of which are incorporated herein by reference.[0001]
BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0002]
• The present invention relates to semiconductor device technology, more specifically to a packaging assembly and a method of assembling a packaging assembly using soldering technology.[0003]
• 2. Description of the Related Art[0004]
• Semiconductor integrated circuits such as LSI have achieved higher levels of integration in recent years. Semiconductor devices themselves are shrinking in geometrical size, increasing in the degree of on-chip integration, and number of pin-counts are increasing. As for the surface-mount package (SMP), flip chip bonding technology which connects a semiconductor chip and a circuit board with bumps has been employed widely. As for the flip chip bonding technology, an encapsulating resin is applied on a surface of a circuit board having bumps on the surface. Next, bumps formed on an element side of a semiconductor chip and the bumps formed on the circuit board are mated and contacted to each other. Furthermore, the circuit board and the semiconductor chip are heated around 150° C. during a reflow process, and oxide films and alien substances contained in the bumps are removed by the resin which serves as a flux. Then, bumps of the circuit board and the semiconductor chip are melted and connected during heating process at 200° C. After that, bumps and the resin are hardened completely in the curing process.[0005]
• In the SMP assembling process, solder bumps made of solder paste are often used as bump electrodes. However, recently, it has been pointed out that the outflow of lead from electronic products dumped onto reclaimed land pollutes underground water. Thus, throughout the world, manufacturers are changing the Sn—Pb eutectic, used for mounting semiconductor chips or printed circuit boards, to lead-free solder alloys.[0006]
• Material examples of lead-free solder alloys, responding to an environmental problem, are tin-silver (Sn-Ag) solder and tin-zinc (Sn—Zn) solder. However, for lead-free solder alloys such as Sn-Ag solder, the melting temperature is generally higher than that of the conventional eutectic alloy. Therefore, lead-free solder alloys having higher melting temperatures have to be reflowed at a relatively high temperature of approximately 200° C. However, when reflow is performed at high temperature conditions, strong thermal stresses are applied to semiconductor chips and mounting bases, and an aggravation of coplanarity and a fall in reliability occurs. Moreover, when organic materials are employed as a circuit board, a gas is generated from the circuit board and that invades into an underfill resin by reflowing at a high temperature of more than 200° C. On the other hand, while a curing reaction advances for the underfill resin, the viscosity of the underfill resin rises. As a result, the gas in the underfill resin remains as a void without being ejected outside of the underfill resin. Furthermore, since the heat shrinkage rate of underfill resin also increases by reflowing, thermal stresses occur to the electrodes on the semiconductor element side, and cracks in the electrodes arise.[0007]
• Meanwhile, since recent microprocessors process huge quantities of information at high speed, there have been problems with the resistance of wires interconnecting transistors, and the capacitances of insulators between interconnect wires. For example, wire materials are changing from aluminum (Al) to copper (Cu) having a high electrical conductivity, and insulators are changing from silicon oxide films to materials having low dielectric constants. However, such materials used in recent electronic devices are generally weak in mechanical strength. In particular, low dielectric constant films (hereinafter called low-k films) used as insulators on semiconductor chips are significantly weak in mechanical strength and in adhesion intensity because of their porous structures necessary to ensure low dielectric constants. Therefore, when reflowing to electrodes is performed using a lead-free solder at a high melting temperature, strong thermal stresses also occur in the low-k films within the semiconductor chip. Furthermore, the low-k films disposed just under the solder electrodes may be damaged by the heat and the adhesive strength between the semiconductor chip and the mounting base is also decreased.[0008]
SUMMARY OF THE INVENTION
• An aspect of the present invention inheres in a packaging assembly embracing a substrate defined by a first surface and a second surface opposing to the first surface; a plurality of chip-site lands disposed on the first surface; a plurality of first solder balls connected to the chip-site lands; a plurality of second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.[0009]
• Another aspect of the present invention inheres in a method of assembling a packaging assembly embracing preparing a substrate having a plurality of chip-site lands disposed on the first surface of a substrate; disposing a plurality of first solder balls on the chip-site lands; applying an underfill resin around the chip-site lands and the first solder balls; disposing a plurality of second solder balls on corresponding bonding pads disposed on a semiconductor chip; aligning the first solder balls with corresponding second solder balls; connecting the first and second solder balls by melting the first solder balls; and hardening the underfill resin.[0010]
BRIEF DESCRIPTION OF DRAWINGS
• FIG. 1 is a sectional view showing an example of packaging assembly according to a first embodiment of the present invention.[0011]
• FIG. 1A is an enlarged view showing an example of a third surface of a semiconductor chip shown in FIG. 1.[0012]
• FIGS.[0013]2 to10 are sectional views showing a first example of assembling the packaging assembly according to the first embodiment of the present invention.
• FIGS. 11 and 12 are sectional views showing a second example of assembling the packaging assembly according to the first embodiment of the present invention.[0014]
• FIG. 13 is a sectional view showing a modification of the first level assembly according to a first embodiment of the present invention.[0015]
• FIGS. 14 and 15 are sectional views showing an example of assembling the modification of the packaging assembly shown in FIG. 13 according to the first embodiment of the present invention.[0016]
• FIG. 16 is a sectional view showing an example of packaging assembly according to a second embodiment of the present invention.[0017]
• FIGS. 17 and 18 are sectional views showing an example of assembling the packaging assembly according to the second embodiment of the present invention.[0018]
• FIGS. 19 and 20 are sectional views showing a modification of packaging assembly according to the second embodiment of the present invention.[0019]
DETAILED DESCRIPTION OF THE INVENTION
• With reference to the accompanying drawings, first and second embodiments of the present inventions are described. Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. Generally, and as is conventional in the representation of semiconductor packaging assemblies, it will be appreciated that the various drawings are not drawn to scale from one figure to another nor inside a given figure, and in particular that the layer thicknesses are arbitrarily drawn for facilitating the reading of the drawings. In the following descriptions, numerous details are set forth such as specific signal values, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details.[0020]
• (FIRST EMBODIMENT)[0021]
• The[0022]packaging assembly100 according to a first embodiment of the present invention encompasses, as shown in FIG. 1, asubstrate1 defined by a first surface and a second surface opposing to the first surface, a plurality of chip-site lands2a,2b,2c, and2d disposed on the first surface, a plurality of afirst solder balls3a,3b,3c, and3d connected to the chip-site lands2a,2b,2c, and2d, a plurality of asecond solder balls4a,4b,4c, and4dconnected to thefirst solder balls3a,3b,3c, and3d, asemiconductor chip6 connected to thesecond solder balls4a,4b,4c, and4d on a third surface, and anunderfill resin7 disposed around thefirst solder balls3a,3b,3c, and3dandsecond solder balls4a,4b,4c, and4d. Theunderfill resin7 also serves as a flux.
• The[0023]substrate1 is a kind of printed circuit board made from a material including epoxy resin. Thesubstrate1 has: awiring layer15 on a second surface, a plurality of chip-site lands2a,2b,2c, and2don a first surface, and a protective film (passivation layer)18 which is made from SiO₂film, PSG film and the like. Theprotective film18 is stacked on the chip-site lands2a,2b,2c, and2d. As the material of thesubstrate1, various organic synthetic resins and inorganic materials including ceramic and glass can be used. Among organic synthetic resins, phenolic resin, polyester resin, epoxy resin, polyimide resin, fluoroplastic, and the like can be used. Meanwhile, paper, woven glass fabric, a glass backing material, or the like is used as a backing material that becomes a core informing a slab-shaped structure. As a general in organic base material, ceramic can be used. Alternatively, a metal substrate is used in order to improve the heat-radiating characteristics. In the case where a transparent substrate is needed, glass is used. As a ceramic substrate, alumina (Al₂O₃), mullite (3Al₂O₃.2SiO₂), beryllia (BeO), aluminum nitride (AlN), silicon nitride (SiN), and the like can be used. Furthermore, it is possible to use a metal insulator substrate in which a polyimide resin plate having high thermal resistance is laminated onto metal, such as iron or copper, to form a multi-layered structure. The thickness of thesubstrate1 is not limited. As for the chip-site lands2a,2b,2c, and2d, and thewiring layer15, electrically conductive material such as alminium (Al,) alminium alloy (Al—Si, Al—Cu—Si), gold, copper, or the like can be used. Alternatively, other electrodes can be provided through a plurality of signal lines such as gate wires connected to a plurality of gate electrodes. As gate electrodes, it is possible to use polysilicon, refractory metal such as tungsten (W), titanium (Ti), and molybdenum (Mo), silicides thereof (WSi₂, TiSi₂and MoSi₂), polycide using these silicides, or the like. Alternatively, inside of thesubstrate1, a plurality of vias can be formed and a plurality of inner buried wires connected to the vias can be disposed.
• The chip-[0024]site lands2a,2b,2c, and2dare aligned at equal intervals on the first surface of thesubstrate1. The positions, material, number, and the like of the chip-site lands2a,2b,2c, and2dare not limited. Thefirst solder balls3a,3b,3c, and3dare connected on the chip-site lands2a,2b,2c, and2d. For thefirst solder balls3a,3b,3c, and3d, solder materials having lower melting temperature can be used. As for thefirst solder balls3a,3b,3cand3d, materials selected from a tin-bismuth (Sn—Bi) alloy, tin-bismuth-silver (Sn—Bi—Ag) alloy, tin-zinc (Sn—Zn) alloy, tin-zinc-bismuth (Sn—Zn-Bi) alloy, tin-bismuth-indium (Sn—Bi—In) alloy, bismuth-indium (Bi—In) alloy, bismuth-palladium (Bi—Pd) alloy, indium-silver (In—Ag) alloy, tin-lead (Sn=5 w %, Pb=95 w %) can be used. Melting temperatures of a these alloys are as follows: Sn—Pb alloy and a Sn—Bi-Ag alloy are from 138° C. to 150° C., Sn—Zn alloy is from 198° C. to 210° C, Sn—Bi—In alloy is from 190° C. to 200° C., Bi—In alloy is from 72° C. to 120° C., Sn-In alloy is from 116° C. to 130° C., In—Ag alloy is from 141° C. to 160° C., Sn—Pb (Sn=5 w %, Pb=95 w %) alloy is from 320° C. to 330° C. In case where the outflow of lead to the environment is taken into consideration, lead-free solders having lower melting temperatures may be used for thefirst solder balls3a,3b,3c, and3d. For example, when a material such as an organic synthetic resin is used for thesubstrate1, solder materials having lower melting temperature such as Sn—Bi alloy and Sn—Bi—Ag alloy can be used to prevent gas generation from the substrate. The top surface of thefirst solder balls3a,3b,3cand3dare taking a shape of concave on the chip-site lands2a,2b,2cand2d. Thesecond solder balls4a,4b,4cand4dtaking spherical shapes are adhered on the top surface of the concave-shaped balls (first solder balls)3a,3b,3c, and3d.
• As shown in FIG. 1, the[0025]second solder balls4a,4b,4cand4dare connected to thebonding pads5a,5b,5cand5ddisposed on the third surface of thesemiconductor chip6. As for thesecond solder balls4a,4b,4c, and4d, solder materials having higher melting temperature than thefirst solder balls3a,3b,3c, and3d. As for thesecond solder balls4a,4b,4c, and4d, materials selected from a tin-silver (Sn—Ag) alloy, tin-silver-cupper (Sn—Ag—Cu) alloy, tin-lead (Sn=63 w % Pb=35 w %) alloy, tin-zinc (Sn—Zn) alloy can be used. Melting temperatures of these alloys are as follows: a Sn—Ag alloy is from 220° C. to 225° C., Sn—Ag—Cu alloy is from 215° C. to 230° C., Sn—Pb (Sn=63 w % Pb=35 w %) alloy is from 180° C. to 185° C., Sn—Zn alloy is from 195° C. to 215° C. Materials of thesecond solderballs4a,4b,4c, and4dmay be changed depending on the melting temperature of the material used for thefirst solder balls3a,3b,3c, and3d. For example, when materials containing lead are used as solder balls, Sn—Pb alloys composed of 5 w % tin and 95 w % lead can be used as thefirst solder balls3a,3b,3cand3dand Sn—Pb alloys composed of 63 w % tin and37 w % of lead can be used as thesecond solder balls4a,4b,4c, and4d. On the other hand, if the outflow the lead to the environment is taken into consideration, lead-free solders having lower melting temperature may be useful for thesecond solder balls4a,4b,4c, and4d. For example, Sn—Bi alloys may be used as thefirst solder balls3a,3b,3c, and3d, and Sn—Ag alloys may be used as thesecond solder balls4a,4b,4c, and4d.
• As shown in FIG. 1A, a plurality of semiconductor elements (circuit elements)[0026]10s₁,10s₂,10d₁, and10d₂, which are heavily-doped impurity regions doped with donors or acceptors of approximately 1×10¹⁸cm^{31 3}to 1×10^{21 cm3}(such as source regions10s₁and10s₂and drain regions10d₁and10d₂or emitter regions/collector regions) or the like are merged on the third surface of thesemiconductor chip6. Insulatingfilms50,51,52,53, and54, made from low-k films are stacked into a multi-level structure using low-k films on the semiconductor elements10s₁,10s₂,10d₁, and10d₂.Metallic interconnections50a,50b,50c,50d,51a,51b,51c,51d,51e,53a,53b,54a,54b, and54cmade of aluminum (Al) aluminum alloy (Al—Si or Al—Cu—Si) or the like are alternatively stacked into the insulatingfilms50,51,52,53, and54 so as to connect the semiconductor elements10s₁,10s₂,10d₁, and10d₂. On the uppermost layer of the insulatingfilms54, low-k films12 as shown in FIG. 1 can be stacked into multi-level structure. As shown in FIG. 1,bonding pads5a,5b,5cand5dare formed just under the low-k film12. Note that, prepositions, such as “on” and “under” are defined with respect to a planar surface of the substrate, regardless of the orientation the substrate is actually held. As shown in FIG. 1, aprotective film13 made from a silicon oxide film (SiO₂), a PSG film, a BPSG film, a silicon nitride film (Si₃N₄), a polyimide film or the like is formed on the low-k film12 andbonding pads5a,5b,5cand5dand covers the third surface of thesemiconductor chip6. In theprotective film13, a plurality of openings (not shown in FIG. 1) are selectively provided so as to expose partially the top surface of therespective bonding pads5a,5b,5cand5d. Thebarrier metals14a,14b,14c, and14d, which are connected to thesecond solder balls4a,4b,4c, and4d, are formed on the respective bonding pads Sa,5b,5cand5d. Note that, as for the low-k film12, a material having an effective dielectric constant of the low-k film is equal to or less than 3.5 is desirable to accomplish lower effective dielectric constant between wirings. As for the low-k films, for example, an inorganic insulator such as fluorine doped silicon mono oxide (SiOF), carbon doped silicon mono oxide (SiOC), organic silica, porous HSQ, benzocycrobutene (BCB) and porous films made from above mentioned materials can be used. Moreover, to prevent exfoliation, it can be agreeable that the coherence strength of the insulatingfilms50,51,52,53 and54, and low-k film12 to the circuit elements10s₁,10s₂,10d₁, and10d₂,metallic interconnections50a,50b,50c,50d,51a,51b,51c,51d,51e,53a,53b,54a,54b, and54c, and thesemiconductor chip6 is equal to or less than 15 J/m².
• As the[0027]underfill resin7, materials such as a resin containing flux, a stiffening material having capability of flux, a resin containing filler, and materials containing acid anhydrides can be used. As for the resin, epoxy resin, acrylic resin, silicon resin, polyimide resin and the like may be useful.
• In the[0028]packaging assembly100 according to the first embodiment of the present invention, thefirst solder balls3a,3b,3c, and3dare disposed on thesubstrate1. Thesefirst solder balls3a,3b,3c, and3dare melted when heated at a lower temperature of approximately 150° C. Therefore, when an organic synthetic resin is used for a material of10 thesubstrate1, because gas is not released from thesubstrate1, voids are not generated in theunderfill resin7. Moreover, since thesubstrate1 and thesemiconductor chip6 are connected at a low temperature of 150° C., the heat contraction of thesubstrate1,semiconductor chip6, andresin7 can be minimized. At the same time, coplanarity and reliability of thesubstrate1 may be improved. Furthermore, since strong thermal stress is not added to thesecond solder balls4a,4b,4c, and4d, the low-k film12 disposed on thebonding pads5a,5b,5cand5ddoes not break. Theprotective film13 containing organic resins is disposed on the surface of the low-k film12. Therefore, the low-k film12 will not exfoliated.
• Furthermore, when lead-free solder materials are used for the first and[0029]second solder balls4a,4b,4c,and4d,5a,5b,5cand5drespectively, thepackaging assembly100 corresponding to the environmental problem may be accomplished.
• (FIRST ASSEMBLING METHOD OF THE FIRST EMBODIMENT)[0030]
• Next, as shown in FIGS.[0031]2 to10, a first assembling method of thepackaging assembly100 according to the first embodiment of the present invention is described. Here, it is obvious that the assembling method of thepackaging assembly100 described below is one example, and thepackaging assembly100 is feasible by other various assembly methods including modifications of the present embodiment.
• (a) First, the semiconductor chip having circuit elements, insulating films, and metallic interconnections on the third surface (omitted in FIG.2) are prepared. Then, as shown in FIG. 2, a multi-level structure of low-[0032]k films12A and12B as interlayer dielectrics are stacked andmetal wires11a,11b,11c,11d, and11emade from Al, Al—Si, Al—Cu—Si, or the like are formed into the low-k films12A and12B are formed. In the uppermost conductive layer, thebonding pad5ais formed. Next, aprotective film13 made from a Sio₂film, a PSG film, a BPSG film, a Si₃N₄film, a polyimide film, or the like is formed around thebonding pads5a. Subsequently, theprotection film13 is partially provided with anopening13A such that the bonding pad5 is exposed.
• (b) Next, as shown in FIG. 3 the titanium (Ti) film[0033]4A, nickel (Ni)film14B on theTi film14A, and thePd film14C on theNi film14B are formed gradually by use of a sputtering equipment or an electron beam evaporation apparatus, abarrier metal film14 is formed. Then, a photo resist film (not shown in FIG. 3) is applied onto thebarrier metal14, and a gap is formed between the photo resistfilms16aand16b. Next, as shown in FIG. 4, aconductive material17 is selectively buried in the groove between the photo resistfilms16aand16b.
• (c) Next, as shown in FIG. 5, the photo resist[0034]films16aand16bare stripped by solvents such as acetone, photo resist stripper and the like. Part of thePd film14C,Ni film14B, andTi film14A are removed by use of theconductive material14 as an etching mask. As for the removal of thePd film14C andNi film14B, an etching solution of aqua regia may be used. As for the removal of theTi film14A, an etching solution of ethylene diamine tetra-acetic acid may be used. Next, flux is applied around theconductive material17, and theconductive material17 is heated around 200° C.˜220° C. for 30 minutes during a reflowing process. Then, as shown in FIG. 6, thesecond solder ball4ais formed. After that, some electric testing may be performed to thesemiconductor chip6.
• (d) Next, as shown in FIG. 7, the[0035]substrate1 which is made from epoxy resin with a thickness of 30 μm˜60 μm is prepared. As for thesubstrate1, phenolic resin, polyester resin, epoxy resin, polyimide resin, fluoroplastic, and the like may be used instead of epoxy resin. Awiring layer15 made from copper or the like is formed on the second surface of thesubstrate1. On the first surface, the chip-site land2ais formed and theprotective film18 made from SiO₂film, PSG film or the like is laminated on the chip-site land2a. Then, theprotection film18 is partially provided with anopening18A such that the chip-site land2ais exposed, thus forming thefirst solder ball3a.
• (e) Next, as shown in FIG. 8,[0036]underfill resin7 having property of flux is applied on the second surface of thesubstrate1 so as to surround the chip-site lands2a,2b,2c, and2d, and thefirst solder balls3a,3b,3c, and3d. Note that, a resin containing filler can be used as theunderfill resin7 to decrease the thermal expansion coefficient and to improve reliability. Then, as shown in FIG. 9, thesecond solderballs4a,4b,4c, and4dare aligned on thefirst solder balls3a,3b,3c, and3dso as to be mated each other. After that, thesubstrate1 and thesemiconductor chip7 are introduced to a furnace or the like and reflow is performed for 1˜15 seconds at about 150° C., pressurizing toward a substrate from upside of thesemiconductor chip6. As a result, since theunderfill resin7 is activated, oxides and impurities of thefirst solder balls3a,3b,3c, and3dare removed by the flux capability of theunderfill resin7. Next, thefirst solder balls3a,3b,3c, and3dare melted and adhered around thesecond solder balls4a,4b,4c, and4d, as shown in FIG. 10. Moreover, in order to harden theunderfill resin7, thesubstrate1 and thesemiconductor chip6 are introduced to the oven and dried.
• As described above, the[0037]packaging assembly100 as shown in FIG. 1 can be assembled. According to thepackaging assembly100 of the first embodiment of the present invention, thefirst solder balls3a,3b,3cand3ddisposed on the chip-site lands2a,2b,2c, and2dmelt at a temperature of about 150° C. and connect temporarily to thesecond solder balls4a,4b,4c, and4d. Therefore, when an organic synthetic resin is used for a material of thesubstrate1, gas will not be released from thesubstrate1, and voids are not generated in theunderfill resin7. Moreover, since thesubstrate1 and thesemiconductor chip6 are connected at a low temperature, the heat contraction of thesubstrate1,semiconductor chip6, andresin7 can be minimized. At the same time, coplanarity and reliability of thesubstrate1 may be improved. Furthermore, since strong thermal stress is not incurred to thesecond solder balls4a,4b,4c, and4d, the low-k film12 disposed on thebonding pads5a,5b,5cand5dwill not break. Theprotective film13 containing organic resin is disposed on the surface of the low-k film12. Therefore, the low-k film12 is not exfoliated.
• (SECOND ASEMBLING METHOD OF THE FIRST EMBODIMENT)[0038]
• Next, as shown in FIGS. 11 and 12, a second assembling method of the[0039]packaging assembly100 according to the first embodiment of the present invention is described. Here, since a sequence of the procedure of the second assembling method before forming thesecond solder balls4a,4b,4c, and4don thesemiconductor chip6 orfirst solder balls3a,3b,3c, and3don thesubstrate1 is substantially the same shown in FIGS.2˜8, detailed explanation is omitted.
• First, an assembling[0040]stage20A and anassembling tool20B are heated to around 150° C. Then, the second surface of thesubstrate1 havingfirst solder balls2a,2b,2c, and2don the first surface is disposed on the assemblingstage20A by use of a vacuum wand and the like. A fourth surface of thesemiconductor chip6 havingsecond solder balls3a,3b,3c, and3don the third surface is fixed on theassembling tool20B by use of the vacuum wand and the like. Next, as shown in FIG. 11, thesecond solder balls4a,4b,4c, and4dare aligned with thefirst solder balls3a,3b,3c, and3dso as to be mated each other. Then, the assemblingstage20A is pressurized by the assemblingtool20B. Thefirst solder balls3a,3b,3c, and3dare melted and their shapes transformed, and are adhered to thesecond solder ball4a,4b,4c, and4d. Moreover, the assemblingstage20A and theassembling tool20B are cooled, theunderfill resin7 is cooled and hardened.
• (MODIFICATION OF THE FIRST EMBODIMENT)[0041]
• As shown in FIG. 13, a[0042]packaging assembly101 according to a modification of the first embodiment of the resent invention differs from thepackaging assembly100 shown in FIG. 1 in that thepackaging assembly101 further includes a plurality of second chip-site lands22a,22b,22c, and22d, a plurality ofthird solder balls23a,23b,23c, and23dconnected to the second chip-site lands22a,22b,22c, and22d, a plurality offourth solder balls24a,24b,24c, and24dconnected to thethird solder balls23a,23b,23c, and23d, and asecond semiconductor chip26 connected to thefourth solder balls24a,24b,24c, and24d. On the third surface of thesemiconductor chip26, a second low-k film32 is disposed. A plurality ofsecond bonding pads25a,25b,2c, and25dare aligned under the second low-k film32. A secondprotective film33 containing organic resin is formed on the surface of the second low-k film32. Although, it is omitted in FIG. 13, a second circuit element are merged in the third surface or thesecond semiconductor chip26, and second multilevel-interconnection having insulating films and metallic interconnections are disposed on the third surface of thesemiconductor chip26 as shown in FIG. 1A.
• Detailed explanation is omitted regarding the second chip-site lands[0043]22a,22b,22c, and22d, thethird solder balls23a,23b,23c, and23d, thefourth solder balls24a,24b,2c,25d, the second low-k film32, the second chip-sideinternal connection pad25a,25b,2c, and25d, and the secondprotective film33, which have the same organization as the chip-site lands2a,2b,2c, and2d,first solder balls3a,3b,3c, and3d, thesecond solder balls4a,4b,4c, and4d, the low-k film12, the chip-sideinternal connection pad5a,5b,5cand5d, and theprotective film33, respectively.
• (ASSEMBLING METHOD OF THE MODIFICATION)[0044]
• Next, as shown in FIGS.[0045]13 to15, an assembling method of thepackaging assembly101 according to the modification of first embodiment of the present invention is described.
• (a) First, the[0046]substrate1 which is made from epoxy resin with a thickness of 30 μm˜60 μm is prepared. Awiring layer15 made from copper is formed on the second surface of thesubstrate1. On the first surface, the chip-site lands2a,2b,2c, and2d, and the second chip-site lands22a,22b,22c, and22dare formed. Then, theprotective film18 made from SiO₂film, PSG film or the like is laminated on the chip-site lands2a,2b,2c, and2d, and the second chip-site lands22a,22b,22c, and22d. Theprotection film18 is partially removed such that the chip-site lands2a,2b,2c, and2d, and the second chip-site lands22a,22b,22c, and22dare exposed. Thus, thefirst solderballs3a,3b,3c, and3dare formed on the chip-site lands2a,2b,2d, and2d. Thethird solder balls23a,23b,23c, and23dare formed on the second chip-site lands22a,22b,22c, and22d. Next, as shown in FIG. 14, thesubstrate1 is disposed on the assemblingstage20A which is heated around 150° C.
• (b) Next,[0047]underfill resin7A serves as flux is applied on the second surface of thesubstrate1 so as to surround the chip-site lands2a,2b,2c, and2d, and thefirst solder balls3a,3b,3c, and3d. Underfill resin (second underfill resin)7B serves as flux is applied so as to surround the second chip-site lands22a,22b,22c, and22d, and thethird solder balls23a,23b,23c, and23d. Then, underfillresins7A and7B are heated and activated by the heat of assemblingstage20A. As a result, oxides and impurities included on the surface offirst solder balls3a,3b,3c, and3dandthird solder balls23a,23b,23c,23dare removed by theunderfill resins7A and7B serving as flux. After that, the surfaces of thefirst solder balls3a,3b,3c, and3dare exposed on the surface of theunderfill resin7A. The surface of thethird solder balls23a,23b,23c, and24dare also exposed on the surface or theunderfill resin7B.
• (c) Next, as shown in FIG. 14, the[0048]second solder balls4a,4b,4c, and4dare aligned on thefirst solder balls3a,3b,3c, and3dso as to be mated to each other, and pressurized by being pushed from the fourth surface of thesemiconductor chip6 toward thesubstrate1. Then, thefirst solder balls3a,3b,3c, and3dare melted with heat from the assemblingstage20A and adhered to the around ofsecond solder balls4a,4b,4c, and4d. Next, as shown in FIG. 15, thefourth solder balls24a,24b,24c, and24dconnected with the second semiconductor chip25 are aligned on thethird solder balls23a,23b,23c, and23dso as to be mated each other, and pressurized by being pushed from fourth surface of thesecond semiconductor chip26 toward thesubstrate1. Then, thethird solder balls23a,23b,23c, and23dare melted with heat from the assemblingstage20A and adhered to the around offourth solder balls24a,24b,24c, and24d. Moreover, the assemblingstage20A and theassembling tool20B are cooled, and theunderfill resin7 is cooled and hardened.
• As described above, the[0049]packaging assembly101 as shown in FIG. 13 can be manufactured. According to thepackaging assembly101 of the first embodiment of the present invention, thefirst solder balls3a,3b,3cand3ddisposed on the chip-site lands2a,2b,2c, and2dmelt with the heat from assemblingstage20A of about 150° C. to be connected temporarily to thesecond solder balls4a,4b,4c, and4d. Therefore, whensecond semiconductor chip26 is mounted next tosemiconductor chip6, it can prevent the position ofsemiconductor chips6 and26 from shifting due to the flow ofunderfill resins7A and7B. Moreover, two or more semiconductor chips can be mounted adjacently. Since thepackaging assembly101 shown in FIG. 13 can be mounted at a low temperature of 150° C., gas is not released from thesubstrate1, and voids are not generated in theunderfill resin7 even if an organic synthetic resin is used for a material of thesubstrate1. Furthermore, since heat expansion of thesubstrate1 andsemiconductor chips6 and26, and heat contraction of theunderfill resin7 can be suppressed at lower level, strong thermal stresses are not be incurred tobonding pads5a,5b,5cand5d, andsecond bonding pads25a,25b,2c, and25d. Therefore, thermal stresses applied to the low-k film12 and second low-k film32 which are disposed close to thebonding pads5a,5b,5cand5d, andsecond bonding pads25a,25b,2c, and25d, can be minimized and breakage of the films can be prevented.
• (SECOND EMBODIMENT)[0050]
• The[0051]packaging assembly102 according to a first embodiment of the present invention encompasses, as shown in FIG. 16, a plurality ofinternal solder joints8a,8b,8c, and8ddisposed between chip-site lands2a,2b,2c, and2d, andbonding pads5a,5b,5cand5d. On the second surface of thesubstrate1, a plurality ofexternal lands15a,15b,15c, and15dare disposed. A plurality ofexternal solder balls21a,21b,21c, and21dare connected on theexternal lands15a,15b,15c, and15d, respectively. Others are the same as apackaging assembly100 shown in FIG. 1, detailed explanations are omitted.
• The[0052]internal solder joints8a,8b,8c, and8dare electrodes mixed withfirst solder balls3a,3b,3c, and3dandsecond solder balls4a,4b,4c, and4das shown in FIG. l. Theinternal solder joints8a,8b,8c, and8dhave higher melting temperature thanfirst solder balls3a,3b,3c, and3d, and have lower melting temperature thansecond solder balls4a,4b,4c, and4d. As for theinternal solder joints8a,8b,8c, and8d, at least two kinds of solder materials having higher and lower melting temperatures can be included. For solder materials having lower melting temperature, Sn—Bi alloys, Sn—Bi—Ag alloys, Sn—Zn alloys, Sn—Zn—Bi alloys, An—Bi—In alloys, Bi—In alloy, Sn—In alloys, In—Ag alloys, Sn—Pb (Sn=5 w %, Pb=95 w %) can be used. For the materials having higher melting temperature, for example, Sn—Ag alloys, Sn—Ag—Cu alloys, Sn—Pb (Sn-=63 w %, Pb=37 w %) alloys, and Sn—Zn alloys can be used.
• As for the[0053]external lands15a,15b,15c, and15d, conductive material such as alminium (Al,) alminium alloy (Al—Si, Al—Cu—Si), gold, copper, or the like can be used.
• Alternatively, other electrodes can be provided through a plurality of signal lines such as gate wires connected to a plurality of polysilicon gate electrodes. Instead of gate electrodes made from polysilicon, it is possible to use gate electrodes made from a metal having a higher melting temperature including W, Ti, and Mo, silicides thereof (WSi[0054]₂, TiSi₂and MoSi₂), polycide using these silicides, or the like. Furthermore, it is also possible to mount a motherboard or the like on theexternal lands15a,15b,15c, and15d.
• As for the[0055]external solder balls21a,21b,21c, and21d, solder materials having higher melting temperature than thefirst solder balls3a,3b,3c, and3dcan be used. As for theexternal solder balls21a,21b,21c, and21d, materials selected from a Sn—Ag alloy, Sn—Ag—Cu alloy, Sn—Pb (Sn=63 w % Pb=35 w %) alloy, Sn—Zn alloy can be used. Mixtures or compounds made from materials such as Au, Ag, Cu, Ni, Fe, Pd, Sn, Pb, Ag, Bi, Zn, In, Sb, Cu, Ge can be also used.
• (ASSEMBLING METHOD OF THE SECOND EMBODIMENT)[0056]
• Next, as shown in FIGS. 17 and 18, an assembling method of the[0057]packaging assembly102 according to the second embodiment of the present invention is described. Here, since the second assembling method before formingsecond solder balls4a,4b,4c, and4don thesemiconductor chip6 orfirst solder balls3a,3b,3c, and3don thesubstrate1 is substantially the same shown in FIGS.2˜8, detailed explanation is omitted.
• A photo resist film (not shown) is coated on the wiring layer[0058]15 (shown in FIG. 1) delineated on the second surface by use of photolithography technology. Thewiring layer15 is partially delineated with the photo resist film as an etching mask, andexternal lands15a,15b,15c, and . . .15dare formed. A protective film (not shown) which is made from SiO₂, SiN and the like can be delineated so as to be surround theexternal lands15a,15b,15c, and15d. Then, as shown in FIG. 17, theexternal solder balls21a,21b,21c, and21d containing such as Sn—Ag alloys are formed on theexternal lands15a,15b,15c, and15d, and heated around 200° C., reflow is performed. Heat from performing reflow is conveyed tofirst solder balls3a,3b,3c, and3d, andsecond solder balls4a,4b,4c, and4d. As a result,first solder balls3a,3b,3c, and3d, andsecond solder balls4a,4b,4c, and4dare melted to be formedinternal solder joints8a,8b,8c, and8d. Since theinternal solder joints8a,8b,8c, and8dare formed from a mixture offirst solder balls3a,3b,3c, and3d, andsecond solder balls4a,4b,4c, and4d, theinternal solder joints8a,8b,8c, and8dhave higher melting temperature thanfirst solder balls3a,3b,3c, and3d, and have lower melting temperature thansecond solder balls4a,4b,4c, and4d.
• As described above, the[0059]packaging assembly102 shown n FIG. 16 can be manufactured. According to thepackaging assembly102 of the second embodiment of the present invention, thefirst solder balls3a,3b,3cand3dmelt at a heat of about 150° C.and connect temporarily to thesecond solder balls4a,4b,4c, and4d. Therefore, when an organic synthetic resin is used for a material of thesubstrate1, gas is not released from thesubstrate1, and voids are not generated in theunderfill resin7. Moreover, since thesubstrate1 and thesemiconductor chip6 are connected at a low temperature, thermal stresses applied to the low-k film12 disposed on thebonding pads5a,5b,5c, and5dcan be minimized. Furthermore, since complete connection is accomplished by forminginternal solder joints8a,8b,8c, and8dto be heated by reflowing process, the reliability of thefirst level assembly102 can be improved. Accordingly,internal solder joints8a,8b,8c, and8ddo not melt even if in a test of a continuous at high temperature of 150° C, or a heat cycle test which repeatedly varies an atmosphere from 120° C. to −55° C.
• (MODIFICATION OF THE SECOND EMBODIMENT)[0060]
• The[0061]packaging assembly103 according to a second embodiment of the present invention encompasses, as shown in FIG. 19, a plurality of secondinternal solder joints28a,28b,28c, and28dare disposed between second chip-site lands22a,22b,22c, and22d, andsecond bonding pads25a,25b,2c, and25d. A plurality ofexternal lands15a,15b,15c, . . . ,15jare disposed on the first surface opposite to the second chip-site lands22a,22b,22c, and22d. A plurality ofexternal solder ball21a,21b,21c, . . . ,21jare connected on theexternal lands15a,15b,15c, . . . ,15j, respectively. Others are the same as apackaging assembly101 shown in FIG. 13, explanations are omitted.
• The second[0062]internal solder joints28a,28b,28c, and28dare electrodes mixed withthird solder balls23a,23b,23c, and23d, andfourth solder balls24a,24b,24c, and24das shown in FIG. 20. The secondinternal solder joints28a,28b,28c, and28dhave higher melting temperature thanthird solder balls23a,23b,23c, and23d, and have lower melting temperature thanfourth solder balls24a,24b,24c, and24d. As for the secondinternal solder joints28a,28b,28c, and28d, at least two kinds of solder materials having higher melting temperature and lower melting temperature can be used. For solder materials of lower melting temperature, Sn—Bi alloys, Sn—Bi—Ag alloys, Sn—Zn alloys, Sn—Zn—Bi alloys, An—Bi—In alloys, Bi—In alloy, Sn—In alloys, In—Ag alloys, Sn—Pb (Sn=5 w %, Pb=95 w %) can be used. Materials of higher melting temperature, for example, Sn—Ag alloys, Sn—Ag—Cu alloys, Sn—Pb (Sn-=63 w %, Pb=37 w %) alloys, and Sn—Zn alloys can be used.
• (ASSEMBLING METHOD)[0063]
• Next, as shown in FIGS. 19 and 20, an assembling method of the[0064]packaging assembly103 according to the modification of the second embodiment of the present invention is described.
• A photo resist film (not shown) is delineated on the[0065]wiring layer15 formed on the second surface by use of photolithography technology. Thewiring layer15 is stripped with the photo resist film as an etching mask,external lands15a,15b,15c, . . .15jare formed. A protective film which is made from SiO₂, SiN and the like can be formed so as to be surround theexternal lands15a,15b,15c, and . . .15j. Then, as shown in FIG. 20, the outerconnection solder balls21a,21b,21c. . .21jcontaining such as Sn—Ag alloys are formed on theexternal lands15a,15b,15c, . . . ,15jand heated around 200° C., reflow is performed. Heat from performing reflow is conveyed to first andthird solder balls3a,3b,3c,d3d,23a,23b,23c, and23d, and second andfourth solder balls4a,4b,24c,24d, and24a,24b,24c, and24d. As a result, first andthird solder balls3a,3b,3c,3d,23a,23b,23c, and23d, and second andfourth solder balls4a,4b,4c,4d,24a,24b,24c, and24dare melted to be formedinternal solder joints8a,8b,8c, and8dand secondinternal solder joints28a,28b,28c, and28d.
• As described above, the[0066]packaging assembly103 as shown in FIG. 19 can be assembled. According to thepackaging assembly103 of the modification of second embodiment of the present invention,third solder balls23a,23b,23c, and23d, andfourth solder balls24a,24b,24c, and24dare connected temporarily after being connected withfirst solder balls3a,3b,3c, and3dandsecond solder balls4a,4b,4c, and4d. Therefore, when thesecond semiconductor chip26 is mounted next to thefirst semiconductor chip6, shifting of the position ofchips6 and26 caused by the flow ofunderfill resin7 can be prevented. Moreover, two or more semiconductor chips can be mounted adjacently. Since thepackaging assembly103 shown in FIG. 19 can be mounted at a low temperature of 150° C., gas is not released from thesubstrate1, and not generated in theunderfill resin7 even if an organic synthetic resin is used for a material of thesubstrate1. Furthermore, since heat expansion of thesubstrate1 andsemiconductor chips6 and26, and heat contraction of theunderfill resin7 can be suppressed at lower level, strong thermal stresses are not be incurred tobonding pads5a,5b,5cand5d, andsecond bonding pads25a,25b,2c, and25d. Therefore, thermal stresses applied to the low-k film12 and second low-k film32 which are disposed close to thebonding pads5a,5b,5cand5d, andsecond bonding pads25a,25b,2c, and25d, can be minimized and the breakage of the films can be prevented. Furthermore, since complete connection is accomplished by forminginternal solder joints8a,8b,8c, and8d, and secondinternal solder joints28a,28b,28c, and28d, to be heated by reflowing process, the reliability of thefirst level assembly102 can be improved. Accordingly, first and secondinternal solder joints8a,8b,8c,8d,28a,28b,28c, and28ddo not melt even if in a test of a continuous at high temperature of 150° C., or a heat cycle test which repeatedly varies an atmosphere from 120° C.to −55° C.
• (OTHER EMBODIMENTS)[0067]
• Various modifications will become possible for those skilled in the art upon receiving the teachings of the present disclosure without departing from the scope thereof.[0068]
• As for the[0069]packaging assembly100,101,102, and103 shown in FIGS.1˜19, materials of thesolder balls3a˜3d,4a˜4d,23a˜23d,24a˜24dcan be partially changed. When thesolder balls3a˜3d,4a˜4d,23a˜23d,24a˜24dare heated by performing reflowing, thesemiconductor chips6 and26 andsubstrate1 are elongated respectively. The thermal stresses caused by heat expansion (elongation) occurring at the central parts of thesemiconductor chips6 and26 or thesubstrate1 are weak. However, thermal stresses occurring at the edges of thesemiconductor chips6 and26 and thesubstrate1 are strong. Therefore, lead-free solders having higher melting temperature can be applied to thesecond solder joints4band4c. The lead-free solders having lower melting temperatures can be applied to thesecond solder joints4aand4d. Accordingly, it is possible to prevent the breakage of materials that have weak mechanical strengths formed in the circuit elements of thesemiconductor chip6, particularly, the breakage of the low-k film12 disposed directly on thesecond solder joints4a,4b,4c, and4d.

Claims (22)

What is claimed is:

1. A packaging assembly comprising:

a substrate defined by a first surface and a second surface opposing to the first surface;

a plurality of chip-site lands disposed on the first surface;

a plurality of first solder balls connected to the chip-site lands;

a plurality of second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls;

a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and

an underfill resin disposed around the first and second solder balls.

2. The packaging assembly ofclaim 1, wherein the first solder balls include at least one material selected from the group consisting of Sn—Bi, Sn—Bi—Ag, Sn—Zn, Sn—Zn—Bi, Sn—Bi—In, Bi—In, Sn—In, Bi—Pd, In—Ag, and Sn—Pb.

3. The packaging assembly of claim l,wherein the second solder balls include at least one material selected from the group consisting of Sn—Ag, An—Ag—Cu, Sn—Pb, and Sn—Zn.

4. The packaging assembly ofclaim 1, wherein a protective film containing an organic synthetic resin is disposed on the surface of the semiconductor chip.

5. The packaging assembly ofclaim 1, wherein a low dielectric constant film is stacked on the surface of the semiconductor chip.

6. The packaging assembly ofclaim 5, wherein an effective dielectric constant of the low dielectric constant film is equal to or less than 3.5.

7. The packaging assembly ofclaim 1, further comprising:

a circuit element merged in the semiconductor chip; and

a multilevel-interconnection disposed on the surface of the semiconductor chip having:

a plurality of insulating films; and

a plurality of metallic interconnections alternatively stacked with the insulating film, wherein the coherence strength of the stacked structure to the semiconductor chip is equal to or less than 15 J/m².

8. The packaging assembly ofclaim 7, wherein the insulating films are made from low dielectric constant films.

9. The packaging assembly ofclaim 1, further comprising:

a plurality of second chip-site lands disposed on the first surface;

a plurality of third solder balls connected to the second chip-site lands;

a plurality of fourth solder balls connected to the third solder balls including solder materials having higher melting temperatures than the third solder balls;

a second semiconductor chip having a plurality of a second bonding pads connected to the fourth solder balls on a surface of the second semiconductor chip; and

an underfill resin disposed around the third and fourth solder balls.

10. The packaging assembly ofclaim 9, wherein the third solder balls include at least one material selected from a group consisting of Sn—Bi, Sn—Bi—Ag, Sn—Zn, Sn—Zn—Bi, Sn—Bi—In, Bi—In, Sn—In, Bi—Pd, In—Ag, and Sn—Pb.

11. The packaging assembly ofclaim 9,wherein the fourth solder balls include at least one material selected from a group consisting of Sn—Ag, An—Ag—Cu, Sn—Pb, and Sn—Zn.

12. The packaging assembly ofclaim 9, wherein a low dielectric constant film is stacked on the surface of the second semiconductor chip.

13. The packaging assembly ofclaim 12, wherein an effective dielectric constant of the low dielectric constant film is equal to or less than 3.5.

14. The packaging assembly ofclaim 9, further comprising:

a second circuit element merged in the second semiconductor chip; and

a second multilevel-interconnection disposed on the second semiconductor chip having:

a plurality of insulating films; and

a plurality of metallic interconnections alternatively stacked with the insulating film, wherein the coherence strength of the second multilevel-interconnection to the second semiconductor chip is equal to or less than 15 J/m².

15. The packaging assembly ofclaim 14, wherein the insulating films are made from low dielectric constant films.

16. A method of assembling a packaging assembly comprising:

preparing a substrate having a plurality of chip-site lands disposed on the first surface of a substrate;

disposing a plurality of first solder balls on the chip-site lands;

applying an under fill resin around the chip-site lands and the first solder balls;

disposing a plurality of second solder balls on corresponding bonding pads disposed on a semiconductor chip;

aligning the first solder balls with corresponding second solder balls;

connecting the first and second solder balls by melting the first solder balls; and

hardening the underfill resin.

17. The method ofclaim 16, wherein the connecting the first and second solder balls includes disposing the substrate on an assembling stage before melting the first solder balls.

18. The method ofclaim 16, wherein the preparing the substrate prepares the substrate having the chip-site lands and a plurality of second chip-site lands, the method further comprising:

disposing a plurality of third solder balls on the second chip-site lands;

applying a second underfill resin around the second chip-site lands ant the third solder balls;

disposing a plurality of fourth solder balls on corresponding bonding pads disposed on a second semiconductor chip;

aligning the third solder balls with corresponding fourth solder balls; and

hardening the second underfill resin.

19. The method ofclaim 16, further comprising:

disposing a plurality of external solder balls on corresponding external lands disposed on the second surface of the substrate after hardening the underfill resin; and

forming a plurality of internal solder joints from first and second solder balls by melting.

20. The method ofclaim 19, wherein the internal solder joints are formed at least one material selected from the group consisting of Sn—Bi, Sn—Bi—Ag, Sn—Zn, Sn—Zn—Bi, Sn—Bi—In, Bi—In, Sn—In, Bi—Pd, In—Ag, Sn—Ag, Sn—Ag—Cu, Sn—Pb, and Sn—Zn.

21. The method ofclaim 16, further comprising stacking a low dielectric constant film on the surface of the semiconductor chip, before disposing the second solder balls.

22. The method ofclaim 21, further comprising applying a protective film containing an organic synthetic resin on the surface of the semiconductor chip, after stacking the low dielectric constant film and before disposing the second solder balls.

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