US20040246039A1 - Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit - Google Patents

Abstract

A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. Several differently sized switch elements are used to selectively switch the capacitor from an internal capacitive node to ground. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect.

Description

BACKGROUND OF INVENTION
• 1. Field of the Inventionbk2E001200303263[0001]
• The present invention relates to a switched capacitor circuit, and more particularly, to a switched capacitor circuit used in a voltage controlled oscillator (VCO) that can minimize the clock feedthrough effect thereby preventing the VCO frequency drift phenomenon during calibration and the synthesizer phase locking period.[0002]
• 2. Description of the Prior Art[0003]
• A voltage controlled oscillator (VCO) is commonly used for frequency synthesis in wireless communication circuits. As Welland, et al. state in U.S. Pat. No. 6,226,506, wireless communication systems typically require frequency synthesis in both the receive path circuitry and the transmit path circuitry.[0004]
• FIG. 1 shows a VCO circuit according to the prior art. An LC type VCO[0005]10 used in a frequency synthesizer contains aresonator, the basic resonant structure includes aninductor12 connected between a first oscillator node OSC_P and a second oscillator node OSC_N. Connected in parallel with theinductor12 is a continuouslyvariable capacitor14 and a plurality of discretelyvariable capacitors16. The continuouslyvariable capacitor14 is used for fine-tuning a desired capacitance while the plurality of discretelyvariable capacitors16 is used for coarse tuning. The resistive loss of the parallel combination of inductor and capacitors is compensated by anegative resistance generator18 to sustain the oscillation.
• Each discretely variable capacitor in the plurality of discretely[0006]variable capacitors16 is made up of a switchedcapacitor circuit20 and each switched capacitor circuit is controlled by anindependent control signal22.
• Based on this[0007]control signal22 the switchedcapacitor circuit20 can selectively connect or disconnect acapacitor24 to the resonator of theVCO10. Different on/off combinations of switched capacitor arrays results in a wider capacitance range of the LC type resonator and hence awider VCO10 oscillation frequency coverage.
• FIG. 2 shows a switched[0008]capacitor circuit20aaccording to the prior art. Acapacitor30 is connected between the first oscillator node OSC_P and a node A. Aswitch element32 selectively connects node A to ground, and theswitch element32 is controlled by a control signal SW. When theswitch element32 is turned on, the capacitance associated with thecapacitor30 is added to the overall capacitance in theVCO10 resonator. When theswitch element32 is turned off, the capacitance looking into the first oscillator node OSC_P is the series combination of thecapacitor30 and the off state capacitance associated with theswitch element32.
• FIG. 3 shows a differential type switched[0009]capacitor circuit20baccording to the prior art. Differential implementations have much greater common-mode noise rejection and are widely used in high-speed integrated circuit environments. In the differential switchedcapacitor circuit20b, apositive side capacitor40 is connected between the first oscillator node OSC_P and a node A. A positiveside switch element42 selectively connects node A to ground. Anegative side capacitor44 is connected between the second oscillator node OSC_N and a node B. A negativeside switch element46 selectively connects node B to ground. There is also acenter switch element48 used to lower the overall turn-on switch resistance connected between node A and node B. All threeswitch elements42,46,48 are controlled by the same control signal SW. When theswitch elements42,46,48 are turned on, the capacitance associated with the series combination of the positive andnegative side capacitors40,44 is added to the overall capacitance in theVCO10. When theswitch elements42,46,48 are turned off, the differential input capacitance is the series combination of the positive andnegative side capacitors40,44 and other switch parasitic capacitance. The overall input capacitance when allswitch elements42,46,48 are turned off is lower than that when allswitch elements42,46,48 are turned on. Without thecenter switch element48, the switchedcapacitor circuit20bis itself another embodiment of the differential type switch capacitor circuit according to the prior art.
• Regardless of whether the single ended implementation shown in FIG. 2 or the differential implementation shown in FIG. 3 is used, when the switched[0010]capacitor circuit20aor20bis turned off, a momentary voltage step change occurs at node A (and in the case of the differential implementation shown in FIG. 3 also at node B). The momentary voltage step causes an undesired change in the overall capacitance, and ultimately, an undesired change in theVCO10 frequency. This momentary voltage step change in FIG. 2 and FIG. 3, by using NMOS switches, is a voltage drop when theswitch elements32,42,46,48 are turned off.
• Using the single ended case shown in FIG. 2 as an example, when the[0011]switch element32 is turned off, charge carriers are injected to the junction capacitance connected between the first terminal and the second terminal of theswitch element32. The injection produces an undesired voltage step change across the capacitive impedance and appears as a voltage drop at node A. This effect is known as clock feedthrough effect and appears as a feedthrough of the control signal SW from the control terminal of theswitch element32 to the first and second terminals of theswitch element32. When theswitch element32 is turned on, node A is connected to ground so the feedthrough of the control signal SW is of no consequence. However, when theswitch element32 is turned off, the feedthrough of the control signal SW causes a voltage step, in the form a voltage drop to appear at node A. Because of the dropped voltage at node A, the diode formed by the N³⁰diffusion ofswitch element32 and the P type substrate in the off state will be slightly forward biased. The voltage level at node A will spike low and then recover to ground potential as the forward biased junction diode formed by theswitch element32 in the off state allows current to flow. The voltage drop and recovery at node A changes the load capacitance of theVCO10 resonator and causes an undesired momentarily drift in theVCO10 frequency.
• When the differential switched[0012]capacitor circuit20bshown in FIG. 3 switches off, it suffers from the same clock feedthrough effect problem at node A and at node B. The positive side node A has an undesired voltage step change caused by the clock feedthrough effect of both the positiveside switch element42 and the clock feedthrough effect of thecenter switch element48. Similarly, the negative side node B has an undesired voltage step caused by the clock feedthrough effect of both the negativeside switch element46 and the clock feedthrough effect of thecenter switch element48. The voltage step change and recovery at node A and node B changes the capacitance of theVCO10 resonator and causes an undesired momentary drift in theVCO10 frequency.
SUMMARY OF INVENTION
• It is therefore a primary objective of the present invention to provide a switched capacitor circuit capable of minimizing the clock feedthrough effect, to solve the above-mentioned problem.[0013]
• According to the present invention, a switched capacitor circuit capable of minimizing clock feedthrough effect. The switched capacitor circuit comprising a switch element having a first terminal connected to a capacitor, a second terminal connected to ground, and a control terminal; and a low-pass filter having an input terminal connected to a control signal and an output terminal connected to the control terminal of the switch element, wherein the low-pass filter is for making the switch element gradually switch off.[0014]
• According to the present invention, a switched capacitor circuit capable of minimizing clock feedthrough effect, comprising a plurality of differently sized switch elements for selectively connecting a capacitor to a node depending upon a control signal applied to a control terminal of each of the switch elements. A sequence controller having a plurality of control signal outputs for switching off the switch elements in the plurality of differently sized pull down switch elements in sequence based on decreasing order of switch size. The switched capacitor circuit further comprising a means for making the smallest switch elements gradually switch off.[0015]
• According to the present invention, a method for minimizing clock feedthrough effect when switching a switched capacitor circuit. The method comprises providing a plurality of differently sized switch elements that selectively connect a capacitor to a node depending upon a control signal applied to a control terminal of each of the switch elements. When switching the switched capacitor circuit to an off state, sequencing the control signals such that the switch elements are switched off in decreasing order based on size, whereby the largest switch element is switched off first and the smallest switch element is switched off last. The method further comprising when switching the switched capacitor circuit to an off state, providing a means for making the smallest switch element gradually switch off.[0016]
• It is a further advantage of the present invention that the switched capacitor circuit is gradually switched off to minimize the clock feedthrough effect and prevent an undesired drift in the[0017]VCO10 frequency. In the prior art, the switched capacitor circuit is instantly switched from an on state to an off state. The clock feedthrough effect in the prior art implementations causes an undesired voltage step change to slightly forward bias the junction diode formed by the switch element in the off state until the voltage potential has returned to ground.
• These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.[0018]
BRIEF DESCRIPTION OF DRAWINGS
• FIG. 1 is a schematic diagram of a typical Voltage Controlled Oscillator (VCO) circuit used in a frequency synthesizer according to the prior art.[0019]
• FIG. 2 shows a switched capacitor circuit used in the VCO of FIG. 1 according to the prior art.[0020]
• FIG. 3 shows a differential type switched capacitor circuit used in the VCO of FIG. 1 according to the prior art.[0021]
• FIG. 4 shows a switched capacitor circuit according to the first embodiment of the present invention.[0022]
• FIG. 5 shows a time domain plot of the control signals for the switched capacitor circuit of FIG. 4[0023]
• FIG. 6 shows a differential switched capacitor circuit according to the second embodiment of the present invention.[0024]
• FIG. 7 shows a time domain plot of the control signals for the differential switched capacitor circuit of FIG. 6.[0025]
• FIG. 8 shows an example switched capacitor circuit according to the third embodiment of the present invention.[0026]
• FIG. 9 shows a time domain plot of the present invention control signals for switching off the switched capacitor circuit of FIG. 8[0027]
• FIG. 10 shows a generalized switched capacitor circuit of FIG. 8 with a low-pass filter added to the control terminal of the smallest switch element.[0028]
• FIG. 11 shows a differential switched capacitor circuit according to the fourth embodiment of the present invention.[0029]
• FIG. 12 shows a time domain plot of the present invention control signals for switching off the differential switched capacitor circuit of FIG. 11.[0030]
• FIG. 13 shows a generalized differential switched capacitor circuit of FIG. 11 with a low-pass filter added to the control terminal of the smallest pull down switch element at the positive side and its corresponding pull down switch element at the negative side.[0031]
• FIG. 14 shows a method flowchart for minimizing clock feedthrough effect when switching off a switched capacitor circuit according to the present invention.[0032]
• FIG. 15 shows a method flowchart for minimizing clock feedthrough effect when switching off a differential switched capacitor circuit according to the present invention.[0033]
DETAILED DESCRIPTION
• FIG. 4 shows a switched[0034]capacitor circuit20caccording to the first embodiment of the present invention. In the first embodiment, the switchedcapacitor circuit20ccomprises acapacitor50, aswitch element52, and a low-pass filter54. Thecapacitor50 is connected between the first oscillator node OSC_P and a node A. Depending on the control signal SW, theswitch element52 selectively connects the node A to ground. When theswitch element52 is turned on, the capacitance associated with thecapacitor50 is added to the overall capacitance in theVCO10. When theswitch element52 is turned off, the capacitance looking into the first oscillator node OSC_P is the series combination of thecapacitor50 and the off state capacitance associated with theswitch element32. A low-pass filter54 is connected to a control terminal of theswitch element52 for making theswitch element52 gradually switch off.
• FIG. 5 is a time domain plot of the control signal SW before the low-[0035]pass filter54 and a signal SW_FILTER after the low-pass filter54. At time t₁the control signal SW changes to a logic low. The low-pass filter54 causes the signal SW_FILTER at the control terminal of theswitch element52 to gradually change from a logic high to a logic low and minimizes the voltage step change seen at node A. Because theswitch element52 is gradually switched off, node A is gradually disconnected from ground. As theswitch element52 is gradually switched off, during a period of delay time there exists a conduction path of the switch element, even with an increasing resistance, to ground to minimize the clock feedthrough effect. In contrast to the prior art, the present invention does not forward bias the diode formed by theswitch element52 in the off state. The clock feedthrough effect at each moment in time is reduced.
• FIG. 6 shows a differential switched[0036]capacitor circuit20daccording to the second embodiment of the present invention. Apositive side capacitor60 is connected between the first oscillator node OSC_P and a node A. A positiveside switch element62 selectively connects node A to ground. Anegative side capacitor64 is connected between the second oscillator node OSC_N and a node B. A negativeside switch element66 selectively connects node B to ground. Acenter switch element68 is used to lower the overall turn-on resistance and is connected between node A and node B. A low-pass filter70 is connected to the control terminals of the positiveside switch element62 and the negativeside switch element66 for making the positive and negativeside switch elements62,66 gradually switch off. Without thecenter switch element68, the switchedcapacitor circuit20dis itself another embodiment of the differential type switched capacitor circuit.
• FIG. 7 is a time domain plot of the control signal SW before the low-pass filter and the signal SW_FILTER after the low-pass filter. The[0037]center switch element68 is directly controlled by the control signal SW while the positive and negativeside switch elements62,66 are controlled by the output of the low-pass filter70, signal SW_FITLER. At time t₁the control signal SW changes from a logic high to a logic low and thecenter switch element68 immediately changes to an off state. Because the positive and negativeside switch elements62,66 gradually switch off, during a period of delay time, node A and node B are still connected to ground and the clock feedthrough effect due to thecenter switch element68 is minimized by the conduction to ground path. As in the single ended embodiment of FIG. 4, as the positive and negativeside switch elements62,66 gradually switch off, the clock feedthrough effect produced at node A and B at each moment of time is reduced.
• FIG. 8 shows an example of the switched[0038]capacitor circuit20eaccording to the third embodiment of the present invention. In the third embodiment, the switchedcapacitor circuit20ecomprises acapacitor80, asequence controller88, and a plurality of differentlysized switch elements82. FIG. 8 shows twoswitch elements84,86 but this is meant as an example only and more switch elements could be used. In this example,switch element84 is larger thanswitch element86. Thecapacitor80 is connected between the first oscillator node OSC_P and a node A. Each of theswitch elements84,86 in the plurality of differentlysized switch elements82 selectively connects node A to ground, and eachswitch element84,86 in the plurality of differentlysized switch elements82 has its own control signal. In this example thelarger switch element84 has a control signal SW1 and thesmaller switch element86 has a control signal SW2.
• FIG. 9 shows a time domain plot of the control signals of the present invention method for switching off the switched[0039]capacitor circuit20eas shown in FIG. 8. In order to gradually switch the switchedcapacitor circuit20eto an off state, thesequence controller88 ensures that theswitch elements84,86 are switched off in decreasing order based on switch size. Becauseswitch element84 is larger thanswitch element86,switch element84 is first switched off at time t₁. At time t₂, which is after t₁,switch element86 is switched off. Since the amount of voltage change at node A due to the clock feedthrough effect depends on the parasitic capacitance ratio of control terminal to first terminal and first terminal to second terminal capacitance, the smaller the control terminal to first terminal capacitance the smaller the voltage change due to the feedthrough of the control signal switching from high to low. The present invention takes advantage of this fact because the larger switch elements with larger voltage drops due to turning off the larger switch elements are switched off first. Until the last switch element is switched off, node A is connected to ground and clock feedthrough effect is not a concern. If the last switch element to be switched off is made sufficiently small, the clock feedthrough effect after the last switch is switched off can be made negligible.
• FIG. 10 shows a generalized third embodiment switched[0040]capacitor circuit20fschematic. Acapacitor90 is connected between the first oscillator node OSC_P and a node A. A plurality of differentlysized switch elements92 selectively connects node A to ground, and each switch element in the plurality of differentlysized switch elements92 has its own control signal. A largest switch element Switch[1] has a control signal SW[1] and a size of W [1]. A smaller switch element Switch[2] has a control signal SW[2] and a size of W[2], where W[2] is smaller than W[1]. A second smallest switch element Switch[N-1] has a control signal SW[N-1] and a size of W[N-1], where W[N-1] is smaller than W[N-2]. A smallest switch element Switch[N] has a control signal SW[N] and a size of W[N], where W[N] is smaller than W[N-1]. Asequence controller96 provides the control signals SW[1] to SW[N] and ensures that the switch elements are switched off in decreasing order based on switch size. As shown in FIG. 10, a low-pass filter94 can be added, or not added, to the control terminal the smallest switch element Switch[N]. Similar to the circuit shown in FIG. 4, the low-pass filter94 will gradually shut off the last switch element Switch[N] minimizing the clock feedthrough effect of the switchedcapacitor circuit20f.
• FIG. 11 shows an example of the differential switched[0041]capacitor circuit20gaccording to the fourth embodiment of the present invention. The differential switchedcapacitor circuit20gcomprises apositive side capacitor100, anegative side capacitor102, acenter switch element104, asequence controller116, a plurality of differently sized positiveside switch elements106, and for each switch element in the plurality of the differently sized positiveside switch elements106, a corresponding negative side switch element having substantially the same size as the positive side switch element. FIG. 11 shows two positiveside switch elements108,110 and two corresponding negativeside switch elements112,114 but this is meant as an example only and more switch elements could be used. In this example, switchelements108 and112 are of substantially the same size and are larger thanswitch elements110 and114, which are also of substantially the same size. Thepositive side capacitor100 is connected between the first oscillator node OSC_P and a node A. Each of theswitch elements108,110 in the plurality of differently sized positiveside switch elements106 selectively connects node A to ground and each switch element in the plurality of differently sized positiveside switch elements106 has its own control signal. Thenegative side capacitor102 is connected between the second oscillator node OSC_N and a node B. Node B is selectively connected to ground by each of the corresponding negativeside switch elements112,114 depending on the control signal of the positiveside switch element108,110 respectively. In this example, thelarger switch elements108,112 have a control signal SW1 and thesmaller switch elements110,114 have a control signal SW2. Without thecenter switch element104, the switchedcapacitor circuit20gis itself another embodiment of the differential type switched capacitor circuit.
• FIG. 12 shows a time domain plot of the control signals of the present invention method for switching off the forth embodiment of the switched[0042]capacitor circuit20gas shown in FIG. 11. In order to gradually switch the switchedcapacitor circuit20gto an off state, thesequence controller116 ensures that thecenter switch element104 is first switched off (at time t₁) and then the remaining switch elements are switched off in pairs in decreasing order based on switch size. At t₂, which is after t₁, switchelements108 and112 are switched off. At t₃, which is after t₂, switchelements110 and114 are switched off. Because the positiveside switch element108 and its corresponding negativeside switch element112 are larger in size than the positiveside switch element110 and its corresponding negativeside switch element114, the positiveside switch element108 and the negativeside switch element112 are switched off next. Until the last positive and negativeside switch elements110,114 are switched off, node A and node B are connected to ground and clock feedthrough effect is not a concern. If the last switch element pair to be switched off is made sufficiently small, the clock feedthrough effect of thedifferential switch circuit20gcan be made negligible.
• FIG. 13 shows a generalized fourth embodiment differential switched[0043]capacitor circuit20h. Apositive side capacitor120 is connected between the first oscillator node OSC_P and a node A. A plurality of differently sized positiveside switch elements122 selectively connects node A to ground and each switch element in the plurality of differently sized positiveside switch elements122 has its own control signal. A largest positive side switch element P_Switch[1] has a control signal SW[1] and a size of W[1]. A smaller positive side switch element P_Switch[2] has a control signal SW[2] and a size of W[2], where W[2] is smaller than W[1]. A second smallest positive side switch element P_Switch[N-1] has a control signal SW[N-1] and a size of W[N-1], where W[N-1] is smaller than W[N-2]. A smallest positive side switch element P_Switch[N] has a control signal SW[N] and a size of W [N], where W[N] is smaller than W[N-1]. For each switch element in the plurality of the differently sized positiveside switch elements122, a corresponding negative side switch element having substantially the same size as the positive side switch element selectively connects a node B to ground depending on the same control signal as the positive side switch element. A largest negative side switch element N_Switch[1] has the control signal SW[1] and the size of W[1]. A smaller negative side switch element N_Switch[2] has the control signal SW[2] and the size of W[2]. A second smallest negative side switch element N_Switch[N-1] has the control signal SW[N-1] and the size of W[N-1]. A smallest negative side switch element N_Switch[N] has the control signal SW[N] and a size of W[N]. Anegative side capacitor124 is connected between node B and the second oscillator node OSC_N. Acenter switch element126 selectively connects node A to node B depending on a control signal SW_CENTER. A low-pass filter128 can be connected, or not connected, to the control terminals for the smallest switch element pair. Similar to the circuit in FIG. 6, the low-pass filter128 will gradually shut off the last switch element pair P_Switch[N], N_Switch[N] minimizing the clock feedthrough effect of the differential switchedcapacitor circuit20h. Asequence controller130 provides the control signals SW_CENTER and SW[1] to SW[N] and ensures that the center switch element is first switched off and then the remaining switch elements are switched off in pairs in decreasing order based on switch size. Without thecenter switch element126, the switched capacitor circuit30his itself another embodiment of the differential type switched capacitor circuit.
• FIG. 14 shows a[0044]method flowchart198 for minimizing clock feedthrough effect when switching off a switchedcapacitor circuit20 according to the present invention. Themethod flowchart198 contains the following steps:
• Step[0045]200: Provide a plurality of differently sized switch elements: Each switch element in the plurality of differently sized switch elements is for selectively connecting a first terminal of a capacitor to a node depending upon a control signal applied to a control terminal of the switch element.
• Step[0046]202: Provide a low-pass filter to gradually switch off the smallest switch element: The low-pass filter is connected to the control terminal of the smallest switch element.
• Step[0047]204: When switching off, sequence the control signals such that the switch elements are switched off in decreasing order based on size: The largest switch element is switched off first, the next largest is switched off next, and so on until the smallest switch element is switched off last. Until the smallest switch element is switched off, the first terminal of the capacitor is connected to the node and the clock feedthrough effect is not a concern. The low-pass filter will gradually switch off the last switch element minimizing the clock feedthrough effect of the smallest switch element and the switchedcapacitor circuit20 as a whole.
• It should be noted that in the[0048]method flowchart198 shown in FIG. 14 the node is preferably connected to ground, however, the method according to the present invention is not limited to this configuration.
• FIG. 15 shows a[0049]method flowchart208 for minimizing clock feedthrough effect when switching off a differential switchedcapacitor circuit20 according to the present invention. Themethod flowchart208 contains the following steps:
• Step[0050]210: Provide a plurality of differently sized positive side switch elements: Each positive side switch element in the plurality of differently sized positive side switch elements is for selectively connecting a first terminal of a positive side capacitor to a first node depending upon a control signal applied to a control terminal of each of the switch elements.
• Step[0051]212: For each positive side switch element, provide a corresponding same size negative side switch element: Each corresponding same size negative side switch element is for selectively connecting a first terminal of a negative side capacitor to a second node depending upon the control signal applied to the control terminal of the positive side switch element.
• Step[0052]214: Provide a low-pass filter to gradually switch off the smallest positive and negative side switch elements: The low-pass filter is connected to the control terminal of the smallest positive and negative side switch element.
• Step[0053]216: Provide a center switch element: The center switch element selectively connects the positive side capacitor to the negative side capacitor depending on a control signal applied to a control terminal of the center switch element.
• Step[0054]218: When switching off, sequence the control signals such that the center switch element is first switched off and then the other switch elements are switched off in pairs in decreasing order based on switch size, whereby the largest positive side switch element and its corresponding negative side switch element are switched off first, the next largest switch element pair is switch off next, and the smallest switch element pair is switched off last. Until the smallest switch element pair is switched off, the first terminal of the positive side capacitor and the first terminal of the negative side capacitor are connected to the first node and the second respectively so that the clock feedthrough effect is not a concern. The low-pass filter gradually switches off the last switch element minimizing the clock feedthrough effect of the smallest switch element and the switchedcapacitor circuit20 as a whole.
• Similarly, it should be noted that in the[0055]method flowchart208 shown in FIG. 15 the first node and the second node are preferably connected to ground, however,the method according to the present invention is not limited to this configuration.
• In contrast to the prior art, the present invention gradually switches off the switched capacitor circuit so that the clock feedthrough effect is minimized and accordingly the undesired frequency drift of the[0056]VCO10 frequency is properly reduced. When switching off, the prior art implementations suffer from clock feedthrough effect that causes a voltage step change to occur at an internal capacitive node of theVCO10. The voltage step change causes the junction diode formed by a switch element in the off state to be slightly forward biased until the dropped voltage returns to the ground potential.
• According to the present invention, the voltage step change at the internal capacitive node is minimized. When switching off, the present invention can minimize the momentary change of the capacitance value of the[0057]VCO10 resonator and the momentary drift in theVCO10 frequency.
• Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims.[0058]

Claims (6)

1. A switched capacitor circuit capable of minimizing clock feedthrough effect, comprising:

a positive side switch element for selectively connecting a positive side first node to a positive side second node depending upon a signal applied to a first control terminal of the positive side switch element, wherein the positive side first node is connected to a positive side capacitor; and

a low-pass filter having an input terminal connected to a control signal and an output terminal connected to the first control terminal of the positive side switch element for making the positive side switch element gradually switch of, wherein the control signal is substantially a two-level signal with a first level for switching off the switched capacitor circuit and a second level for switching on the switched capacitor circuit.

2. The switched capacitor circuit ofclaim 1, wherein the positive side second node is ground and the positive side switch element is an NMOS transistor.

3. The switched capacitor circuit ofclaim 1, further comprising:

a negative side switch element of substantially the same size as the positive side switch element for selectively connecting a negative side first node to a negative side second node depending upon the control signal applied to the first control terminal of the positive side switch element, wherein the negative side first node is connected to a negative side capacitor.

4. The switched capacitor circuit ofclaim 3, further comprising:

a center switch element having a first terminal connected to the positive side first node, a second terminal connected to the negative side first node, and a third control terminal connected to the control signal.

5. The switched capacitor circuit ofclaim 4, wherein the positive side second node is ground, the negative side second node is ground, and the positive side switch element, the negative side switch element, and the center switch element are NMOS transistors.

6-24. (cancelled)

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