US20040235289A1 - Semiconductor integrated circuit device and method for making the same - Google Patents
Semiconductor integrated circuit device and method for making the sameDownload PDFInfo
- Publication number
- US20040235289A1 US20040235289A1US10/872,508US87250804AUS2004235289A1US 20040235289 A1US20040235289 A1US 20040235289A1US 87250804 AUS87250804 AUS 87250804AUS 2004235289 A1US2004235289 A1US 2004235289A1
- Authority
- US
- United States
- Prior art keywords
- film
- titanium
- tin
- interconnection
- titanium nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
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Definitions
- This inventionrelates to a semiconductor integrated circuit device and also to a method for making the device. More particularly, the invention relates to a technique which is effective when applied to an interconnection structure and an interconnecting process of LSI having multilayer interconnections.
- connection holesIn recent years, integration of LSI has been in progress. This leads to increased aspect ratios (i.e., the depth of a connection hole formed on an inter-layer insulating film between a given Al interconnection and a low conductor layer, semiconductor region or a lower Al interconnection.
- aspect ratiosi.e., the depth of a connection hole formed on an inter-layer insulating film between a given Al interconnection and a low conductor layer, semiconductor region or a lower Al interconnection.
- tungsten plug techniqueIn order to prevent the breakage of the Al interconnections in the inside of the connection holes, a so-called tungsten plug technique has been utilized wherein a W (tungsten) film is filled in the connection holes.
- a W filmis deposited, according to the CVD method, on the entire surface of an insulating film in which connection holes have been formed. Subsequently, the W film on the insulating film is etched back, thereby leaving the W film only in the connection holes.
- a F (fluorine) plasmais used for the etching back of the W film.
- a underlying layerwhich is constituted of stacked films including a Ti film and a TiN film, has been formed beneath the W film.
- the underlying film constituted of the Ti/TiN stacked filmsis very resistant to electromigration or stress migration, and has been employed for interconnection of LSI which is fabricated according to the design rule on the order of submicrons. Interconnections having such a stacked structure as of Ti/TiN/Al—Cu/TiN formed in this order and tungsten plug techniques for this are set out, for example, in LVSI Multi-level Conference Jun. 7-8, 1994, pp. 36-43.
- the semiconductor integrated circuit device to which the invention is directedis of the type which comprises three-layered metallic interconnections including a first layer made of a tungsten film, and second and third layers made of an aluminium alloy film, respectively.
- the interconnection for the first layeris constituted of a three-layered structure made of Ti/TiN/W formed in this order.
- a titanium (Ti) underlying film, a titanium nitride (TiN) underlying film and a titanium (Ti) underlying filmare provided beneath each of the second and third-layered aluminium alloy (Al—Si—Cu) layers.
- Ti/TiN cap filmsare provided on each of the second and third-layered aluminum alloy (Al—Si—Cu) layers.
- a six-layered structure of Ti/TiN/Ti/Al—Si—Cu/Ti/TiN as viewed from the bottomis established.
- a tungsten (W) filmis filled in connection holes connecting the first and second layers and the second and third layers therewith. Each tungsten film exists in the connection hole between the titanium nitride (TiN) underlying film and the titanium (Ti) underlying film formed on the TiN film.
- the process of filling the tungsten (W) film in the connection holesessentially requires removal of the W film from the insulating film through etching-back by use of a fluorine (F) plasma as set out hereinbefore.
- Ffluorine
- the thus left fluorinereacts with titanium to provide a solid compound. Hence, the compound is left on the underlying film.
- the uppermost interconnection layerpartly serves as a bonding pad.
- the padWhen a wire is bonded to the bonding pad, the pad may separate owing to the impact of the bonding. More particularly, it has been found that the underlying film on which the compound has been left separates from another underlying film formed thereon at the bonding pad portion.
- the process of filling the W film in the connection holesincludes the etching-back step wherein the W film is allowed to be left only in the connection holes. This requires over-etching in order to completely remove the W film from the surface of the insulating film. At the time, the W film in the connection holes is also etched out from the outer surface thereof. This leaves a step between the surface of the insulating film or the surface of the underlying film and the surface of the W film in each connection hole.
- the upper layer film formed on the Al interconnectionsuffers a coverage failure, thus Al being partially exposed from the upper layer film.
- the thus exposed Alreacts with F left at the time of the formation of the W film, thereby forming an insulating AlF 3 film. This is the reason why there arises the problem that the conduction failure or an increase in contact resistance between the Al interconnection and the upper Al interconnection takes place.
- the Al interconnectionis constituted of multi-layered interconnection (Ti/TiN/Ti/Al—Si—Cu/Ti/TiN).
- an uppermost interconnectionis used as a bonding pad.
- the uppermost interconnectionis constituted of this type of multi-layered interconnection and part of a passivation film covering the uppermost interconnection therewith is removed by etching to form a bonding pad, a compound formed by reaction between Al and Ti is deposited at the interface between the Al film and the upper film (Ti/TiN stacked film) formed on the Al film. This compound is so hard that the bonding force between the bonding pad and a wire lowers. It should be noted that the etching of the passivation film does not make it possible to fully remove the compound of Al and Ti.
- the Al interconnectionsare formed by depositing the Al composite film by sputtering and dry etching the deposited film. If the coverage of the Al film on deposition of the Al composite film lowers by the influence of the step formed in the underlying layer, the processing accuracy of the interconnection through dry etching unfavorably lowers. To avoid this, a so-called high temperature Al sputtering technique has been proposed. In the technique, a semiconductor substrate is maintained at high temperatures, and the Al film is deposited while re-flowing the Al film by application of heat from the substrate, thereby ensuring a good coverage of the Al.
- connection holes for an upper layerare located just above connection holes of an interlayer insulating film, respectively.
- a method for making a semiconductor integrated circuit devicewhich comprises the steps of:
- a semiconductor integrated circuit devicewhich comprises:
- a method for making a semiconductor integrated circuit devicecomprising forming an aluminium film on a main surface of a semiconductor substrate by sputtering, characterized in that a first aluminium film is formed on the semiconductor substrate which is kept at a relatively low temperature, and a second aluminium film is formed at a substrate temperature which is higher than the first-mentioned temperature
- a method for making a semiconductor integrated circuit devicewhich comprises the steps of:
- FIGS. 1 to 11 and 15 to 17are, respectively, a sectional view of an essential part of a semiconductor substrate which illustrates a method for making a semiconductor integrated circuit device according to one embodiment of the invention
- FIG. 12is an AES spectrum chart of the surface of a TiN film prior to sputter etching
- FIG. 13is a graph showing the relation between the content of F at the interface of Ti/TiN films and the thickness of a sputter etched titanium nitride film.
- FIG. 14is a graph showing the relation between the intensity of F ions at the interface of Ti/TiN films and the thickness of sputter-etched titanium nitride.
- FIGS. 1 to 17illustrate an embodiment of the invention applied to MOS-LSI having a three-layered interconnection structure initially, as shown in FIG. 1, a semiconductor substrate 1 made of p-type single crystal silicon is ion-implanted with a p-type impurity (boron) on the main surface thereof to form a p-type well 2 . Thereafter, a field oxide film 3 is formed on the main surface of the p-type well according to a selective oxidation (LOCOS) method.
- LOCselective oxidation
- a gate oxide 5is formed on the main surface of the p-type well 2 surrounded with the field oxide film 3 according to a thermal oxidation method, followed by ion implantation of a p-type impurity (boron) into the p-type well 2 , thereby creating a p-type channel stopper layer 4 in the p-type well 2 including the lower portion of the field oxide film 3 .
- a p-type impurityboron
- a polysilicon film and a silicon oxide film 9are successively deposited on the semiconductor substrate 1 according to a CVD method, followed by patterning of this two-layered film by drying etching through a photoresist mask to form gate electrodes 6 of MISFET made of the polysilicon film.
- the polysilicon forming each gate electrode 6is introduced with an n-type impurity (e.g. P) in order to reduce the resistance thereof.
- the gate electrodes 6may be constituted of a polyside film which is made of a refractory metal silicide film, such as WSix, MoSix, TiSix or TaSix, built on the top of the polysilicon film.
- n-type impuritye.g. P
- Pn-type impurity
- a silicon oxide filmis deposited over the semiconductor substrate 1 by a CVD method, followed by anisotropic etching of the silicon oxide film by a reactive ion etching (RIE) method to form side wall spacers 8 at side walls of the gate electrode 6 , respectively.
- RIEreactive ion etching
- an oxide film 10 and a BPSG film 11are successively formed over the semiconductor substrate 1 by a CVD method, followed by dry etching the BPSG film 11 and the silicon oxide film 10 through a photoresist mask, thereby forming a connection hole 12 arriving at one of the paired semiconductor regions 7 , 7 of the MISFET.
- an underlying filmcomprising a first underlying Ti film 13 (30 nm in thickness) and a second underlying TiN film 14 (70 nm in thickness) is deposited on the BPSG film 11 including the inner surfaces of the connection hole 12 according to a sputtering method, followed by further deposition of a W film 15 (250 nm in thickness) on the TiN film 14 by a CVD method. Subsequently, as shown in FIG. 4, the W film 15 and the underlying film (consisting of the TiN film 14 and the Ti film 13 ) are subjected to patterning through a photoresist mask, thereby forming a tungsten (W) interconnection 16 which is a first interconnection layer.
- Wtungsten
- the first underlying titanium (Ti) film 13is provided for the following reason: the film 13 is in contact with the n-type and p-type semiconductor regions (not shown) formed on the main surface of the semiconductor substrate 1 to form titanium silicide (TiSi); and hence the contact resistance can be reduced.
- the second underlying titanium nitride (TiN) film 14is provided in order to prevent the reaction between the gas (WF 6 ) used to form the tungsten film (W) 15 and the titanium film 13 .
- a first interlayer insulating film 17is deposited on the top of the W interconnection 16 .
- the interlayer insulating film 17is constituted, for example, of a three-layer film made of a silicon oxide film deposited by a CVD method, a spin-on-glass film deposited by spin coating, and a silicon oxide film deposited by the CVD method.
- connection hole 18is formed in the insulating film 17 on the W interconnection 16 by dry etching using a photoresist as a mask, followed by deposition, on the interlayer insulating film 17 including the inner surfaces of the connection hole 18 , of an underlying film consisting of a titanium (Ti) film 19 (30 nm in thickness), a titanium nitride (TiN) film 20 (100 nm in thickness) according to a sputtering method. Thereafter, a tungsten (W) film 21 (500 nm in thickness) is formed on the titanium nitride (TiN) film 20 by the CVD method.
- Tititanium
- TiNtitanium nitride
- the underlying titanium (Ti) film 19is provided so that it properly controls the crystal orientation of an aluminium alloy film to be subsequently formed, thereby imparting a high electromigration resistance thereto.
- the underlying titanium nitride (TiN) film 20is provided in order to prevent the reaction between the gas (WF 6 ) used to form the tungsten (W) film 21 and the titanium (Ti) film 19 , like the afore-stated titanium nitride (TiN) film 14 .
- the tungsten (W) film 21is etched back by use of a fluorine (F) plasma (e.g. SF 6 gas) to remove the tungsten (W) film 21 from the interlayer insulating film 17 but to leave the tungsten (W) film 21 only in the connection holes 18 .
- Ffluorine
- the tungsten (W) film 21has to be over-etched. This permits the tungsten (W) film 21 in each connection hole 18 to be removed to a degree, thereby establishing a step with the surface of the interlayer insulating film 17 or the underlying titanium nitride film 20 .
- the underlying film, particularly the TiN film 20 , formed on the interlayer insulating film 17serves as an etching stopper at the time of the etching-back.
- a titanium (Ti) film 22 (10 nm in thickness) and an Al—Si—Cu film 23 (400 nm in thickness)are successively deposited, by a sputtering method, on the titanium nitride (TiN) film 20 exposed at the surface thereof on the interlayer insulating film 17 .
- the aluminium alloy (Al—Si—Cu) film 23has a stepped surface at position just above the connection hole 18 formed in the insulating film 17 , correspondingly stepped between the surfaces of the interlayer insulating film 17 and the W film 21 in the connection hole 18 .
- the semiconductor substrate 1is heated after deposition of the aluminium alloy (Al—Si—Cu) film 23 as is particularly shown in FIG. 8, so that the aluminium alloy (Al—Si—Cu) film 23 is re-flown thereby permitting the surface to be flattened.
- the re-flowing conditionsinclude a substrate temperature of 450° C., a pressure of 1 mTorr, and a heating time of 180 seconds.
- the re-flown aluminium (Al—Si—Cu) film 23has a surface reflectivity of 91% (wavelength: 365 nm) and is thus very flat.
- an upper filmcomprising a titanium (Ti) film 24 (10 nm in thickness) and a titanium nitride (TiN) film (60 nm in thickness) is deposited on the aluminium alloy (Al—Si—Cu) film 23 by a sputtering method, followed by patterning the titanium nitride (TiN) film 25 , titanium (Ti) film 24 , aluminium alloy (Al—Si—Cu) film 23 , titanium nitride (TiN) film 20 , titanium (Ti) film 19 by dry etching using a photoresist as a mask, thereby forming an aluminium (Al) interconnection 26 which is a second layer interconnection.
- the titanium nitride (TiN) upper film 25serves as an antireflection film which prevents halation occurring during the course of the patterning of the aluminium second interconnection 26 .
- the titanium film 24is provided in order to prevent formation of an aluminium nitride (Al 3 N) film when the titanium nitride (TiN) film 25 is formed on the aluminium alloy (Al—Si—Cu) film 23 .
- a second interlayer insulating film 27is deposited on the top of the aliminium (Al) interconnection 26 .
- the interlayer insulating film 27is constituted, for example, of a three-layered film consisting of a silicon oxide film deposited by a CVD method, a spin-on-glass film deposited by a spin coating method, and a silicon oxide film deposited by a CVD method.
- connection hole 28is formed in the interlayer insulating film 27 at a position just above the connection hole 18 formed in the first interlayer insulating film 17 .
- the aluminium (Al) interconnection 26is flattened on the surface thereof (i.e. the bottom of the connection hole 28 ) by the re-flowing. Accordingly, when the connection hole 28 is located at a position just above the connection hole 18 and then formed with a Ti film 29 , a TiN film 30 and a W film in this order, the conduction failure between the Al interconnection 26 and the upper Al interconnection layer can be appropriately prevented without formation of any insulating film in the connection hole 28 .
- an underlying filmcomprising a titanium (Ti) film 29 (30 nm in thickness) and a titanium nitride (TiN) film 30 (100 nm in thickness) is deposited on the interlayer insulating film 27 including the inner surfaces of the connection hole 28 .
- a tungsten (W) film 31(500 nm in thickness) is deposited on the titanium nitride (TiN) film 30 .
- the tungsten (W) film 31 on the insulating film 27is etched back by use of a fluorine (F) plasma to remove the film 31 from the film 27 while leaving the tungsten (W) film 31 within the connection hole 28 .
- Ffluorine
- the titanium nitride (TiN) film 30is subjected to sputter etching with argon (Ar) gas to an extent of approximately 15 nm, calculated as a thermally oxidized film (silicon oxide film), thereby removing the remaining fluorine (F).
- Arargon
- TiN film 30is sputter-etched on the surface thereof is that when the surface of the titanium nitride (TiN) film 30 is contaminated with the fluorine (F), bonding at the interface with a film to be further deposited lowers. More particularly, we have found that when a wire is bonded to a bonding pad in a subsequent step, separation takes place at the interface beneath the bonding pad. It will be noted that the underlying titanium nitride (TiN) film 30 may be replaced by a zirconium nitride (ZrN) film.
- ZrNzirconium nitride
- FIG. 12is a graph showing AES (Auger Electron Spectroscopy) spectra of the surface of the titanium nitride (TiN) film 30 prior to the sputter etching. From the spectral analysis, the content of fluorine (F) in or on the surfaces of the titanium nitride (TiN) film 30 is calculated as 12 atomic percent.
- AESAlger Electron Spectroscopy
- FIG. 13is a graph showing the relation between the content of fluorine (F) and the thickness of the sputter etched titanium nitride.
- the content of fluorineis determined by successively depositing, as will be described hereinafter, a titanium (Ti) film 32 and an aluminium alloy (Al—Si—Cu) film 33 on the titanium nitride (TiN) film 30 by a sputtering method and measuring the content of fluorine at the interface between the titanium nitride (TiN) film 30 and the titanium (Ti) film 32 by the SIMS analysis.
- the thickness of the sputter-etched titanium nitride (TiN) film 30is indicated as a thickness of a sputter-etched silicon oxide film formed by thermal oxidation (wherein the sputter etching rate of the TiN film is 40% of the sputter etching rate of the silicon oxide film). From this, it has been calculated that the content of fluorine at the time when no sputter etching is conducted (A point in the figure) is 12 atomic percent, and the content of fluorine (F) at the time when the thickness of the sputter etched titanium nitride is 5 nm (B point in the figure) is 6 atomic percent.
- FIG. 14is a graph showing the relation between the fluorine (F) ion intensity at the interface between the titanium nitride (TiN) film 30 and the titanium (Ti) film 32 and the thickness of sputter-etched titanium nitride film (calculated as a silicon oxide film). The relation is determined from the results of the AES spectra of FIG. 12 and the SIMS analysis of FIG. 13. The thickness of the sputter etched film and the bonding failure is shown in Table 1. TABLE 1 Relation between the thickness of the sputter etched film and the bonding failure thickness of sputter etched film (nm) 0 5 10 20 30 50 bonding failure x ⁇ ⁇ ⁇ ⁇ ⁇ ⁇
- any bonding padis formed at the second-layered interconnection (Al interconnection 26 ), the above problem does not arise.
- the titanium nitride (TiN) film 20is contaminated with fluorine (F) on the surface thereof, the bonding force at the interface with the titanium (Ti) film 22 being deposited thereon lowers. Accordingly, it is preferred to subject the surface of the titanium nitride (TiN) film 20 to sputter etching prior to the deposition of the titanium (Ti) film 22 . The lowering of the bonding force by the action of the fluorine (F) does not take place only when the titanium (Ti) film is deposited on the titanium nitride (TiN) film.
- the titanium nitride (TiN) filmshould preferably be sputter etched prior to the deposition of the aluminium alloy (Al—Si—Cu) film.
- a titanium (Ti) film 32 (20 nm in thickness) and an aluminium alloy (Al—Si—Cu) film 33 (600 nm in thickness)are successively deposited on the titanium nitride (TiN) film 30 by a sputtering method.
- the aluminium alloy (Al—Si—Cu) film 33is deposited at two stages. More particularly, the semiconductor substrate 1 is kept at a temperature not higher than 150° C. at which first-stage deposition is carried out at a sputtering rate of approximately 1300 to 1700 nm/minute (300 nm in thickness). Subsequently, the semiconductor substrate 1 is kept at a temperature of 250 to 350° C., at which second-stage deposition is performed at a sputtering rate of approximately 400 to 800 nm (300 nm in thickness).
- the aluminium alloy (Al—Si—Cu) films 33 (B, C, D)are deposited by the two-stage sputtering process including a stage of a low temperature (165° C.) and a high sputtering rate (1500 nm/minute) and a stage of a high temperature (250 to 350° C.) and a low sputtering rate (600 nm/minute), they have sheet resistances and reflectivities almost the same as those of the film obtained by the one-stage sputtering process (A), but have reduced numbers of surface irregularities and precipitates of a reaction product in the film.
- the aluminium alloy (Al—Si—Cu) films 33 (B, C, D)exhibit a good coverage for all the cases.
- an upper filmis further deposited on the aluminium alloy (Al—Si—Cu) film 33 .
- the upper filmis constituted of a single-layered titanium nitride (TiN) film 34 (60 nm in film thickness).
- TiNtitanium nitride
- any titanium (Ti) filmis not formed on the aluminium alloy (Al—Si—Cu) film 33 .
- a titanium (Ti) filmis provided, the compound of titanium and the aluminium alloy is formed, thereby causing the bonding failure.
- a titanium (Ti) filmis not provided, the compound of aluminium and the nitride is formed on the surface of the aluminium alloy film.
- this compoundcan be removed during the step of removing the titanium nitride at the time of making an opening for the bonding pad.
- the re-flowing as set out hereinbeforemay be carried out to cause the surface to be more flattened.
- the semiconductor substratemay be removed to outside of the sputtering apparatus, and thus the aluminium alloy (Al—Si—Cu) film 33 may be exposed to the air to form an oxide film on the surface thereof.
- the upper film (TiN film 34 )may be deposited thereon. In the case, the formation of the compound of aluminium and the nitride can be prevented.
- the procedure of forming the aluminium alloy film by the two-stage processmay also be applied to the formation of the aluminium alloy film 23 of the second-layered aluminium interconnection 26 .
- the re-flowing step of the aluminium interconnection 26may be omitted.
- the titanium nitride (TiN) film 34 , aluminium alloy (Al—Si—Cu) film 33 , titanium (Ti) film 32 , titanium nitride (TiN) film 30 and titanium (Ti) film 29are, respectively, patterned by dry etching using photoresist as a mask to form an uppermost aluminium (Al) interconnection 35 , followed by further deposition of a passivation film 36 on the top of the aluminium (Al) interconnection 35 .
- the passivation film 36is constituted, for example, of a two-layered film consisting of a silicon oxide film deposited by a CVD method and a silicon nitride film deposited by a CVD method.
- part of the passivation film 36is made with a hole by dry etching using photoresist as a mask, thereby exposing part of the aluminium (Al) interconnection film 35 to form a bonding pad 37 .
- the upper film on the surface of the bonding pad 37 (Al interconnection 35 )is constituted of the single-layered titanium nitride (TiN) film 34 (provided that where the Al—Si—Cu film 33 is oxidized on the surface thereof, it is made of TiN film and oxide film).
- the bonding pad 37is not deposited with the compound of aluminium (Al) and titanium (Ti) unlike the case where the upper film is constituted of a builtup film of the titanium nitride (TiN) film and the titanium (Ti) film.
- the titanium nitride (TiN) film 30which is a part of the uppermost aluminium (Al) interconnection is sputter etched on the surface thereof to remove the fluorine (F) therefrom, so that a satisfactory bonding force at the interface between the titanium nitride (TiN) film 30 and the titanium film (Ti) film 32 deposited thereon can be attained.
- the bonding pad 37does not separate such as by impact of bonding of the wire 38 to the surface of the bonding pad 37 .
- the upper film on the top of the uppermost interconnectionis constituted of a titanium nitride (TiN) film. Accordingly, when part of the passivation film covering the uppermost interconnection is removed by etching to form the bonding pad, the reaction product of the aluminium alloy and titanium is prevented from precipitation at the interface between the Al film and the upper film.
- TiNtitanium nitride
- the underlying filmis sputter etched on the surface thereof with use of Ar gas to remove fluorine from the surface. This contributes to improving the bonding force at the interface between the underlying film and the underlying film or aluminium alloy film deposited on the first-mentioned underlying film.
- the aluminium (Al) filmis deposited by two stages including a first stage of deposing an aluminium (Al) film under low temperature and high sputtering rate conditions and a second stage of depositing another aluminium film under high temperature and low sputtering rate conditions.
- a first stage of deposing an aluminium (Al) film under low temperature and high sputtering rate conditionsand a second stage of depositing another aluminium film under high temperature and low sputtering rate conditions.
- the filmis re-flown at such high temperatures that the aluminium (Al) interconnection just above the connection hole filled up with the tungsten (W) film can be flattened.
- the bonding force between a bonding pad and a metallic wireincreases, thereby improving the reliability of connection between the bonding pad and the wire.
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Abstract
Description
- This application is a Continuation application of application Ser. No. 09/998,644, filed Dec. 3, 2001, which is a Divisional application of application Ser. No. 09/245,743, filed Feb. 8, 1999, which is a Divisional application of application Ser. No. 08/584,065, filed Jan. 11, 1996, now U.S. Pat. No. 5,904,556, the contents of which are incorporated herein by reference in their entirety.[0001]
- This invention relates to a semiconductor integrated circuit device and also to a method for making the device. More particularly, the invention relates to a technique which is effective when applied to an interconnection structure and an interconnecting process of LSI having multilayer interconnections.[0002]
- In recent years, integration of LSI has been in progress. This leads to increased aspect ratios (i.e., the depth of a connection hole formed on an inter-layer insulating film between a given Al interconnection and a low conductor layer, semiconductor region or a lower Al interconnection. In order to prevent the breakage of the Al interconnections in the inside of the connection holes, a so-called tungsten plug technique has been utilized wherein a W (tungsten) film is filled in the connection holes.[0003]
- To fill the W film up in the connection hole, a W film is deposited, according to the CVD method, on the entire surface of an insulating film in which connection holes have been formed. Subsequently, the W film on the insulating film is etched back, thereby leaving the W film only in the connection holes. For the etching back of the W film, a F (fluorine) plasma is used. In order to prevent the underlying insulating film (silicon oxide film) from being etched out with the F plasma, a underlying layer, which is constituted of stacked films including a Ti film and a TiN film, has been formed beneath the W film.[0004]
- The underlying film constituted of the Ti/TiN stacked films is very resistant to electromigration or stress migration, and has been employed for interconnection of LSI which is fabricated according to the design rule on the order of submicrons. Interconnections having such a stacked structure as of Ti/TiN/Al—Cu/TiN formed in this order and tungsten plug techniques for this are set out, for example, in LVSI Multi-level Conference Jun. 7-8, 1994, pp. 36-43.[0005]
- The semiconductor integrated circuit device to which the invention is directed is of the type which comprises three-layered metallic interconnections including a first layer made of a tungsten film, and second and third layers made of an aluminium alloy film, respectively.[0006]
- A titanium (Ti) film and a titanium nitride (TiN) film, both serving as a underlying layer, are provided beneath the first-layered tungsten film. The interconnection for the first layer is constituted of a three-layered structure made of Ti/TiN/W formed in this order.[0007]
- Likewise, a titanium (Ti) underlying film, a titanium nitride (TiN) underlying film and a titanium (Ti) underlying film are provided beneath each of the second and third-layered aluminium alloy (Al—Si—Cu) layers. Ti/TiN cap films are provided on each of the second and third-layered aluminum alloy (Al—Si—Cu) layers. More particularly, a six-layered structure of Ti/TiN/Ti/Al—Si—Cu/Ti/TiN as viewed from the bottom is established. As a matter of course, a tungsten (W) film is filled in connection holes connecting the first and second layers and the second and third layers therewith. Each tungsten film exists in the connection hole between the titanium nitride (TiN) underlying film and the titanium (Ti) underlying film formed on the TiN film.[0008]
- We found that the semiconductor integrated circuit having such an interconnection structure as set out above has the following problems.[0009]
- (1) The process of filling the tungsten (W) film in the connection holes essentially requires removal of the W film from the insulating film through etching-back by use of a fluorine (F) plasma as set out hereinbefore. This permits part of the fluorine in the plasma to be left on the surface of the underlying film (Ti/TiN stacked film) formed on the insulating film and exposed by the etching-back step. The thus left fluorine reacts with titanium to provide a solid compound. Hence, the compound is left on the underlying film. When another underlying film (Ti film) is formed on the first-mentioned underlying film, or when an aluminium alloy film is deposited subsequently to the etching-back step, the bonding force at the interface between the underlying film on which the compound has remained and the film formed on this underlying film lowers by the influence of the fluorine (F) residue.[0010]
- Especially, the uppermost interconnection layer partly serves as a bonding pad. When a wire is bonded to the bonding pad, the pad may separate owing to the impact of the bonding. More particularly, it has been found that the underlying film on which the compound has been left separates from another underlying film formed thereon at the bonding pad portion.[0011]
- (2) The process of filling the W film in the connection holes includes the etching-back step wherein the W film is allowed to be left only in the connection holes. This requires over-etching in order to completely remove the W film from the surface of the insulating film. At the time, the W film in the connection holes is also etched out from the outer surface thereof. This leaves a step between the surface of the insulating film or the surface of the underlying film and the surface of the W film in each connection hole.[0012]
- In this condition, when an Al interconnection is formed on the insulating film, the Al interconnection is stepped at a surface portion just above the connection hole owing to the above-mentioned step. If a second connection hole is formed in the interlayer insulating film just above the first-mentioned connection hole in order to connect the Al interconnection and the upper Al interconnection therewith and the second connection hole is filled up with the W film, an insulating martial made of AlF[0013]3is formed in the second connection hole at the time of the formation of the W film. This presents the problem that the conduction failure takes place between the Al interconnection and the upper Al interconnection.
- Owing to the step appearing at the surface of the Al interconnection, the upper layer film formed on the Al interconnection suffers a coverage failure, thus Al being partially exposed from the upper layer film. The thus exposed Al reacts with F left at the time of the formation of the W film, thereby forming an insulating AlF[0014]3film. This is the reason why there arises the problem that the conduction failure or an increase in contact resistance between the Al interconnection and the upper Al interconnection takes place.
- (3) As having set out hereinabove, the Al interconnection is constituted of multi-layered interconnection (Ti/TiN/Ti/Al—Si—Cu/Ti/TiN). Usually, an uppermost interconnection is used as a bonding pad. However, if the uppermost interconnection is constituted of this type of multi-layered interconnection and part of a passivation film covering the uppermost interconnection therewith is removed by etching to form a bonding pad, a compound formed by reaction between Al and Ti is deposited at the interface between the Al film and the upper film (Ti/TiN stacked film) formed on the Al film. This compound is so hard that the bonding force between the bonding pad and a wire lowers. It should be noted that the etching of the passivation film does not make it possible to fully remove the compound of Al and Ti.[0015]
- (4) The Al interconnections are formed by depositing the Al composite film by sputtering and dry etching the deposited film. If the coverage of the Al film on deposition of the Al composite film lowers by the influence of the step formed in the underlying layer, the processing accuracy of the interconnection through dry etching unfavorably lowers. To avoid this, a so-called high temperature Al sputtering technique has been proposed. In the technique, a semiconductor substrate is maintained at high temperatures, and the Al film is deposited while re-flowing the Al film by application of heat from the substrate, thereby ensuring a good coverage of the Al.[0016]
- In this connection, however, when an Al film, particularly an Al—Si—Cu film or an Al—Cu film, is deposited according to the high temperature sputtering method, a reaction product is also precipitated in the film. The reaction product is left after dry etching, thus creating another cause of lowering the processing accuracy of the Al interconnection.[0017]
- It is therefore an object of the invention to provide a technique whereby a bonding pad constituted of multi-layered interconnection is prevented from separation.[0018]
- It is another object of the invention to provide a technique whereby an bonding force between a bonding pad constituted of multi-layered interconnection and a wire is improved.[0019]
- It is a further object of the invention to provide a technique which is able to realize a stack-on-plug structure wherein connection holes for an upper layer are located just above connection holes of an interlayer insulating film, respectively.[0020]
- It is a still further object of the invention to provide a technique wherein when an Al film is deposited according to a high temperature sputtering method, any reaction product is prevented from formation as precipitated in the Al film.[0021]
- These and other objects and novel features of the invention will become apparent from the following description and the accompanying drawings.[0022]
- Typical embodiments of the invention are summarized below.[0023]
- According to one embodiment of the invention, there is provided a method for making a semiconductor integrated circuit device which comprises the steps of:[0024]
- (a) forming a first insulating film formed on a semiconductor substrate and having a plurality of through-holes;[0025]
- (b) forming a first underlying film on the first insulating film and in the plurality of through-holes and forming a tungsten film on the underlying film in such a thickness that the through-holes are filled therewith;[0026]
- (c) etching the tungsten film to remove the tungsten film from said first insulating film thereby exposing the surface of the first underlying film and selectively leaving the tungsten film in the through-holes;[0027]
- (d) sputter etching the surface of the first underlying film;[0028]
- (e) forming a first metallic film on the sputter-etched first underlying film; and[0029]
- (f) electrically connecting a metallic wire to the first metallic film in regions other than regions where the through-holes are formed.[0030]
- According to another embodiment of the invention, there is also provided a semiconductor integrated circuit device which comprises:[0031]
- (a) a semiconductor substrate;[0032]
- (b) a first interconnection film formed on the semiconductor substrate;[0033]
- (c) an insulating film formed on the first interconnection film and having a plurality of through-holes;[0034]
- (d) a second interconnection film connected with the first interconnection film through the through-holes and formed on the insulating film; and[0035]
- (e) a bonding wire connected to the second interconnection film, wherein the first interconnection film is constituted of a first aluminium alloy film, a titanium film formed on the first aluminium film, and a first titanium nitride formed on the titanium film, and the second interconnection film is constituted of a second aluminium alloy film and a second titanium nitride film formed on the second aluminium alloy film.[0036]
- According to a further embodiment of the invention, there is provided a method for making a semiconductor integrated circuit device, which method comprising forming an aluminium film on a main surface of a semiconductor substrate by sputtering, characterized in that a first aluminium film is formed on the semiconductor substrate which is kept at a relatively low temperature, and a second aluminium film is formed at a substrate temperature which is higher than the first-mentioned temperature[0037]
- According to a still further embodiment of the invention, there is provided a method for making a semiconductor integrated circuit device, which comprises the steps of:[0038]
- (a) forming a first insulating film formed on a semiconductor substrate and having a plurality of first through-holes;[0039]
- (b) forming a tungsten film formed on the first insulating film and in the first through-holes in such a thickness that the first through-holes are filled with the tungsten film;[0040]
- (c) etching the tungsten film to remove it from the first insulating film until the surface of the first insulating film is exposed while selectively leaving the tungsten film in the individual first through-holes;[0041]
- (d) forming a first aluminium film on the exposed surface of the first insulating film and on the tungsten film in the first through-holes; and[0042]
- (e) re-flowing the first aluminium film at a given temperature.[0043]
- FIGS.[0044]1 to11 and15 to17 are, respectively, a sectional view of an essential part of a semiconductor substrate which illustrates a method for making a semiconductor integrated circuit device according to one embodiment of the invention;
- FIG. 12 is an AES spectrum chart of the surface of a TiN film prior to sputter etching;[0045]
- FIG. 13 is a graph showing the relation between the content of F at the interface of Ti/TiN films and the thickness of a sputter etched titanium nitride film; and[0046]
- FIG. 14 is a graph showing the relation between the intensity of F ions at the interface of Ti/TiN films and the thickness of sputter-etched titanium nitride.[0047]
- Embodiments of the invention are described in detail with reference to the accompanying drawings, in which like reference numerals indicate like parts or members throughout the specification.[0048]
- Reference is now made to FIGS.[0049]1 to17 which illustrate an embodiment of the invention applied to MOS-LSI having a three-layered interconnection structure initially, as shown in FIG. 1, a
semiconductor substrate 1 made of p-type single crystal silicon is ion-implanted with a p-type impurity (boron) on the main surface thereof to form a p-type well 2. Thereafter, afield oxide film 3 is formed on the main surface of the p-type well according to a selective oxidation (LOCOS) method. Subsequently, agate oxide 5 is formed on the main surface of the p-type well2 surrounded with thefield oxide film 3 according to a thermal oxidation method, followed by ion implantation of a p-type impurity (boron) into the p-type well 2, thereby creating a p-typechannel stopper layer 4 in the p-type well2 including the lower portion of thefield oxide film 3. - Next, a polysilicon film and a[0050]
silicon oxide film 9 are successively deposited on thesemiconductor substrate 1 according to a CVD method, followed by patterning of this two-layered film by drying etching through a photoresist mask to formgate electrodes 6 of MISFET made of the polysilicon film. The polysilicon forming eachgate electrode 6 is introduced with an n-type impurity (e.g. P) in order to reduce the resistance thereof. It will be noted that thegate electrodes 6 may be constituted of a polyside film which is made of a refractory metal silicide film, such as WSix, MoSix, TiSix or TaSix, built on the top of the polysilicon film. - An n-type impurity (e.g. P) is ion-implanted into the p-type well[0051]2 in self-aligned with the
gate electrodes 6, so that a pair of n-type semiconductor regions gate electrode 6. - Thereafter, a silicon oxide film is deposited over the[0052]
semiconductor substrate 1 by a CVD method, followed by anisotropic etching of the silicon oxide film by a reactive ion etching (RIE) method to formside wall spacers 8 at side walls of thegate electrode 6, respectively. - Then, as shown in FIG. 2, an[0053]
oxide film 10 and aBPSG film 11 are successively formed over thesemiconductor substrate 1 by a CVD method, followed by dry etching theBPSG film 11 and thesilicon oxide film 10 through a photoresist mask, thereby forming aconnection hole 12 arriving at one of the pairedsemiconductor regions - As shown in FIG. 3, an underlying film comprising a first underlying Ti film[0054]13 (30 nm in thickness) and a second underlying TiN film14 (70 nm in thickness) is deposited on the
BPSG film 11 including the inner surfaces of theconnection hole 12 according to a sputtering method, followed by further deposition of a W film15 (250 nm in thickness) on theTiN film 14 by a CVD method. Subsequently, as shown in FIG. 4, theW film 15 and the underlying film (consisting of theTiN film 14 and the Ti film13) are subjected to patterning through a photoresist mask, thereby forming a tungsten (W)interconnection 16 which is a first interconnection layer. - The first underlying titanium (Ti)[0055]
film 13 is provided for the following reason: thefilm 13 is in contact with the n-type and p-type semiconductor regions (not shown) formed on the main surface of thesemiconductor substrate 1 to form titanium silicide (TiSi); and hence the contact resistance can be reduced. - On the other hand, the second underlying titanium nitride (TiN)[0056]
film 14 is provided in order to prevent the reaction between the gas (WF6) used to form the tungsten film (W)15 and thetitanium film 13. - As shown in FIG. 5, a first[0057]
interlayer insulating film 17 is deposited on the top of theW interconnection 16. Theinterlayer insulating film 17 is constituted, for example, of a three-layer film made of a silicon oxide film deposited by a CVD method, a spin-on-glass film deposited by spin coating, and a silicon oxide film deposited by the CVD method. - Next, a[0058]
connection hole 18 is formed in the insulatingfilm 17 on theW interconnection 16 by dry etching using a photoresist as a mask, followed by deposition, on theinterlayer insulating film 17 including the inner surfaces of theconnection hole 18, of an underlying film consisting of a titanium (Ti) film19 (30 nm in thickness), a titanium nitride (TiN) film20 (100 nm in thickness) according to a sputtering method. Thereafter, a tungsten (W) film21 (500 nm in thickness) is formed on the titanium nitride (TiN)film 20 by the CVD method. - It will be noted that the underlying titanium (Ti)[0059]
film 19 is provided so that it properly controls the crystal orientation of an aluminium alloy film to be subsequently formed, thereby imparting a high electromigration resistance thereto. Likewise, the underlying titanium nitride (TiN)film 20 is provided in order to prevent the reaction between the gas (WF6) used to form the tungsten (W)film 21 and the titanium (Ti)film 19, like the afore-stated titanium nitride (TiN)film 14. - As shown in FIG. 6, the tungsten (W)[0060]
film 21 is etched back by use of a fluorine (F) plasma (e.g. SF6gas) to remove the tungsten (W)film 21 from theinterlayer insulating film 17 but to leave the tungsten (W)film 21 only in the connection holes18. In order to completely remove the tungsten (W)film 21 from theinterlayer insulating film 17, the tungsten (W)film 21 has to be over-etched. This permits the tungsten (W)film 21 in eachconnection hole 18 to be removed to a degree, thereby establishing a step with the surface of theinterlayer insulating film 17 or the underlyingtitanium nitride film 20. The underlying film, particularly theTiN film 20, formed on theinterlayer insulating film 17 serves as an etching stopper at the time of the etching-back. - Then, as shown in FIG. 7, a titanium (Ti) film[0061]22 (10 nm in thickness) and an Al—Si—Cu film23 (400 nm in thickness) are successively deposited, by a sputtering method, on the titanium nitride (TiN)
film 20 exposed at the surface thereof on theinterlayer insulating film 17. At the time, the aluminium alloy (Al—Si—Cu)film 23 has a stepped surface at position just above theconnection hole 18 formed in the insulatingfilm 17, correspondingly stepped between the surfaces of theinterlayer insulating film 17 and theW film 21 in theconnection hole 18. - To avoid this, according to this embodiment, the[0062]
semiconductor substrate 1 is heated after deposition of the aluminium alloy (Al—Si—Cu)film 23 as is particularly shown in FIG. 8, so that the aluminium alloy (Al—Si—Cu)film 23 is re-flown thereby permitting the surface to be flattened. The re-flowing conditions include a substrate temperature of 450° C., a pressure of 1 mTorr, and a heating time of 180 seconds. The re-flown aluminium (Al—Si—Cu)film 23 has a surface reflectivity of 91% (wavelength: 365 nm) and is thus very flat. - Next, as shown in FIG. 9, an upper film comprising a titanium (Ti) film[0063]24 (10 nm in thickness) and a titanium nitride (TiN) film (60 nm in thickness) is deposited on the aluminium alloy (Al—Si—Cu)
film 23 by a sputtering method, followed by patterning the titanium nitride (TiN)film 25, titanium (Ti) film24, aluminium alloy (Al—Si—Cu)film 23, titanium nitride (TiN)film 20, titanium (Ti)film 19 by dry etching using a photoresist as a mask, thereby forming an aluminium (Al)interconnection 26 which is a second layer interconnection. - The titanium nitride (TiN)[0064]
upper film 25 serves as an antireflection film which prevents halation occurring during the course of the patterning of the aluminiumsecond interconnection 26. The titanium film24 is provided in order to prevent formation of an aluminium nitride (Al3N) film when the titanium nitride (TiN)film 25 is formed on the aluminium alloy (Al—Si—Cu)film 23. - As shown in FIG. 10, a second[0065]
interlayer insulating film 27 is deposited on the top of the aliminium (Al)interconnection 26. Theinterlayer insulating film 27 is constituted, for example, of a three-layered film consisting of a silicon oxide film deposited by a CVD method, a spin-on-glass film deposited by a spin coating method, and a silicon oxide film deposited by a CVD method. - Next, according to the dry etching using photoresist as a mask, a[0066]
connection hole 28 is formed in theinterlayer insulating film 27 at a position just above theconnection hole 18 formed in the firstinterlayer insulating film 17. The aluminium (Al)interconnection 26 is flattened on the surface thereof (i.e. the bottom of the connection hole28) by the re-flowing. Accordingly, when theconnection hole 28 is located at a position just above theconnection hole 18 and then formed with aTi film 29, aTiN film 30 and a W film in this order, the conduction failure between theAl interconnection 26 and the upper Al interconnection layer can be appropriately prevented without formation of any insulating film in theconnection hole 28. - Then, as shown in FIG. 11, an underlying film comprising a titanium (Ti) film[0067]29 (30 nm in thickness) and a titanium nitride (TiN) film30 (100 nm in thickness) is deposited on the
interlayer insulating film 27 including the inner surfaces of theconnection hole 28. Thereafter, a tungsten (W) film31 (500 nm in thickness) is deposited on the titanium nitride (TiN)film 30. Subsequently, the tungsten (W)film 31 on the insulatingfilm 27 is etched back by use of a fluorine (F) plasma to remove thefilm 31 from thefilm 27 while leaving the tungsten (W)film 31 within theconnection hole 28. Because part of F from the plasma undesirably remains on the surface of the titanium nitride (TiN)film 30 on the top of theinterlayer insulating film 27 exposed by the etching-back, the titanium nitride (TiN)film 30 is subjected to sputter etching with argon (Ar) gas to an extent of approximately 15 nm, calculated as a thermally oxidized film (silicon oxide film), thereby removing the remaining fluorine (F). - The reason why the titanium nitride (TiN)[0068]
film 30 is sputter-etched on the surface thereof is that when the surface of the titanium nitride (TiN)film 30 is contaminated with the fluorine (F), bonding at the interface with a film to be further deposited lowers. More particularly, we have found that when a wire is bonded to a bonding pad in a subsequent step, separation takes place at the interface beneath the bonding pad. It will be noted that the underlying titanium nitride (TiN)film 30 may be replaced by a zirconium nitride (ZrN) film. - FIG. 12 is a graph showing AES (Auger Electron Spectroscopy) spectra of the surface of the titanium nitride (TiN)[0069]
film 30 prior to the sputter etching. From the spectral analysis, the content of fluorine (F) in or on the surfaces of the titanium nitride (TiN)film 30 is calculated as 12 atomic percent. - FIG. 13 is a graph showing the relation between the content of fluorine (F) and the thickness of the sputter etched titanium nitride. The content of fluorine is determined by successively depositing, as will be described hereinafter, a titanium (Ti)[0070]
film 32 and an aluminium alloy (Al—Si—Cu)film 33 on the titanium nitride (TiN)film 30 by a sputtering method and measuring the content of fluorine at the interface between the titanium nitride (TiN)film 30 and the titanium (Ti)film 32 by the SIMS analysis. For convenience's sake, the thickness of the sputter-etched titanium nitride (TiN)film 30 is indicated as a thickness of a sputter-etched silicon oxide film formed by thermal oxidation (wherein the sputter etching rate of the TiN film is 40% of the sputter etching rate of the silicon oxide film). From this, it has been calculated that the content of fluorine at the time when no sputter etching is conducted (A point in the figure) is 12 atomic percent, and the content of fluorine (F) at the time when the thickness of the sputter etched titanium nitride is 5 nm (B point in the figure) is 6 atomic percent. - FIG. 14 is a graph showing the relation between the fluorine (F) ion intensity at the interface between the titanium nitride (TiN)[0071]
film 30 and the titanium (Ti)film 32 and the thickness of sputter-etched titanium nitride film (calculated as a silicon oxide film). The relation is determined from the results of the AES spectra of FIG. 12 and the SIMS analysis of FIG. 13. The thickness of the sputter etched film and the bonding failure is shown in Table 1.TABLE 1 Relation between the thickness of the sputter etched film and the bonding failure thickness of sputter etched film (nm) 0 5 10 20 30 50 bonding failure x ∘ ∘ ∘ ∘ ∘ - As will be apparent from Table 1, when the titanium nitride (TiN)[0072]
film 30 is not sputter etched on the surface thereof, separation in the bonding pad takes place. On the other hand, when the thickness of the sputter etched film is 5, 10, 20, 30 or 50 nm, no separation takes place. This reveals that the separation in the bonding pad can be prevented when the sputter etching is performed until the content of the fluorine (F) is 6 atomic percent or below (i.e. the thickness of the sputter etching is not smaller than 5 nm calculated as the silicon oxide film or not smaller than 2 nm for the titanium nitride film). - Since any bonding pad is formed at the second-layered interconnection (Al interconnection[0073]26), the above problem does not arise. However, when the titanium nitride (TiN)
film 20 is contaminated with fluorine (F) on the surface thereof, the bonding force at the interface with the titanium (Ti)film 22 being deposited thereon lowers. Accordingly, it is preferred to subject the surface of the titanium nitride (TiN)film 20 to sputter etching prior to the deposition of the titanium (Ti)film 22. The lowering of the bonding force by the action of the fluorine (F) does not take place only when the titanium (Ti) film is deposited on the titanium nitride (TiN) film. For instance, it will be highly possible that such a lowering occurs on direct deposition of the aluminium alloy (Al—Si—Cu) film on the titanium nitride (TiN)film 20. In the case, the titanium nitride (TiN) film should preferably be sputter etched prior to the deposition of the aluminium alloy (Al—Si—Cu) film. - Next, as shown in FIG. 15, a titanium (Ti) film[0074]32 (20 nm in thickness) and an aluminium alloy (Al—Si—Cu) film33 (600 nm in thickness) are successively deposited on the titanium nitride (TiN)
film 30 by a sputtering method. In this embodiment, the aluminium alloy (Al—Si—Cu)film 33 is deposited at two stages. More particularly, thesemiconductor substrate 1 is kept at a temperature not higher than 150° C. at which first-stage deposition is carried out at a sputtering rate of approximately 1300 to 1700 nm/minute (300 nm in thickness). Subsequently, thesemiconductor substrate 1 is kept at a temperature of 250 to 350° C., at which second-stage deposition is performed at a sputtering rate of approximately 400 to 800 nm (300 nm in thickness). - The sheet resistance and reflectivity of the aluminium alloy (Al—Si—Cu) film deposited under such conditions as set out hereinabove are shown in Table 2. Point A in Table 2 shows the case where the substrate temperature is maintained at 165° C., and the aluminium alloy (Al—Si—Cu)[0075]
film 33 is deposited by one stage. With points B, C and D, the substrate temperature at the second stage is, respectively, maintained at 250° C., 300° C. and 350° C., and the respective aluminium alloy (Al—Si—Cu)films 33 are formed by two stages.TABLE 2 Resistance and reflectivity under different A1 sputtering conditions Film Sputtering Rate Temper- Sheet Reflect- thickness (nm/minute) ature (° C.) Resist- ivity (%) of AlCuSi first second first second ance (Wavelength: (nm) stage stage stage stage (mΩ) 365 nm) A 600 1500 — 165 — 51.7 97.5 B 600 1500 600 165 250 50 97.9 C 600 1500 600 165 300 49.1 96.4 D 600 1500 600 165 350 49.6 83.3 - The above results reveal that when the aluminium alloy (Al—Si—Cu) films[0076]33 (B, C, D) are deposited by the two-stage sputtering process including a stage of a low temperature (165° C.) and a high sputtering rate (1500 nm/minute) and a stage of a high temperature (250 to 350° C.) and a low sputtering rate (600 nm/minute), they have sheet resistances and reflectivities almost the same as those of the film obtained by the one-stage sputtering process (A), but have reduced numbers of surface irregularities and precipitates of a reaction product in the film. Thus, the aluminium alloy (Al—Si—Cu) films33 (B, C, D) exhibit a good coverage for all the cases.
- As shown in FIG. 16, an upper film is further deposited on the aluminium alloy (Al—Si—Cu)[0077]
film 33. The upper film is constituted of a single-layered titanium nitride (TiN) film34 (60 nm in film thickness). In other words, any titanium (Ti) film is not formed on the aluminium alloy (Al—Si—Cu)film 33. If a titanium (Ti) film is provided, the compound of titanium and the aluminium alloy is formed, thereby causing the bonding failure. As a mater of course, if a titanium (Ti) film is not provided, the compound of aluminium and the nitride is formed on the surface of the aluminium alloy film. However, this compound can be removed during the step of removing the titanium nitride at the time of making an opening for the bonding pad. After the deposition of the aluminium alloy (Al—Si—Cu)film 33, the re-flowing as set out hereinbefore may be carried out to cause the surface to be more flattened. Alternatively, after the deposition of the aluminium alloy (Al—Si—Cu)film 33, the semiconductor substrate may be removed to outside of the sputtering apparatus, and thus the aluminium alloy (Al—Si—Cu)film 33 may be exposed to the air to form an oxide film on the surface thereof. Thereafter, the upper film (TiN film34) may be deposited thereon. In the case, the formation of the compound of aluminium and the nitride can be prevented. - The procedure of forming the aluminium alloy film by the two-stage process may also be applied to the formation of the[0078]
aluminium alloy film 23 of the second-layeredaluminium interconnection 26. In this case, the re-flowing step of thealuminium interconnection 26 may be omitted. - Then, the titanium nitride (TiN)[0079]
film 34, aluminium alloy (Al—Si—Cu)film 33, titanium (Ti)film 32, titanium nitride (TiN)film 30 and titanium (Ti)film 29 are, respectively, patterned by dry etching using photoresist as a mask to form an uppermost aluminium (Al)interconnection 35, followed by further deposition of apassivation film 36 on the top of the aluminium (Al)interconnection 35. Thepassivation film 36 is constituted, for example, of a two-layered film consisting of a silicon oxide film deposited by a CVD method and a silicon nitride film deposited by a CVD method. - Next, as shown in FIG. 17, part of the[0080]
passivation film 36 is made with a hole by dry etching using photoresist as a mask, thereby exposing part of the aluminium (Al)interconnection film 35 to form abonding pad 37. The upper film on the surface of the bonding pad37 (Al interconnection35) is constituted of the single-layered titanium nitride (TiN) film34 (provided that where the Al—Si—Cu film 33 is oxidized on the surface thereof, it is made of TiN film and oxide film). Accordingly, thebonding pad 37 is not deposited with the compound of aluminium (Al) and titanium (Ti) unlike the case where the upper film is constituted of a builtup film of the titanium nitride (TiN) film and the titanium (Ti) film. - Thus, according to this embodiment of the invention, when a gold (Au) wire[0081]38 (i.e. a metallic wire) is bonded to the
bonding pad 37, good bonding force between thebonding pad 37 and thewire 38 is ensured. - Moreover, according to the embodiment, the titanium nitride (TiN)[0082]
film 30 which is a part of the uppermost aluminium (Al) interconnection is sputter etched on the surface thereof to remove the fluorine (F) therefrom, so that a satisfactory bonding force at the interface between the titanium nitride (TiN)film 30 and the titanium film (Ti)film 32 deposited thereon can be attained. Thus, thebonding pad 37 does not separate such as by impact of bonding of thewire 38 to the surface of thebonding pad 37. - In this embodiment, the upper film on the top of the uppermost interconnection is constituted of a titanium nitride (TiN) film. Accordingly, when part of the passivation film covering the uppermost interconnection is removed by etching to form the bonding pad, the reaction product of the aluminium alloy and titanium is prevented from precipitation at the interface between the Al film and the upper film.[0083]
- Furthermore, the underlying film is sputter etched on the surface thereof with use of Ar gas to remove fluorine from the surface. This contributes to improving the bonding force at the interface between the underlying film and the underlying film or aluminium alloy film deposited on the first-mentioned underlying film.[0084]
- The aluminium (Al) film is deposited by two stages including a first stage of deposing an aluminium (Al) film under low temperature and high sputtering rate conditions and a second stage of depositing another aluminium film under high temperature and low sputtering rate conditions. By this, the precipitation of a reaction product in the aluminium (Al) film can be prevented. Thus, the aluminium (Al) film obtained has a good coverage and a reduced degree of surface irregularities.[0085]
- In addition, after deposition of the aluminium (Al) film by a sputtering method, the film is re-flown at such high temperatures that the aluminium (Al) interconnection just above the connection hole filled up with the tungsten (W) film can be flattened.[0086]
- Having been described based on the embodiments, the invention should not be construed as limiting thereto. Many modifications and variations may be possible without departing from the scope of the invention.[0087]
- For instance, applications to MOS-LSI having a three-layered interconnection have been set out in the embodiments, and the invention is applicable to LSI having a four-layered or multi-layered interconnection.[0088]
- The effects attained by typical embodiments of the invention may be summarized below.[0089]
- (1) According to the invention, the bonding force between a bonding pad and a metallic wire increases, thereby improving the reliability of connection between the bonding pad and the wire.[0090]
- (2) The bonding force at the interface between the underlying films at the uppermost interconnection increases, thereby preventing separation of the bonding pad.[0091]
- (3) An Al film is obtained as having a good coverage and a reduced degree of surface irregularities, thereby leading to improved processability of the Al interconnections.[0092]
- (4) A stack-on-plug structure wherein an upper connection hole is made in an interlayer insulating film at a position just above a lower connection hole is realized, thereby ensuring a reduced chip area.[0093]
Claims (2)
1. A method of fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first aluminum film over a first insulating film formed over a semiconductor substrate;
(b) forming a first titanium film over said first aluminum film;
(c) forming a first titanium nitride film over said first titanium film;
(d) forming a second insulating film over said first titanium nitride film;
(e) forming first through-holes in said second insulating film, said first through-holes being connected with said first titanium film;
(f) forming a second titanium film over a surface of said first through-holes and said second insulating film;
(g) forming a second titanium nitride film over said second titanium film;
(h) forming a first tungsten film over said second titanium nitride film such that said first through-holes are filled with said first tungsten film;
(i) removing said first tungsten film over said second titanium nitride film such that said first tungsten film formed in said first through-holes is left;
(j) forming a third titanium film over said second titanium film and said first tungsten film formed in said first through-holes; and
(k) forming a second aluminum film over said third titanium film;
wherein said step (a) comprises:
a first step of depositing a first aluminum by sputtering under conditions that said semiconductor substrate is kept at a first temperature and said first aluminum is deposited at a first deposition rate; and
a second step of depositing a second aluminum by sputtering on said first aluminum under conditions that said semiconductor substrate is kept at a second temperature higher than said first temperature and said second aluminum is deposited at a second deposition rate lower than said first deposition rate, and
wherein said step (k) comprises:
a first step of depositing a third aluminum by sputtering under conditions that said semiconductor substrate is kept at a third temperature and said third aluminum is deposited at a third deposition rate; and
a second step of depositing a fourth aluminum by sputtering on said third aluminum under conditions that said semiconductor substrate is kept at a fourth temperature higher than said third temperature and said fourth aluminum is deposited at a fourth deposition rate lower than said third deposition rate.
2. A method of fabricating a semiconductor integrated circuit device according toclaim 1 , wherein each of the first and second aluminum films contains silicon and copper in addition to aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/872,508US20040235289A1 (en) | 1995-01-11 | 2004-06-22 | Semiconductor integrated circuit device and method for making the same |
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7-2551 | 1995-01-11 | ||
| JP7002551AJPH08191104A (en) | 1995-01-11 | 1995-01-11 | Semiconductor integrated circuit device and manufacturing method thereof |
| US08/584,065US5904556A (en) | 1995-01-11 | 1996-01-11 | Method for making semiconductor integrated circuit device having interconnection structure using tungsten film |
| US09/245,743US6300237B1 (en) | 1995-01-11 | 1999-02-08 | Semiconductor integrated circuit device and method for making the same |
| US09/933,163US6538329B2 (en) | 1995-01-11 | 2001-08-21 | Semiconductor integrated circuit device and method for making the same |
| US09/998,644US6583049B2 (en) | 1995-01-11 | 2001-12-03 | Semiconductor integrated circuit device and method for making the same |
| US10/430,402US6780757B2 (en) | 1995-01-11 | 2003-05-07 | Semiconductor integrated circuit device and method for making the same |
| US10/872,508US20040235289A1 (en) | 1995-01-11 | 2004-06-22 | Semiconductor integrated circuit device and method for making the same |
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| US10/430,402ContinuationUS6780757B2 (en) | 1995-01-11 | 2003-05-07 | Semiconductor integrated circuit device and method for making the same |
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| US08/584,065Expired - LifetimeUS5904556A (en) | 1995-01-11 | 1996-01-11 | Method for making semiconductor integrated circuit device having interconnection structure using tungsten film |
| US09/245,743Expired - LifetimeUS6300237B1 (en) | 1995-01-11 | 1999-02-08 | Semiconductor integrated circuit device and method for making the same |
| US09/933,163Expired - Fee RelatedUS6538329B2 (en) | 1995-01-11 | 2001-08-21 | Semiconductor integrated circuit device and method for making the same |
| US09/998,644Expired - Fee RelatedUS6583049B2 (en) | 1995-01-11 | 2001-12-03 | Semiconductor integrated circuit device and method for making the same |
| US10/430,402Expired - Fee RelatedUS6780757B2 (en) | 1995-01-11 | 2003-05-07 | Semiconductor integrated circuit device and method for making the same |
| US10/872,508AbandonedUS20040235289A1 (en) | 1995-01-11 | 2004-06-22 | Semiconductor integrated circuit device and method for making the same |
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| US08/584,065Expired - LifetimeUS5904556A (en) | 1995-01-11 | 1996-01-11 | Method for making semiconductor integrated circuit device having interconnection structure using tungsten film |
| US09/245,743Expired - LifetimeUS6300237B1 (en) | 1995-01-11 | 1999-02-08 | Semiconductor integrated circuit device and method for making the same |
| US09/933,163Expired - Fee RelatedUS6538329B2 (en) | 1995-01-11 | 2001-08-21 | Semiconductor integrated circuit device and method for making the same |
| US09/998,644Expired - Fee RelatedUS6583049B2 (en) | 1995-01-11 | 2001-12-03 | Semiconductor integrated circuit device and method for making the same |
| US10/430,402Expired - Fee RelatedUS6780757B2 (en) | 1995-01-11 | 2003-05-07 | Semiconductor integrated circuit device and method for making the same |
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| JP (1) | JPH08191104A (en) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| WO2014130452A1 (en)* | 2013-02-19 | 2014-08-28 | Alumiplate, Inc. | Hard aluminum films formed using high current density plating |
Families Citing this family (44)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| JPH09321239A (en)* | 1996-05-30 | 1997-12-12 | Hitachi Ltd | Method for manufacturing semiconductor integrated circuit device |
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| JP2001185552A (en)* | 1999-12-27 | 2001-07-06 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
| JP3449333B2 (en)* | 2000-03-27 | 2003-09-22 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| US20050181600A1 (en)* | 2000-06-30 | 2005-08-18 | Hynix Semiconductor, Inc. | Method of forming a semiconductor device having a Ti/TiN/Ti<002>/a1<111> laminate |
| KR20020004539A (en)* | 2000-07-06 | 2002-01-16 | 박종섭 | Method for forming FeRAM capable of preventing hydrogen diffusion |
| US6683380B2 (en)* | 2000-07-07 | 2004-01-27 | Texas Instruments Incorporated | Integrated circuit with bonding layer over active circuitry |
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Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4017886A (en)* | 1972-10-18 | 1977-04-12 | Hitachi, Ltd. | Discrete semiconductor device having polymer resin as insulator and method for making the same |
| US4782380A (en)* | 1987-01-22 | 1988-11-01 | Advanced Micro Devices, Inc. | Multilayer interconnection for integrated circuit structure having two or more conductive metal layers |
| US4970176A (en)* | 1989-09-29 | 1990-11-13 | Motorola, Inc. | Multiple step metallization process |
| US4994410A (en)* | 1988-04-04 | 1991-02-19 | Motorola, Inc. | Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process |
| US5143865A (en)* | 1988-09-02 | 1992-09-01 | Kabushiki Kaisha Toshiba | Metal bump type semiconductor device and method for manufacturing the same |
| US5356836A (en)* | 1993-08-19 | 1994-10-18 | Industrial Technology Research Institute | Aluminum plug process |
| US5407861A (en)* | 1992-05-27 | 1995-04-18 | Sgs-Thomson Microelectronics, S.R.L. | Metallization over tungsten plugs |
| US5407863A (en)* | 1990-11-30 | 1995-04-18 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| US5420070A (en)* | 1991-10-14 | 1995-05-30 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of interconnection structure of semiconductor device |
| US5529955A (en)* | 1993-08-27 | 1996-06-25 | Yamaha Corporation | Wiring forming method |
| US5567647A (en)* | 1993-12-07 | 1996-10-22 | Nec Corporation | Method for fabricating a gate electrode structure of compound semiconductor device |
| US5614765A (en)* | 1995-06-07 | 1997-03-25 | Advanced Micro Devices, Inc. | Self aligned via dual damascene |
| US5635763A (en)* | 1993-03-22 | 1997-06-03 | Sanyo Electric Co., Ltd. | Semiconductor device having cap-metal layer |
| US5804505A (en)* | 1992-10-27 | 1998-09-08 | Nec Corporation | Method of producing semiconductor device having buried contact structure |
| US5904556A (en)* | 1995-01-11 | 1999-05-18 | Hitachi, Ltd. | Method for making semiconductor integrated circuit device having interconnection structure using tungsten film |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271137B1 (en)* | 1989-11-30 | 2001-08-07 | Stmicroelectronics, Inc. | Method of producing an aluminum stacked contact/via for multilayer |
| JPH07109030B2 (en) | 1991-02-12 | 1995-11-22 | アプライド マテリアルズ インコーポレイテッド | Method for sputtering aluminum layer on semiconductor wafer |
| JPH04296041A (en) | 1991-03-26 | 1992-10-20 | Hitachi Ltd | Semiconductor device and its manufacturing method |
| JPH0547762A (en) | 1991-08-12 | 1993-02-26 | Nec Corp | Method of forming aluminum based wiring |
| US5565378A (en)* | 1992-02-17 | 1996-10-15 | Mitsubishi Denki Kabushiki Kaisha | Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution |
| JP2906815B2 (en) | 1992-03-30 | 1999-06-21 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH07297189A (en) | 1994-04-25 | 1995-11-10 | Sony Corp | Wiring film and its film formation method |
- 1995
- 1995-01-11JPJP7002551Apatent/JPH08191104A/enactivePending
- 1995-12-13TWTW084113309Apatent/TW302531B/zhnot_activeIP Right Cessation
- 1996
- 1996-01-11USUS08/584,065patent/US5904556A/ennot_activeExpired - Lifetime
- 1999
- 1999-02-08USUS09/245,743patent/US6300237B1/ennot_activeExpired - Lifetime
- 2001
- 2001-08-21USUS09/933,163patent/US6538329B2/ennot_activeExpired - Fee Related
- 2001-12-03USUS09/998,644patent/US6583049B2/ennot_activeExpired - Fee Related
- 2003
- 2003-05-07USUS10/430,402patent/US6780757B2/ennot_activeExpired - Fee Related
- 2004
- 2004-06-22USUS10/872,508patent/US20040235289A1/ennot_activeAbandoned
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4017886A (en)* | 1972-10-18 | 1977-04-12 | Hitachi, Ltd. | Discrete semiconductor device having polymer resin as insulator and method for making the same |
| US4782380A (en)* | 1987-01-22 | 1988-11-01 | Advanced Micro Devices, Inc. | Multilayer interconnection for integrated circuit structure having two or more conductive metal layers |
| US4994410A (en)* | 1988-04-04 | 1991-02-19 | Motorola, Inc. | Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process |
| US5143865A (en)* | 1988-09-02 | 1992-09-01 | Kabushiki Kaisha Toshiba | Metal bump type semiconductor device and method for manufacturing the same |
| US4970176A (en)* | 1989-09-29 | 1990-11-13 | Motorola, Inc. | Multiple step metallization process |
| US5407863A (en)* | 1990-11-30 | 1995-04-18 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| US5420070A (en)* | 1991-10-14 | 1995-05-30 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of interconnection structure of semiconductor device |
| US5407861A (en)* | 1992-05-27 | 1995-04-18 | Sgs-Thomson Microelectronics, S.R.L. | Metallization over tungsten plugs |
| US5804505A (en)* | 1992-10-27 | 1998-09-08 | Nec Corporation | Method of producing semiconductor device having buried contact structure |
| US5635763A (en)* | 1993-03-22 | 1997-06-03 | Sanyo Electric Co., Ltd. | Semiconductor device having cap-metal layer |
| US5356836A (en)* | 1993-08-19 | 1994-10-18 | Industrial Technology Research Institute | Aluminum plug process |
| US5529955A (en)* | 1993-08-27 | 1996-06-25 | Yamaha Corporation | Wiring forming method |
| US5567647A (en)* | 1993-12-07 | 1996-10-22 | Nec Corporation | Method for fabricating a gate electrode structure of compound semiconductor device |
| US5904556A (en)* | 1995-01-11 | 1999-05-18 | Hitachi, Ltd. | Method for making semiconductor integrated circuit device having interconnection structure using tungsten film |
| US5614765A (en)* | 1995-06-07 | 1997-03-25 | Advanced Micro Devices, Inc. | Self aligned via dual damascene |
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| US20110183513A1 (en)* | 2005-07-06 | 2011-07-28 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
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| US20080286964A1 (en)* | 2005-07-06 | 2008-11-20 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US10600683B2 (en) | 2005-07-06 | 2020-03-24 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
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| US10000859B2 (en) | 2013-02-19 | 2018-06-19 | Alumiplate, Inc. | Hard aluminum films formed using high current density plating |
| WO2014130452A1 (en)* | 2013-02-19 | 2014-08-28 | Alumiplate, Inc. | Hard aluminum films formed using high current density plating |
Also Published As
| Publication number | Publication date |
|---|---|
| US6583049B2 (en) | 2003-06-24 |
| TW302531B (en) | 1997-04-11 |
| US6538329B2 (en) | 2003-03-25 |
| US6300237B1 (en) | 2001-10-09 |
| US6780757B2 (en) | 2004-08-24 |
| JPH08191104A (en) | 1996-07-23 |
| US5904556A (en) | 1999-05-18 |
| US20020019124A1 (en) | 2002-02-14 |
| US20030199161A1 (en) | 2003-10-23 |
| US20020115281A1 (en) | 2002-08-22 |
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