US20040221188A1 - Apparatus and method for providing a clock signal for testing - Google Patents

Abstract

A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during normal operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device's internal circuitry is responsive to the test clock signal during the test mode of operation.

Description

CROSS-RELATED APPLICATIONS
• This application is a continuation of U.S. application Ser. No. 09/507,302, filed Feb. 18, 2000, entitled “Apparatus and Method For Providing A Clock Signal For Testing,” which is incorporated by reference herein in its entirety.[0001]
FIELD OF THE INVENTION
• The present invention relates to an apparatus for and a method of providing a clock signal for testing a device.[0002]
BACKGROUND OF THE INVENTION
• Semiconductor memories are used to store information in computer systems. As processor speeds continue to increase, the capacity and data rate of memory devices also continues to increase. Typically the processor accesses data at a much higher data rate than the data rate of the memories. In a memory system, a memory controller provides an interface between the memories and the processor. The memory controller and memories are designed to operate in accordance with predefined specifications. During the manufacturing process, the memory controller and memories are tested to ensure that they operate in accordance with the specifications. For example, the memory controller has inputs or pins that transmit and receive external clock signals, control signals and data signals. To test the memory controller, the memory controller is placed in a socket at a test station and the external clock signal and data signals are supplied, varied, and the performance of the memory controller is measured. As data rates increase, the frequency of the external clock signal increases. Supplying an external high speed clock requires an expensive high speed tester. Memory controllers are becoming increasingly sophisticated and may provide an internal high speed clock signal. Therefore, to reduce cost and simplify testing, an apparatus and method that uses the internal high speed clock for testing the memory controller is needed.[0003]
SUMMARY OF THE INVENTION
• In summary, the present invention provides a clock signal driven device that has a clock pin for receiving an externally generated clock signal during a normal mode of operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during the normal mode of operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device's internal circuitry is responsive to the test clock signal during the test mode of operation.[0004]
• In a preferred embodiment, the device has two clock pins that receive externally generated differential clock signals, and the internal clock generator generates a pair of differential test clock signals that are asserted on the two clock pins. A set of clock current control bits are stored in a register. The internal clock generator includes a plurality of clock output drivers for generating each test clock signal, with each of the clock output drivers being selectively enabled by a corresponding one of the clock current control bits. Each clock output driver preferably includes a slew rate controlled predrive circuit that generates an intermediate clock signal having a slew rate in accordance with a set of slew rate control bits stored in a slew rate control register.[0005]
BRIEF DESCRIPTION OF THE DRAWINGS
• Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:[0006]
• FIG. 1 is a block diagram a memory system including a memory controller and memories during normal operation, the memory controller and memories having a clock interface circuit that generates an internal clock signal during testing in accordance with an embodiment of the present invention.[0007]
• FIG. 2 is a block diagram of an alternate embodiment the memory system of FIG. 1 that uses differential clock signaling including a clock-to-master (CTM) signal and a complementary clock-to-master (/CTM) signal.[0008]
• FIG. 3 is a block diagram of an exemplary device that generates an internal CTM clock signal in accordance with an embodiment of the present invention.[0009]
• FIG. 4 is a block diagram of the memory controller in a test environment which emulates the memory systems of FIGS. 1 and 2 during normal operation.[0010]
• FIG. 5 is a circuit diagram of an exemplary data output driver of FIG. 4.[0011]
• FIG. 6 is a circuit diagram of the internal CTM clock generator of FIG. 4.[0012]
• FIG. 7 is a circuit diagram of an exemplary slew rate controlled predriver of FIGS. 5 and 6.[0013]
• FIG. 8 is a flowchart of a method of setting clock current control bits of a clock current control register of FIG. 3.[0014]
DESCRIPTION OF THE PREFERRED EMBODIMENTS
• In FIG. 1, the overall architecture of a[0015]bus20 using a single-ended clock signal is shown. Thebus20 interconnects amemory controller22 and memories24. In thememory controller22 and memories24, a bus interface (Bus I/F)30 provides the connections to and signaling with thebus20. Thebus20 is formed of signal lines20-1,20-2,20-3 and20-4 that transmit control, data and clock signals. Physically, on eachdevice22,24, the control, data and clock signals are supplied to and output from external connections, calledpins32, and thesignal lines20 interconnectrespective pins32 on different devices. Eachdevice22,24 has busoutput driver circuits34 that connect to thepins32 to transmit signals to other devices attached to thebus20. In a device, each busoutput driver circuit34 drives a single signal line of thebus20. For example, bus output driver34-1 in thememory controller22 drives signal line20-1. The device may be implemented using one set of signals, such as CMOS signals, while the bus may be implemented using bus signals different from the CMOS signals. In one implementation, the CMOS signals use a first set of voltage levels to represent information, while the bus uses a second set of voltage levels. The first set of voltage levels is different from the second set of voltage levels. The first and second sets of voltage levels may have different voltage swings. Alternately, the first and second sets of voltage levels may also use different numbers of predefined voltage levels to encode information. Although multiplebus output drivers34 are attached to a single signal line, logic in the bus interface30 synchronizes the transmission of data among the devices on the bus so that the devices transmit data at times such that the receivers will properly decode the data. Thebus20 supports signaling with characteristics that are a function of many factors such as the system clock speed, the bus length, the amount of current that the output driver circuits can drive, the supply voltages, the spacing and width of the wires or traces making up thebus20, the physical layout of thebus20 itself and the resistance of a terminating resistor Z₀36 that may be attached to some of the signal lines of thebus20.
• The[0016]bus20 uses current mode signaling. Theoutput driver circuits34 are designed to drive thebus20 with a predetermined amount of current; and thebus receivers38 are designed to receive the signals sent by theoutput driver circuits34 on thebus20. The amount of current used to drive the bus is determined, at least in part, by theoutput driver circuits34 and terminating resistors Z₀36.
• A subset of the[0017]signal lines20 connect to terminating resistors Z₀36 which connect to a termination voltage V_TERM. In one embodiment, the resistance of the terminating resistors Z₀36 is equal to twenty-eight ohms. The termination voltage V_TERMcan be different from the supply voltage V_DD. For instance, the supply voltage V_DDmay be equal to 2.5 volts while the termination voltage V_TERMis equal to 1.8 volts. With respect to the bus signals, the termination voltage V_TERMrepresents a logical zero. When driving the logical zero, theoutput driver circuit34 does not drive current on itsrespective signal line20. The bus voltage for a signal at a low level V_OL, which represents a logical one, is equal to approximately 1 volt. When driving the logical one, theoutput driver circuit34 drives approximately 36 milliamps on thesignal line20. The voltage swing of the signal line is 0.8 volts. In an alternate embodiment, the bus voltage for a signal at the low voltage level represents a logical zero, while the bus termination voltage V_TERMrepresents a logical one.
• In one embodiment, the memories[0018]24 are random access memories (RAMs). In an alternate embodiment, the memories24 are read-only memories (ROMs). Alternately, the bus interface30 is implemented in other semiconductor devices that use abus20 to interconnect various types of integrated circuits such as microprocessors and disk controllers.
• In the exemplary memory system of FIG. 1, the[0019]memory controller22 supplies an address to the memory24-1 using the control signal line20-1 to transmit one bit of the address. For simplicity, the other control signal lines are not shown. In the memory24-1, a bus receiver38-3 receives the address bit and passes the received address to adecoder42. To receive the entire address, thedecoder42 receives address bits from multiple bus receivers. For simplicity, only one bus receiver38-3 is shown. Thedecoder42 generates the signals to access the data stored at a particular row and column of amemory cell array44. To read data from the memory24, in response to thedecoder42 and other control signals from thebus20, thememory cell array44 supplies data from the desired address to an input/output (I/O)buffer46 which supplies the data to the bus20-2 via the output driver34-4. To write data to the memory, thememory controller22 supplies an address as described above. Thememory controller22 also supplies data signals via theoutput driver circuits34 to thebus20. The memory24-1 receives the address as described above, and also receives the data signals via the receiver38-4 and passes the data to thememory cell array44 for storage via the I/O buffer46.
• A single-ended clock signal synchronizes the bidirectional transmission of data on the[0020]bus20. When memory devices24 transmit data towards thememory controller22, a clock-to-master (CTM) signal synchronizes the data transmission. Aclock generator48 supplies the CTM signal on clock signal line20-3. Themaster device22 supplies the clock-from-master signal on clock signal line20-4 which is terminated by resistor36-4. On eachdevice22,24, a CTM pin32-3,32-7,32-9 receives the CTM signal. In the bus interface30, aclock interface circuit54 receives the CTM signal from the CTM pin32-3 at theCTM node50.
• When the[0021]memory controller22 transmits data and/or control signals to a memory device24, the clock-from-master (CFM) signal synchronizes the transmission on thebus20. The bus interface30 of thememory controller22 provides the CFM signal to clock signal line20-4 via CFM pin32-4. In the bus interface30, theCTM node50 is connected to the CFM pin32-4. In this way, the CTM signal becomes the CFM signal. The CFM signal is transmitted via the CFM pin32-4 on signal line20-4 which is terminated by resistor36-4. On each device24, a CFM pin32-7 and32-10 receives the CFM signal from thememory controller22.
• FIG. 2 is an alternate embodiment of the bus system of FIG. 1 that uses differential clock signals. Complementary CTM and CFM signals, /CTM and /CFM, respectively, are used in addition to the CTM and CFM signals. The bus interface[0022]30 of each memory device24 overlays the bus signal lines20. Theclock generator48 supplies the /CTM signal on signal line20-5 which is received at the /CTM pin32-15 on each device24 and at the /CTM pin32-13 of thememory controller22. A /CTM node52 connects the /CTM pin32-13 to a /CFM pin32-14 and the /CTM signal becomes the /CFM signal. The /CTM signal is received at a /CFM pin32-16 on each device24.
• As shown in FIG. 3, the[0023]exemplary memory controller22 has the bus interface30 and acore62. In one implementation, the bus interface30 is a library macrocell that is used in application specific integrated circuit (ASIC) designs to interface the core of a CMOS ASIC device to a high-speed bus20. The CMOS ASIC device may be the memory controller22 (FIG. 1), the memory device24 (FIG. 1) or other integrated circuit.
• The[0024]core62 is the portion of a device that implements a specified function. In this example, thecore62 includes memory controller logic. In another example, referring back to FIG. 1, in a memory24, thecore62 includes thedecoder42,memory array44 and I/O buffer46.
• In FIG. 3, the bus interface[0025]30 provides the circuitry and signaling to allow the core62 to communicate with other devices on thebus20. One function of the bus interface30 is to provide an interface between a slow, wide internal CMOS bus to the hi-speednarrow device bus20. The data, control and clock pins,64,66,32-3 and32-13, connect to the control, data and clock signal lines,72,74,20-3 and20-5, respectively, of thebus20. For simplicity, a single data signal line72, control signal line74,data pin64 and control pin68 are shown. As described above, eachdata pin64 connects to areceiver38 and to anoutput driver34.Other output drivers34 transmit the control signals onto the control signal lines74 via control pins66.
• During normal operation, the external clock signals, the CTM and /CTM signals, are supplied to the CTM and /CTM clock input pins,[0026]32-3 and32-13, by an external clock source via the CTM and /CTM clock signal lines,20-3 and20-13, respectively.
• During testing, the[0027]device22 internally generates the CTM and /CTM signals, rather than receiving the CTM and /CTM signals from an external source. In thecore62, a phase-locked loop (PLL)80 supplies an internal PLL clock signal to theclock interface circuit54. The internal PLL clock signal has a frequency approximately equal to 400 MHz, and uses CMOS voltage levels rather than the voltage levels of thebus20. Theclock interface circuit54 generates internal CTM and /CTM signals from the internal PLL clock signal. The internal CTM and /CTM signals have substantially the same high voltage level, low voltage level, slew rate and frequency as the externally supplied clock signals. In particular, like the external CTM and /CTM clock signals, the internal CTM and /CTM clock signals have a frequency approximately equal to 400 MHz, a high voltage of about 1.8 volts and a low voltage of approximately 1 volt.
• The[0028]clock interface circuit54 receives the CTM and /CTM signals from the CTM and /CTM nodes, respectively, and generates a ˜0° clock signal and a ˜90° clock signal, and a ˜/0° clock signal and a ˜/90° clock signal from the CTM and /CTM signals, respectively, to synchronize the transmission of data over thebus20. The specified number of degrees, such as 0° , in the signal name describes the approximate phase shift of that signal with respect to the CTM and /CTM clock signals atnodes50 and52, whether supplied externally or generated internally. The tilde (˜) indicates that the respective clock signal includes an offset with respect to the actual transmission time of the data over thebus20 at pins64.
• A data current control register[0029]82 sets the amount of drive current that thedata output drivers34 use to drive an outgoing data signal onto a data signal line of the bus. A clockcurrent control register84 connects to theclock interface circuit54 to set the amount of drive current to drive the internal clock signals during testing. Theclock interface circuit54 will be further described with reference to FIG. 6.
• A slew rate control (SRC) register[0030]86 supplies slew rate control bits to theoutput drivers34 to set the slew rate of the data and control signals. The SRC register86 also supplies the slew rate control bits to theclock interface circuit54 to set the slew rate of the internal CTM and /CTM clock signals.
• A[0031]logic circuit88 connects to the datacurrent control register82, clockcurrent control register84 and slewrate control register86. Thelogic circuit88 determines operational values for the data current control bits, the clock current control bits and slew rate control bits in the datacurrent control register82, the clockcurrent control register84 and the slewrate control register86, respectively.
• In FIG. 4, the overall architecture of the[0032]clock interface circuit54 of the bus interface in thememory controller22 in accordance with an embodiment of the present invention is shown. The data receiver38-2 receives the data signal from the data pin32-2 and the ˜0° clock signal, and outputs a received data signal. The data signal at pin32-2 is received in accordance with an ideal 0° clock signal, the CTM signal. The ˜0° clock signal is offset with respect to the actual appearance of the data signal at data pin32-2 by the set-up time of the receiver. Similarly, other data receivers receive data in accordance with the ˜/0° clock signal which is offset with respect to the actual appearance of the data signal at the data pins by the set-up time of the receivers. In other words, the ˜/0° clock signal is offset with respect to the /CTM signal.
• The data output drive circuit[0033]34-2 drives data to be output onto the data signal line20-2 in accordance with the ˜90° clock signal, data current control register and slew rate control register of FIG. 3. The ˜90° clock signal includes an offset with respect to the ideal data transmission time at data pin32-2. The offset is substantially equal to a delay of a predriver circuit in the output drive circuit34-2. Because of the offset, the output driver circuit34-2 transmits data at pin32-2 at the ideal data transmission time, that is, synchronized to the CFM clock. Similarly, other data output drive circuits drive data onto the data signal line in accordance with the complementary ˜/90° clock signal. The ˜/90° clock signal also includes the offset of the predriver, and transmits data at pin32-2 at the ideal complementary data transmission time, that is, synchronized to the /CFM clock.
• During testing, termination resistor[0034]36-2 connects the data pin32-2 to the termination voltage V_TERM. The resistor36-2 has an impedance Z₀substantially equal to 28 ohms. Thecylinder92 on the data signal line20-2 represents the impedance of the data signal line20-2 which is substantially equal to the impedance of the termination resistor36-2, that is, 28 ohms.
• The[0035]clock interface circuit54 includes a delay-locked loop (DLL)94 that receives the CTM and /CTM signals from the CTM and /CTM nodes,50 and52, respectively. TheDLL94 generates the ˜0° clock signal and the ˜/90° clock signal from the incoming CTM signal at theCTM node50. TheDLL94 generates the ˜90° clock signal by delaying the incoming CTM signal from theCTM node50. The ˜0° clock signal and the ˜90° clock signal are supplied to at least a subset of theoutput drivers34 andreceivers38 to synchronize the timing of data transmission between thedevice22 and thebus20. Similar to the ˜0° and ˜90° clock signals, theDLL94 also generates the complementary ˜/0° and ˜/90° clock signals from the /CTM signal at the /CTM node52. TheDLL94 supplies the ˜/0° and ˜/90° clock signals to at least a subset of thedata output drivers34 and receivers to synchronize the timing of data transmission between thedevice22 and thebus20.
• When the[0036]device22 is tested, atest clock generator100 in theclock interface circuit54 generates and provides the internal CTM and /CTM clock signals at the CTM and /CTM nodes,50 and52, rather than receiving the external CTM and /CTM clock signals, respectively.
• The[0037]PLL80 supplies the internal PLL clock signal totri-state inverter104. During testing, a PLL clock enable signal from a control register in the bus interface activates thetri-state inverter104. When active, thetri-state inverter104 supplies the internal PLL clock signal to atest circuit106 and acomplementary test circuit108 in the test-clock generator100. Thetest circuit106 provides the internal CTM clock signal to theCTM node50. Thecomplementary test circuit108 provides the complementary internal /CTM clock signal to the /CTM node52.
• For testing, the[0038]device22 is placed in a test socket at a testing station. Unlike in normal operation, in test operation, to prevent undesirable reflections while using the internal clock signals, the CTM, CFM, /CTM and /CFM pins,32-3,32-4,32-13 and32-14, are pulled up to the termination voltage V_TERMvia 28 ohm termination resistors,112,114,116 and118, respectively.
• FIG. 5 is a circuit diagram of an exemplary data output driver[0039]34-2 of FIG. 4 that alternately outputs even and odd data on opposite phases of the ˜90° clock signal. Because the data and control output drivers are the same, the description of data output driver34-2 also applies to the control output drivers34-1. The data output driver34-2 connects to data pin32-2 which is pulled-up to the termination voltage by the termination resistor36-2 which has an impedance of 28 ohms. The data output driver34-2 has one or more current-control-data-output circuits132 that are connected together atdata node134. Each current-control-data-output circuit132 drives thedata node134 with a predetermined amount of drive current in response to a distinct current control bit. Current control data output circuit132-1 is responsive tocurrent control bit0, and current control data output circuit132-2 is responsive to current control bit N.
• Each current-control-data-output circuit[0040]132 has a data input circuit136, a even-odd multiplexing circuit138, a slew-rate-controlled (SRC) predriver140, and an output-data-drive block142. The output-data-drive block142 has an NMOS drive transistor144 that sinks a predetermined amount of current from thedata node134 to ground in response to an intermediate data signal provided by the SRC predriver140 to its gate. The amount of current that the NMOS drive transistor144 sinks is determined by its width and length. The NMOS drive transistors144 of the current-control-data-output circuits132 are binary weighted with respect to each other. For example, the NMOS drive transistor144-1 of the current-control-data-output circuit132-1 associated with current control bit0 (CC<0>) is sized to sink an amount of drive current equal to I₀, while the NMOS drive transistor144-2 of the current-control-data-output circuit associated with current control bit1 (CC<1>) is sized to sink an amount of drive current equal to one-half of I₀. More generally, where i represents the particular current control bit associated with a current-control-data-output circuit132, the corresponding NMOS drive transistor144 of the current-control-data-output circuit132 associated with current control bit i (CC<i>) is sized to sink an amount of drive current Ii in accordance with relationship (1) as follows:$\begin{array}{cc}{I}_i=\frac{1}{2^i}I_o& \left(1\right)\end{array}$

  
• In sum, all of the current-control-data-output circuits[0041]132 are the same, except for receiving a distinct current control bit and having an NMOS drive transistor144 with a distinct binary weighting.
• The data input circuit[0042]136 receives data bits to be output as even and odd data. The even data bit is output on the rising edge of the ˜90° clock signal, and the odd data bit is output on the falling edge of the ˜90° clock signal. The data input circuit136 also receives one of the current control bits that determines whether a respective current-control-data output circuit132 will drive thedata node134. In the data input circuit136, a first ANDgate146 receives the even-data and a second ANDgate148 receives the odd data. Both the first and second AND gates,146 and148, respectively, receive the current control bit. When the current control bit is a digital one, the first and second AND gates,146 and148, allow the even-data and the odd-data to be output, respectively. For example, when current control bit0 (cc<0>) is a digital one and the even-data is a digital one, the first ANDgate146 outputs a digital one. When current control bit0 (cc<0>) is a digital zero, the first and second AND gates,146 and148, respectively, output a digital zero, regardless of the state of the even and odd data, and that current-control-data-output circuit132-1 does not drive current from thedata node134.
• In the even-odd-multiplexing circuit[0043]138, first and second tri-state inverters,152 and154, receive the even and odd data signals from the first and second AND gates,146 and148, respectively. The outputs of the first and second tri-state inverters,152 and154, respectively, are connected together. The ˜90° clock signal is supplied to complementary enable inputs on the first and second tri-state inverters,152 and154, to alternately output the even and odd data signals, respectively, during alternate phases of the ˜90° clock signal as a multiplexed-data signal. The multiplexed-data signal is supplied to the slew-rate-controlledpredriver140, and subsequently to the output-data-drive block142. The slew-rate-controlledpredriver140 will be further described with respect to FIG. 7.
• FIG. 6 includes a more detailed circuit diagram of the[0044]test clock generator100 of FIG. 4. Thetest clock generator100 provides internal CTM and /CTM clock signals with substantially the same characteristics as the external CTM and /CTM clock signals that are provided during normal operation, thereby eliminating the need for an external clock generator. The internal CTM and /CTM clock signals have substantially the same frequency, duty cycle, slew rate, low output voltage, high output voltage, and voltage range as the external clock signals. Because the present invention supplies the internal CTM and /CTM clock signals to the CTM and /CTM nodes,50 and52, respectively, probes can be attached to the CTM, CFM, /CTM and /CFM output pins,32-3,32-4,32-13, and32-14, respectively, to monitor the respective signals which provides additional testing capability.
• For example, the[0045]DLL94 supplies the ˜90° clock signal to the output driver circuit34-1 (FIG. 4). During testing, the ˜90° clock signal is derived from the internal CTM clock signal atnode50, and has a ˜90° phase shift with respect to the internal CTM clock signal. In other words, the ˜90° clock signal includes the offset for the predriver with respect to the internal CTM clock signal. Therefore, the output data will be shifted 90° with respect to the internal CTM clock signal. If thedevice22 fails a test, to further identify the cause of the failure, probes can be attached to the data pin32-1, the CTM pin32-3 and /CTM pin32-13 to display the signals on a display and examine the relationship between their timing.
• Because the CTM, CFM, /CTM and /CFM pins,[0046]32-3,32-4,32-5 and32-6, respectively, are connected during testing to terminatingresistors112,114,116 and118 having the same resistance as the terminating resistors in normal operation, twice as much drive current is needed to drive the CTM and /CTM nodes,50 and52, respectively, during testing as compared to normal operation. The amount of drive current to drive the data and clock signals to the same low output voltage also depends on process, temperature and internal device characteristics. To more precisely adjust the drive current to provide an internal clock signal with substantially the same characteristics as the external clock signal, the test circuit uses one or more current-controlled-clock output circuits170 that are similar to the current-controlled-data output circuits132 of FIG. 5.
• The current-controlled-clock output circuits[0047]170 are connected to theCTM node50. Each current-controlled-clock output circuit170 drives a predetermined amount of current from theCTM node50 in response to a respective a distinct clock current control bit from the clock current control register84 (FIG. 3). In thetest circuit106, the number of clock current control bits and the number of current-controlled-clock output circuits170 is preferably the same as the number of data current control bits and current-control-data-output circuits132, respectively, of the data output driver32-1 (FIG. 5).
• In the data input block[0048]172 of the current-controlled-clock output circuit170, the data input is fixed. The input of the ANDgate174 is connected to the supply voltage to fix the even data signal to a digital one rather than receiving an even data signal. The input to the ANDgate176 is connected to ground to fix the odd data signal to a digital zero, rather than receiving an odd data signal. Because the data input to the second ANDgate174 is a digital zero, that is, one input to the second ANDgate174 is connected to ground, the second ANDgate174 always outputs a digital zero, regardless of the state of the current control bit for that ANDgate174. When the current control bit associated with the data input block becomes active, the first AND gate172 outputs a digital one.
• The even-odd-multiplexing circuit[0049]138 and the slew-rate-controlledpredriver140 are the same as the even-odd-multiplexing circuit138 of the data output driver34-1. When the internal PLL clock enable signal is active and thePLL clock buffer104 is enabled, the internal PLL clock signal alternately enables and disables the respective tri-state inverters of the even-odd-multiplexing circuit to alternately output a “1” and a “0”.
• The slew-rate-controlled[0050]predriver140 is the same as the slew-rate-controlledpredriver140 of the data output driver. The slew-rate-controlledpredriver140 receives the output of theinverters152,154, and the same slew rate control bits as the slew-rate-controlledpredriver140 of the data output driver. The slew rate control register86 (FIG. 3) sets the slew rate of the transitions of the internal CTM clock signal. The slew-rate-controlledpredriver140 outputs an adjusted clock signal.
• In the output drive block[0051]180, the adjusted clock signal alternately activates and deactivates theNMOS drive transistors182,184 to generate the internal CTM clock signal atnode50. Since the internal PLL clock signal has a fifty percent duty cycle and the even input data is fixed to a digital one and the odd input data is fixed to a digital zero, the internal clock signal has a fifty percent duty cycle.
• Because the CTM and CFM pins are both pulled up to 28 ohms, the combined impedance at the[0052]CTM node50 is 14 ohms rather than 28 ohms and twice as much drive current is needed to drive theCTM node50. Similarly, twice as much drive current is needed to drive the /CTM node52. Because twice as much drive current is needed to drive the CTM and /CTM nodes, each current-controlled-clock output circuits170 sinks twice as much current as its respective current-controlled-data output circuits132 counterpart. In addition, because the CTM and CFM pins,32-3 and32-4, are both connected to the termination voltage V_TERMvia terminatingresistors112 and114, respectively, during testing, for the internal CTM clock signal to have the same low output voltage, high output voltage, voltage swing, and slew rate as the external clock signal, the output-clock-drive blocks180 of thetest circuit106 have twooutput drive transistors182,184, rather than the one output drive transistor144 of the data output driver34-1 (FIG. 5). Eachdrive transistor182,184 has the same geometry (and thus the same operating characteristics) as its respective drive transistor144 of its counterpart current-controlled-data output circuit132.
• Similar to the output-data-drive blocks[0053]132 (FIG. 5), the output-clock-drive blocks170 of thetest circuit106 have binary-weightedNMOS transistors182 and184. In particular, eachNMOS transistor182,184 of an output-clock-drive block circuit170 has the same geometry as the NMOS transistor output-data drive block132 that receives the corresponding data current control bit. Therefore, the drive transistors of the output-clock-drive blocks170 closely match and have the same process variation as the drive transistors of the output-data-drive blocks.
• In an alternate embodiment, a single NMOS drive transistor is provided in the output drive block of the adjustment circuit rather than two NMOS drive transistors. The single NMOS drive transistor is sized to sink the same amount of current as the two NMOS drive transistors. Because the single NMOS drive transistor does not have the same geometry as the drive transistors of the data output drivers, the single NMOS drive transistor has different operating characteristics with respect to process variation and the internal clock signal may not provide the same low output voltage, voltage range and slew rate as the dual NMOS driver transistor embodiment.[0054]
• The complementary internal clock signals, /CTM and /CFM, are provided via the /CTM and /CFM pins, which are connected together at the /[0055]CTM node52. The /CTM node52 is connected to a complementary-test circuit108. The complementary-test circuit is the same as thetest circuit106 that was described above, except that in the data input block the “1” and “0” are supplied to opposite AND gates.
• FIG. 7 is a circuit diagram of an exemplary slew rate controlled[0056]pre-driver140 used with the present invention. The SRC predriver140 has a plurality ofpredriver sub-blocks202,204,206. The number of predriver sub-blocks may be more or less than the three shown in FIG. 7, depending on the amount of slew rate control required. Generally, there will be one more predriver sub-block than there are Slew Rate Control bits.
• Each[0057]predriver sub-block202,204,206 has aninverter208,210,212 and apassgate pair214,216,218 respectively. Onepredriver sub-block202 is always enabled with the gate of each transistor of thepassgate pair214 connected to the supply voltage Vcc and to ground, respectively. The other passgate pairs216,218 of thepredriver sub-blocks204,206 connect to the slew rate control bits, Slew Rate Control <0> and Slew Rate Control <1>. The slew rate of thepredriver140 is adjusted by enabling and disabling thepassgates216,218 with slew rate control signals on the slew rate control bits.
• In particular, when the slew rate control signal on Slew Rate Control bit <[0058]1> is high, the passgate pair216 of thepredriver sub-block204 is enabled. The passgate pair216 increases the rate of transition between a high voltage level and a low voltage level of an intermediate signal onnode220. When the slew rate control bit <1> is low, the corresponding passgate pair216 of thepredriver sub-block204 is effectively disabled and the slew rate is unaffected. Enabling the additional passgate pairs ofadditional predriver sub-blocks206 further increases the slew rate of the q-node signal.
• FIG. 8 is a flowchart of a method of setting clock current control bits of a clock current control register of FIG. 5. In[0059]step240, the logic circuit88 (FIG. 3) sets the clock current control bits of the clock current control register84 (FIG. 3) to a predetermined initial value that guarantees the generation of a clock signal. Instep242, the logic circuit88 (FIG. 3) sets the data current control bits of the data current control register82 (FIG. 3) to another predetermined initial value. Instep244, the logic circuit88 (FIG. 3) adjusts the setting of the data current control bits to provide adjusted data current control bits so that a specified rail-to-rail voltage swing on the bus is maintained. Instep246, the logic circuit88 (FIG. 3) updates the clock current control bits of the clock current control register84 (FIG. 3) to the same value as the adjusted data current control bits. Instep248, after setting the clock current control bits, device testing continues.
• U.S. Pat. No. 5,254,883, to Horowitz et al. is hereby incorporated by reference in its entirety as background information on a method of setting the data current control bits. U.S. patent application Ser. No. 09/222,590 to Stark et al. is hereby incorporated by reference in its entirety as background information of an alternate embodiment of an output driver and a method of setting the data current control bits.[0060]
• During testing, the slew rate control bits are simultaneously adjusted for both the output drivers and the[0061]test clock generator100. While calibrating the current control bits, the voltage level of the output data signal changes. To set data current control bits to a desired operating value, a stable internal clock is supplied to the DLL94 (FIG. 3) so that the 9020 clock signal is guaranteed to be supplied to the output drivers. If the clock current control bits were to be changed while calibrating the data current control bits, the internal clock signal and therefore the 90° clock signal may disappear and testing would fail. Therefore, the current control bits for theinternal clock generator100 are stored in a separate register, the clock current control register84 (FIG. 3), from the data current control register82 (FIG. 2) that stores the data current control bits.
• The predetermined initial value of the clock and data current control bits depends on the process used to manufacture the device and the specification of the bus. Although the predetermined initial value of the clock current control bits may not be the final value, the predetermined initial value is sufficient to ensure that the 90° clock signal will be generated.[0062]
• Although the invention was described with respect to a memory controller, in another embodiment, the bus interface of the present invention provides a high-speed device-to-device interface. In an alternate embodiment, the bus interface is used in the memory devices[0063]24 (FIG. 1). When using the test-clock generator100 (FIG. 4) in a memory device24, the CTM and CFM pins, and the /CTM and /CFM pins, are not shorted together. Rather, the memory device uses two pairs of differential clock signals to control their operation. The test-clock generator100 for memory devices24 therefore generates two pairs of differential clock signals, instead of just one pair of differential clock signals as described above for the test-clock generator for thememory controller device22. All four external clock pins for the device are connected to termination resistors112-118 during the test mode of operation.
• While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.[0064]

Claims (32)

What is claimed is:

1. A memory controller, comprising:

a phase compensation circuit adapted for receiving a first clock signal, the phase compensation circuit configured to use the first clock signal to synchronize data communications between the memory controller and a memory device during a first mode of operation; and

a clock generator circuit coupled to the phase compensation circuit and configured to provide a second clock signal to the phase compensation circuit during a second mode of operation, wherein the first and second clock signals have at least one substantially similar signal characteristic.

2. The memory controller ofclaim 1, wherein the clock generator circuit provides differential clock signals.

3. The memory controller ofclaim 1, wherein the first and second clock signals have substantially the same voltage levels.

4. The memory controller ofclaim 1, wherein the first and second clock signals have substantially the same frequency.

5. The memory controller ofclaim 4, wherein the frequency is about 400 MHz.

6. The memory controller ofclaim 1, further comprising:

an output driver circuit coupled to the phase compensation circuit and to at least one data output node, the output driver circuit configured to drive outgoing data signals on the data output node.

7. The memory controller ofclaim 6, further comprising:

a drive current control register coupled to the output driver circuit and configured to set an amount of drive current that the output driver circuit uses to drive the outgoing data signal on the data output node.

8. The memory controller ofclaim 6, further comprising:

a slew rate control register coupled to the output driver circuit and storing slew rate control data for configuring the output driver circuit to control slew rates of data signals applied to the data output node.

9. The memory controller ofclaim 1, further comprising:

a clock current register coupled to the clock generator circuit and configured to set an amount of drive current that the clock generator circuit uses to drive the second clock signal on a clock output node.

10. A memory device, comprising:

a phase compensation circuit adapted for receiving a first clock signal, the phase compensation circuit configured to use the first clock signal to synchronize data communications between the memory device and a memory controller during a first mode of operation; and

a clock generator circuit coupled to the phase compensation circuit during a second mode of operation, and configured to provide a second clock signal to the phase compensation circuit, wherein the first and second clock signals have at least one substantially similar signal characteristic.

11. The memory device ofclaim 10, wherein the clock generator circuit provides differential clock signals.

12. The memory device ofclaim 11, wherein the clock generator circuit generates two pairs of differential clock signals.

13. The memory device ofclaim 10, wherein the first and second clock signals have substantially the same voltage levels.

14. The memory device ofclaim 10, wherein the first and second clock signals have substantially the same frequency.

15. The memory device ofclaim 14, wherein the frequency is about 400 MHz.

16. The memory device ofclaim 10, further comprising:

an output driver circuit coupled to the phase compensation circuit and to at least one data output node, the output driver circuit configured to drive outgoing data signals on the data output node.

17. The memory device ofclaim 16, further comprising:

a drive current control register coupled to the output driver circuit and configured to set an amount of drive current that the output driver circuit use to drive the outgoing data signal on the data output node.

18. The memory device ofclaim 16, further comprising:

a slew rate control register coupled to the output driver circuit and storing slew rate control data for configuring the output driver circuit to control slew rates of data signals applied to the data output node.

19. The memory device ofclaim 16, further comprising:

a clock current register coupled to the clock generator circuit and configured to set an amount of drive current that the clock generator circuit uses to drive the second clock signal on a clock output node.

20. A method of providing clock signals for testing a memory controller, comprising:

in the memory controller:

generating a test clock signal during a first mode of operation, wherein the test clock signal has substantially similar signal characteristics to a clock signal received by the memory controller during a second mode of operation.

21. The method ofclaim 20, wherein the clock signal and the test clock signal are differential clock signals.

22. The method ofclaim 20, wherein the clock signal and the test clock signal have substantially the same voltage levels.

23. The method ofclaim 20, wherein the clock signal and the test clock signal have substantially the same frequency.

24. The method ofclaim 23, wherein the frequency is about 400 MHz.

25. The method ofclaim 20, further comprising:

setting an amount of drive current that a clock generator circuit uses to drive the test clock signal on a clock output node.

26. A method of providing clock signals for testing a memory device, comprising:

in the memory device:

generating a test clock signal during a first mode of operation, wherein the test clock signal has substantially similar signal characteristics to a clock signal received by the memory device during a second mode of operation.

27. The method ofclaim 26, wherein the clock signal and the test clock signal have substantially the same voltage levels.

28. The method ofclaim 26, wherein the clock signal and the test clock signal have substantially the same frequency.

29. The method ofclaim 28, wherein the frequency is about 400 MHz.

30. The method ofclaim 26, further comprising:

setting an amount of drive current that a clock generator circuit uses to drive the test clock signal on a clock output node.

31. A memory controller, comprising:

means for receiving a clock signal for synchronizing data communications between the memory controller and a memory device during a first mode of operation; and

means for providing a test clock signal during a second mode of operation for testing the memory controller, wherein the clock signal and the test clock signal have at least one substantially similar signal characteristic.

32. A memory device, comprising:

means for receiving a clock signal for synchronizing data communications between the memory device and a memory controller during a first mode of operation; and

means for providing a test clock signal during a second mode of operation for testing the memory device, wherein the clock signal and the test clock signal have at least one substantially similar signal characteristic.

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