US20040190666A1 - Ultra wide band transmitter - Google Patents

Abstract

A transmitter system is provided. In one embodiment, the transmitter system includes a data modulation unit, which generates a stream of data that is synchronized with a master clock. The transmitter system additionally includes a transmitter that transmits the stream of synchronized data by way of an attached antenna. In another embodiment the transmitter system includes a Medium Access Control (MAC) layer. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims

Description

This is a divisional of co-pending U.S. patent application Ser. No. 09/599,969, filed Jun. 21, 2000, entitled: ULTRA WIDE BAND TRANSMITTER.BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0001]
• This invention pertains generally to a wireless data transmitter. More particularly, the invention relates to an ultra wide band transmitter for transmitting base band signals.[0002]
• 2. The Prior Art[0003]
• Wireless communication increasingly relies on the transmission of data in digital formats. Typically, a data stream is modulated onto a carrier frequency, and the modulated carrier signal is transmitted over a communications channel from a transmitter to a receiver. Generally, these communication systems use conventional narrow band modulated carriers for wireless network communication associated with using conventional narrowband modulated carrier frequencies. Particularly, in multipath environments such as inside rooms and buildings, data communication degrades because of multipath propagation or fading and can result in poor signal reception. Further, the rapidly increasing use of 5 wireless consumer products has “crowded the airwaves” and will result in increasing interference with reception of data. Still further, narrow band modulated carriers rely on use of relatively expensive components such as high-Q filters, precise local high-frequency oscillators, and power amplifiers.[0004]
• Spread-spectrum signals for digital communications were originally developed and used for military communications either to provide resistance to jamming or to hide the signal by transmitting the signal at low power and, thus, make it difficult for an unintended listener to detect its presence in noise. More recently, spread-spectrum signals have been used to provide reliable communications in a variety of civilian applications, including mobile vehicular communications.[0005]
• There are several types of spread spectrum signals. In one type, the basic elements of a spread spectrum digital communication system include a channel encoder, modulator, channel decoder, demodulator, and two synchronized sequence generators, one which interfaces with the modulator at the transmitting end and the second which interfaces with a demodulator at the receiving end. These two generators produce a binary-valued sequence that is used to periodically change the carrier frequency and thus spread the transmitted signal frequency at the modulator and to follow the carrier frequency of the received signals at the demodulator.[0006]
• In carrier-based frequency-hopped spread spectrum the available channel bandwidth is subdivided into a large number of non-overlapping frequency slots. In any signaling interval the transmitted signal carrier occupies one of the available frequency slots. The selection of the frequency slots in each signal interval is made either sequentially or pseudorandomly according to the output from a pseudo-noise generator. The receiver tuning follows the frequency hopping of the transmitted carrier.[0007]
• Another alternative spread spectrum communication system uses base band signals. In base band spread spectrum communication, information may be transmitted in short pulses, modulated by relatively simple keying techniques, with power spread across a frequency band. With the signal spectrum spread across a frequency band, frequency selective fading and other disadvantages of narrow band communication can be avoided. Base band technology has previously been used in radar applications, wherein a single short impulse is directed to a target. The short impulse, spread across a large bandwidth, has significantly reduced spectral power density and thus has a reduced probability of detection and interference.[0008]
• Ultra wide band (UWB) is a wireless technology for transmitting large amounts of digital data over a wide spectrum of frequency bands with very low power. UWB is an extension of conventional spread spectrum technology. The major distinction is that while conventional spread spectrum signals require a few megahertz to about 20 to 30 MHz of bandwidth, UWB uses vastly more spectrum from a few megahertz to several gigahertz. Therefore, UWB communication systems broadcast digital pulses that are timed very precisely on a signal across a very wide spectrum. The transmitter and receiver must be coordinated to send and receive at the proper time. One of the applications for UWB is to allow low powered voice and data communications at very high bit rates.[0009]
• The transmission of digital data of short pulses over an UWB spectrum would avoid the problems associated with narrow band data communications, and the cost and complexity of spread spectrum communications. Suitable, cost effective transmitter architectures for transmitting such data transmissions, have heretofore been unavailable.[0010]
• Accordingly, there is a need for a UWB base band transmitter system and method which can transmit data in the form of short UWB pulses which can be used with a network of transceiver node devices, which is not susceptible to multipath fading or interference with a narrowband communication system, which can be used for indoor applications, and which is relatively simple and inexpensive to implement. The present invention satisfies these needs, as well as others, and generally overcomes the deficiencies found in the background art.[0011]
• Therefore, it would be beneficial to provide an invention having a base band transmitter which transmits data in the form of ultra-short spread spectrum pulses.[0012]
• It would also be beneficial to provide a base band transmitter capable of transmitting signals using different modulation techniques.[0013]
• It would be further beneficial to provide a base band transmitter capable of transmitting signals with a variable pulse repetition frequencies.[0014]
• It would be beneficial to provide a base band transmitter capable of transmitting two different modulation methods such as on-off keying and pulse amplitude modulation.[0015]
• It would be beneficial to provide a base band transmitter which allows synchronization to a master clock of a remote master transceiver device in a multiple transceiver device network.[0016]
• Further benefits of the invention will be brought out in the following portion of the specification wherein the detailed description is for the purpose of fully disclosing the preferred embodiment of the invention without placing limitations thereon.[0017]
SUMMARY OF THE INVENTION
• The present invention is a transmitter system comprising a data modulation unit, a transmitter unit and an antenna. The data modulation unit is configured to generate a digital data pulse stream which is synchronized with a master clock. The transmitter unit is coupled to the data modulation unit. The transmitter unit is configured to receive the digital stream of pulse data and generates a RF pulse stream for transmission. The antenna is coupled to the transmitter unit and the antenna is configured to transmit the RF pulse stream.[0018]
• The data modulation unit is configured to support pulse streams having different modulation techniques. The different modulation techniques include on-off keying and pulse amplitude modulation. The data modulation unit includes a pulse amplitude modulation module which is configured to vary the amplitude of a modulated pulse. The data modulation unit may also be configured to include a pulse repetition frequency module which is configured to vary the pulse repetition frequency. Further still, the data modulation unit may be configured to include both a pulse amplitude modulation module and a pulse repetition frequency module.[0019]
• The present invention includes a transmitter Medium Access Control (MAC) layer comprising a clock synchronization unit, at least one frequency divider, at least one slot allocation unit, and a multiplexer/demultiplexer. The clock synchronization unit has a timing device with a clock speed. The at least one frequency divider is coupled to the clock synchronization unit in which the at least one frequency divider is configured to reduce the clock speed to obtain a desired pulse repetition frequency. The multiplexer/demultiplexer is operatively coupled to the at least one slot allocation unit and the multiplexer/demultiplexer is configured to merge outgoing signals generated by the slot allocation units and distribute incoming signals.[0020]
• The present invention also describes a transmitter system configured to transmit pulse amplitude modulated signals, comprising a clock interface, a pulse generator system, a drive system, a data interface, and a variable gain amplifier or attenuator. The clock interface is configured to generate a clock signal. The pulse generator system is coupled to the clock interface and generates a pulse shape for incoming pulses. The drive system coupled to the pulse generator system is configured to amplify and combine the incoming pulses. The data interface is configured to generate a data signal. The variable gain amplifier or attenuator is operatively coupled to the data interface and is coupled to the drive system. The variable gain amplifier or attenuator provides a means to obtain the desired amplitude for pulse amplitude modulated transmissions.[0021]
BRIEF DESCRIPTION OF THE DRAWING FIGURES
• The present invention will be more fully understood by reference to the following drawings, which are for illustrative purposes only.[0022]
• FIG. 1 is a wireless network system having a plurality of mobile transceiver devices.[0023]
• FIG. 2 is a functional block diagram of the physical layer of a node having a transmitter and data modulation component.[0024]
• FIG. 3 is a TDMA frame generated by the ultra wideband transmitter.[0025]
• FIG. 4 is a block diagram of the transmitting system of the present invention.[0026]
• FIG. 5[0027]ais a block diagram of the pulse generator system of the ultra wideband transmitter.
• FIG. 5[0028]bis a block diagram of the transmitter drive system of the ultra wideband transmitter.
• FIG. 6[0029]apresents a method for generating a baseband signal.
• FIG. 6[0030]bis an illustrative baseband signal generated by the transmitter.
• FIG. 7 presents a block diagram of a pulse repetition frequency module.[0031]
• FIG. 8 is a block diagram of a pulse amplitude modulation module.[0032]
• FIG. 9[0033]aprovides an illustrative example of an output signal with a variable pulse repetition frequency.
• FIG. 9[0034]bprovides illustrative examples of output signals using different modulation techniques.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.[0035]
• The present invention provides a Time Division Multiple Access (TDMA) system and method that allows sharing a wireless medium which can identify and operate in a variable bit rate environment. The present invention provides a system and method capable of supporting devices with vastly different bandwidth requirements. Some devices, such as television receivers, require high bandwidth data communication. The higher cost associated with a television allows for the design of a television receiver having high data rate modulation techniques. Other devices such as home thermostats have lower bandwidth requirements and require simpler modulation techniques for lower cost connectivity.[0036]
• The present invention operates within a network which allows devices to operate at different bit rates and employ different modulation techniques and permits sharing of the same wireless medium. Additionally, the transceivers of the present invention are capable of negotiating links between one another which are dependent on environmental characteristics such as noise and reflection. Further still the present invention allows backward compatibility to be designed into the network so that newer devices communicate with older devices. The system preferable works in a baseband or ultra wide band environment. However, the system and method may operate in other environments which use carrier signals.[0037]
• The TDMA system and method of the present invention will be more fully understood by first referring to FIG. 1, which shows a[0038]wireless network system10 comprising a plurality ofmobile transceivers12a-12d, also identified as radio devices A-D, wherein each transceiver has a correspondingantenna14a-14d. Onetransceiver12ais acting as a “master” transceiver or device, while the remainingtransceivers12b,12cand12dact as “slave” transceivers. It shall be appreciated by those skilled in the art that the terms transceiver and devices may be used interchangeably. Theparticular transceiver node12a-12dwhich acts as the master transceiver may change depending upon the manner in which thenetwork system10 is used, and thus the components and hardware for eachtransceiver12a-12dare generally the same.
• By way of example and not of limitation, the illustrative example of four[0039]transceivers12a-12dare shown innetwork system10. Themaster transceiver12acarries out the operation of managing network communications betweentransceivers12b-12dby synchronizing the communications between the transceivers using amaster clock13. Therefore, themaster transceiver12amaintains communication withslave transceivers12bthrough12d. Additionally, the slave transceivers are able to communicate amongst themselves, as illustrated by the typical communications betweenslave transceiver12cand12d. The systems and methods for communications are described in further detail below.
• The present invention provides that the master transceiver need not include dedicated communication hardware to provide simultaneous open links between itself and all the slave transceivers. However, the master transceiver must maintain communications with the slave transceivers so that all transceivers on the network are properly synchronized. The present design guarantees that media can be broadcast to many nodes at the same time. It shall be appreciated by those skilled in the art and having the benefit of this disclosure, that the[0040]network system10 may comprise a larger number of transceivers, with the actual number of transceivers innetwork system10 varying depending on the particular application for thesystem10.
• Referring now to FIG. 2 as well as FIG. 1, a functional block diagram of the “Physical layer” implementation of a[0041]transceiver node device12 in accordance with the present invention is shown. The “Physical layer” as described herein refers to the physical layer according to the Open Systems Interconnection (OSI) Reference Model.
• Each[0042]transceiver node device12a-12dis structured and configured astransceiver device12 of FIG. 2. Thetransceiver node device12 comprises an integrated circuit or like hardware device providing the functions described below.Transceiver device12 comprises anantenna14 coupled to atransmitter16 and areceiver18. Thetransmitter16 is connected to adata modulation unit20.Transmitter gain control21 is coupled totransmitter16. Both thetransmitter16 and thedata modulation unit20 are coupled to an interface to Data Link Layer (DLL)22. Thereceiver18 coupled to theantenna14 comprises generally an RFfront end section24, apulse detector26, a data demodulation ordata recovery unit28. Areceiver gain control30 is included in association withreceiver18.
• A framing[0043]control unit32 and aclock synchronization unit34 are operatively coupled to thereceiver18 and thedata modulation unit20 associated with thetransmitter16.Transmitter16 andreceiver18 are operatively coupled toantenna14, preferably through a RF switch (not shown).
• Data[0044]Link Layer interface22 comprises circuitry which provides an interface or higher communication exchange layer between the Physical Layer ofnetwork10, as embodied intransceiver12, and the “higher” layers according to the OSI reference model. The layer immediately “above” the Physical Layer is the Data Link Layer. Output information from the Data Link Layer is communicated todata modulation unit20 viainterface22. Input data fromreceiver18 is communicated to the Data Link Layer viainterface22.
• The[0045]data modulation unit20 comprises circuitry which converts information received frominterface22 into a modulated stream of pulses. Various forms of pulse modulation may be employed bydata modulator20. One modulation scheme which may be used is on-off keying wherein the presence and absence of pulses respectively represent the “ones” and “zeros” for digital information. In this situation,data modulation unit20 causes a pulse to be generated at the appropriate bit time to represent a “one”, or causes the absence of a pulse to represent a “zero”. In another embodiment, pulse amplitude modulation is employed wherein the amplitude of a pulse represents a digital value. The number of bits that may be represented by a pulse depends on the dynamic range and signal-to-noise ratio available. The data modulation method is described in further detail below.
• The pulse stream generated by[0046]data modulator20 and transmitted bytransmitter16 is synchronized with a master clock associated with theclock synchronization function34, and is sent in an appropriate time slot according to a frame definition provided by the framingcontrol unit32, as described further below. In order to maintain a synchronized network, one device must serve the function of being a clock master and maintaining the master clock for thenetwork10.
• [0047]Transmitter16 is preferably a wide band transmitter device which generates a modulated ultra wide band pulse stream output fromdata modulation unit20 and transmits the shaped modulated ultra wide band pulse stream viaantenna14 as a stream of electromagnetic radio frequency (RF) pulses. In the preferred embodiment, data is10 transmitted via impulses having 100 picosecond risetime and 200 picosecond width, which corresponds to a bandwidth of between about 2.5 GHz and 5 GHz. Thetransmitter gain control21 preferably comprises a power control circuit.
• [0048]Antenna14 comprises a radio-frequency (RF) transducer and is structured and configured for both transmission and reception. During reception,antenna14 converts RF pulses into corresponding voltage signals. Duringtransmission antenna14 converts an electric current containing pulse information into corresponding ultra wide band RF pulses. In one preferred embodiment,antenna14 is structured and configured as a ground plane antenna having an edge with a notch or cutout portion operating at a broad spectrum frequency at about 3.75 GHz. The structure and configuration ofantenna14 may vary in order to accommodate various frequency spectrum ranges.Antenna14 may alternatively comprise a “dual antenna” configuration wherein transmission and reception occur from different portions or regions ofantenna14.
• [0049]Clock synchronization unit34 includes a clock function (not shown) which maintains a clock or timing device (also not shown). The clock is preferably a conventional voltage controlled oscillating crystal device which operates at a multiple of the bit rate for the system. In the case of themaster transceiver12a, the clock in the clock synchronization unit serves as a master clock13 (FIG. 1) fornetwork10. As noted 10 above, anytransceiver node12a-12dmay act as the master transceiver for the network. A clock recovery function, described further below, is included withreceiver18 wherein timing information from the master clock is recovered.
• [0050]Framing control unit32 comprises circuitry which carries out the operations of generating and maintaining time frame information with respect to transmitted data.Framing control unit32 is utilized by the transceiver node which is acting as the master transceiver by dividing up the transmitted pulse information into “frames”. Data transmission between theseveral node transceivers12a-12dis preferably carried out via a Medium Access Control protocol utilizing a Time Division Multiple Access (TDMA) frame definition.
• Subject to the TDMA frame definition, data is transmitted as short RF pulses and is divided into discrete data frames, wherein each data frame is further subdivided into “slots”. The frame definition is provided to[0051]transceivers12a-12dfrom the Data Link Layer viainterface22. The TDMA frame definition is defined by Medium Access Control (MAC) sublayer software associated with the Data Link Layer.Framing control unit32 inmaster transceiver12agenerates and maintains time frame information through use of “Start-Of-Frame” (SOF) symbols, which are used by theslave transceivers12b-12dto identify the frames in the incoming data stream.
• In the most general terms, the[0052]preferred receiver18 includes a RFfront end module24,pulse detection unit26, and adata demodulation unit28. Thereceiver18 detects modulated ultra wide band pulses generated by the transmitter. The receiver apparatus comprises a RFfront end section28, apulse detection unit26, anddata recovery unit24. A more detailed description of the preferred receiver of the present invention is provided below.
• [0053]Transceiver12 further includes circuitry providing means for controlling the gain of signals received and transmitted shown asgain control units30 and21, respectively. The transmitgain control unit21 carries out the operation of controlling the power output of thetransmitter12 and receivegain control unit30 carries out the operation of controlling the input gain of thereceiver18. The optimized gain for each control unit is dependent on maximizing the power demands for transceiver communications while minimizing the energy consumption of each control unit.
• As described in further detail below, the physical layer of the[0054]system10 includes atransmitter unit16 and adata modulation unit20, the completion of which is capable of modifying the pulse repetition frequency and modulation technique for the base band signals. Preferably, thetransmitter unit16 anddata modulation unit20 are configured to modify the modulation scheme for thenetwork10 by shifting from on-off keying modulation to pulse amplitude modulation and vice versa. Additionally, thereceiver18 is capable of detecting the variable pulse repetition frequency and different modulation techniques generated by thetransmitter16.
• Referring to FIG. 3 there is shown an illustrative TDM A frame useable in the present invention. The[0055]TDMA frame50 is an illustrative frame arrangement provided by the Medium Access Control (MAC) protocol of the present invention. The MAC protocol of the present invention provides services at the MAC sublayer of the Data Link layer according to the Open Systems Interconnection (OSI) reference model. The Logical Link Control (LLC) sublayer is the (upper) portion of the Data Link layer and provides virtual linking services to the Network layer of the OSI reference model. Data transmission framing fortransceivers12a-12dis provided by the MAC protocol executed within each transceiver on the network. The MAC protocol provides a TDMA frame definition and a framing control function. The TDMA architecture divides data transmission time into discrete data “frames”. Frames are further subdivided into “slots”.
• [0056]TDMA frame50 is an illustrative frame arrangement provided by the MAC layer protocol of the present invention. In general, the MAC layer of the present invention provides themaster transceiver12 with the functions and routines for carrying out the operation of managing eachTDMA frame50 which is communicated in thenetwork system10. In the preferred embodiment, theTDMA frame50 comprises a Start-Of-Frame section52, a command section54, and adata slot section56. Thedata slot section56 is further subdivided into a plurality of data slots60athrough60n.
• The architecture of[0057]TDMA frame definition50 provides for isochronous data communications between themaster transceiver12aand theslave transceivers12b-12d. It shall be appreciated by those skilled in the art that isochronous data communication refers to processes where data must be delivered within a certain time constraint. Isochronous data communication is supported byframe definition50 by sharing transmit time so that eachtransceiver12a-12dis permitted to transmit data during a specific allotted time slot.
• Asynchronous communication is also supported by the[0058]frame definition50. It shall be appreciated by those skilled in the art that asynchronous data communications refers to communications in which data can be transmitted intermittently rather than in a steady stream. Within the TDMA frame, slot may be assigned to be random access using a technique such as Carrier Sense Multiple access with Collision Avoidance (CSMA-CA). For the illustrative CSMA-CA case, themaster12acreates a slot to be used as a random access slot. Themaster12athen communicates through the command slot to all random access capable devices that this slot is now available for random access. Themaster12aalso communicates the start and length of the command slot. The random access slot might be used for all Internet Protocol (IP) devices, for example, such that all IP capable devices will listen to and transmit using only the random access slot reserved for IP traffic. Each IP device on the network listens to this slot. If no communication is detected in this slot for certain number of frames, this channel is considered “free”. A device wishing to transmit waits until the channel is free before retransmitting, and then start packet transmission by transmitting to the random access slot for each frame until the transmission was completed. Various schemes for collision avoidance are known in the art.
• The Start of[0059]Frame section52 includes asynchronization slot58 and atimestamp slot59. Thesynchronization slot58 identifies the start of each new TDMA frame and synchronizes themaster transceiver12awith theslave transceiver12bthrough12d. Thesynchronization slot58 from themaster transceiver12aincludes a master synchronization code which is generated at least once per frame. Preferably, the master synchronization code comprises a unique bit pattern which identifies the master transceiver as the source of transmission with timing information associated with the master clock in the clock synchronization unit of the master transceiver. By way of example and not of limitation, the master synchronization code uses a 10-bit code comprising “0111111110”. Preferably,master12asynchronization is performed with On-Off Keying where 1's are represented by full amplitude pulses and 0's are represented by lack of pulses.
• Various encoding schemes known in the art may be used to guarantee that the master synchronization code within[0060]synchronization slot58 will not appear anywhere else in the data sequence of theTDMA frame50. For example, a common encoding scheme is4B/5B encoding, where a 4-bit values is encoded as a 5-bit value. Several criteria or “rules” specified in a4B/5B, such as “each encoded 5-bit value may contain no more than three ones or three zeros” and “each encoded 5-bit value may not end with three ones or three zeros”, ensure that a pulse stream will not have a string of six or more ones or zeros. Other encoding techniques known in the art may also be used for master synchronization code including bit stuffing or zero stuffing.
• The[0061]timestamp slot59 includes a bit-field which is incremented by a timestamp counter (not shown) in themaster transceiver12a. The timestamp slot is used by themaster transceiver12aand theslave transceivers12bthrough12dto coordinate the assignment or changes in slot parameters. Thetimestamp slot59 permits themaster12ato dynamically reassign the data slot time and length parameters. In operation, themaster12adetermines a predetermined time interval required for the modification of the data slot time and/or data slot length to the slave transceivers. Additionally, the master schedules each participating slave device to make the switch to the new time/length at a specific time which is provided by a timecode resident intimestamp slot59.
• The command section[0062]54 contains a protocol message exchanged between thetransceivers12athrough12dofnetwork10, are used by themaster transceiver12afor managing network communications. The flow of protocol messages in the command slot42 may be governed, for example, by a sequence retransmission request or “SRQ” protocol scheme wherein confirmation of protocol transactions are provided following completion of an entire protocol sequence.
• The data slots[0063]60athrough60nare assigned by themaster transceiver12ato requestingslave transceivers12bthrough12d. Data slots60athrough60nare further structured and configured to be arranged dynamically and permit the reassigning of the relative start time and the length of the data slots60athrough60nwithin thedata slot section56 of theframe50. This arrangement allows themaster transceiver12ato dynamically manage the usage of thedata slot section56 to optimize the bandwidth capabilities of the transport medium of the network and the transceivers of the network. Thus, themaster transceiver12amay allocate a wider data slot to a slave transceiver which can utilize a wider bandwidth. Conversely, themaster transceiver12amay also allocate a narrower data slot to a slave transceiver which has more limited bandwidth capabilities. The granularity for data slots60athrough60nis one (1) bit. The granularity for data slots60athrough60nis allocated by themaster transceiver12a.
• Each data slot[0064]60athrough60nhas a correspondingdata synchronization sub-slot62athrough62nand adata payload sub-slot64athrough64n. Thedata payload64athrough64ncontains the encoded actual data or bit information which is transmitted from the source transceiver to the target transceiver. Thedata synchronization sub-slot62athrough62nare used by each transceiver for providing timing synchronization signals to a corresponding target transceivers to accommodate for propagation delays between the source and target transceivers. Propagation delays vary in length depending on the distance between source and target transceivers. As described above, the master synchronization code provides timing signals to allow slave transceivers to synchronize with the master clock of themaster transceiver12a. Likewise, the symbols within thedata synchronization sub-slot62athrough62nare symbols which allow target slave transceivers to synchronize with corresponding source slave transceivers using similar synchronization algorithms such as phase offset detectors and controllers. Proper target to source transceiver synchronization is fundamental for reliable data communication exchange between the slave transceiver.
• Each data slot[0065]60athrough60nhas a corresponding slot starttime66athrough66nandcorresponding slot length68athrough68n. The slot starttime66athrough66ncorresponds to the time position within thedata slot section56 of the frame at which point the device begins its transmission. Theslot length68athrough68nmeasured from the slot start time provides the time position within the frame at which transmission is terminated for the data slot for each frame. Theslot lengths68athrough68ncorresponds to the bandwidth allocated to the devices within thedata slot section56 of the frame and may be of varying lengths as assigned by themaster transceiver12a.
• The[0066]framing control unit32 in theslave transceivers12bthrough12dprovide framing means such as local counters, correlators, phase lock loop functions, and phase offset detectors and controllers which allow frame synchronization betweenslave transceivers12bthrough12dand themaster transceiver12ato be reestablished when the size or length offrame50 is altered by themaster transceiver12a.
• Referring back to FIG. 1, as well as FIG. 3, each device operates as a finite-state machine having at least three states: offline, online and engaged. Each slave transceiver maintains and tracks its state by storing its state information internally, usually in random access memory (RAM) (not shown) or other memory means known in the art. The state of each slave transceiver is further maintained and tracked by the[0067]master transceiver12aby storing the states of the slaves in a master table which is well known in the art and which is stored in RAM.
• Each slave transceiver must first be registered with the[0068]master transceiver12 before the slave transceiver may engage in data communication with the other slave transceivers of the network. Once a transceiver is considered “online” it is ready for communication. A slave transceiver that is in the “online” state is ready to send or receive data from the other devices on thenetwork10. Additionally, a slave transceiver is in the “online” state if it is not currently engaged in communication with other slave transceivers. A slave transceiver is “engaged” when the transceiver is currently communicating with one or more slave transceivers. For example, where a source slave transceiver is transmitting audio signal data to a target slave transceiver, both the source and target slave transceiver are in the “engaged” state.
• The slave transceivers[0069]12bthrough12duse the command slot for requesting data transmission and indicating its start-up (on-line) state, engaged state, or shut-down (offline) state. The data slots are used for data transmission between the node transceivers of the network. Generally, each transmitting device of the networks is assigned one or more corresponding data slots within the frame in which the device may transmit data directly to another slave transceiver without the need for a “store and forward” scheme as is presently used in the prior art.
• Referring to FIG. 4, there is shown a block diagram of the transmitter system of the present invention which may be used in either master transceiver or slave transceiver. The[0070]transmitter system70 includes adata modulation unit20 coupled to atransmitter16, a transmitgain control unit21 which is also coupled totransmitter16, and anantenna14 which receives signals fromtransmitter16 for transmission viaantenna14. Thedata modulation unit20 further comprises a pulseamplitude modulation module72, a pulserepetition frequency module74 and a transmitmodule76. The pulse repetition frequency module is configured to provide a variable pulse repetition frequency totransmitter system70. The pulse amplitude modulation module is configured to provide modulation techniques in which the amplitude for pulses may be varied depending on the value represented by the pulse amplitude modulated pulse. The transmitmodule76 is in direct communication withpulse amplitude module72 and pulserepetition frequency module74. The pulseamplitude modulation module72 is coupled toamplitude control system75. The pulseamplitude modulation module72,amplitude control system75, and the pulserepetition frequency module74 are described in further detail below. Preferably,data modulation unit20 is configured to generate a digital stream of pulse data. Preferably, the digital stream of pulse data generated by thedata modulation unit20 includes a transmit module configured to generate a clock pulse and pulse amplitude modulation module configured to generate a data stream for a desired pulse amplitude.
• The transmit[0071]module76 provides the ability to distinguish between different modulation techniques such as pulse amplitude modulation (PAM) and on-off keying (OOK). If the transmit module detects that a signal is modulated by OOK, the OOK signal is communicated directly to thetransmitter16. If the transmit module detects that a signal is modulated by PAM, then the transmit signal is communicated to thePAM module72.
• Additionally, the transmit[0072]module76 communicates with a pulserepetition frequency module72. Preferably, the transmit pulses are digital clock pulses which are communicated at the particular pulse repetition frequency. The pulserepetition frequency module72 performs the function of varying the pulse repetition frequency and the corresponding bit rate for communications. The bit rate is varied depending on environmental and network demands. Another benefit provided by the pulserepetition frequency module72 is to reduce the amount of interference generated by the baseband transmitter by periodically modifying the pulse repetition rate of the baseband transmitter.
• The transmit[0073]module76 generates the transmit pulse signals which are communicated to thetransmitter16pulse generator system78. The transmit pulses are digital clock pulses which are communicated at a particular pulse repetition frequency. Additionally, the transmitmodule76 provides the ability to distinguish between different modulation techniques such as pulse amplitude modulation (PAM) and on-off keying (OOK). If the transmit module detects that a signal is modulated by OOK, the OOK signal is communicated directly to thetransistor drive system79. If the transmit module detects that a signal is modulated by PAM, then the transmit signal is communicated to thePAM module72.
• The modulation technique for the pulse stream generated by the[0074]data modulator20 is synchronized with themaster clock13 associated with theclock synchronization unit34, and is sent in an appropriate time slot according to a frame definition provided by the framingcontrol unit32. To maintain a synchronized network, one device must serve the function of being a clock master and maintaining themaster clock13 for thenetwork10.
• Various forms of pulse modulation may be employed by[0075]data modulation unit20. In the simplest case on-off keying is used wherein the presence and absence of pulses represent the “ones” and “zeros”, respectively, of digital information. In this typical situation, thedata modulation unit20 causes a pulse to be generated at the appropriate bit time to represent a “one” or causes the absence of a pulse to represent a “zero.”
• Another modulation method that may be used is pulse amplitude modulation in which the amplitude of a pulse is represented by a digital value. The[0076]amplitude control system75 receives data signals from thepulse amplitude module72 in which the data signals provide data about the desired pulse amplitude to be generated by theamplitude control system75. Two illustrative amplitude control systems described in further detail below include a variable gain amplifier and an attenuator.
• Referring to FIG. 5[0077]aas well as FIG. 4 there is shown a block diagram of the pulse generator system for the ultra wide band transmitter. In its preferred embodiment, the present invention is a baseband signal generator that generates an output RF signal from digital data pulses. The baseband signal generator of the present invention comprises a pull-up circuit and a pull-down circuit which generate the RF baseband output signal that approximates the shape of the filter transfer function associated with theantenna14. The pull-up circuit includes apulse generator system78 and adrive system79 which produces positive going signal excursions and negative going signal excursions. The composite of the positive going signal excursions and the negative going signal excursions generate the RF output base band signal that approximates the shape of the filter transfer function associated with theantenna14.
• By way of example and not of limitation, the output baseband signal may have a spectral content bandwidth which matches the filter bandwidth between 2.5 GHz to 5.0 GHz. Note that in the preferred embodiment, the filter is an antenna transmitting signals between 2.5 GHz and 5.0 GHz.[0078]
• As previously described, the pull-up circuits and pull-down circuits also include a[0079]pulse generator system78. By way of example and not of limitation, the pulse generator system includes fourpulse generators80,82,84 and86. In operation, thepulse generating system78 presents the rising edge of an input transmitpulse88 to the one or more pulse generators. The pulse generator system generates output signals that are presented to the drive system as pull-up turn-onsignals90, pull-up turn-off signals92, pull-down turn-onsignals94, and pull-down turn-off signals96.
• Preferably, each typical pulse generator includes four pairs of coupled edge delay circuits which are coupled to one another. By way of example,[0080]pulse generator80 includesedge delay circuits98 through112, which function in pairs. Preferably thepulse generator80 is composed of four (4) pairs of edge delay circuits in which each pair of edge delay circuit includes an edge delay circuit that generates a leading edge and another edge delay circuit that generates a trailing edge. By way of example, the first pair of edge delay circuits inpulse generator80 include a firstedge delay circuit98 which generates the leading edge for the delayed pulse signal and the second edge delay circuit100 which generates the trailing edge for the delayed pulse signal. It shall be appreciated by those skilled in the art having the benefit of this disclosure that each pair of edge delay circuits generates the leading and trailing edges for each delayed pulse signal. More particularly, each edge delay circuit may comprise a switched bank of capacitors that provide a programmable edge delay. It shall be appreciated by those skilled in the art having the benefit of this disclosure that the outputs from each pair of edge delay circuits are combined to produce a composite series of delayed output pulses forpulse generator80. Each of the remainingpulse generators82,84 and86 also each generate a composite series of delayed output pulses. The delayed output pulses frompulse generators80,82,84 and86 are presented as pull-up turn-on signals90 (identified as Pon), pull-up turn-off signals92 (identified as Poff), pull-down turn-on signals94 (identified as Non), and pull-down turn-off signals96 (identified as Noff) to thedrive system79. Thedrive system79 combines these pull-up turn-onsignals90, pull-up turn-off signals92, pull-down turn-onsignals94, and pull-down turn-off signals96 to generate a waveform which is communicated toantenna14.
• Referring to FIG. 5[0081]bthere is shown an illustrative example of a transistor drive system for the ultra wide band transmitter. The transistor drive system combines and amplifies the signals generated by the pulse generator system to produce a shaped modulated pulse stream for transmission byantenna14. Preferably the drive system is also operatively coupled to the pulse amplitude modulation module. The drive system receives the pull-up circuit which generates the positive going signal excursion includes abipolar pnp transistor120. Thepnp transistor120 is a pull-up transistor in a common emitter configuration that receives the pull-up signals at itsbase122. Generally, the pull-up signals are a combination of the Pon signals90 and the Noff signals96. The pull down circuit which generates the negative going signals excursion includes abipolar npn transistor124. Thenpn transistor124 is a pull-down transistor in a common emitter configuration that receives the pull down signals at itsbase126. Generally, the pull-down signals are a combination of the Poff signals92 and the Non signals94. The outputs from the bipolar transistors are capacitively coupled to theload128.
• Preferably, the output signal generated by the signal generator operate between 2.5 GHz to 5.0 GHz. At these operating frequencies, the base-emitter capacitance at each[0082]transistor120 and124 prevents the bipolar transistors from rapidly turning off. To ensure rapid turnoffs of thepnp transistor120 and thenpn transistor124, the transistor of the present invention generates “turn off’ signals which are presented totransistors120 and124 and are represented as Poff signals92 and Noff signals96. The turn-off signals discharge the base-emitter capacitance at eachtransistor120 and124. The discharging of the base-emitter capacitive charge turns off the transistors. Additionally, “turn on” signals may be generated without having to generate simultaneously the “turn off signals when there is little or no base-emitter capacitive charge.
• Referring to FIG. 6[0083]aas well as FIG. 5aand FIG. 5bthere is shown a method for employing the pulse generator and transistor drive system of FIG. 5aand FIG. 5b, respectively. Themethod150 includes aprocess50 in which input transmitpulse88 for transmission is communicated topulse generator system78.
• The method then proceeds to process block[0084]154 where a positive signal excursions generated by a pull-circuit are produced. Thepulse generator system78 comprises a plurality ofpulse generators82,82,84 and86 which produce pull-up turn-on signals90 (identified as Pon), pull-up turn-off signals92 (identified as Poff), pull-down turn-on signals94 (identified as Non), and pull-down turn-off signals96 (identified as Noff), respectively. The positive signal excursions are generated preferably by abipolar pnp transistor120. The pnp transistor is a pull-up transistor in a common emitter configuration that receives the pull-up signals at itsbase122. Generally, the pull-up signals are a combination of the pull-up turn on (Pon) signals90 and the pull down turn off signals (Noff)96. The method then proceeds to process156.
• At[0085]process156, negative signal excursions are generated by a pull-down circuit. The pull-down circuit which generates the negative going signal excursion includes abipolar npn transistor124. Thenpn transistor124 is a pull-down transistor in a common emitter configuration the receives the pull-down signals at itsbase126. Generally, the pull-down signals are a combination of the pull-up turn off (Poff) signals92 and the pull-down turn-on (Non) signals94. The method then proceeds to process158.
• At[0086]process158, the positive and negative signal excursions are combined to generate a base band signal. Preferably, the positive and negative signal excursions are combined and amplified by thedrive system79 to generate a RF pulse stream. The method then proceeds to process160.
• At[0087]process160, the RF pulse stream fromprocess158 is communicated to anantenna14 for transmission. Preferably, the RF pulse stream is a baseband signal is a doublet as shown in FIG. 6b.
• Referring to FIG. 7 there is shown a block diagram of a pulse repetition frequency module and pulse amplitude modulation module which is resident on the Medium Access Control (MAC)[0088]170 layer of the transmitter of the present invention. In general theMAC170 is provided at the Data Link Layer, which is located between the Network Layer and Physical Layer of the OSI reference model. TheMAC170 of the present invention provides the circuitry for varying the pulse repetition frequency.
• The[0089]MAC170 comprises an integrated circuit or like hardware device providing the functions described herein. It shall be appreciated by those skilled in the art that some MAC services may be implemented in software. The MAC functions implemented herein refer to those MAC functions implemented in hardware that are unique to the present invention. The MAC hardware includes a clock synchronization function34 (FIG. 2) which is coupled to a plurality offrequency dividers174,176,178 and180 in which each frequency divider is configured to divide down the clock speed. A plurality ofslot allocation units182,184,186 and188 having different pulse repetition frequencies and different modulation techniques are each coupled tofrequency dividers174,176,178 and180, respectively. Eachslot allocation unit182 through188 is operatively coupled to a multiplexer/demultiplexer unit190 which is operatively coupled to an interface to the Physical Layer192.
• The[0090]clock sync function34 is configured to synchronize a local clock on the transmitter to themaster transceiver12aclock13. Theclock sync function34 produces a high speed clock that is a multiple of the highest pulse repetition frequency supported by the transmitter of the present invention. Eachprogrammable frequency divider174 through180 is capable of generating a varying pulse repetition frequency by dividing down the high-speed clock associated with theclock sync function34.
• Each[0091]slot allocation unit182 through188 may have a different pulse repetition frequency and different modulation technique. Preferably, eachslot allocation unit182 through188 also has a common undivided clock (not shown) to serve as reference for counting out the start location of each slot based on a uniform time base. Additionally, eachslot allocation unit182 through188 is programmed to provide a symbol stream to the physical layer and transmit data pulses and clocking information at the appropriate pulse repetition frequency.
• Further still each[0092]slot allocation unit182 through188 provides data in the appropriate data width to support different modulation techniques. By way of example, for on-off keying, data will be supplied at a rate of one-bit per clock cycle. Additionally for a pulse amplitude modulated signal having four (4) levels, the modulation technique provides for two bits to be communicated per clock cycle. For pulse amplitude modulated signals having eight (8) levels, the modulation technique provides for three bits to be communicated per clock cycle.
• In operation each slot allocation unit has an associated start time, length, and modulation technique. When the start time occurs, the slot allocation unit will take over control the physical layer through communications with multiplexer/[0093]demultiplexer190. Each slot allocation unit provides data signals having the proper width and proper pulse repetition frequency in the form of data control and clock. At the end of an illustrative slot, as determined by slot length, the slot allocation unit relinquishes control and the following slot allocation unit has the opportunity to take control during its respective designated transmit time.
• The structure and function of the slot allocation unit is more carefully described in the patent application titled “Baseband Wireless Network for Isochronous Communication” having patent application Ser. No. 09/393,126. It shall be appreciated by those of ordinary skill in the art, that the slot allocation unit described in this invention Is not confined to isochronous communications as described above.[0094]
• Additionally, it shall be appreciated by those of ordinary skill in the art having the benefit of this disclosure that the data and clock information supplied by the[0095]MAC170 to the physical layer will be fed to thepulse generation system78 and thedrive system79 which will generate the proper waveform at the appropriate time and amplitude.
• The Mux/[0096]Demux190 carries out the operation of merging outgoing bit streams fromslot allocation units182 through188 into a single signal transmitted to the transmitmodule76 and then topulse generating system78 anddrive system79.
• Referring to FIG. 8[0097]a, there is shown a block diagram of one embodiment of an amplitude control system having avariable gain amplifier204. A transmit module which generates a clock pulse at the proper time, communicates the clock pulse to thepulse generator system78 of thetransmitter16. The output frompulse generator system78 is submitted to adrive system79 which generates a RF pulse stream that is communicated to avariable gain amplifier204. Thevariable gain amplifier204 is operatively coupled to the transmittingantenna14. A pulseamplitude modulation module72 is coupled to thevariable gain amplifier204. Thevariable gain amplifier204 amplifies the pulse generated by thedrive system79.
• In operation, the[0098]pulse generator system78 is supplied with a clock or strobe signal from transmitmodule76. The transmitmodule76 generates a clock pulse which is communicated to thepulse generator system78. The pulseamplitude modulation module72 is configured to generate a data stream which is communicated to the amplitude control system having avariable gain amplifier204. The output from thedrive system79 is submitted to thevariable gain amplifier204 which provides the requisite gain to generate an RF pulse for transmission byantenna14 having the desired amplitude.
• Referring to FIG. 8[0099]b, there is shown an alternative block diagram of another amplitude control system having anattenuator214. A transmit module which generates a clock pulse at the proper time, communicates the clock pulse topulse generator system78. The output frompulse generator78 is submitted to adrive system79 which generates a RF pulse stream at a maximum amplitude. The maximum amplitude output from thedrive system79 is communicated to a digitally controlledattenuator214 which is coupled toantenna14. A pulseamplitude modulation module72 is coupled to theattenuator214 which attenuates the waveform generated by thedrive system79. Theattenuator214 reduces the amplitude of the waveform as needed to provide the correct signal for transmission byantenna14.
• In operation, the[0100]pulse generator system78 is supplied with a clock or strobe signal from transmitmodule76. The transmitmodule76 generates a clock pulse which is communicated to thepulse generator system78. The pulseamplitude modulation module72 is configured to generate a data stream which is communicated to the amplitude control system having anattenuator214. The output from thedrive system79 is then submitted toattenuator214 which reduces the amplitude of the RF pulses according to the output generated by the data interface216.
• The present invention is configured to employ various pulse repetition frequencies and various modulation techniques. Referring back to FIG. 7, FIG. 8[0101]a, FIG. 8b, and FIG. 3, when a new data slot such asdata slot64b(FIG. 3) is to be transmitted the slot allocation unit, e.g.slot allocation unit184, is activated and signals to thedata modulation module20, the modulation technique to be employed. If the modulation technique is on-off keying, the data interface for the pulseamplitude modulation module72 will be disabled, and the amplifier206 orattenuator214 will be set to a fixed value, typically full power. If the modulation technique is pulse amplitude modulation, the data interface for the pulseamplitude modulation module72 will be enabled to support the number of bits used for pulse amplitude modulation. For example if the transmitter supports both four (4) level pulse amplitude modulation (2 bits) and eight (8) level pulse amplitude modulation (3 bits), either, two or three bits of the digital interface are enabled. By way of example and not of limitation, the data interface will typically be tied to logic ‘1’, so that symbols001,011,101 and111 are used for the four (4) level pulse amplitude modulated signals. In an alternative embodiment, the pulse amplitude modulation unit may be reconfigured to ignore one bit of the three bit value and generate four equally spaced voltage outputs representing thesymbols00,01,10, and11. It shall be appreciated by those skilled in the art that there are other alternatives for the illustrative four symbols.
• Referring to FIG. 9[0102]a, as well as FIG. 3 and FIG. 1, there is shown a typical illustrative example of the timing for two TDMA slots having different pulse repetition frequencies. A firsttypical TDMA slot220 and secondtypical TDMA slot222 provides communications within a data slot.
• To accommodate variable pulse repetition frequencies for each TDMA slot, the master sync code synchronizes communications between transceiver devices using a[0103]clock synchronization unit34 operating at a nominal pulse repetition frequency that thesystem10 will support. Thetransmitter16 andreceiver18 are capable of frequency multiplying the clock from theclock synchronization unit34 to support higher pulse repetition frequencies. The pulse repetition frequencies employed may depend on the devices particular bandwidth demands, noise constraints, or signal reflection.
• Client bit clock_[0104]1,224, provides the timing for the pulse repetition frequency associated with TDMA Slot N+1,222. The signals transmitted byTDMA slot222 are transmitted during the leading edge of client bit clock_1,224. Client bit clock_2226 provides the timing for the pulse repetition frequency associated withTDMA slot N220. The signals transmitted byTDMA Slot N220 are transmitted during the leading edge ofclient bit clock_2226. The pulse repetition frequency for TDMA Slot N,220, is two times greater, i.e. faster, that the pulse repetition frequency for TDMA Slot N+1,222. The pulse repetition frequency for TDMA Slot N,220, and TDMA Slot N+1,222, is identified by the frequency pulses, identified by arrows, shown inline228.
• Referring to FIG. 9[0105]bthere is shown a typical example of the transceiver timing having a different modulation method for each TDMA slot. Aclient bit clock230 provides the timing for the two typical TDMA slot in the data slot section of TDMA frame. The two typical TDMA frames are identified as TDMA Slot N,232, and TDMA Slot N+1,234. It shall be appreciated by those skilled in the art having the benefit of this disclosure that for TDMA Slot N,232, the signal transmitted employs pulse amplitude modulation as depicted by the symbols inline236. The timing for each of the pulses having a different amplitude is established by theclient bit clock230. Additionally, it shall be appreciated by those skilled in the art that forTDMA Slot N+1234 the signal transmitted employs on-off keying as depicted by the symbols inline236. Again, the timing for each of the pulses operating with on-off keying is established by theclient bit clock230.
• The techniques described above use different bit pulse repetition frequencies and modulation techniques for baseband communications or ultra-wide-band communications. An additional modulation technique referred to as pulse-position modulation is well known in the art and may also be employed with the present system and method. During pulse position modulation, pulses are transmitted at some basic symbol frequency, e.g. 20 MHz. At a 20 MHz symbol repetition frequency that pulses are spaced 50 nanoseconds apart. A pulse falling exactly where expected may indicate a binary “1”, while a pulse delayed by some small delta time may indicate a binary “0”.[0106]
• The system of the present invention may be broadened for use with carrier signals and other modulation technique. Therefore, while embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.[0107]

Claims (15)

What is claimed is:

1. A transmitter Medium Access Control (MAC) layer, comprising:

a clock synchronization unit having a timing device with a clock speed;

at least one frequency divider coupled to said clock synchronization unit, said frequency divider configured to reduce said clock speed to generate a desired pulse repetition frequency;

at least one slot allocation unit coupled to said at least one frequency divider; and

a multiplexer/demultiplexer operatively coupled to said at least one slot allocation unit, said multiplexer/demultiplexer configured to merge a plurality of outgoing signals and configured to distribute a plurality of incoming signals.

2. The transmitter MAC layer recited inclaim 1, wherein each of said at least one slot allocation unit has a particular pulse repetition frequency.

3. The transmitter MAC layer recited inclaim 1, wherein each of said at least one slot allocation unit is configured to support different modulation techniques.

4. The transmitter MAC layer recited inclaim 1, wherein each of said at least one slot allocation unit is configured to support pulse amplitude modulation.

5. The transmitter MAC layer recited inclaim 1, where each of said at least one slot allocation unit is configured to support on-off keying.

6. An ultra wide band transmitter Medium Access Control (MAC) layer, comprising:

a clock synchronization unit;

at least one frequency divider communicating with the clock synchronization unit, the frequency divider structured to generate a pulse repetition frequency;

at least one slot allocation unit communicating with the at least one frequency divider; and

a multiplexer/demultiplexer communicating with the at least one slot allocation unit, the multiplexer/demultiplexer structured to merge a plurality of outgoing ultra wide band pulses and configured to distribute a plurality of incoming ultra wide band pulses.

7. The ultra wide band transmitter Medium Access Control (MAC) layer ofclaim 6, wherein the clock synchronization unit further comprises a timing device with a clock speed.

8. The ultra wide band transmitter Medium Access Control (MAC) layer ofclaim 6, wherein each of the at least one slot allocation unit has a particular pulse repetition frequency.

9. The ultra wide band transmitter Medium Access Control (MAC) layer ofclaim 6, wherein each of the at least one slot allocation unit is configured to support different modulation techniques.

10. The ultra wide band transmitter Medium Access Control (MAC) layer ofclaim 6, wherein each of the at least one slot allocation unit is configured to support on-off keying.

11. An ultra wide band Medium Access Control (MAC) layer, comprising:

a time division multiple access frame comprising a plurality of slots, with each slot configured to receive at least one ultra wide band pulse.

12. The ultra wide band Medium Access Control (MAC) layer ofclaim 11, wherein the time division multiple access frame operates in an aloha mode.

13. The ultra wide band Medium Access Control (MAC) layer ofclaim 11, wherein an ultra wide band pulse repetition frequency varies between different slots.

14. The ultra wide band Medium Access Control (MAC) layer ofclaim 11, wherein an ultra wide band pulse position varies between different slots.

15. The ultra wide band Medium Access Control (MAC) layer ofclaim 11, wherein an ultra wide band pulse amplitude varies between different slots.

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