US20040178449A1 - Silicon-on-insulator comprising integrated circuitry and methods of forming silicon-on-insulator circuitry - Google Patents
Silicon-on-insulator comprising integrated circuitry and methods of forming silicon-on-insulator circuitryDownload PDFInfo
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- US20040178449A1 US20040178449A1US10/809,420US80942004AUS2004178449A1US 20040178449 A1US20040178449 A1US 20040178449A1US 80942004 AUS80942004 AUS 80942004AUS 2004178449 A1US2004178449 A1US 2004178449A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
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- This inventionrelates to silicon-on-insulator comprising integrated circuitry and to methods of forming silicon-on-insulator comprising integrated circuitry, including wafer bonding methods.
- Floating body effect or voltageis determined by forward current leakage to the source and reverse leakage to the drain.
- One known prior art method of reducing the floating body effectis to increase the source/drain junction forward bias current, thus resulting in any charge build-up in the body promptly being discharged to the source.
- the inventionincludes silicon-on-insulator comprising integrated circuitry and methods of forming silicon-on-insulator circuitry, including wafer bonding methods.
- a wafer bonding method of forming silicon-on-insulator comprising integrated circuitryincludes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer.
- a method of forming silicon-on-insulator comprising integrated circuitryincludes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer.
- a method of forming silicon-on-insulator comprising integrated circuitryincludes forming the silicon comprising layer of the silicon-on-insulator circuitry.
- a pair of source/drain regionsare formed in the silicon comprising layer and a channel region is formed in the silicon comprising layer which is received intermediate the source/drain regions.
- a transistor gateis formed operably proximate the channel region.
- the insulator layer of the silicon-on-insulator circuitryis formed.
- the insulator layeris formed to comprise a first silicon dioxide comprising region in contact with the silicon comprising layer and running along at least a portion of the channel region between the source/drain regions.
- a silicon nitride comprising regionis formed in contact with the first silicon dioxide comprising region and runs along at least a portion of the channel region.
- a second silicon dioxide comprising regionis formed in contact with the silicon nitride comprising region. The silicon nitride comprising region is received intermediate the first and second silicon dioxide comprising regions.
- Integrated circuitryis also contemplated regardless of the method of fabrication.
- FIG. 1is a diagrammatic view of a wafer in process in accordance with an aspect of the invention.
- FIG. 2is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 1.
- FIG. 3is a view of the FIG. 2 wafer at a processing step subsequent to that shown by FIG. 2.
- FIG. 4is a view of the FIG. 3 wafer at a processing step subsequent to that shown by FIG. 3, and positioned relative to another wafer.
- FIG. 6is an enlarged diagrammatic sectional view of a portion of the joined wafers of FIG. 5 after subsequent processing.
- FIG. 7is a view of an alternate embodiment to that depicted by FIG. 6.
- FIG. 8is a view of another alternate embodiment to that depicted by FIG. 6.
- FIG. 9is a view of still another alternate embodiment to that depicted by FIG. 6.
- FIG. 1depicts a device wafer or first substrate 10 .
- a device wafer or first substrate 10Preferably, such comprises a bulk monocrystalline silicon substrate 12 .
- semiconductor substrateor “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
- substraterefers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated.
- Substrate 12includes an outer surface 14 . Some portion 15 thereof is intended to be joined with another substrate, as will be apparent from the continuing discussion in a preferred wafer bonding method of forming silicon-on-insulator comprising integrated circuitry. In the depicted and preferred embodiment, outer surface 14 comprises crystalline silicon.
- nitridizingmight include any one or combination of ion implanting, direct plasma nitridation, remote plasma nitridation, and chemical vapor deposition.
- the nitridationmight also be conducted to be void of either direct or remote nitrogen containing plasma exposure, for example by furnace annealing in a nitrogen containing atmosphere.
- Example nitrogen containing species for any of the aboveinclude N 2 , NO x , NH 3 and N 2 O.
- a preferred thickness for region 16is from about 5 Angstroms to about 50 Angstroms.
- nitride comprising layer 16is oxidized, preferably to form a silicon dioxide or silicon oxynitride layer 18 .
- nitride comprising layer 16has a thickness of from about 5 Angstroms to about 50 Angstroms at the conclusion of the oxidizing.
- An exemplary thickness for oxide layer 18is from about 50 Angstroms to about 500 Angstroms.
- device wafer or first substrate 10is depicted diagrammatically proximate a handle wafer or second substrate 20 .
- Second substrate 20also preferably comprises a bulk monocrystalline silicon substrate 22 which has been oxidized to form a silicon dioxide comprising layer 24 .
- An example process for forming layer 24includes thermal growth or deposition, for example by CVD.
- handle wafer 20can be considered as comprising a silicon dioxide comprising surface 25 .
- device wafer 10is joined with handle wafer 20 , with the preferred embodiment depicting joining device wafer 10 with silicon dioxide comprising surface 25 of handle wafer 20 .
- Such aspectincludes a wafer bonding method of forming silicon-on-insulator comprising integrated circuitry whereby the method comprises nitridizing at least a portion of an outer surface of silicon of a device wafer. Thereafter, the device wafer is joined with the handle wafer and regardless of what subsequent processing occurs to finally form integrated circuitry.
- One exemplary method to bond substrate 10 with substrate 20includes applying a suitable high voltage with opposite polarity on the device wafer and on the handle wafer. Pressing the substrates together at elevated temperature and pressure can also result in a suitable bonding. Further, by way of example only and if the oxide layer is very thin, a thermal oxidation can be conducted while pressing them together a high pressure.
- layers/regions 16 / 18 / 24comprise an insulator layer 42 of the silicon-on-insulator circuitry which contacts silicon comprising layer 12 .
- Source/drain regions 32 and 34extend to be in contact with insulator layer 42 .
- source/drain regions 32 and 34 and transistor gate construction 36form a channel region 44 which is received intermediate the source/drain regions, and in the preferred embodiment, is partially depleted (not extending completely through the thickness of silicon comprising layer 12 ) in operation, as shown.
- nitridized portion 16is received intermediate source/drain regions 32 , 34 and silicon dioxide 18 / 24 .
- Silicon nitride comprising region 16ideally has greater leakage current characteristics whereby increased leakage current can occur across that portion of silicon comprising layer 12 received between source/drain regions 32 and 34 than would otherwise occur in the absence of silicon nitride comprising region 16 .
- source/drain forward bias current and leakageare increased, which preferably increases trap density and reduces carrier lifetime, which results in higher junction current.
- the inventionalso contemplates nitridizing at least a portion of an outer surface of silicon dioxide comprising layer 24 of handle wafer 20 with or without any nitridation or oxidation of any portion of the outer surface of device wafer 10 .
- the outer surface of the device wafer to which the handle wafer is joinedmight comprise crystalline silicon, silicon nitride and/or silicon dioxide.
- the inventionalso contemplates a lesser preferred embodiment wherein the nitridizing of the interface occurs after forming the joined substrate.
- the FIG. 6 constructionmight be formed by conducting an ion implant after joining to form silicon nitride comprising region 16 .
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Abstract
Description
- This invention relates to silicon-on-insulator comprising integrated circuitry and to methods of forming silicon-on-insulator comprising integrated circuitry, including wafer bonding methods.[0001]
- A problem which motivated the invention related to overcoming undesired floating body effects inherent in silicon-on-insulator field effect transistors. Such is characterized by channel region voltage inherently floating during operation, thereby affecting the threshold voltage and operation consistency of the transistor. Floating body effect typically is not an issue in bulk semiconductor circuitry, as the bulk substrate is tied or held to a specific voltage such that the substrate voltage and threshold voltage are not allowed to float. However in silicon-on-insulator field effect transistors, such does not presently occur and is particularly problematic in what are known as partially depleted silicon-on-insulator transistors. A partially depleted silicon-on-insulator transistor has its channel region only partially extending through the thickness of the silicon layer beneath the transistor gate. Factors which determine whether a field effect transistor is partially or fully depleted include the thickness of the silicon layer and the thickness of the source/drain region within the silicon layer.[0002]
- Floating body effect or voltage is determined by forward current leakage to the source and reverse leakage to the drain. One known prior art method of reducing the floating body effect is to increase the source/drain junction forward bias current, thus resulting in any charge build-up in the body promptly being discharged to the source.[0003]
- The following invention was motivated in addressing the above identified problems, although such is in no way so limited. The invention is limited only by the accompanying claims as literally worded without limiting reference to the specification, and in accordance with the doctrine of equivalents.[0004]
- The invention includes silicon-on-insulator comprising integrated circuitry and methods of forming silicon-on-insulator circuitry, including wafer bonding methods. In one implementation, a wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer.[0005]
- In one implementation, a method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer.[0006]
- In one implementation, a method of forming silicon-on-insulator comprising integrated circuitry includes forming the silicon comprising layer of the silicon-on-insulator circuitry. A pair of source/drain regions are formed in the silicon comprising layer and a channel region is formed in the silicon comprising layer which is received intermediate the source/drain regions. A transistor gate is formed operably proximate the channel region. The insulator layer of the silicon-on-insulator circuitry is formed. The insulator layer is formed to comprise a first silicon dioxide comprising region in contact with the silicon comprising layer and running along at least a portion of the channel region between the source/drain regions. A silicon nitride comprising region is formed in contact with the first silicon dioxide comprising region and runs along at least a portion of the channel region. A second silicon dioxide comprising region is formed in contact with the silicon nitride comprising region. The silicon nitride comprising region is received intermediate the first and second silicon dioxide comprising regions.[0007]
- Integrated circuitry is also contemplated regardless of the method of fabrication.[0008]
- Preferred embodiments of the invention are described below with reference to the following accompanying drawings.[0009]
- FIG. 1 is a diagrammatic view of a wafer in process in accordance with an aspect of the invention.[0010]
- FIG. 2 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 1.[0011]
- FIG. 3 is a view of the FIG. 2 wafer at a processing step subsequent to that shown by FIG. 2.[0012]
- FIG. 4 is a view of the FIG. 3 wafer at a processing step subsequent to that shown by FIG. 3, and positioned relative to another wafer.[0013]
- FIG. 5 is a view of the FIG. 4 wafers at a processing step subsequent to that shown by FIG. 4.[0014]
- FIG. 6 is an enlarged diagrammatic sectional view of a portion of the joined wafers of FIG. 5 after subsequent processing.[0015]
- FIG. 7 is a view of an alternate embodiment to that depicted by FIG. 6.[0016]
- FIG. 8 is a view of another alternate embodiment to that depicted by FIG. 6.[0017]
- FIG. 9 is a view of still another alternate embodiment to that depicted by FIG. 6.[0018]
- This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).[0019]
- A first embodiment of a method of forming silicon-on-insulator comprising integrated circuitry is described with reference to FIGS. 1-6, and comprises a wafer bonding method. FIG. 1 depicts a device wafer or[0020]
first substrate 10. Preferably, such comprises a bulkmonocrystalline silicon substrate 12. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated.Substrate 12 includes anouter surface 14. Someportion 15 thereof is intended to be joined with another substrate, as will be apparent from the continuing discussion in a preferred wafer bonding method of forming silicon-on-insulator comprising integrated circuitry. In the depicted and preferred embodiment,outer surface 14 comprises crystalline silicon. - Referring to FIG. 2, at least a portion of outer silicon surface of[0021]
device wafer 10 is nitridized, with the depictedportion including portion 15 and all ofouter surface 14, to form a siliconnitride comprising region 16. By way of example only, such nitridizing might include any one or combination of ion implanting, direct plasma nitridation, remote plasma nitridation, and chemical vapor deposition. The nitridation might also be conducted to be void of either direct or remote nitrogen containing plasma exposure, for example by furnace annealing in a nitrogen containing atmosphere. Example nitrogen containing species for any of the above include N2, NOx, NH3and N2O. A preferred thickness forregion 16 is from about 5 Angstroms to about 50 Angstroms. - Referring to FIG. 3, at least a portion of[0022]
nitride comprising layer 16 is oxidized, preferably to form a silicon dioxide orsilicon oxynitride layer 18. In one preferred embodiment,nitride comprising layer 16 has a thickness of from about 5 Angstroms to about 50 Angstroms at the conclusion of the oxidizing. An exemplary thickness foroxide layer 18 is from about 50 Angstroms to about 500 Angstroms. - Referring to FIG. 4, device wafer or[0023]
first substrate 10 is depicted diagrammatically proximate a handle wafer orsecond substrate 20.Second substrate 20 also preferably comprises a bulkmonocrystalline silicon substrate 22 which has been oxidized to form a silicondioxide comprising layer 24. An example process for forminglayer 24 includes thermal growth or deposition, for example by CVD. For purposes of the continuing discussion,handle wafer 20 can be considered as comprising a silicondioxide comprising surface 25. - Referring to FIG. 5,[0024]
device wafer 10 is joined withhandle wafer 20, with the preferred embodiment depicting joiningdevice wafer 10 with silicondioxide comprising surface 25 ofhandle wafer 20. Such forms a joinedsubstrate 30. Such comprises but one preferred embodiment of an aspect of the invention. Such aspect includes a wafer bonding method of forming silicon-on-insulator comprising integrated circuitry whereby the method comprises nitridizing at least a portion of an outer surface of silicon of a device wafer. Thereafter, the device wafer is joined with the handle wafer and regardless of what subsequent processing occurs to finally form integrated circuitry. One exemplary method to bondsubstrate 10 withsubstrate 20 includes applying a suitable high voltage with opposite polarity on the device wafer and on the handle wafer. Pressing the substrates together at elevated temperature and pressure can also result in a suitable bonding. Further, by way of example only and if the oxide layer is very thin, a thermal oxidation can be conducted while pressing them together a high pressure. - The most preferred embodiment ultimately includes forming the integrated circuitry to comprise a silicon-on-insulator field effect transistor, for example and by way of example only, that depicted by FIG. 6. FIG. 6 depicts joined[0025]
substrate 30 having been polished or otherwise etched back to form the depictedsilicon comprising material 12 from what was theindependent device wafer 10. Further thinning of joinedsubstrate 30 can be accomplished by polishing or chemical/etching means, if desired. An exemplarythickness form material 12 in FIG. 6 is from about 1000 Angstroms to about 2000 Angstroms. A pair of source/drain regions silicon comprising layer 12. Agate construction 36 overliessilicon comprising layer 12 intermediate source/drain regions gate dielectric layer 38,insulative sidewall spacers 40, and a conductivetransistor gate region 41. Exemplary materials forlayers gate region 41 including conductively doped polysilicon and silicides. - In the depicted and preferred embodiment, layers/[0026]
regions 16/18/24 comprise aninsulator layer 42 of the silicon-on-insulator circuitry which contactssilicon comprising layer 12. Such results in the formation of aninterface 43 ofsilicon comprising layer 12 of the silicon-on-insulator circuitry withinsulator layer 42 of the silicon-on-insulator circuitry. Source/drain regions insulator layer 42. Also in the depicted and preferred embodiment, source/drain regions transistor gate construction 36 form achannel region 44 which is received intermediate the source/drain regions, and in the preferred embodiment, is partially depleted (not extending completely through the thickness of silicon comprising layer12) in operation, as shown. Regardless,nitridized portion 16 is received intermediate source/drain regions silicon dioxide 18/24. Siliconnitride comprising region 16 ideally has greater leakage current characteristics whereby increased leakage current can occur across that portion ofsilicon comprising layer 12 received between source/drain regions nitride comprising region 16. Alternately considered, and in no way by means of limitation, source/drain forward bias current and leakage are increased, which preferably increases trap density and reduces carrier lifetime, which results in higher junction current. - The above describes but one exemplary preferred embodiment of nitridizing an interface of a silicon comprising layer of silicon-on-insulator circuitry with an insulator of the silicon-on-insulator circuitry. After such nitridizing, a field effect transistor gate is formed operably proximate the silicon nitride comprising layer. The above-described preferred embodiment comprises forming the circuitry by joining a first substrate comprising the silicon comprising layer with a second substrate comprising the insulator layer to form a joined substrate. In the above-described depicted preferred embodiment, the nitridizing includes nitridizing at least one of the first and second substrates prior to the joining. Accordingly, either or both of the substrates could be nitridized prior to the joining. By way of example only, the invention also contemplates nitridizing at least a portion of an outer surface of silicon[0027]
dioxide comprising layer 24 ofhandle wafer 20 with or without any nitridation or oxidation of any portion of the outer surface ofdevice wafer 10. Accordingly, in such embodiment, the outer surface of the device wafer to which the handle wafer is joined might comprise crystalline silicon, silicon nitride and/or silicon dioxide. - The invention also contemplates a lesser preferred embodiment wherein the nitridizing of the interface occurs after forming the joined substrate. For example, the FIG. 6 construction might be formed by conducting an ion implant after joining to form silicon[0028]
nitride comprising region 16. - Regardless of the method of fabrication, the invention also contemplates silicon-on-insulator comprising integrated circuitry, by way of example only, such as the integrated circuitry depicted by FIG. 6. The invention contemplates a substrate comprising an insulator layer of silicon-on-insulator circuitry where such insulator layer comprises silicon dioxide. The silicon-on-insulator circuitry comprises a semiconductive silicon comprising layer received proximate the insulator layer, with the silicon comprising layer comprising a pair of source/drain regions formed therein and a channel region formed therein which is received intermediate the source/drain regions. A transistor gate is received operably proximate the channel region. A silicon nitride comprising region is received intermediate the silicon dioxide comprising layer and the source/drain regions, and runs along at least a portion of the channel region between the source/drain regions.[0029]
- FIG. 6 depicts a construction whereby a silicon[0030]
nitride comprising region 16 runs entirely along and against the channel region between the source/drain regions. FIGS. 7 and 8 depictalternate embodiments 30aand30bcomprising alternate siliconnitride comprising regions channel region 44 between source/drain regions - Further by way of example only, FIG. 9 depicts an alternate construction contemplated in both a method and in circuitry independent of the method in accordance with aspects of the invention. FIG. 9 depicts a[0031]
wafer fragment 30ccomprising an alternate embodiment siliconnitride comprising region 16c. Such could, by way of example only, be formed by any of the nitridation and joining methods described above. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated with the suffix “c”.Insulator layer 42cis formed to comprise a first silicondioxide comprising region 50 in contact withsilicon comprising layer 12 and running along at least a portion ofchannel region 44 between source/drain regions region 50 is from about 10 Angstroms to 30 Angstroms. Siliconnitride comprising region 16cis formed in contact with first silicondioxide comprising region 50 and runs along at least a portion ofchannel region 44. A second silicondioxide comprising region 52 is formed in contact with siliconnitride comprising region 16c, with siliconnitride comprising region 16cbeing received intermediate first silicondioxide comprising region 50 and second silicondioxide comprising region 52. - In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.[0032]
Claims (61)
1. Silicon-on-insulator comprising integrated circuitry, comprising:
a substrate comprising an insulator layer of silicon-on-insulator circuitry, the insulator layer comprising silicon dioxide;
a semiconductive silicon comprising layer of the silicon-on-insulator circuitry, the silicon comprising layer being received proximate the insulator layer, the silicon comprising layer comprising a pair of source/drain regions formed therein and a channel region formed therein which is received intermediate the source/drain regions;
a transistor gate received operably proximate the channel region; and
a silicon nitride comprising region received intermediate the silicon dioxide comprising layer and the source/drain regions and running along at least a portion of the channel region between the source/drain regions.
2. The circuitry ofclaim 1 wherein the silicon nitride comprising region runs along only a portion of the channel region between the source/drain regions.
3. The circuitry ofclaim 1 wherein the silicon nitride comprising region runs entirely along the channel region between the source/drain regions.
4. The circuitry ofclaim 1 wherein the silicon comprising layer contacts the insulator layer, and the source/drain regions extend to the insulator layer.
5. The circuitry ofclaim 1 wherein,
the silicon nitride comprising region runs entirely along the channel region between the source/drain regions; and
the silicon comprising layer contacts the insulator layer, and the source/drain regions extend to the insulator layer.
6. The circuitry ofclaim 1 wherein the silicon nitride comprising region has a thickness of from about 10 Angstroms to about 50 Angstroms.
7. Silicon-on-insulator comprising integrated circuitry, comprising:
a substrate comprising an insulator layer of silicon-on-insulator circuitry, the insulator layer comprising silicon dioxide;
a semiconductive silicon comprising layer of the silicon-on-insulator circuitry, the silicon comprising layer being received on the insulator layer, the silicon comprising layer comprising a pair of source/drain regions formed therein and extending to the insulator layer, the silicon comprising layer comprising a partially depleted channel region formed therein which is received intermediate the source/drain regions;
a transistor gate received operably proximate the channel region; and
a silicon nitride comprising region received intermediate the silicon dioxide comprising layer and the source/drain regions and running along at least a portion of the channel region between the source/drain regions.
8. The circuitry ofclaim 7 wherein the silicon nitride comprising region runs along only a portion of the channel region between the source/drain regions.
9. The circuitry ofclaim 7 wherein the silicon nitride comprising region runs entirely along the channel region between the source/drain regions.
10. The circuitry ofclaim 7 wherein the silicon nitride comprising region has a thickness of from about 10 Angstroms to about 50 Angstroms.
11. Silicon-on-insulator comprising integrated circuitry, comprising:
a substrate comprising a semiconductive silicon comprising layer of silicon-on-insulator circuitry, the silicon comprising layer comprising a pair of source/drain regions formed therein and a channel region formed therein which is received intermediate the source/drain regions;
a transistor gate received operably proximate the channel region; and
an insulator layer of the silicon-on-insulator circuitry received on the silicon comprising layer, the insulator layer comprising a first silicon dioxide comprising region in contact with the silicon comprising layer and running along at least a portion of the channel region between the source/drain regions, a silicon nitride comprising region in contact with the first silicon dioxide comprising region and running along at least a portion of the channel region, and a second silicon dioxide comprising region in contact with the silicon nitride comprising region, the silicon nitride comprising region being received intermediate the first and second silicon dioxide comprising regions.
12. The circuitry ofclaim 11 wherein the silicon nitride comprising region runs along only a portion of the channel region between the source/drain regions.
13. The circuitry ofclaim 11 wherein the silicon nitride comprising region runs entirely along the channel region between the source/drain regions.
14. The circuitry ofclaim 11 wherein the silicon nitride comprising region has a thickness of from about 10 Angstroms to about 50 Angstroms.
15. The circuitry ofclaim 11 wherein the first silicon dioxide comprising region has a thickness of from about 10 Angstroms to about 30 Angstroms.
16. The circuitry ofclaim 11 wherein the source/drain regions extend to the insulator layer.
17. A method of forming silicon-on-insulator comprising integrated circuitry, comprising:
nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry; and
after the nitridizing, forming a field effect transistor gate operably proximate the silicon comprising layer.
18. The method ofclaim 17 comprising forming said circuitry by joining a first substrate comprising the silicon comprising layer with a second substrate comprising the insulator layer, the nitridizing comprising nitridizing at least one of the first and second substrates prior to the joining.
19. The method ofclaim 18 wherein the nitridizing comprises chemical vapor deposition.
20. The method ofclaim 17 comprising forming said circuitry by joining a first substrate comprising the silicon comprising layer with a second substrate comprising the insulator layer to form a joined substrate, the nitridizing comprising nitridizing after forming the joined substrate.
21. The method ofclaim 17 wherein the nitridizing comprises ion implanting.
22. The method ofclaim 17 wherein the nitridizing comprises direct plasma nitridation.
23. The method ofclaim 17 wherein the nitridizing comprises remote plasma nitridation.
24. The method ofclaim 17 wherein the nitridation is void of either direct or remote nitrogen containing plasma exposure.
25. A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry, comprising:
nitridizing at least a portion of an outer surface of silicon of a device wafer; and
after the nitridizing, joining the device wafer with a handle wafer.
26. The method ofclaim 25 further comprising oxidizing at least the nitridized portion prior to the joining.
27. The method ofclaim 25 comprising forming the integrated circuitry to comprise a silicon-on-insulator field effect transistor.
28. The method ofclaim 25 wherein the nitridizing comprises ion implanting.
29. The method ofclaim 25 wherein the nitridizing comprises direct plasma nitridation.
30. The method ofclaim 25 wherein the nitridizing comprises remote plasma nitridation.
31. The method ofclaim 25 wherein the nitridizing comprises chemical vapor deposition.
32. The method ofclaim 25 wherein the nitridation is void of either direct or remote nitrogen containing plasma exposure.
33. A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry, comprising:
nitridizing at least a portion of an outer surface of silicon of a device wafer;
after the nitridizing, joining the device wafer with a silicon dioxide comprising surface of a handle wafer;
forming a pair of source/drain regions separated by a channel region within the silicon, the nitridized portion being received intermediate the source/drain regions and the silicon dioxide comprising surface; and
forming a field effect transistor gate operably proximate the channel region.
34. The method ofclaim 33 further comprising oxidizing at least the nitridized portion prior to the joining.
35. The method ofclaim 33 wherein the nitridizing comprises ion implanting.
36. The method ofclaim 33 wherein the nitridizing comprises direct plasma nitridation.
37. The method ofclaim 33 wherein the nitridizing comprises remote plasma nitridation.
38. The method ofclaim 33 wherein the nitridizing comprises chemical vapor deposition.
39. The method ofclaim 33 wherein the nitridation is void of either direct or remote nitrogen containing plasma exposure.
40. A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry, comprising:
forming silicon dioxide on at least a portion of an outer surface of a handle wafer;
nitridizing at least a portion of an outer surface of the silicon dioxide;
after the nitridizing, joining the handle wafer with an outer surface of a device wafer;
forming a pair of source/drain regions separated by a channel region within the silicon, the nitridized portion being received intermediate the source/drain regions and the silicon dioxide; and
forming a field effect transistor gate operably proximate the channel region.
41. The method ofclaim 40 wherein the outer surface of the device wafer to which the handle wafer is joined comprises crystalline silicon.
42. The method ofclaim 40 wherein the outer surface of the device wafer to which the handle wafer is joined comprises silicon nitride.
43. The method ofclaim 40 wherein the outer surface of the device wafer to which the handle wafer is joined comprises silicon dioxide.
44. The method ofclaim 40 wherein the nitridizing comprises ion implanting.
45. The method ofclaim 40 wherein the nitridizing comprises direct plasma nitridation.
46. The method ofclaim 40 wherein the nitridizing comprises remote plasma nitridation.
47. The method of claim.40 wherein the nitridizing comprises chemical vapor deposition.
48. The method ofclaim 40 wherein the nitridation is void of either direct or remote nitride containing plasma exposure.
49. A method of forming silicon-on-insulator comprising integrated circuitry, comprising:
forming the silicon comprising layer of the silicon-on-insulator circuitry;
forming a pair of source/drain regions in the silicon comprising layer and a channel region in the silicon comprising layer which is received intermediate the source/drain regions;
forming a transistor gate operably proximate the channel region;
forming the insulator layer of the silicon-on-insulator circuitry, the insulator layer being formed to comprise a first silicon dioxide comprising region in contact with the silicon comprising layer and running along at least a portion of the channel region between the source/drain regions, a silicon nitride comprising region in contact with the first silicon dioxide comprising region and running along at least a portion of the channel region, and a second silicon dioxide comprising region in contact with the silicon nitride comprising region, the silicon nitride comprising region being received intermediate the first and second silicon dioxide comprising regions.
50. The method ofclaim 49 comprising forming said circuitry by joining a first substrate comprising the silicon comprising layer with a second substrate comprising the insulator layer, forming the silicon nitride comprising region comprising nitridizing at least one of the first and second substrates prior to the joining.
51. The method ofclaim 50 wherein the nitridizing comprises ion implanting.
52. The method ofclaim 50 wherein the nitridizing comprises direct plasma nitridation.
53. The method ofclaim 50 wherein the nitridizing comprises remote plasma nitridation.
54. The method ofclaim 50 wherein the nitridation is void of either direct or remote nitrogen containing plasma exposure.
55. The method ofclaim 49 comprising forming said circuitry by joining a first substrate comprising the silicon comprising layer with a second substrate comprising the insulator layer to form a joined substrate, forming the silicon nitride comprising region comprising nitridizing after forming the joined substrate.
56. The method ofclaim 55 wherein the nitridizing comprises ion implanting.
57. The method ofclaim 55 wherein the nitridizing comprises direct plasma nitridation.
58. The method ofclaim 55 wherein the nitridizing comprises remote plasma nitridation.
59. The method ofclaim 55 wherein the nitridation is void of either direct or remote nitrogen containing plasma exposure.
60. The method ofclaim 55 comprising forming the silicon nitride comprising region to have a thickness of from about 10 Angstroms to about 50 Angstroms.
61. The method ofclaim 55 comprising forming the first silicon dioxide comprising region to have a thickness of from about 10 Angstroms to about 50 Angstroms.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/809,420US20040178449A1 (en) | 2002-01-16 | 2004-03-26 | Silicon-on-insulator comprising integrated circuitry and methods of forming silicon-on-insulator circuitry |
| US11/013,377US6936894B2 (en) | 2002-01-16 | 2004-12-17 | Silicon-on-insulator comprising integrated circuitry |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/051,981US20030134486A1 (en) | 2002-01-16 | 2002-01-16 | Semiconductor-on-insulator comprising integrated circuitry |
| US10/809,420US20040178449A1 (en) | 2002-01-16 | 2004-03-26 | Silicon-on-insulator comprising integrated circuitry and methods of forming silicon-on-insulator circuitry |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/051,981ContinuationUS20030134486A1 (en) | 2002-01-16 | 2002-01-16 | Semiconductor-on-insulator comprising integrated circuitry |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/013,377ContinuationUS6936894B2 (en) | 2002-01-16 | 2004-12-17 | Silicon-on-insulator comprising integrated circuitry |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20040178449A1true US20040178449A1 (en) | 2004-09-16 |
Family
ID=21974620
Family Applications (7)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/051,981AbandonedUS20030134486A1 (en) | 2002-01-16 | 2002-01-16 | Semiconductor-on-insulator comprising integrated circuitry |
| US10/340,126Expired - Fee RelatedUS6864155B2 (en) | 2002-01-16 | 2003-01-10 | Methods of forming silicon-on-insulator comprising integrated circuitry, and wafer bonding methods of forming silicon-on-insulator comprising integrated circuitry |
| US10/607,869Expired - LifetimeUS6974757B2 (en) | 2002-01-16 | 2003-06-27 | Method of forming silicon-on-insulator comprising integrated circuitry |
| US10/735,355Expired - Fee RelatedUS6984570B2 (en) | 2002-01-16 | 2003-12-12 | Wafer bonding method of forming silicon-on-insulator comprising integrated circuitry |
| US10/749,659Expired - LifetimeUS6903420B2 (en) | 2002-01-16 | 2003-12-30 | Silicon-on-insulator comprising integrated circuitry |
| US10/809,420AbandonedUS20040178449A1 (en) | 2002-01-16 | 2004-03-26 | Silicon-on-insulator comprising integrated circuitry and methods of forming silicon-on-insulator circuitry |
| US11/013,377Expired - LifetimeUS6936894B2 (en) | 2002-01-16 | 2004-12-17 | Silicon-on-insulator comprising integrated circuitry |
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| Application Number | Title | Priority Date | Filing Date |
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| US10/051,981AbandonedUS20030134486A1 (en) | 2002-01-16 | 2002-01-16 | Semiconductor-on-insulator comprising integrated circuitry |
| US10/340,126Expired - Fee RelatedUS6864155B2 (en) | 2002-01-16 | 2003-01-10 | Methods of forming silicon-on-insulator comprising integrated circuitry, and wafer bonding methods of forming silicon-on-insulator comprising integrated circuitry |
| US10/607,869Expired - LifetimeUS6974757B2 (en) | 2002-01-16 | 2003-06-27 | Method of forming silicon-on-insulator comprising integrated circuitry |
| US10/735,355Expired - Fee RelatedUS6984570B2 (en) | 2002-01-16 | 2003-12-12 | Wafer bonding method of forming silicon-on-insulator comprising integrated circuitry |
| US10/749,659Expired - LifetimeUS6903420B2 (en) | 2002-01-16 | 2003-12-30 | Silicon-on-insulator comprising integrated circuitry |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
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| US11/013,377Expired - LifetimeUS6936894B2 (en) | 2002-01-16 | 2004-12-17 | Silicon-on-insulator comprising integrated circuitry |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20050098828A1 (en) | 2005-05-12 |
| US6974757B2 (en) | 2005-12-13 |
| US20030134486A1 (en) | 2003-07-17 |
| US20040150046A1 (en) | 2004-08-05 |
| US20040124470A1 (en) | 2004-07-01 |
| US6984570B2 (en) | 2006-01-10 |
| US20040089863A1 (en) | 2004-05-13 |
| US6903420B2 (en) | 2005-06-07 |
| US6936894B2 (en) | 2005-08-30 |
| US6864155B2 (en) | 2005-03-08 |
| US20030138997A1 (en) | 2003-07-24 |
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