US20040166669A1 - Method of manufacturing semiconductor device having dual damascene structure - Google Patents

Abstract

A via hole is formed so as to reach a Cu interconnection through an interlayer insulating film that covers the Cu interconnection. A conductive polymeric member is buried in the via hole by electrolysis. A resist pattern is formed on the interlayer insulating film by photolithography, and a trench is formed so as to be connected to the via hole by etching by using the resist pattern as a mask. The resist pattern and the conductive polymeric member are removed thereafter.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0001]
• The present invention relates to a method of manufacturing a semiconductor device and, in particular, to a method of forming a dual damascene structure.[0002]
• 2. Description of the Background Art[0003]
• In recent years, wiring structures of semiconductor devices have come to be formed by a dual damascene process in which a via hole (connection hole) and a trench (wiring trench) are formed integrally. As described in Japanese Patent Laid-Open No. 2002-203898, for example, a via-first method in which the via hole is formed before the trench has an advantage over a trench-first method that a sufficient opening margin is secured even if the trench is deviated from the via hole.[0004]
• However, in the via-first method, to prevent a Cu interconnection from being damaged by trench formation etching, it is necessary to fill in the via hole with a filler material such as a resist or an organic ARC (anti-reflective coating) or the like in the following manner.[0005]
• FIGS. 5A to[0006]5G are sectional views showing a conventional method of manufacturing a semiconductor device.
• First, as shown in FIG. 5A, an[0007]interlayer insulating film2 is formed so as to cover aCu interconnection1. Then, as shown in FIG. 5B, avia hole3 is formed through theinterlayer insulating film2 by photolithography and etching. Then, as shown in FIG. 5C, afiller member21 is formed on theinterlayer insulating film2 including inside thevia hole3 by spin coating or the like.
• Subsequently, the[0008]filler member21 is etched back as shown in FIG. 5D. Aresist pattern22 is thereafter formed on theinterlayer insulating film2 as shown in FIG. 5E. Then, as shown in FIG. 5F, atrench23 is formed by etching by using theresist pattern22 as a mask.
• Then, the[0009]resist pattern22 and thefiller member21 are removed as shown in FIG. 5G. Thereafter, a wiring material such as Cu or the like is buried in thetrench23 and thevia hole3 to form a wiring structure.
• In the above conventional method in which the[0010]filler member21 is formed by spin coating, thefiller member21 needs to be etched back.
• However, it is difficult to accurately control a thickness of the[0011]filler member21 in an etch-back step, raising a problem that a height of thefiller member21 varies within the substrate and a height of the trench formation resist22 varies accordingly as shown in FIG. 6A.
• If photolithography is performed in such a state, differences occur between opening widths A of the[0012]resist pattern22 as shown in FIG. 6B, as a result of which a dimension of a trench interconnection varies.
SUMMARY OF THE INVENTION
• The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful method of manufacturing a semiconductor device.[0013]
• A more specific object of the present invention is to increase a controllability of a dimension of a trench formation resist pattern.[0014]
• The above object of the present invention is attained by a following method of manufacturing a semiconductor device.[0015]
• According to an aspect of the present invention, in the method, a via hole, which reaches an underlying interconnection through an interlayer insulating film that covers the underlying interconnection, is first formed. Next, a conductive polymeric member is formed in the via hole by electrolysis. Then, a resist pattern is formed on the interlayer insulating film. Finally, a trench connected to the via hole is formed by etching by using the resist pattern as a mask.[0016]
• Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.[0017]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIGS. 1A to[0018]1F are process sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention;
• FIGS. 2A to[0019]2G are sectional views showing a process of a modification of the first embodiment
• FIGS. 3A to[0020]3F are process sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the invention;
• FIGS. 4A to[0021]4E are process sectional views showing a method of manufacturing a semiconductor device according to a third embodiment of the invention;
• FIGS. 5A to[0022]5G are sectional views showing a conventional method of manufacturing a semiconductor device; and
• FIGS. 6A and 6B are sectional views showing a change in dimension of a resist pattern in the conventional manufacturing method.[0023]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• In the following, principles and embodiments of the present invention will be described with reference to the accompanying drawings. The members and steps that are common to some of the drawings are given the same reference numerals and redundant descriptions therefore may be omitted.[0024]
• First Embodiment[0025]
• FIGS. 1A to[0026]1F are process sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. More specifically, FIGS. 1A to1F illustrate a method of forming a dual damascene structure by a via-first method.
• First, as shown in FIG. 1A, a Cu interconnection as an underlying interconnection (lower-layer interconnection) is formed on a substrate (not shown) and an interlayer[0027]insulating film2 is formed above the entire substrate so as to cover theCu interconnection1.
• Then, as shown in FIG. 1B, after a resist pattern (not shown) is formed on the[0028]interlayer insulating film2 by photolithography, avia hole3 is formed through theinterlayer insulating film2 so as to reach the top surface of theCu interconnection1 by etching by using the resist pattern as a mask. The resist pattern is removed thereafter.
• Subsequently, as shown in FIG. 1C, a[0029]conductive polymeric member4 is formed only in the viahole3 by electrolysis. The burying of theconductive polymeric member4 is stopped at a top surface of theinterlayer insulating film2 by adjusting the time of the electrolysis. For example, theconductive polymeric member4 is made of a conductive polymer such as an aniline, pyrrole, or thiophene polymer. The pyrrole polymer is formed by electrolyzing a pyrrole monomer of 0.14 mol/l and a p-toluenesulfonate of 0.05 mol/l in a propylene carbonate solution as an electrolyte.
• Then, as shown in FIG. 1D, a trench formation resist[0030]pattern5 is formed on theinterlayer insulating film2 by photolithography. At this time, contrary to the conventional case, it is not necessary to etch back theconductive polymeric member4 because the top surface of theconductive polymeric member4 is flush with that of theinterlayer insulating film2, that is, a number of conductivepolymeric members4 have the same height within the substrate. Therefore, this manufacturing method is free of the problems that the resist film thickness varies due to difficulty in controlling the height of theconductivity polymeric member4 and that the dimension of the resistpattern5 varies.
• Then, as shown in FIG. 1E, a[0031]trench6 for an upper-layer interconnection is formed by etching theinterlayer insulating film2 and theconductive polymeric member4 by using the resistpattern5 as a mask.
• Then, the resist[0032]pattern5 and theconductive polymeric member4 are removed as shown in FIG. 1F. Thereafter, a wiring material such as Cu or the like is buried in thetrench6 and the viahole3, whereby a dual damascene structure is completed.
• As described above, in the first embodiment, after a via[0033]hole3 has been formed aconductive polymeric member4 is buried in the viahole3 by electrolysis. Since theconductive polymeric member4 is formed only in the viahole3, that is, it is not formed on theinterlayer insulating film2, it is not necessary to etch back the filler member like in the conventional case. Therefore, the number of manufacturing steps can be reduced and the manufacturing cost of a semiconductor device can be made lower than in the conventional case.
• Since it is not necessary to control the etch-back amount of the[0034]conductive polymeric member4, the dimensional variation of the trench formation resistpattern5 due to non-uniformity in the etch-back amount can be reduced. That is, the controllability of the dimension of the trench formation resistpattern5 is increased. The present inventor has found that it has become possible to reduce the dimensional variation of the line of a 0.14-μm line/space pattern from 0.14±0.02 μm to 0.14±0.01 μm. Using the resistpattern5 that is formed with such superior dimension controllability makes it possible to form, with high accuracy, thetrench6 and hence a dual damascene structure.
• In the first embodiment, the[0035]conductive polymeric member4 is buried in the viahole3 in such a manner that the top surface of theconductive polymeric member4 is flush with that of theinterlayer insulating film2. However, the position of the top surface of the conductive polymeric member4 (i.e., the height of the conductive polymeric member4) can easily be controlled by controlling the conditions, such as the time or the like, of the electrolysis.
• It is also possible to lower a height of the[0036]conductive polymeric member4 buried in the viahole3 by etching back theconductive polymeric member4 formed by the electrolysis.
• A modification of the first embodiment will be described below. FIGS. 2A to[0037]2G are sectional views showing a process of a modification of the first embodiment.
• This modification is basically the same as the first embodiment and is different from it in the following. In this modification, after a[0038]conductive polymeric member4 is formed in a viahole3 by electrolysis as shown in FIG. 2C, an organic ARC (anti-reflective coating)8 is formed on aninterlayer insulating film2 and theconductive polymeric member4 as shown in FIG. 2D. Then, a trench formation resistpattern5 is formed on the organic ARC as shown in FIG. 2E. At this time, theorganic ARC8 can be used as an anti-reflective coating when the resistpattern5 is formed by photolithography. Therefore, the controllability of the dimension of the resistpattern5 can be improved and hence thetrench6 can be formed with higher accuracy than even in the first embodiment.
• Second Embodiment[0039]
• FIGS. 3A to[0040]3F are process sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the invention.
• First, similarly as in the case of the first embodiment, an[0041]interlayer insulating film2 is formed so as to cover theCu interconnection1 and a viahole3 is formed through the interlayer insulating film2 (see FIGS. 3A and 3B).
• Then, as shown in FIG. 3C, a[0042]conductive polymeric member9 having a function of an anti-reflective coating is formed in the viahole3 and on theinterlayer insulating film2 by electrolysis. Theconductive polymeric member9 is made of a material that absorbs KrF excimer laser light, such as an anthracene derivative.
• Subsequently, as shown in FIG. 3D, a resist[0043]pattern5 is formed on theconductive polymeric member9 by photolithography by using a KrF excimer laser, for example, as a light source. During the photolithography, theconductive polymeric member9 which functions as an anti-reflective film exists under the resistpattern5, the controllability of the dimension of the resistpattern5 is improved. Since theconductive polymeric member9 is superior in flatness because it was formed by the electrolysis, it need not be etched back unlike in the conventional case.
• Then, as shown in FIG. 3E, a[0044]trench6 for an upper-layer interconnection is formed by etching theinterlayer insulating film2 and theconductive polymeric member9 by using the resistpattern5 as a mask.
• Then, as shown in FIG. 3F, the resist[0045]pattern5 and theconductive polymeric member9 are removed. Thereafter, a wiring material such as Cu or the like is buried in thetrench6 and the viahole3, whereby a dual damascene structure is completed.
• As described above, in the second embodiment, the[0046]conductive polymeric member9 is formed in the viahole3 and on theinterlayer insulating film2 by controlling the electrolysis time or the like and theconductive polymeric member9 is given the function of an anti-reflective coating. Thereby, theconductive polymeric member9 can be used as an anti-reflective coating when the trench formation resistpattern5 is formed. This increases the controllability of the dimension of the resistpattern5. Further, since it is not necessary to etch back the filler member unlike in the conventional case, the number of manufacturing steps can be reduced and the manufacturing cost of a semiconductor device can be lowered.
• Third Embodiment[0047]
• FIGS. 4A to[0048]4E are process sectional views showing a method of manufacturing a semiconductor device according to a third embodiment of the invention.
• First, as shown in FIG. 4A, a plurality of[0049]Cu interconnections11 and12 are formed on a substrate and aninterlayer insulating film2 is formed above the entire substrate so as to cover the Cu interconnections11 and12. Then, viaholes13 and14 are formed through theinterlayer insulating film2 by photolithography and etching so as to reach therespective Cu interconnections11 and12. Then, a resist pattern is formed as amask15 that covers a region including inside of the viahole13 where a dual damascene structure will not be formed and that does not cover a region where to form the dual damascene structure.
• Then, as shown in FIG. 4B, a[0050]conductive polymeric member16 is formed by electrolysis only in the viahole14 which is not covered with the resistfilm15.
• Subsequently, as shown in FIG. 4C, the resist[0051]pattern15 is removed by using an organic solvent. Since theconductive polymeric member16 is insoluble in the organic solvent, only the resistpattern15 is removed selectively.
• Then, as shown in FIG. 4D, a trench formation resist[0052]pattern17 is formed on theinterlayer insulating film2 including inside the viahole13 by photolithography.
• Then, as shown in FIG. 4E, a[0053]trench18 for an upper-layer interconnection is formed by etching theinterlayer insulating film2 and theconductive polymeric member16 using the resistpattern17 as a mask. Then, the resistpattern17 and theconductive polymeric member16 are removed. Thereafter, a wiring material such as Cu is buried in the viahole13, thetrench18, and the viahole14, whereby wiring structures are completed.
• As described above, in the third embodiment, after the via[0054]hole13 for which a trench will not be formed of the plurality of viaholes13 and14 is covered with the resistpattern15, theconductive polymeric member16 is formed by electrolysis in the viahole14 which is not covered with the resistpattern15. In this manner, a conductive polymeric member can be buried selectively by using a mask in a via hole that needs to be filled with a filler member among a plurality of via holes.
• Although the third embodiment is directed to the case that two via holes are formed, three or more via holes may be formed.[0055]
• This invention, when practiced illustratively in the manner described above, provides the following major effects:[0056]
• According to the invention, the controllability of the dimension of a trench formation resist pattern can be improved.[0057]
• Further, the present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention.[0058]
• The entire disclosure of Japanese Patent Application No. 2003-043303 filed on Feb. 20, 2003 containing specification, claims, drawings and summary are incorporated herein by reference in its entirety.[0059]

Claims (6)

What is claimed is:

1. A method of manufacturing a semiconductor device having a dual damascene structure, comprising the steps of:

forming a via hole which reaches an underlying interconnection through an interlayer insulating film that covers the underlying interconnection;

forming a conductive polymeric member in the via hole by electrolysis;

forming a resist pattern on the interlayer insulating film after said step of forming a conductive polymeric member; and

forming a trench connected to the via hole by etching by using the resist pattern as a mask.

2. The method according toclaim 1, wherein the conductive polymeric member is made of one selected from an aniline polymer, a pyrrole polymer, and a thiophene polymer.

3. The method according toclaim 1, wherein the conductive polymeric member is also formed on the interlayer insulating film and absorbs exposure light used in said step of forming a resist pattern.

4. The method according toclaim 3, wherein the exposure light is KrF excimer laser light, and the conductive polymeric member contains an anthracene derivative.

5. The method according toclaim 1, further comprising the step of forming an anti-reflective film on the interlayer insulating film and the conductive polymeric member after said step of forming a conductive polymeric member,

wherein the resist pattern is formed on the anti-reflective film.

6. The method according toclaim 1, wherein a plurality of via holes are formed in said step of forming a via hole, and wherein the method further comprises the step of masking, before the conductive polymeric member is formed, a via hole in which the conductive polymeric member is not be formed among the plurality of via holes.

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