US20040166604A1 - Phase changeable memory cells and methods of fabricating the same - Google Patents

Abstract

A phase changeable memory cell is disclosed. According to embodiments of the invention, a phase changeable memory cell is formed that has a reduced contact area with one of the electrodes, compared to previously known phase changeable memory cells. This contact area can be a sidewall of one of the electrodes, or a perimeter edge of a contact opening through the electrode. Thus, when the thickness of the electrode is relatively thin, the contact area between the electrode and the phase changeable material pattern is relatively very small. As a result, it is possible to reduce power consumption of the phase changeable memory device and to form reliable and compact phase changeable memory cells.

Description

TECHNICAL FIELD
• This disclosure relates to phase changeable memory devices and, more particularly, to phase changeable memory cells having sidewall contacts adjacent to a phase changeable material, and methods of fabricating the same.[0001]
BACKGROUND
• Semiconductor memory devices for storing data can be typically categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when they are no longer coupled to their power supplies, whereas nonvolatile memory devices retain their stored data even without supplied power. Thus, nonvolatile memory devices are widely used in applications where the possibility of power supply interruption is present. For example, nonvolatile memory cells are widely used in cellular phones, digital cameras, MP[0002]3 players, etc.
• One popular type of nonvolatile memory device is made of flash memory cells having stacked gate structures. Each of the stacked gate structures includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked.[0003]
• Although flash memory cells have been widely used for a number of years, a relatively new type nonvolatile memory cell is being developed that has several advantages over flash cells. Specifically, a nonvolatile memory device including a phase changeable memory cell is being developed, in part, to replace flash type memory cells.[0004]
• FIG. 1 is an equivalent circuit diagram of a typical phase changeable memory cell. In FIG. 1, a phase changeable memory cell[0005]10 includes a single access transistor T_Aand a single variable resistor R_v. The variable resistor R_vincludes a bottom electrode, a top electrode and a phase changeable material layer pattern interposed therebetween. The top electrode is electrically connected to a bit line BL. Also, the access transistor T_Aincludes a source region S that is electrically connected to the bottom electrode, a drain region D which is spaced apart from the source region, and a gate electrode G that is disposed over a channel region between the source region S and the drain region D. The gate electrode G and the drain region D are electrically connected to a word line WL and an interconnection line IL, respectively. As a result, the equivalent circuit of the phase changeable memory cell is similar to that of a DRAM cell. However, properties of the phase changeable material are quite different from that of the dielectric layer of the DRAM cell capacitor. Specifically, the phase changeable material has two stable states that change from one to another based on temperature and time. This allows the variable resistor R_vto have a relatively low or relatively high resistance value, dependent on the state of the phase changeable material. Because this resistance value affects the operation of the memory cell, the state of the phase changeable can be determined by sensing the affect of electrical signals applied to the cell.
• FIG. 2 is a graph that illustrates a method of writing data into a phase changeable memory cell. The x-axis represents time T, and the y-axis represents temperature TMP that is applied to the phase changeable material.[0006]
• Referring to FIG. 2, when the phase changeable material layer is heated to a temperature that is higher than its melting temperature Tm and is cooled down rapidly within a quenching time t[0007]1, which is shorter than the crystallization time of the phase changeable material, the phase changeable material layer is transformed into an amorphous state (refer to curve {circle over (1)}). On the contrary, when the phase changeable material layer is heated to a temperature that is in a range between the crystallization temperature Tc and the melting temperature Tm for a second duration T2 (longer than the first duration T1) and is cooled down, the phase changeable material layer is transformed into a crystalline state (refer to curve {circle over (2)}).
• Here, a resistivity of the phase changeable material layer in the amorphous state is higher than that of the phase changeable material layer in the crystalline state. Thus, it is possible to determine whether the information stored in the memory cell is a logic “1” or a logic “0” by detecting current that flows through the phase changeable material layer in a read operation of the memory cell.[0008]
• A material that is widely used as a phase changeable material layer is a compound containing germanium Ge, antimony (stibium) Sb and tellurium Te (hereinafter, referred to as a GST layer).[0009]
• FIG. 3 is a cross-sectional view of a conventional phase changeable memory cell. In that figure, an[0010]isolation layer13 is located at a predetermined region of asemiconductor substrate11. Theisolation layer13 defines an active region. Asource region17sand adrain region17dare disposed in the active region and are spaced apart from each other. A word line is coupled to agate electrode15, which is disposed across the active region between thesource region17sand thedrain region17d. Thegate electrode15, thesource region17sand thedrain region17dform an access transistor (T_Aof FIG. 1). Thesubstrate11 having the access transistor is covered with a firstinsulating layer19. An interconnection line21 is disposed on the firstinsulating layer19. The interconnection line21 is electrically connected to thedrain region17dthrough a contact hole that penetrates the firstinsulating layer19. A secondinsulating layer23 covers the interconnection line21. Aheating plug25 is disposed in the first and secondinsulating layers19 and23. Theheating plug25 is electrically connected to thesource region17s. A phase changeablematerial layer pattern27 and atop electrode29 are sequentially stacked on the secondinsulating layer23. A bottom surface of the phase changeablematerial layer pattern27 is in contact with theheating plug25. A thirdinsulating layer31 is disposed on the secondinsulating layer23, and sidewalls of the phase changeablematerial layer pattern27 and thetop electrode29 are surrounded by the thirdinsulating layer31. Abit line33 is located on the third insulatinglayer31 and is in contact with thetop electrode29.
• In a write mode, the access transistor T[0011]_Ais turned on and a large current flows through theheating plug25. As a result, an interface between the phase changeablematerial layer pattern27 and theheating plug25 is heated up to transform aportion27aof the phasechangeable material layer27 into either the amorphous state or the crystalline state, dependant on the length of time and amount of current that flows through theheating plug25, as explained with reference to FIG. 2.
• One problem with the conventional phase changeable transistor as shown in FIG. 3 is that it requires a relatively large amount of current to successfully change the state of the phase changeable material in a successful write operation. One solution would be to reduce a diameter D of the[0012]heating plug25. However, there is a limitation in reducing the diameter D of theheating plug25, because the minimum diameter D is determined by a photolithographic process. That is to say, it is difficult to consistently make theheating plug25 with a small diameter because of limitations in the present semiconductor processes.
• Embodiments of the invention address this and other limitations of the prior art.[0013]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a schematic diagram of a phase changeable transistor.[0014]
• FIG. 2 is a graph illustrating times and temperatures applied to a phase changeable transistor material to cause the material to change into different states.[0015]
• FIG. 3 is a cross-sectional view of a portion of a phase changeable memory cell according to the prior art.[0016]
• FIG. 4 is a diagram of a layout view of a pair of phase changeable memory cells according to embodiments of the invention.[0017]
• FIG. 5 is a cross-sectional view of a portion of the pair of phase changeable memory cells of FIG. 4.[0018]
• FIG. 6 is a diagram of a layout view of a pair of phase changeable memory cells according to embodiments of the invention.[0019]
• FIG. 7 is a cross-sectional view of a portion of the pair of phase changeable memory cells of FIG. 6.[0020]
• FIGS.[0021]8-13 are cross-sectional diagrams illustrating processes used to form memory cells according to embodiments of the invention as illustrated in FIGS. 4 and 5.
• FIGS.[0022]14-16 are cross-sectional diagrams illustrating processes used to form memory cells according to embodiments of the invention as illustrated in FIGS. 6 and 7.
• FIG. 17 is a diagram of a layout view of a pair of phase changeable memory cells according to embodiments of the invention.[0023]
• FIG. 18 is a cross-sectional view of a portion of the pair of phase changeable memory cells of FIG. 17.[0024]
• FIGS.[0025]19-21 are cross-sectional diagrams illustrating processes used to form memory cells according to embodiments of the invention as illustrated in FIGS. 17 and 18.
DETAILED DESCRIPTION
• Embodiments of the present invention include phase changeable memory cells having a phase changeable material formed between a first electrode and adjacent to a sidewall contact of a second electrode. Because the structure of the inventive memory cells does not include features that depend on minimum design constraints of semiconductor processing, elements of the cells can be made much smaller than elements in conventional memory cells. Therefore, memory cells according to embodiments of the invention can be designed to use much less power than conventional phase changeable memory cells.[0026]
• FIG. 4 is a top plan view illustrating a pair of phase changeable memory cells according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along a line I-I′ of FIG. 4.[0027]
• Referring to FIGS. 4 and 5, an[0028]isolation layer53 is disposed at a predetermined region of asemiconductor substrate51. Theisolation layer53 defines edges of anactive region53a. Afirst source region61s′ and asecond source region61s″ are located at both ends of theactive region53a, respectively. In addition, acommon drain region61dis centrally disposed in theactive region53a. Afirst gate electrode57aspans a first channel region between thefirst source region61s′ and thecommon drain region61d. Similarly, asecond gate electrode57bspans a second channel region between thesecond source region61s″ and thecommon drain region61d. The first andsecond gate electrodes57aand57bact as a first word line and a second word line, respectively. Thefirst gate electrode57a, thefirst source region61s′ and thecommon drain region61dconstitute a first access transistor. Also, thesecond gate electrode57b, thesecond source region61s″ and thecommon drain region61dconstitute a second access transistor.
• The[0029]substrate51 is covered with a first insulatinglayer63. Aninterconnection line67iis disposed on the first insulatinglayer63 and is electrically connected to thecommon drain region61dthrough adrain contact hole63ithat penetrates a portion of the first insulatinglayer63. Theinterconnection line67iruns in parallel with the word lines57aand57b. However, theinterconnection line67imay overlap the word lines57aand57b. The substrate having theinterconnection line67iis covered with a second insulatinglayer75. In some embodiments, the second insulatinglayer75 includes a lower insulatinglayer69, anetch stop layer71 and an upper insulatinglayer73. In this case, the lower insulatinglayer69 and the upper insulatinglayer73 may be a silicon oxide layer, for instance, and the etch stop layer may be a silicon nitride layer having an etch selectivity with respect to the silicon oxide layer, for instance.
• The[0030]first source region61s′ is exposed by a firstelectrode contact hole75athat passes through the first and second insulatinglayers63 and75. Similarly, thesecond source region61s″ is exposed by a secondelectrode contact hole75bthat passes through the first and second insulatinglayers63 and75. The firstelectrode contact hole75ais filled with a first electrode contact plug77p′, and the secondelectrode contact hole75bis filled with a second electrode contact plug77p″. Although not shown in FIG. 5, the contact plugs77p′ and77p″ may be fornmed in two stages, i.e., a first portion extending through only the insulatinglayer63, and a second portion extending through only the insulatinglayer75.
• A[0031]first bottom electrode79a′ and a secondbottom electrode79b′ are disposed on the second insulatinglayer75. The firstbottom electrode79a′ covers the first electrode contact plug77p′, and thesecond bottom electrode79b′ covers the second electrode contact plug77p″. The substrate having the first and secondbottom electrodes79a′ and79b′ is covered with a third insulatinglayer81.
• A portion of the[0032]etch stop layer71 is exposed by afirst trench83a, and another portion of theetch stop layer71 is exposed by asecond trench83b. Also, the first andsecond trenches83aand83bexpose a portion of the sidewall of the firstbottom electrode79a′ and a portion of the sidewall of thesecond bottom electrode79b′, respectively. Even when the second insulatinglayer75 is a single oxide layer, it is preferable that theinterconnection line67ibe still covered with a portion of the second insulatinglayer75.
• It is relatively easy to control the thickness of the[0033]bottom electrodes79a′ and79b′. Accordingly, in the event that the thickness of thebottom electrodes79a′ and79b′ is very thin, the areas of the exposed sidewalls of thebottom electrodes79a′ and79b′ are remarkably decreased as compared to the contact area between the bottom electrode and the phase changeable material of the conventional art (FIG. 3). In addition, it is preferable that a width of the first and secondbottom electrodes79a′ and79b′ (a first width W1) (FIG. 4) is less than a width of the first andsecond trenches83aand83b(a second width W2). This allows for uniform areas of the exposed sidewalls of thebottom electrodes79a′ and79b′, even if a misalignment between the bottom electrodes and thetrenches83aand83boccurs along a direction that is parallel to the word lines57aand57b.
• The first and[0034]second trenches83aand83bare filled with a first phase changeablematerial layer pattern85aand a second phase changeablematerial layer pattern85b, respectively. As described above, a common phase changeable material is a compound containing germanium Ge, antimony (stibium) Sb and tellurium Te (a GST layer), although any material having the appropriate qualities is useable by embodiments of the invention.
• When the[0035]trenches83aand83bare filled with the GST layer, the GST layer is adjacent to sidewall contact areas of thebottom electrodes79a′ and79b′. The contact area between the GST layer and these sidewall contacts is remarkably reduced as compared to the contact area of the conventional art. This translates into a much lower amount of current compared to prior art circuits (FIG. 3) necessary to set or reset the GST layer to store data within the memory cell.
• Top surfaces of the first and second phase changeable[0036]material layer patterns85aand85bare covered with a firsttop electrode87aand a secondtop electrode87b, respectively. A fourth insulatinglayer89 covers thetop electrodes87aand87b, as well as other areas of thesubstrate11. The firsttop electrode87ais exposed by a first bitline contact hole91athat passes through a portion of the fourth insulatinglayer89. Similarly, the secondtop electrode87bis exposed by a second bitline contact hole91bthat passes through another portion of the fourth insulatinglayer89. Abit line93 is located on the fourth insulatinglayer89. Thebit line93 is disposed to cross over the word lines57aand57b. Also, thebit line93 is electrically connected to thetop electrodes87aand87bthrough the bit line contact holes91aand91b.
• As described above, the respective phase changeable memory cells according to embodiments of the invention include the sidewall contact between the bottom electrode and the phase changeable material layer pattern. As mentioned above, the sidewall contact area of the bottom electrodes is not subject to the minimum design rule, which is determined by the resolution limit of the photolithography process. Rather, the sidewall contact area can be formed to be much smaller than the contact area between the bottom electrode and the phase changeable material layer pattern in the conventional art. Accordingly, it is possible to increase the current density at the sidewall contact of the bottom electrodes without employing a large access transistor. Thus,[0037]phase transition regions85p′ and85p″ can be successfully formed in the first and second phase changeablematerial layer patterns85aand85bwith small access transistors. Consequently, power consumption of memory cells according to embodiments of the invention is typically markedly reduced compared to cells of the prior art.
• FIG. 6 is a top plan view for illustrating a pair of phase changeable memory cells according to another embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along a line II-II′ of FIG. 6. This embodiment differs from the embodiment illustrated in FIGS. 4 and 5 in that a pair of memory cells are formed in a single active region and share a single common phase changeable material layer pattern. However, the active region, access transistors, interconnection line, insulating layers, bottom electrodes and the bit line of this embodiment have the same configurations as in the previously described embodiment. Thus, the explanations for those areas are omitted or mentioned only briefly.[0038]
• Referring to FIGS. 6 and 7, the[0039]bottom electrodes79a′ and79b′ are covered with a thirdinsulating layer101. Theetch stop layer71 between the first and secondbottom electrodes79a′ and79b′ is exposed by a singlecommon trench83c. Also, thecommon trench83cexposes a portion of the sidewall of the firstbottom electrode79a′ and a portion of the sidewall of thesecond bottom electrode79b′. It is preferable that a width of thecommon trench83c(a second width W2) (FIG. 6) is greater than a width of thebottom electrodes79a′ and79b′ (a first width W1). Thecommon trench83cis filled with a common phase changeablematerial layer pattern105a. Afirst portion105p′ of the common phase changeablematerial layer pattern105a, which is in contact with the exposed sidewall of the firstbottom electrode79a′, can be transformed into an amorphous state or a crystalline state according to current density at the interface between the firstbottom electrode79a′ and the common phase changeablematerial layer pattern105a. Similarly, asecond portion105p″ of the common phase changeablematerial layer pattern105a, which is in contact with the exposed sidewall of thesecond bottom electrode79b′, can be transformed into an amorphous state or a crystalline state according to current density at the interface between thesecond bottom electrode79b′ and the common phase changeablematerial layer pattern105a. A top surface of the common phase changeablematerial layer pattern105ais covered with atop electrode107a.
• The[0040]top electrode107aand other portions of thesubstrate51 are covered with a fourth insulatinglayer109. Thetop electrode107ais exposed by a first bitline contact hole111aand a second bitline contact hole111bthat pass through the fourth insulatinglayer109. Alternatively, thetop electrode107amay be exposed by a single bit line contact hole (not shown) instead of the first and second bit line contact holes11aand111b. Abit line113 is located on the fourth insulatinglayer109 as in the embodiment described with reference to FIGS. 4 and 5. Thebit line113 is formed such that it can cross over the word lines57aand57b. Also, thebit line113 electrically connects to thetop electrode107athrough the bit line contact holes111aand111b.
• In this embodiment, a pair of memory cells shares the single common phase changeable[0041]material layer pattern105a. Thus, it is possible to form a compact memory cell.
• FIGS.[0042]8-13 illustrate methods of fabricating the phase changeable memory cells described with reference to the earlier FIGS. 4 and 5. Referring to FIGS. 4, 5 and8, anisolation layer53 is formed at a predetermined region of asemiconductor substrate51. Theisolation layer53 defines edges of an active region (53aof FIG. 4). Theisolation layer53 may be formed by a conventional manner such as a trench isolation technique. Agate insulating layer55 is formed on theactive region53a. Thegate insulating layer55 may be formed of a thermal oxide layer, for instance. A gate conductive layer is then formed on an entire surface of the substrate having thegate insulating layer55. The gate conductive layer is patterned to form a pair ofgate electrodes57aand57bthat cross over theactive region53a. Thegate electrodes57aand57bact as word lines in the completed memory cell.
• After the[0043]gate electrodes57aand57bare formed, impurity ions are implanted into the active region using the gate electrodes as ion implantation masks. As a result, acommon drain region61dis formed in the active region between the first andsecond gate electrodes57aand57b. In addition, afirst source region61s′ is formed at the active region that is adjacent to thefirst gate electrode57aand opposite thecommon drain region61d, and asecond source region61s″ is formed in the active region that is adjacent to thesecond gate electrode57band opposite thecommon drain region61d. Therefore, a pair of access transistors is formed in the active region. The first access transistor includes thefirst gate electrode57a, thefirst source region61s′ and thecommon drain region61d, and the second access transistor includes thesecond gate electrode57b, thesecond source region61s″ and thecommon drain region61d.
• Further, a[0044]gate spacer59 may be formed on sidewalls of thegate electrodes57aand57b. In this case, the source/drain regions61s′,61s″ and61dmay have an LDD-type structure. As illustrated in FIG. 8, a first insulatinglayer63 is then formed on the entire surface of thesubstrate51.
• Referring to FIGS. 4, 5 and[0045]9, the first insulatinglayer63 is patterned to form adrain contact hole63i, and first and second source contact holes (unnumbered but illustrated). Thedrain contact hole63iexposes thecommon drain region61d. Also, the first and second source contact holes expose the first andsecond source regions61s′ and61s″, respectively. A first source contact plug65s′, a second source contact plug65s″ and adrain contact plug65dare formed in the respective contact holes in a conventional manner.
• A conductive layer is formed on the[0046]substrate51 after the contact plugs65d,65s′ and65s″ have been formed. The conductive layer is then patterned to form afirst pad67p′, asecond pad67p″ and aninterconnection line67i. The first andsecond pads67p′ and67p″ are formed to cover the first and second source contact plugs65s′ and65s″, respectively. Also, theinterconnection line67iis formed to cover thedrain contact plug65d. As illustrated in FIG. 9, theinterconnection line67iis formed to be parallel to the word lines57aand57b. However, theinterconnection line67imay be formed to cross over the word lines57aand57b.
• It is not strictly necessary that the first and second source contact holes, the first and second source contact plugs[0047]65s′ and65s″, and the first andsecond pads67p′ and67p″ even be formed. For instance, the memory cells illustrated in FIGS. 5 and 7 do not include these structures. Having these multiple-stage contact structures, however, relieves the necessity of making contact holes through both the insulatinglayers75 and63 at the same time in a later step, which may be difficult to accurately control. Additionally, because the same or similar process steps are used in forming those structures as forming thedrain contact plug65dand theinterconnect line67i, it is not a large extra expense to create these intermediate first and second pads69p′ and67p″.
• Referring to FIGS. 4, 5 and[0048]10, a second insulatinglayer75 is formed on thesubstrate51 over theinterconnection line67i, and over thepads67p′ and67p″ if present. The second insulatinglayer75 is preferably formed by sequentially stacking alower oxide layer69, anetch stop layer71 and anupper oxide layer73. In this case, theetch stop layer71 may be formed of a nitride layer that has an etch selectivity with respect to theupper oxide layer73. Alternatively, the second insulatinglayer75 can be formed of a single oxide layer. The second insulatinglayer75 is patterned to form a firstelectrode contact hole75aand a secondelectrode contact hole75b. The first and second electrode contact holes75aand75bexpose the first andsecond pads67p′ and67p″, respectively. If the first andsecond pads67p′ and67p″ and the first and second source contact plugs65s′ and65s″ are not formed in the previous processes, the first and second electrode contact holes75aand75bare formed by successively patterning both the second insulatinglayer75 and the first insulatinglayer63. In this case, the first and second electrode contact holes75aand75bexpose the first andsecond source regions61s′ and61s″, respectively.
• Subsequently, a first electrode contact plug[0049]77p′ and a second electrode contact plug77p″ are formed in the first and second electrode contact holes75aand75b, respectively. The first and second electrode contact plugs77p′ and77p″ may be formed using conventional processes.
• Next, a[0050]bottom electrode layer79 is formed on the surface of thesubstrate51, over the electrode contact plugs77p′ and77p″. Thebottom electrode layer79 may be formed of, for example, a TiN layer, a TiAIN layer, a TaN layer, a carbon layer or a TiW layer using a PVD process or a CVD process. Thebottom electrode layer79 is preferably formed to have a thickness of between about 1 nano-meter and 50 nano-meters. It is relatively easy to control the thickness of thebottom electrode layer79 by using processes known in the art. In addition, compared to the contact holes of the prior art (FIG. 3), it is recognizable to those skilled in the art that the thickness uniformity of the bottom electrode layer79 (which becomes the sidewall contacts of the memory cells) throughout the substrate is superior to the critical dimension (feature size) variation of the contact holes defined by the photolithography process.
• In some embodiments, a further insulating layer (not shown) is formed on the[0051]bottom electrode layer79 before performing the next process.
• Referring to FIGS. 4, 5 and[0052]11, the bottom electrode layer79 (and the insulating layer formed thereon, if present) is patterned to form a firstpreliminary bottom electrode79aand a secondpreliminary bottom electrode79bthat are spaced apart from each other. The firstpreliminary bottom electrode79acovers the first electrode contact plug77p′, and the secondpreliminary bottom electrode79bcovers the second electrode contact plug77p″. The first and secondpreliminary bottom electrodes79aand79bare formed to have a first width (W1 of FIG. 4). Next, a third insulatinglayer81 is formed on the substrate having thepreliminary bottom electrodes79aand79b. Aphotoresist pattern83 is then formed on the third insulatinglayer81.
• Referring to FIGS. 4, 5 and[0053]12, the third insulatinglayer81, thepreliminary bottom electrodes79aand79b, and theupper oxide layer73 are successively etched using thephotoresist pattern83 as an etching mask. As a result, afirst trench83aand asecond trench83bare formed in the third insulatinglayer81 and in theupper oxide layer73 in a location between the first and second electrode contact plugs77p′ and77p″. In addition, the firstpreliminary bottom electrode79ais etched to form a firstbottom electrode79a′, and the secondpreliminary bottom electrode79bis etched to form a secondbottom electrode79b′. Thus, thefirst trench83aexposes a portion of sidewall (79W) of the firstbottom electrode79a′ as well as a portion of theetch stop layer71, and thesecond trench83bexposes a portion of sidewall (79W) of thesecond bottom electrode79b′ as well as another portion of theetch stop layer71. Using this technique, it is possible to reduce significantly the area of the exposed sidewall79W of thebottom electrodes79a′ and79b′. That is to say, the area of the exposed sidewall79W is not subject to the resolution limit of the photolithography process, as is the conventional art, but rather the area of the exposed sidewall79W is a function of the thickness of thelayer79 used to form thebottom electrodes79a′ and79b′. This thickness can be precisely controlled.
• The first and[0054]second trenches83aand83bare preferably formed to have a second width (W2 of FIG. 4) that is greater than the first width W1. This allows for uniform areas of the exposed sidewalls of thebottom electrodes79a′ and79b′, even though a misalignment between the bottom electrodes and thephotoresist pattern83 may occur along a direction that is parallel to the word lines57aand57b.
• In an alternative embodiment, if the second insulating[0055]layer75 is formed of a single oxide layer, then the second insulatinglayer75 is preferably only partially etched during the formation of thetrenches83aand83b. This prevents theinterconnection line67ifrom being exposed by thetrenches83aand83b.
• Subsequent to forming the[0056]trenches83aand83b, thephotoresist pattern83 is removed. A phasechangeable material layer85 and atop electrode layer87 are sequentially formed on the substrate where thephotoresist pattern83 was removed. The phasechangeable material layer85 may be formed of the GST layer, described above, and thetop electrode layer87 can be formed of, for example, a TiN layer, a TiAIN layer, a TaN layer, a carbon layer or a TiW layer using a PVD technique or a CVD technique.
• Referring to FIGS. 4, 5 and[0057]13, thetop electrode layer87 and the phasechangeable material layer85 are patterned to form a first data storage pattern and a second data storage pattern. The first data storage pattern includes a first phasechangeable material pattern85aon which is stacked a firsttop electrode87a, and the second data storage pattern includes a second phasechangeable material pattern85bon which a secondtop electrode87bis stacked. Also, the first phasechangeable material pattern85agenerally fills thefirst trench83a, and the second phasechangeable material pattern85bgenerally fills thesecond trench83b. Contact regions C between thebottom electrodes79a′ and79b′ and the phasechangeable material patterns85aand85b, respectively, are illustrated in FIG. 13. They are much smaller than the comparable contact regions of the prior art, illustrated in FIG. 3.
• Next, a fourth insulating[0058]layer89 is formed covering the phasechangeable material patterns85a,85band thetop electrodes87a,87b. The fourth insulatinglayer89 is patterned to form a first bitline contact hole91aand a second bitline contact hole91b. The first and second bit line contact holes91aand91bexpose the first and secondtop electrodes87aand87b, respectively. A conductive layer is formed on the fourth insulatinglayer89 and in the bit line contact holes91aand91b. The conductive layer is patterned to form abit line93, which crosses over the word lines57aand57b. As illustrated in FIG. 13, thebit line93 is electrically connectable to the first and secondtop electrodes87aand87bthrough the first and second bit line contact holes91aand91b.
• FIGS.[0059]14 to16 are cross-sectional views for illustrating a method of fabricating the phase changeable memory cells according to embodiments of the invention illustrated in FIGS. 6 and 7.
• Referring to FIGS. 6, 7 and[0060]14, a pair of access transistors, aninterconnection line67iand a bottom electrode layer are formed in the same manner as described above with reference to FIGS.8 to10. The bottom electrode layer is then patterned to form apreliminary bottom electrode79cthat covers the first and second electrode contact plugs77p′ and77p″ as well as a second insulatinglayer75 between the first and second electrode contact plugs. Alternatively, the bottom electrode layer may be patterned to form the first and secondpreliminary bottom electrodes79aand79bas explained in the embodiments illustrated in FIGS.4-5. Thepreliminary bottom electrode79cis formed to have a first width (W1 of FIG. 6). A third insulatinglayer101 is formed over thepreliminary bottom electrode79cand other areas of thesubstrate51. Aphotoresist pattern103 is then formed on the third insulatinglayer101.
• Referring to FIGS. 6, 7 and[0061]15, the third insulatinglayer101, thepreliminary bottom electrode79cand theupper oxide layer73 are successively etched using thephotoresist pattern103 as an etching mask. As a result, thepreliminary bottom electrode79cis separated into twobottom electrodes79a′ and79b′, and acommon trench83cis formed on theetch stop layer71 between the first and second electrode contact plugs77p′ and77p″. Therefore, thecommon trench83cexposes a portion of the sidewall (79W) of the firstbottom electrode79a′, a portion of the sidewall (79W) of thesecond bottom electrode79b′, and a portion of theetch stop layer71. The first and secondbottom electrodes79a′ and79b′ cover the first and second electrode contact plugs77p′ and77b′, respectively. Also, thecommon trench83cis preferably formed to have a second width (W2 of FIG. 6), which is greater than the first width (W1 of FIG. 6) in order to obtain uniform areas of the exposed sidewalls79W of thebottom electrodes79a′ and79b′ regardless of any misalignment between the bottom electrodes and thephotoresist pattern83.
• In an alternative embodiment, if the second insulating[0062]layer75 is formed of a single oxide layer, then the second insulatinglayer75 is preferably only partially etched during the formation of thecommon trench83c. This prevents theinterconnection line67ifrom being exposed by thecommon trench83c.
• Subsequently, the[0063]photoresist pattern103 is removed. A phasechangeable material layer105 and atop electrode layer107 are sequentially formed, as illustrated in FIG. 15. The phasechangeable material layer105 may be formed of the GST layer, and thetop electrode layer107 can be formed of, for example, a TiN layer, a TiAIN layer, a TaN layer, a carbon layer or a TiW layer using a PVD technique or a CVD technique.
• Referring to FIGS. 6, 7 and[0064]16, thetop electrode layer107 and the phasechangeable material layer105 are patterned to form a common data storage pattern. The common data storage pattern includes a common phasechangeable material pattern105aand a commontop electrode107astacked thereon. Also, the common phasechangeable material pattern105ais formed to cover thecommon trench83c. As a result, the area of the contact regions C, between thebottom electrodes77p′ and77p″ and the common phase changeable material pattern, is much smaller than the comparable area in memory cells of the prior art.
• A fourth insulating[0065]layer109 is then formed on thetop electrode layer107, as illustrated in FIG. 16. The fourth insulatinglayer109 is patterned to form a first bitline contact hole111aand a second bitline contact hole111b. The first and second bit line contact holes111aand111bare preferably formed to be adjacent to the first and secondbottom electrodes79a′ and79b′, respectively. Alternatively, the fourth insulatinglayer109 may be patterned to form a single bit line contact hole (not shown) that exposes a center region of the commontop electrode107a. Abit line113 is then formed on the fourth insulatinglayer109 using the same manner as described above with reference tobit line93.
• FIG. 17 is a top plan view illustrating a pair of phase changeable memory cells according to a further embodiment of the present invention, and FIG. 18 is a cross-sectional view taken along a line III-III′ of FIG. 17. The memory cells of FIG. 17 differ from those of the earlier figures in that a[0066]bottom electrode79d′ and79e′ is formed much larger than thebottom electrodes79a′ and79b′ of FIGS. 4 and 6. Additionally, thecontact openings83dand83eextend through thebottom electrodes79d′ and79e′, respectively, whereas thecontact openings83a,83b, and83conly extend through one edge of their respective bottom electrodes. Therefore, a portion of thebottom electrodes79d′ and79e′ that contact aphase transition region155p′ and155p″ (FIG. 18) is larger than the similar portion of thebottom electrodes79a′ and79b′ of FIGS. 4 and 6. This may be counter-intuitive as compared to the other embodiments, in that one benefit of embodiments of the invention is to reduce the amount of area of the bottom electrode in contact with the phase transition region. However, the total amount of contact area will still be small compared to cells of the prior art (FIG. 3), and the amount of area of contact has very little variance from cell to cell due to production variances, which provides other benefits to manufacturing the cells in this way.
• FIGS.[0067]19-21 illustrate fabrication processes used in making the memory cells shown in FIGS. 17 and 18. For brevity, processes illustrated and described above are not repeated here. FIG. 19 shows abottom electrode layer79dand79eas formed on the insulatinglayer75. The bottom electrode layers79dand79eare much larger than thebottom electrodes79aand79billustrated in FIGS.4-7. An insulatinglayer151 is formed on the bottom electrode layers79aand79band aphotoresist layer153 is formed on the insulatinglayer151. The photoresist layer is patterned as illustrated in FIG. 19.
• After patterning the[0068]photoresist layer153, an etching process creates thetrenches83dand83eby etching through portions of the insulatinglayer151, completely through the bottom electrode layers79aand79b(such that a hole in the bottom electrode layers remains), and through some of the insulatinglayer75. If the insulatinglayer75 includes an etch stop layer (as illustrated in FIGS. 19 and 20), the etching process ends at the etch stop layer. Once etched, a phasechangeable material layer155 is deposited within thetrenches83dand83e, and on the insulatinglayer151. Atop electrode layer157 is formed on the phasechangeable layer155.
• As illustrated in FIG. 21, the[0069]top electrode layer157 is patterned to form a pair of top electrodes,157aand157b. Next, a second insulatinglayer159 is formed over thetop electrodes157aand157b, and in other areas over the insulatinglayer151. The secondinsulating layer159 is patterned withcontact holes161aand161b, and a contact line is formed on the second insulating layer and within the contact holes. Thecontact line163 is electrically connected to thetop electrodes157aand157b.
• In the finished pair of memory cells, the phase[0070]changeable material layer155 is in contact with an edge “C” of thebottom electrodes77p′ and77p″. Although FIG. 21 shows the contacts “C” as four discrete areas (two for each cell), the section line III (FIG. 17) actually cuts through the center of thebottom electrodes77p′ and77p″. Therefore, the contacts “C” are really a perimeter edge through thebottom electrodes77p′ and77p″, one perimeter edge per each cell. That is, the contacts C are each a respective sidewall of a hole through thebottom electrodes77p′ and77p″. Although illustrated in FIG. 17 as having square or rectangular holes, the shape of the holes through thebottom electrodes77p′ and77p″ within thetrenches83dand83emay be any shape, including circular or oval, for instance.
• In operation, when current flows through a cell as illustrated in FIG. 21 for the desired time and temperature (explained above with reference to FIG. 2), a portion of the phase[0071]changeable layer155 changes state and resistivity. Because the contact “C” in this embodiment extends along a perimeter through thebottom electrode77p′ and77p″, the portion of the phasechangeable layer155 that changes state is an area all along the perimeter of the opening in the bottom electrode. This portion will have the same shape as the hole through the bottom electrode, of course.
• According to embodiments of the present invention as described above, a portion of the sidewall of the bottom electrode, or a perimeter edge of a contact opening through the bottom electrode is in direct contact with the phase changeable material pattern. Thus, when the thickness of the bottom electrode is relatively thin, the contact area between the bottom electrode and the phase changeable material pattern is significantly decreased as compared to the memory cells of the prior art. As a result, it is possible to reduce power consumption of the phase changeable memory device and to form reliable and compact phase changeable memory cells.[0072]

Claims (51)

What is claimed is:

1. A phase changeable memory cell, comprising:

a transistor including a source region coupled to a source contact, a drain region coupled to a drain contact, and a gate electrode; and

a variable resistor including a first electrode, a second electrode having a top, bottom, and a sidewall, and a phase changeable material intermediate the first and second electrode, the phase changeable material covering at least a portion of the sidewall of the second electrode.

2. The phase changeable memory cell ofclaim 1 wherein the second electrode of the variable resistor is coupled to one of the source and drain contacts.

3. The memory cell ofclaim 1 wherein the phase changeable material is a chalcogenide material.

4. The phase changeable memory cell ofclaim 1 wherein the phase changeable material is a compound that includes germanium, antimony, and tellurium.

5. The phase changeable memory cell ofclaim 1 wherein the phase changeable material covers the entire portion of the sidewall of the second electrode.

6. The phase changeable memory cell ofclaim 1 wherein the sidewall of the second electrode is a sidewall of a hole formed through the second electrode.

7. A phase changeable memory cell, comprising:

a transistor including a source region coupled to a source contact, a drain region coupled to a drain contact, and a gate electrode; and

a variable resistor including a first electrode, a second electrode having a top, bottom, and a sidewall, and a phase changeable material intermediate the first and second electrode, the phase changeable material covering less than 5000 square nanometers of the sidewall of the second electrode.

8. The phase changeable memory cell ofclaim 7 wherein the phase changeable material covers an entire sidewall of the second electrode.

9. The phase changeable memory cell ofclaim 7 wherein the phase changeable material covers less than 500 square nanometers of the sidewall of the second electrode.

10. The phase changeable memory cell variable resistor ofclaim 7 wherein the sidewall of the second electrode has a height less than 50 nanometers.

11. The variable resistor ofclaim 7 wherein the sidewall of the second electrode a height between about 3 to 7 nanometers and a width between about 20 to 150 nanometers.

12. A variable resistor in a non-volatile memory cell, the variable resistor comprising:

a first electrode;

a phase changeable material adjacent the first electrode; and

a second electrode having a top surface, a bottom surface, and one or more side surfaces, wherein one of the side surfaces of the second electrode is adjacent to the phase changeable material.

13. The variable resistor ofclaim 12 wherein the phase changeable material is formed within an isolation trench of an insulating material, the isolation trench having at least one side that is longer than at least one of the side surfaces of the second electrode.

14. The variable resistor ofclaim 12 wherein the side surface of the second electrode adjacent the phase changeable material has a height less than 50 nanometers.

15. The variable resistor ofclaim 12 wherein the side surface of the second electrode adjacent the phase changeable material has a height between about 3 to 7 nanometers and a width between about 20 to 150 nanometers.

16. The variable resistor ofclaim 12 wherein the only portion of the second electrode that contacts the phase changing material is one of the side surfaces.

17. The variable resistor ofclaim 12 wherein an entire one of the side surfaces of the second electrode contacts the phase changeable material.

18. The variable resistor ofclaim 12 wherein the one of the side surfaces adjacent to the phase changeable material is a sidewall surface of a hole extending through the second electrode.

19. A phase changeable memory cell, comprising:

a substrate having a source region and a drain region, and having a channel region therebetween;

a transistor gate disposed over the channel region;

a cell insulating layer covering portions of the source and drain regions, and covering at least a portion of the transistor gate;

a source contact formed through the cell insulating layer and coupled to the source region;

a drain contact formed through the cell insulating layer and coupled to the drain region; and

a variable resistor, including:

a first electrode,

a phase changeable material, and

a second electrode coupled to the source contact, at least a portion of a side surface of the second electrode covered by the phase changeable material.

20. The memory cell ofclaim 19 wherein the phase changeable material is disposed in a trench in the cell insulating layer.

21. The memory cell ofclaim 20 wherein the side surface of the second electrode has a length that is shorter than a length of a side of the trench of the insulating layer.

22. The memory cell ofclaim 19 wherein the second electrode comprises Titanium.

23. The memory cell ofclaim 19, wherein the second electrode comprises a material selected from the group consisting of Titanium nitride (TiN), Titanium Aluminum Nitride (TiAIN), TiW, TiSiC, and TaN.

24. The memory cell ofclaim 19 wherein the second electrode has a thickness less than 50 nanometers.

25. The memory cell ofclaim 19 wherein the second electrode has a thickness between about 3 to 7 nanometers.

26. The memory cell ofclaim 19 wherein the phase changeable material is a chalcogenide material.

27. A pair of phase changeable memory cells, comprising:

a substrate having a first cell transistor and a second cell transistor, the first and second cell transistor each having a separate source and gate, and the first and second cell transistor sharing a common drain;

a cell insulating layer covering the first and second cell transistors; and

a first and a second variable resistor, each of the resistors including:

a first electrode,

a phase changeable material, and

a second electrode coupled to the source of a respective cell transistor, a side surface of the second electrode adjacent to the phase changeable material.

28. The pair of phase changeable memory cells ofclaim 27 wherein the phase changeable material for each of the variable resistors is formed in a separate trench in the cell insulating layer.

29. The pair of phase changeable memory cells ofclaim 28, further comprising a bit line coupled to the first electrode of each of the variable resistors.

30. The pair of phase changeable memory cells ofclaim 27 wherein the phase changeable material of the first and second variable resistors is formed in a single trench in the cell insulating layer.

31. The pair of phase changeable memory cells ofclaim 28 wherein the first electrode for each of the cells is electrically coupled to one another, and further comprising a bit line coupled to the first electrode of each of the variable resistors.

32. A method for forming a non-volatile memory cell, the method comprising:

in a substrate, forming a cell transistor;

forming an insulating layer adjacent to the cell transistor;

forming a first electrode on the insulating layer and coupled to the cell transistor;

forming a trench in the insulating layer, a sidewall of the trench adjacent to a sidewall of the first electrode;

filling the trench with a phase changeable material, a portion of the phase changeable material adjacent the sidewall of the first electrode; and

forming a second electrode on the phase changeable material.

33. The method ofclaim 32, further comprising:

forming a cell contact line; and

coupling the cell contact line to the second electrode.

34. The method ofclaim 32 wherein forming the trench comprises etching through a portion of the insulating layer and a through a portion of the first electrode.

35. The method ofclaim 32 wherein forming the trench comprises etching through a portion of the insulating layer and etching a hole through the first electrode.

36. The method ofclaim 32 wherein forming the trench comprises forming a trench that has a length greater than a length of an edge of the first electrode.

37. The method ofclaim 32 wherein filling the trench with a phase changeable material comprises filling the trench with chalcogenide.

38. The method ofclaim 32 wherein forming a first electrode comprises forming an electrode comprising Titanium.

39. The method ofclaim 32, wherein forming a first electrode comprises forming an electrode comprising a material selected from the group consisting of Titanium nitride (TiN), Titanium Aluminum Nitride (TiAIN), TiW, TiSiC, and TaN.

40. The method ofclaim 32 wherein forming a first electrode comprises forming an electrode by plasma vapor deposition and chemical vapor deposition.

41. A method for forming a pair of non-volatile memory cells, the method comprising:

in a substrate, forming a first cell transistor and a second cell transistor;

forming an insulating layer adjacent to the first and second cell transistors;

forming a first bottom electrode on the insulating layer and coupled to the first cell transistor;

forming a second bottom electrode on the insulating layer and coupled to the second cell transistor;

forming a first trench in the insulating layer, a sidewall of the first trench adjacent to a sidewall of the first bottom electrode;

forming a second trench in the insulating layer, a sidewall of the second trench adjacent to a sidewall of the second bottom electrode;

filling the first and second trenches with a phase changeable material, a portion of the phase changeable material adjacent the sidewall of the first bottom electrode and the second bottom electrode;

forming a first top electrode on the phase changeable material; and

forming a second top electrode on the phase changeable material.

42. The method ofclaim 41 wherein forming a first trench and forming a second trench comprises forming a single trench.

43. The method ofclaim 41 wherein forming a first top electrode and forming a second top electrode comprises forming a single electrode.

44. The method ofclaim 41 wherein forming the first trench comprises etching through a portion of the insulating layer and a through a portion of the first electrode.

45. The method ofclaim 41 wherein forming the first trench comprises etching through a portion of the insulating layer and etching a hole through the first bottom electrode.

46. The method ofclaim 41 wherein forming the first trench comprises forming a trench that has a length greater than a length of an edge of the first bottom electrode.

47. The method ofclaim 41 wherein filling the first trench with a phase changeable material comprises filling the first trench with chalcogenide.

48. A method for forming a non-volatile memory cell, comprising:

in a substrate, forming a source region, a drain region and a channel region portion lying therebetween;

forming a transistor gate disposed on the channel region portion of the substrate;

depositing a first insulating material over the source region, the drain region, and transistor gate;

forming a source contact through the first insulating material, the source contact electrically coupled to the source region;

forming a first variable resistor electrode adjacent to and electrically coupled to the source contact;

forming a second insulating material over the resulting substrate surface;

forming an opening in the second insulating material;

exposing a sidewall of the first variable resistor electrode to the opening in the second insulating material;

filling the opening in the second insulating material with a phase changeable material; and

forming a second variable resistor electrode on the phase changeable material and separate from the first variable resistor contact.

49. The method ofclaim 48 wherein forming an opening in the second insulating material comprises forming a trench in the second insulating material.

50. The method ofclaim 48 wherein exposing a sidewall of the first variable resistor contact comprises etching a hole through the first variable resistor contact.

51. The method ofclaim 48 wherein forming an opening in the second insulating material and exposing a side of the variable resistor contact to the opening in the second insulating material occur simultaneously.

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