US20040153583A1 - Serial communication device with dynamic allocation of acceptance masks using serial implementation - Google Patents

Abstract

A CAN module or a microcontroller comprises a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.

Description

FIELD OF THE INVENTION
• The present invention relates to a serial communication device, in particular a Controller Area Network (CAN) device. Furthermore, the present invention relates to a microcontroller with a serial communication device and a method of operating a serial communication device.[0001]
BACKGROUND OF THE RELATED TECHNOLOGY
• Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a high level of security. Applications of CAN range from high speed digital communications networks to low cost multiplex wiring. CAN is a high-integrity serial data communications bus for real-time applications. CAN operates at data rates of up to 1 Megabits per second, has excellent error detection and confinement capabilities, and was originally developed for use in automobiles. The interface between the CAN bus and the CPU is usually called the CAN controller. The motivation behind CAN was to make automobiles more reliable, safe and fuel-efficient by improving the interoperability of automotive electronics, engine control units, sensors, anti-skid brake systems, etc., while decreasing wiring harness weight and complexity. Since CAN's inception, the CAN protocol has gained widespread popularity in industrial automation and automotive/truck applications. The robustness of the CAN bus in noisy environments and the ability to detect and recover from fault conditions makes CAN suitable for use with, industrial control equipment, medical equipment, test equipment, mobile and portable machines, appliances, etc.[0002]
• CAN is an asynchronous serial bus system with one logical bus line. It has an open, linear bus structure with equal bus nodes. A CAN bus consists of two or more nodes. The number of nodes on the bus may be changed dynamically without disturbing the communication of the other nodes.[0003]
• The CAN logic bus corresponds to a “wired-AND” mechanism, “recessive” bits (mostly, but not necessarily equivalent to the logic level “1“) are overwritten by “dominant” bits (mostly logic level “0”). As long as no bus node is sending a dominant bit, the bus line is in the recessive state, but a dominant bit from any bus node generates the dominant bus state. Therefore, for the CAN bus line, a medium is chosen that is able to transmit the two possible bit states (dominant and recessive). A common physical medium used is a twisted wire pair. The bus lines are then called “CANH” and “CANL,” and may be connected directly to the CAN controller nodes or via a connector thereto.[0004]
• In the CAN bus protocol it is not bus nodes that are addressed, but rather the address information is contained in the messages that are transmitted. This is done via an identifier (part of each message) which identifies the message content, e.g., engine speed, oil temperature, etc. The identifier additionally indicates the priority of the message. The lower the binary value of the identifier, the higher the priority of the message (more dominant bits).[0005]
• The original CAN specifications (Versions 1.0, 1.2 and 2.0A) defined the message identifier as having a length of 11 bits, giving a possible 2048 message identifiers. An “extended CAN” specification Version 2.0B allows message identifier lengths of 11 and/or 29 bits to be used (an identifier length of 29 bits allows over 536 Million message identifiers). The CAN specifications (all versions) are incorporated by reference herein for all purposes.[0006]
• Generally, two approaches may be used for CAN since an architecture for the CAN controller is not covered by the CAN standard, these two approaches are: “BasicCAN” and “FullCAN” (not to be confused with CAN 1 and CAN 2, or standard identifiers and extended identifiers); they differ in the buffering of messages.[0007]
• The BasicCAN controller architecture is similar to simple UART, except that complete frames are sent instead of characters. Typically, there is a single transmit buffer and a double-buffered receive buffer. For example, a microcontroller puts a frame in the transmit buffer, and receives an interrupt when the frame is sent. When a frame is received in the receive buffer, the microcontroller receives an interrupt to empty the receive buffer and empties the frame from the receive buffer before a subsequent frame is received. In the BasicCAN controller architecture the microcontroller must manage the transmission and reception, and handle the storage of the frames.[0008]
• The FullCAN controller architecture stores frames in the controller itself. A limited number of frames may be dealt with. Each frame buffer is tagged with the identifier of the frame mapped to the buffer. The microcontroller can update a frame in the buffer and mark it for transmission. Receive buffers can be examined to see if a frame with a matching identifier has been received. In addition, filters may be used to pre-screen a received frame so that only those frames intended for use by the particular CAN controller is stored in a receive buffer.[0009]
• Standard CAN vs Extended CAN[0010]
• The CAN protocol usually comes in two versions: CAN 1.0 and CAN 2.0. CAN 2.0 is backwardly compatible with CAN 1.0, and most new controllers are built according to CAN 2.0. There are two parts to the CAN 2.0 standard: part A and part B. With CAN 1.0 and CAN 2.0A, identifiers must be 11-bits long. With CAN 2.0B identifiers can be 11-bits (a “standard” identifier) or 29-bits (an “extended” identifier). To comply with CAN 2.0 a controller must be either 2.0 part B passive, or 2.0 part B active. If it is passive, then it must ignore extended frames (CAN 1.0 controllers will generate error frames when they see frames with 29-bit identifiers). If it is active then it must allow extended frames to be received and transmitted. There are some compatibility rules for sending and receiving the two types of frames:[0011]
• CAN 2.0B active controllers will send and accept both standard and extended frames.[0012]
• CAN 2.0B passive controllers will send and receive standard frames, and will discard extended frames without error.[0013]
• CAN 1.0 controllers will generate errors when they see extended frames.[0014]
• So a network where there is a single CAN 1.0 controller on the network cannot live with extended frames on the network; all the controllers must send using standard frames.”[0015]
• Controller Architectures[0016]
• The architecture of controllers isn't covered by the CAN standard, so there is a variation in how they are used. There are, though, two general approaches: BasicCAN and FullCAN (not to be confused with CAN 1.0 and 2.0, or standard identifiers and extended identifiers); they differ in the buffering of messages.”[0017]
• In a BasicCAN controller the architecture is similar to a simple UART, except that complete frames are sent instead of characters: there is (typically) a single transmit buffer, and a double-buffered receive buffer. The CPU puts a frame in the transmit buffer, and takes an interrupt when the frame is sent; the CPU receives a frame in the receive buffer, takes an interrupt and empties the buffer (before a subsequent frame is received). The CPU must manage the transmission and reception, and handle the storage of the frames.”[0018]
• In a FullCAN controller the frames are stored in the controller. A limited number of frames can be dealt with (typically 16); because there can be many more frames on the network, each buffer is tagged with the identifier of the frame mapped to the buffer. The CPU can update a frame in the buffer and mark it for transmission; buffers can be examined to see if a frame with a matching identifier has been received.”[0019]
• The intention with the FulICAN design is to provide a set of “shared variables” in the network; the CPU periodically updates the variables (i.e., the contents of frames in the buffer); the CPU also can examine the variables. In practice, things are not so simple (of course) because of concurrency difficulties: while reading a set of bytes from a frame, the controller could overwrite the data with the contents of a new frame, and in many controllers this is signaled only by a status flag.”[0020]
• In “Basic CAN” implementations, there is generally one double buffered receive channel with one or more associated message acceptance filters. Having but one double buffered message channel means that the processor must be capable of handling the previous message within this time. In “Full CAN” implementations, there are generally up to 15 message buffers or channels, each with one associated message acceptance filter. Having a large number of receive-buffers can be helpful in dealing with bursts of message traffic if the processor is very slow, however, if the total message traffic is such that it overwhelms the processor capability, no amount of buffering can prevent the eventual loss of a message. If a processor's CPU is very slow, to receive many different addressed messages requires separate receive buffers and acceptance filters. With a faster processor, it is possible to use a more limited number of receive buffers with flexibility in the programming of the acceptance filters. In short, the processor must have the bandwidth to service the total traffic on the bus. A plurality of buffers is usually implemented as a compromise. However, each receive buffer has associated a plurality of mask registers and filter registers as well as associated comparators. This requires a large amount of silicon real estate.[0021]
• There is, therefore, a need in the art for a CAN implementation that does not require a large amount of silicon area.[0022]
SUMMARY OF THE INVENTION
• The invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by a CAN module or a microcontroller comprising a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.[0023]
• A further enhancement can comprise a mask register with a bit select input and a single bit output and a mask unit receiving the mask single bit output and the comparison result and generating a result signal being fed to the register. In addition, at least two mask registers with a bit select input and a single bit output and a multiplexer for selecting one of the mask register single bit outputs can be provided .[0024]
• In yet another enhancement, the multiplexer comprises an input which is coupled with the single bit output of a further filter register and/or an input which is coupled with a constant signal indicating no mask function. The multiplexer can be controlled by at least one bit from the filter register. For example, the filter register comprises two additional bits to control the multiplexer. In an exemplary embodiment, the comparator is an EXCLUSIVE NOR gate, the mask unit is a NOR gate, and the register is a D-Flip-Flop.[0025]
• A method of operating a CAN module comprises the steps of:[0026]
• receiving a data stream;[0027]
• generating an identifier and data out of the data stream;[0028]
• comparing said identifier with a filter value on a bit by bit base;[0029]
• generating an acceptance signal if the comparison is positive;[0030]
• storing associated data in a buffer upon generation of the acceptance signal.[0031]
• An enhancement of this method comprises the step of masking the comparison result on a bit by bit base. Furthermore, a mask value can be selected from a plurality of mask values. In yet another enhancement the filter value provides additional data information for selecting the mask value. For example, the mask values is selected from a plurality of mask registers and filter registers and one mask value can provide a non-masking function.[0032]
• The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.[0033]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a schematic diagram of the receive buffers and their associated filters according to the prior art.[0034]
• FIG. 2 is a schematic diagram of the receive buffers and their associated filters and comparators according to a first exemplary embodiment of the present invention;[0035]
• FIG. 3 shows details of the CAN protocol engine according to the exemplary embodiment shown in FIG. 2;[0036]
• FIG. 4 shows details of a serial bit comparator unit according to FIG. 2; and[0037]
• FIG. 5 shows another embodiment of a serial bit comparator according to FIG. 2.[0038]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
• Referring to FIG. 1, receive[0039]buffers118,120, and122 and associatedmask102,108 and filterregisters104,106,110,112,114,116 according to the prior art are illustrated.Buffer120, designated as a message assembly buffer (MAB), functions only to monitor the CAN logic bus (not shown) for incoming messages. TheMAB120 holds a de-stuffed bit stream from the bus line. The bit stream consists of a message, i.e. a data frame, remote frame, or other frame, comprising an identifier and data field (not shown). TheMAB120 allows receivebuffers118 and122 parallel access to the message.MAB120 also allows acceptance filters106 and116 access to the identifier portion of the message. Parallel transfer of the bit stream message to receivebuffers118 or122 is not allowed until acceptance masks102 and108 and acceptance filters104,106,110,112,114, and116 apply an acceptance match test to the message.
• Programmable acceptance filter masks[0040]102 and108, respectively, are used to select which bits of the unstuffed bit-stream message should be compared with the contents of acceptance filters104 and106, and110,112,114, and116.
• The acceptance match test proceeds as follows:[0041]Filters104,106,110,112,114, and116 receive the identifier field of the message and compare that field to filter values. If there is a match between the identifier field and a filter value, then the message is loaded into the matching filter's corresponding receivebuffer118 or122.Filters104 and106 are connected to buffer118,filters110,112,114, and116 to buffer122.
• There is an implied priority to the receive buffers.[0042]Buffer118 is the higher priority buffer and has message acceptance filters104 and106 associated with it.Buffer122 is the lower priority buffer and has acceptance filters110,112,114, and116 associated with it. That fewer filters are associated withbuffer118 than withbuffer122 means thatbuffer118 is more restrictive thanbuffer122. The morerestrictive buffer118 has, by implication, the higher criticality associated with it.
• On the occasion when two “high-priority” messages are received by[0043]MAB120 in quick succession, receivebuffer118, designated as the first high-priority buffer, will receive the first high-priority message. Upon receipt of the second high-priority message,MAB120 finds thatbuffer118 is currently occupied by a high-priority message.MAB120 then directsbuffer122, designated as the second high-priority buffer, to receive the second high-priority message.Buffers118 and122 are ranked, respectively, as the first high-priority buffer and the second high-priority buffer in this scenario.
• The central processing unit (CPU) (not shown) may operate on one of the receive[0044]buffers118 and122, while the other is available for reception or holding a previously received message.
• The protocol in the case of the arrival of two high-priority messages is effected by the BUKT bit in the control registers (not shown) of receive[0045]buffers118 and122. Table I depicts and explains the control register of receivebuffer118, wherein R/W means Readable/Writable bit, and wherein R means Read-only bit.

  TABLE I
  bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
  R/W	R/W	R/W	R/W	R/W	R/W	R	R/W

• bit7: Message Ready Status[0046]
• [0047]1=Receive Buffer contains a valid received message
• [0048]0=Receive Buffer open to receive new message
• Bit is only set by CAN module, bit is only cleared by CPU.[0049]
• bit6-5: Receive Buffer Operating Mode[0050]
• [0051]11=receive all messages including those with errors
• [0052]10=receive only valid messages with extended identifiers
• [0053]01=receive only valid messages with standard identifiers
• [0054]00=receive all valid messages
• bit4: Message Reception Interrupt Enable[0055]
• [0056]1=Interrupt Enabled
• [0057]0=Interrupt Disabled
• bit3: Received Remote Transfer Request[0058]
• [0059]1=Remote Transfer Request Received
• [0060]0=No Remote Transfer Request Received
• bit2: (BUKT) Enable Overflow to Receive[0061]Buffer122
• [0062]1=ReceiveBuffer118 Overflow Will Write to Buffer122
• [0063]0=No Overflow to Buffer122 Allowed
• bit1: Read Only Copy of bit2 (BUKT)[0064]
• bit0: Indicates which acceptance filter enabled the message reception[0065]
• [0066]1=acceptance filter associated withBuffer122
• [0067]0=acceptance filter associated withBuffer118
• If set to “1,” the BUKT bit implements the priority-based protocol of the present invention.[0068]
• Table II depicts and explains the control register of receive[0069]buffer122.

  TABLE II
  bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
  R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

• bit7: Message Ready Status[0070]
• [0071]1=Receive Buffer contains a valid received message
• [0072]0=Receive Buffer open to receive new message
• Bit is only set by CAN module, bit is only cleared by CPU.[0073]
• bit6-5: Receive Buffer Operating Mode [these bits are optional][0074]
• [0075]11=receive all messages including those with errors
• [0076]10=receive only valid messages with extended identifiers
• [0077]01=receive only valid messages with standard identifiers
• [0078]00=receive all valid messages
• bit4: Message Reception Interrupt Enable[0079]
• [0080]1=Interrupt Enabled
• [0081]0=Interrupt Disabled
• bit3: Received Remote Transfer Request[0082]
• [0083]1=Remote Transfer Request Received
• [0084]0=No Remote Transfer Request Received
• bit2-0: Indicates which acceptance filter enabled the message reception[0085]
• [0086]101=acceptance filter116
• [0087]100=acceptance filter114
• [0088]011=acceptance filter112
• [0089]010=acceptance filter110
• [0090]001=acceptance filter106 [only if BUKT bit set to “1” in control register for buffer118]
• [0091]000=acceptance filter104 [only if BUKT bit set to “1” in control register for buffer118]
• FIG. 2 shows an exemplary embodiment of the present invention with a serial comparison according to the present invention. A first and[0092]second mask register415 and420 are bit-wise addressable and comprise a single output bit. Furthermore, a plurality offilter registers0 . . . N (only two are shown) are designated bynumerals425 and430. The filter registers425,430 also comprise a single output bit and are bit-wise addressable. In addition mask registers415 and420 as well as all filter registers425,430 are read and write-able in a parallel mode by a central processing unit497 (connection not shown in FIG. 2). A sequencer andcontrol unit410 operates as a bit select unit and generates address signals which are fed to mask register415 and420 and all filterregisters425,430. Eachfilter register425,430 comprises an associated bitcomparator unit435,440. The bit output signal ofmask register415 and420 are fed to first and second inputs of bitcomparator units435,440. Furthermore, each bit output of the filter registers425,430 is fed to a third input of their associated bitcomparator unit435,440. A bit stream signal from a CAN bus is provided by aCAN protocol engine495 and fed to a fourth input of eachbit comparator unit435,440. Filter registers425,430 can provided additional storage bits which are coupled with a fifth input of each associated bit comparator unit. The output of eachbit comparator unit435,440 carries the acceptance signal and is coupled with a control input of an associatedbuffer pointer445,450. An ORgate455 is provided having as many inputs as the number of filter registers. Each input receives an acceptance signal from a respective bitcomparator unit435,440. The outputs of eachbuffer pointer445 and450 are coupled with abuffer pointer bus462 which is connected to an address input of a multiplefunction address register460. The output of ORgate455 is coupled with a control input ofmultiple function register460.Multiple function register460 further comprises amode control input465, afirst status output475 indicating whether abuffer memory485 is full, asecond status output480 indicating whether abuffer memory485 is empty, and an up/down control input for a counter function of the multiplefunction address register460. An address output464 of multiplefunction address register460 is coupled with the address input ofbuffer memory485.Buffer memory485 is preferably a dual port memory whose first port is coupled with a message assemblybuffer shift register490 receiving the serial data stream from theCAN protocol engine495. The second port of is coupled withcentral processing unit497 which is furthermore coupled with amemory496 for storing program and data information.
• Even this is not crucial to the present invention, this embodiment provides two options to write data from a serial data stream into the[0093]buffer memory485. Both options can be implemented as a stand alone embodiment or combined as shown in FIG. 2 with the features of the present invention. The comparison of filter values stored in filter registers425,430 and transmitted identifiers is done in a bit-wise fashion rather than in parallel. Thus, parallel comparators, which need a relatively big amount of silicon real estate, are avoided. A serial data stream provided byCAN protocol engine495 comprises an identifier which is fed directly to all bitcomparator units435,440. Sequencer andcontrol unit410 address the mask registers415,420 and all filterregisters425,430 to output a corresponding bit to thebit comparator units435,440. Thebit comparator units435,440 compare all filter register bits with the respective identifier bit within a frame. The result is further processed by comparing it to the respective mask register bit. To this end, the additional storage bits of eachfilter register425,430 can indicate which mask register should be used for this comparison. This function will be explained in more detail below. The final comparison result will be accumulated for all bits of each identifier within a frame. If a single comparison fails the acceptance signal will not be generated. If every bit comparison is positive the acceptance signal will be fed to therespective buffer pointer445,450 and to a respective input of ORgate455.
• A central processing unit can control the multiple[0094]function address register460 in the following manner. Two modes can be selected throughmode signal465. In the first mode thebuffer pointer445,450 work in the same way as described above in conjunction with FIG. 2. Multiple function address register460 latches an address which has been put onaddress bus462 and addressesbuffer memory485 stores data in parallel that has been assembled by message assemblybuffer shift register490.
• A second mode can be selected by means of[0095]control signal465. In this mode thebuffer pointers445,450 are not needed and therefore their output signals will be neglected. When this mode is activated the actual address register within multiple function address register is, for example, set to “Fh” and thestatus signal480 will signal an empty buffer. Every time abit comparator unit435,440 generates an acceptance signal this triggers an increment function of the multiplefunction address register460 and its content will therefore be incremented by 1. Thus, the first data assembled by message assemblybuffer shift register490 will be stored atmemory location0. This function provides a so called FIFO functionality of the CAN module in which no buffer is associated with any bit comparator. Thebuffer memory485 will be sequentially written until the address reaches “Fh” again which indicates that the buffer is full unless the CPU has read previous entries. Afull buffer memory485 will be indicated bycontrol signal475. In an additionalmode control signal470 can select between a incrementing and decrementing function of the address register. Additional signals can be provided by the CPU to indicate whether a buffer value has been read for generating the proper status signals475, and480 and to ensure that no value will be overwritten before it has been fetched by the CPU.
• FIG. 3 shows the[0096]CAN protocol engine495 from FIG. 2 in more detail. Theprotocol engine495 combines several functional blocks. The heart of theengine495 is the protocol finite state machine310 (FSM). This state machine sequences through the messages on a bit by bit basis, changing states of the machine as various fields of various frame types are transmitted or received. TheFSM310 is a sequencer controlling the sequential data stream between the RX/TX shift register320,325, theCRC Register330, and the receivebus line350 and transmitbus line360, respectively. The shift registers320,325 can be part of the message assembly register270.Additional components355 and365 are provided to convert the data streams and adapt to the respective timing on thebus lines350 and360. The FSM also controls the Error Management Logic340 (EML) and the parallel data stream RecData between the TX/RX shift register320,325 and other components of the CAN module. The processes of reception arbitration, transmission, and error signaling are performed according to the CAN protocol. TheFSM310 also handles any automatic transmission of messages on the bus line.
• The data interface to the[0097]protocol engine495 consists of byte wide transmit and receive data. Rather than assembling and shifting an entire frame, the frames are broken into bytes. A receive or transmit address from theprotocol FSM310 signifies which byte of the frame is current. For transmission, the appropriate byte from the transmit buffer is selected and presented to the engine, which then uses an 8-bit shift register to serialize the data. For reception, an 8-bit shift register assembles a byte which is then loaded within the appropriate byte in the message assembly buffer270.
• The cyclic[0098]redundancy check register330 generates the Cyclic Redundancy Check (CRC) code to be transmitted over the data bytes and checks the CRC code of incoming messages. The Error Management Logic (EML)340 is responsible for the fault confinement of the CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are incremented and decremented by commands from the Bit stream processor. According to the values of the error counters, the CAN controller is set into states error active, error passive or bus off.
• The Bit Timing Logic (BTL) within[0099]unit355 monitors the bus line input and handles the bus line related bit timing according to the CAN protocol. The BTL synchronizes on a recessive to dominant bus line transition at Start of Frame and on any further recessive to dominant bus line transition, if the CAN controller itself does not transmit a dominant bit. The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and in defining the position of the Sample Point in the bit time. The programming of the BTL depends on the baud rate and on external physical delay times.
• In FIG. 4 an exemplary embodiment of a comparator unit according to the present invention is shown. The details are shown for a single Bit comparator unit but apply for all other bit comparator units accordingly.[0100]Numeral600 indicates a unit providing a CAN serial data stream which is fed to a messageassembly buffer register680 and the first input of an Exclusive NORgate690. The single bit output of afilter register620 is coupled with the second input of Exclusive NORgate690 whose output is connected with the first input of a NORgate650. The second input of NORgate650 receives the single bit output signal frommask register630. The output of NORgate650 is coupled with the first input of an ANDgate660 whose output is coupled with the control input of a D-Flip-Flop670. Input D of D-Flip-Flop670 is coupled with a logical “low” signal such as Vcc. The inverting output of D-Flip-Flop670 is coupled with the first input of ANDgate640 whose output provides the acceptance signal. ANDgates640 and660 comprises second inputs ACC_RDY and BIT_RDY, respectively, which are used for synchronization with the respective input signals. ABit Select Logic610 is coupled withfilter register620 and mask register630 to select the respective bits which will be used for comparison within each frame.
• The incoming CAN bit stream is synchronized with the bit[0101]select logic610. In other words, bitselect logic610 selects the respective bit infilter register620 and mask register630 that corresponds to the incoming bit of the serial bit stream. The actual comparator is formed by Exclusive NORgate690 which only generates a logic “high” at its output if both input signals are identical. NORgate650 is used as a mask unit to mask out a result if a respective bit within themask register630 is set. D-Flip-Flop670 is used as a register to accumulate the results within a chain of comparisons and is preset to “1” at the start of a frame. Only if all comparisons within a frame are successful, then the acceptance signal AccN at the output of ANDgate640 will be generated. Otherwise the D-Flip-Flop670 is set to “0” by a false comparison result and stays “0” until the end of the frame. The two control signals ACC_RDY and BIT_RDY are used to synchronize and activate the respective signals.
• FIG. 5 shows another exemplary embodiment of a[0102]bit comparator unit435,440 with even more functionality in more detail. Again, the details are shown forBit comparator unit0 but apply for all other bit comparator units accordingly. The outputs ofmask register415 and420 are coupled with first and second inputs of a 4:1multiplexer520.Additional input560 and570 can be provided at the third and fourth input ofmultiplexer520. For example,input560 is coupled with the output of filter register15 which is designated bynumeral580.Filter register425 comprises, for example, two additional outputs which are coupled with the select input ofmultiplexer520.Multiplexer520 can have any size, for example, can be expanded to a N:1 multiplexer increasing the number of masks to N. The output ofmultiplexer520 is connected to the first input of a NORgate530. NORgate530 operates as a validation unit indicating whether a comparison result will be used or ignored. The second input of NORgate530 is coupled with the output of an Exclusive NORgate510 whose first input receives the bit output signal fromfilter register425 and whose second input receives the serial data stream fromCAN protocol engine495. The output of NORgate530 is coupled with the control input of a D-Flip-Flop540. The D-input of D-Flip-Flop540 receives a logical low signal. The acceptance signal is carried at the negatingoutput550 of D-Flip-Flop540.
• The first comparison stage is formed by Exclusive NOR[0103]gate510. In this stage the identifier bits of the serial bit stream are compared with the respective bits offilter register425. Exclusive NORgate510 only generates a logic “high” at its output if both input signals are identical.Sequencer unit410 selects the respective bits withinfilter register425.Filter register425 comprises additional data bits which indicate which mask register should be used. In this exemplary embodiment four different values can be selected. Either one of the mask registers415 or420 can be selected or a third value can be provided by another filter register, forexample filter register15. The fourthpossible selection570 can be used to indicate that no mask will be used by providing a respective level, for example, a logical “1”. Thus, eachfilter register425,430 can be assigned an individual mask function. The selected mask value will be put at the first input of NORgate530. If the mask value indicates that the respective bit infilter register425 should be used NORgate530 will operate as a controllable switch and feed the comparison result of Exclusive NORgate510 to the control input D-Flip-Flop540. D-Flip-Flop540 is used as a register which is preset to “1”. If the result of one comparison is negative indicating no match and the respective mask bit is valid D-Flip-Flop540 will be cleared and noacceptance signal550 will be generated. D-Flip-Flop540 thus will be reset to “0”. D-Flip-Flop540 will be preset to “1” again beginning with the next frame to compare another identifier as described above.
• Any other type of appropriate logic can be used to implement the comparator. For example, controllable switches, equivalent Boolean operators, etc. can be used. Furthermore, the validation unit can be either put in front of the comparator or after the comparator. The essential function of a validation unit is to either incorporate selected bits or exclude them from comparison.[0104]
• The invention, therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned, as well as others inherent therein. While the invention has been depicted, described, and is defined by reference to particular preferred embodiments of the invention, such references do not imply a limitation on the invention, and no such limitation is to be inferred. The invention is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent arts. The depicted and described preferred embodiments of the invention are exemplary only, and are not exhaustive of the scope of the invention. Consequently, the invention is intended to be limited only by the spirit and scope of the appended claims, giving full cognizance to equivalents in all respects.[0105]

Claims (26)

What is claimed is:

1. A CAN module receiving a serial bit stream comprising:

a filter register having a bit select input and a single bit output;

a bit select unit for selecting a bit of said filter register in accordance with said serial bit stream;

a comparator coupled with said single bit output and with said serial bit stream for generating a comparison signal;

a register receiving said comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.

2. CAN module according toclaim 1, further comprising

a mask register having a bit select input and a single bit output;

a mask unit receiving said mask single bit output and said comparison result and generating a result signal being fed to said register.

3. CAN module according toclaim 2, further comprising

at least two mask register s having a bit select input and a single bit output;

a multiplexer for selecting one of said mask register single bit output s .

4. CAN module according toclaim 3, wherein said multiplexer comprises an input which is coupled with the single bit output of a further filter register.

5. CAN module according toclaim 3, wherein said multiplexer comprises an input which is coupled with a constant signal indicating no mask function.

6. CAN module according toclaim 3, wherein said multiplexer is controlled by at least one bit from said filter register.

7. CAN module according toclaim 6, wherein said filter register comprises two additional bits to control said multiplexer.

8. CAN module according toclaim 1, wherein said comparator is an EXCLUSIVE NOR gate.

9. CAN module according toclaim 1, wherein said mask unit is a NOR gate.

10. CAN module according toclaim 1, wherein said register is a D-Flip-Flop.

11. A microcontroller comprising:

a central processing unit;

a random access memory connected to said central processing unit; and

a CAN module coupled with said central processing unit, wherein said CAN module comprises:

a filter register having a bit select input and a single bit output;

a bit select unit for selecting a bit of said filter register in accordance with said serial bit stream;

a comparator coupled with said single bit output and with said serial bit stream for generating a comparison signal;

a register receiving said comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.

12. The microcontroller according toclaim 11, further comprising:

a mask register having a bit select input and a single bit output;

a mask unit receiving said mask single bit output and said comparison result and generating a result signal being fed to said register.

13. The microcontroller according toclaim 12, further comprising:

at least two mask registers having a bit select input and a single bit output;

a multiplexer for selecting one of said mask register single bit outputs.

14. The microcontroller according toclaim 13, wherein said multiplexer comprises an input which is coupled with the single bit output of a further filter register.

15. The microcontroller according toclaim 13, wherein said multiplexer comprises an input which is coupled with a constant signal indicating no mask function.

16. The microcontroller according toclaim 13, wherein said multiplexer is controlled by at least one bit from said filter register.

17. The microcontroller according toclaim 16, wherein said filter register comprises two additional bits to control said multiplexer.

18. The microcontroller according toclaim 11, wherein said comparator is an EXCLUSIVE NOR gate.

19. The microcontroller according toclaim 11, wherein said mask unit is a NOR gate.

20. The microcontroller according toclaim 11, wherein said register is a D-Flip-Flop.

21. A method of operating a CAN module comprising the steps of:

receiving a data stream;

generating an identifier and data out of said data stream;

comparing said identifier with a filter value on a bit by bit base;

generating an acceptance signal if said comparison is positive;

storing associated data in a buffer upon generation of said acceptance signal.

22. A method according toclaim 21, further comprising the step of masking said comparison result on a bit by bit base.

23. A method according toclaim 22, further comprising the step selecting a mask value from a plurality of mask values.

24. A method according toclaim 23, wherein said filter value provides additional data information for selecting said mask value.

25. A method according toclaim 23, wherein said mask values is selected from a plurality of mask registers and filter registers.

26. A method according toclaim 23, wherein one mask value provides a non-masking function.

Images